Re: [flashrom] [PATCH] dummyflasher: Add a status register to SPI chips.

[Carl-Daniel Hailfinger]

Am 31.01.2012 06:51 schrieb Stefan Tauner:
> This is just a quick hack, that could be expanded. What do you think?
>
> Signed-off-by: Stefan Tauner

Very good idea!
> --- a/dummyflasher.c
> +++ b/dummyflasher.c
> @@ -55,6 +55,7 @@ static unsigned int emu_jedec_be_52_size = 0;
>  static unsigned int emu_jedec_be_d8_size = 0;
>  static unsigned int emu_jedec_ce_60_size = 0;
>  static unsigned int emu_jedec_ce_c7_size = 0;
> +static uint8_t emu_status = 0;
>  #endif
>  #endif
>
> @@ -126,6 +127,9 @@ int dummy_init(void)
>  {
>    char *bustext = NULL;
>    char *tmp = NULL;
> +#if EMULATE_SPI_CHIP
> char *status = NULL;
>
> +#endif
>  #if EMULATE_CHIP
>    struct stat image_stat;
>  #endif
> @@ -178,6 +182,14 @@ int dummy_init(void)
>    	goto dummy_init_out;
>    }
>  #if EMULATE_SPI_CHIP
> status = extract_programmer_param("status");
> if (status) {
> emu_status = atoi(status);
> msg_pdbg("Initial status register is set to 0x%02x.\n",
> 	 emu_status);
> free(status);
> }
> if (!strcmp(tmp, "M25P10.RES")) {
>   emu_chip = EMULATE_ST_M25P10_RES;
>   emu_chip_size = 128 * 1024;
>
> @@ -385,10 +397,26 @@ static int emulate_spi_chip_response(unsigned int writecnt,
>    	if (readcnt > 2)
>    		readarr[2] = 0x4a;
>    	break;
> case JEDEC_RDSR:
> memset(readarr, 0, readcnt);
> case JEDEC_RDSR: {
> uint8_t tmp_status = emu_status;
> if (aai_active)
> 	memset(readarr, 1 << 6, readcnt);
> 	tmp_status |= 1 << 6;

The WIP (write in progress) / WEL (write enable latch) /AIP (AAI in
progress) logic should be moved to the respective commands so RDSR just does
memset(readarr, emu_status, readcnt);
> memset(readarr, tmp_status, readcnt);
> break;
> }
> case JEDEC_WREN:
> emu_status |= (1 << 1);
> break;
> case JEDEC_WRSR:
> if (!(emu_status & (1 << 1))) {
> 	msg_perr("WRSR attempted, but WEL is 0!\n");
> 	return 1;

Don't return 1 because a real chip wouldn't return an error either, it
would just ignore the command.
> }
> if (aai_active) {
> 	msg_perr("WRSR attempted during AAI sequence!\n");
> 	return 1;

dito.
> }
> emu_status = writearr[1] & 0xFC; /* resets WEL and WIP */
> break;
> case JEDEC_READ:
> offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];

After the end of the switch statement we should clear WEL if the command
was not WREN/EWSR.

Regards,
Carl-Daniel