I completely rewrote it *again* :) Apparently the SPI 100 controller in Yangtze is quite different to the existing interface. I spend quite some time on figuring out why the FIFO ring buffer does not seem to work: my diagnose is that it is not a ring buffer at all. I have no idea why they call it FIFO either... we have full indexed access to it. Whatever... these patches should work fine on Kabini (tested on the A180-H). Tests on any other board especially older generations are very welcomed!
Stefan Tauner (6): sbxxx: Add detection for the remaining AMD chipset families. sbxxx: Set SPI clock to 16.5 MHz and disable fast reads. sbxxx: Cleanup. sbxxx: Add support for new AMD SPI controller. sbxxx: Add spispeed parameter. debug
flashrom.8 | 21 +++ programmer.h | 1 + sb600spi.c | 538 ++++++++++++++++++++++++++++++++++++++++++++--------------- 3 files changed, 424 insertions(+), 136 deletions(-)