Hi Michael,
seems to me that the GPIO is accessed as you predicted. I attach the output of superiorool -deV.
Regards, Michal
2011/3/2 Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de:
Hello jankeso,
in the process of writing a board enable procedure for your mainboard I stumbled upon the fact that the chip used to control the write enable line is most likely your Super I/O chip, which is a NSC PC87364. superiotool currently does not support dumping that chip, so I can not verify that indeed the GPIO port of the Super I/O chip is accessed (at address 0x80C). I attached a patch to dump the contents of that chip to this mail. Please apply that patch to current superiotool CVS sources (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool) and attach the output to a reply to this mail or upload to paste.flashrom.org.
This mail has been cc'ed to the coreboot list for getting this patch included into superiotool. If something is wrong with that patch, please Cc: me, as I am not subscribed to the coreboot list. Thanks.
Regards, Michael Karcher