As a followup to the layout usage scenarios I'd like to suggest a structure for hardware restrictions.
struct chipaccess { unsigned int start; unsigned int len; unsigned int perms; };
struct chipaccess chipaccess_flash[32]; struct chipaccess chipaccess_controller[32]; struct chipaccess chipaccess[32]; //merged
start and len should be self-explanatory. perms has two bits: WRITE_ALLOWED and READ_ALLOWED (preferably with a better name).
The chipaccess* arrays MUST (in the RFC 2119 sense of the word) cover the whole flash chip, holes are not allowed. This presents a unique challenge for controller restrictions because those restrictions are detected before the flash chip is known. As such, it is not obvious how to store controller restrictions. One way would be to set chip size as maximum chip size supported by the controller and store the alignment direction (i.e. upper alignment in x86). The chipaccess array for the flash chip itself (chipaccess_flash) would be separate from the chipaccess array for the controller (chipaccess_controller) and after detection of the flash chip both would be merged into chipaccess, taking alignment direction into account.
Regards, Carl-Daniel