On 23.09.2009 13:44, Luc Verhaegen wrote:
On Wed, Sep 23, 2009 at 03:51:29AM +0200, Carl-Daniel Hailfinger wrote:
Switch SST49LF004A/B to block erase, remove the hack which simulated (unsupported) chip erase. Annotate SST49LF004B quirks for TBL#.
Add TEST_OK_PRW which is useful when a PREW chip gets a new erase routine.
Change a few erase function prototypes to use unsigned int instead of int.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
@@ -2148,10 +2151,23 @@ .model_id = SST_49LF004A, .total_size = 512, .page_size = 64 * 1024,
.tested = TEST_OK_PREW,
.tested = TEST_OK_PRW,Can we not consider E as tested here? I believe you got ulf to test both, and with the board enable, even the 64k block erase succeeded.
Well, I didn't have him test the erase functions inside the new eraseblock framework, I only used the old framework. The effect (comands executed) should be identical, though. If you think that is good enough, I'll resend without the PRW change for this chip, but with the added definition of PRW (I need that one for a boatload of other eraseblock changes).
Regards, Carl-Daniel