thanks rudolf for the patch. the chipset/soc itself seems to be named R8610 afaics. i could not find any references to R6030 as a model name. the pci id is 6030h though... i would suggest changing the R6030 strings to R8610 if i am not mistaken.
Maybe R8610/R3210 SoC because the R3210 is non-industrial version. Also VortexCPUs use same chipset enable register.
+static int enable_flash_rdc(struct pci_dev *dev, const char *name)
please also add a suffix to the function name to indicate the model.
OK
i have verified that this enables write cycles as you said. i am (still) not familiar with LPC, but there must be a few other things that are needed to get this chipset to work (at least in non-bifferboard configurations)(?) and afaics we would also like to check a few other things.
LPC is just a "Serial" version of plain old ISA BUS. Which has 16Data lines (wires) and 24? Address wires. Aka "PARALEL type of flashes in flashrom". Plus of course bits (wires) to tell what transacation is on the bus...
there is "FRS" which indicates the flash type boot strap, which could also be X bus. guess X bus does not work transparently, does it?
what about the FRR (flash rom region) registers?
Yeah right maybe we can tell flashrom if it is worth to probe for LPC/FWH or just for "PARALLEL" type flashes.
this does not registers a flashrom programmer!?
It should not? From a programming point of view Paralel/FWH/LPC flashes are detected via reads/writes to the 4G-something memory space with magic sequences like AAA 555 etc... The ROM_CS just tells the SoC to generate chipselect also for writes, effectively making "write protection" disabled. There still could be some flashchip based protection.
I will update the patch to look for LPC/FWH and rename that a bit.
Thanks Rudolf