Re: [flashrom] [PATCH] Refactor MCP SPI detection

[Michael Karcher]

Am Mittwoch, den 17.02.2010, 15:19 +0100 schrieb Carl-Daniel Hailfinger:
> Refactor MCP SPI detection:
> Set supported buses based on ISA bridge reg 0x8a
> Use MCP55 chipset enable only if LPC is detected
> Allow LPC on MCP61
> Eliminate duplicated code where possible

Sounds great.
> /* dev is the ISA bridge. No idea what the stuff below does. */
>    byte = pci_read_byte(dev, 0x8a);
> msg_pdbg("ISA bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 is "
>  "%i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
> msg_pdbg("Guessed flash bus type is %s\n", ((byte >> 5) & 0x3) == 0x2 ?
>  "SPI" : "unknown, probably LPC");
> msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
>  "is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
> switch ((byte >> 5) & 0x3) {
> case 0x0:
> buses_supported = CHIP_BUSTYPE_LPC;
> break;
> case 0x2:
> buses_supported = CHIP_BUSTYPE_SPI;
> break;
> default:
> buses_supported = CHIP_BUSTYPE_UNKNOWN;
> break;
> }
> busname = flashbuses_to_text(buses_supported);
> msg_pdbg("Guessed flash bus type is %s\n", busname);
> free(busname);

Hmm. I think there was a report with 0x1 for LPC, but I have to recheck
that.
> @@ -1088,8 +1097,9 @@
>    /* Look for the SMBus device (SMBus PCI class) */
>    smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
>    if (!smbusdev) {
> msg_perr("ERROR: SMBus device not found. Aborting.\n");
> exit(1);
> msg_perr("ERROR: SMBus device not found.\n");
> buses_supported = CHIP_BUSTYPE_NONE;
> return 1;

We don't need the SMBus device for LPC flashing, unless GPIOs are to be
toggled.
> } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
> msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
> 	 " doesn't support SPI.\n");

The chipset might support SPI, it's just not enabled. Maybe more like
"flash chip apperently is not SPI".
> +/**
> The MCP67 code is guesswork based on cleanroom reverse engineering.
> Due to that, it only reads info and doesn't change any settings.
> It is assumed that LPC chips need the MCP55 code and SPI chips need the

For the MCP61, I have seen the MCP55 code in an board enable.

Regards,
  Michael Karcher