On 10/04/2010 08:58 AM, Carl-Daniel Hailfinger wrote:
Bugfix, 0.9.3 candidate.
SPI write status register (WRSR) may take longer than 100 ms, and it makes sense to poll for completion in 10 ms steps. This patch complements r1115.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
* This may take 50-85 ms in most cases, and some chips apparently
* allow running RDSR only once. Pick an initial delay of 100 ms,
* then wait in 10 ms steps.
programmer_delay(100 * 1000);*/
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
programmer_delay(10 * 1000);
I might say "So, pick an initial delay..." or "Therefore pick an initial delay..." to make it a little clearer. With or without,
Acked-by: Joshua Roys roysjosh@gmail.com