On Tue, 24 May 2011 18:15:52 -0700 Stefan Reinauer stefan.reinauer@coreboot.org wrote:
On 5/23/11 4:23 PM, Stefan Tauner wrote:
Signed-off-by: Stefan Taunerstefan.tauner@student.tuwien.ac.at
chipset_enable.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/chipset_enable.c b/chipset_enable.c index 83b49ad..339c6bb 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, (old& (1<< 0)) ? "en" : "dis"); msg_pdbg("BIOS_CNTL is 0x%x\n", old);
- new = old | 1;
- /*
* Quote from the 6 Series datasheet:* "5: SMM BIOS Write Protect Disable (SMM_BWP)* 1 = BIOS region SMM protection is enabled.* The BIOS Region is not writable unless all processors are in SMM."* In earlier chipsets this bit is reserved. */- if (old& (5<< 1)) {
msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");return -1;You might still be successful doing the write, in case the SMM handler does not enforce the protection, so maybe you should just print a warning but not return here?
in chromium-os you are trying to unset that bit[1], but according to the data sheet this is impossible - it is R/W LO (read/write lock once). and you degraded the warning to dbg level... certainly not suited for upstream, but maybe desirable for chromium(?). have you tested this on a board where SMM_BWP is really set to 1? we may wanna try to write it anyway, but it would be far more interesting if it really works on some chipsets :)
1: http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=comm...