On 16.09.2009 19:07, Stefan Reinauer wrote:
Carl-Daniel Hailfinger wrote:
For optimal partial reflashing, we have to find out which parts of the chip can be written without erase. For that, the only criterion (except a limit on the number of writes for very old chips) is whether the write will only clear bits (set them to 0). If (current&new==new) we can skip the erase. If any bit would have to be set to 1, we need to erase.
Is that sufficient? Ie is it always ok to skip an erase if we're only clearing bits?
It depends on the chip, but given that the following appears in the ICH7 and all later datasheets as absolute flash requirement, I'm positive most current flash chips support it.
----------------- The system BIOS and Intel® Active Management Technology firmware usage models require that the serial flash device support multiple writes (minimum of 512 writes) to a page (256 bytes) without requiring a preceding erase command. -----------------
Flash vendors typically do not mention this in their datasheets, but many BIOSes use flash for parameter storage (heck, even boot date/time logging) since years.
We could restrict this feature to SPI chips only (which are almost guaranteed to be recent enough), but since this patch only provides infrastructure which is not used yet, I'd say the patch is harmless and useful for future partial flashing tries.
Regards, Carl-Daniel