On Thu, 8 Aug 2013 17:15:01 -0700 Wei Hu wei@aristanetworks.com wrote:
Thanks for your great work. I just tested it on AMD Olive Hill, and found a few issues.
- Your patch defaults SPI clock to 16.5 MHz, which didn't work. I
also found none of 22, 33, 100 MHz worked. Only passing -p internal:spispeed="66 MHz" worked.
Please be more specific and/or attach logs. Did the parsing of the value not work or did the actual register changes not work?
- Reading is much faster than my/Carl's patch, but some bits were
incorrect. The speedup must have come from your use of the now longer FIFO, but why is it reading bad values?
Yes, the speedup is from the new FIFO, and I think your problems stems from the 66 MHz.