On 12/30/2011 07:42 AM, Rudolf Marek wrote:
I know bit more about IMC now (I did some research in this direction).
- Do some IO:
I know what it is. It is mailbox interface to the firmware. I described that here: http://www.coreboot.org/AMD_IMC the 0x3e base is set in LDN9 as mailbox base. You should obtain this address from the LDN9.
8.a. Write 0x82 to 0x003E 8.b. Write 0x00 to 0x003F 8.c. Write 0x83 to 0x003E 8.d. Write 0xB4 to 0x003F
Are you sure the 0x00 goes to 82? and B4 goes to 83? While analyzing the firmware I think it was vice-versa. I can recheck this.
I'm fairly certain that is correct for the firmware I'm looking at. 0x00 to 0x82 is not an argument to the "send IMC command" function; it is hard-coded as the second step of the function after checking the IMC present/active bit.
8.e. Write 0x84 to 0x003E 8.f. Write 0x00 to 0x003F 8.g. Write 0x80 to 0x003E 8.h. Write 0x96 to 0x003F
The command is 0x96 which means go to sleep. You should check in 0x82 for 0xfa maybe? It means firmware acked command.
- Set bit 0 in SMBus/ACPI register 79 (00:14.00)
- Set bit 6 in Isa_Misc
Hm the bit6 is documented in SB600 and it shhould be used only if PCI bus is used instead of flash.?
I haven't the foggiest idea. Maybe it was slightly re-tasked to enable writes to "things that aren't internal/BIOS" flash?