On Fri, 25 Jan 2013 01:40:20 -0500 Olivier Langlois olivier@olivierlanglois.net wrote:
Because...
Found chipset "Intel NM10" with PCI ID 8086:27bc. Enabling flash write... … GCS = 0x5d0c60: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (LPC)
The chipset is configured to boot via LPC, hence we do only probe for LPC chips. But your chip is SPI, how does that fit together? The solution of this apparent contradiction is that the superio is translating between LPC on the host side and SPI on the flash side. This is (or was) a common scheme in laptops and one of the reasons why adding support for them is so hard (the superio datasheets are often hard to come by). There is nobody working on adding support for your superio ATM, but Carl-Daniel might have a further developed patch on his harddisk or be able to give you more details about it.
This stuff is so fun! I kid you not, I spent only 1 evening with your tools and I am already seeing dmesg output much differently then yesterday :-)
I will be working on my superio if necessary. Hopefully, I'll be able to get some assistance from you.
Maybe not from me because I am not very familiar with the SPI-LPC-translation of ECs, but you are welcomed to ask (also in the IRC channels #coreboot and #flashrom). First of all you should get the datasheet for the EC. I dont have it, but if you can not google it, someone else in the channel might have it.
That being said, I am a little bit surprised by your diagnostic because I have gathered information as suggested on
http://www.coreboot.org/Laptop
and superiotool has reported:
Found ITE IT8502E/TE/G (id=0x8502, rev=0x1) at 0x4e
Since the first entry in the Laptop survey table on the same page is reporting a successful installation with the same superio, I was hoping that my quest would be trivial. Apparently things aren't that simple
But in that case the flash IS LPC not SPI so no translation is needed. I am not sure if the flash chip is attached to the SB directly or shared with the EC, but the bus difference alone would explain the difference.
So the same superio chip can be configured to work with LPC or SPI flash?
I am not sure about that, but I think so. The main question in general is though if the firmware for the host (usually a BIOS) shares the same flash chip with the firmware for the EC. Since most(?) ECs execute the code directly from flash it is of course not a good idea to erase the flash while the EC fetches instructions from it... :) The host needs to tell the EC to stop executing that code before flashing and reenable it afterwards, see also: http://flashrom.org/Laptops http://flashrom.org/Laptop_enable
For my flash chip, god I think I'll need a magnifying glass. On the chip, it is written:
25Q168VSIC 1120 or maybe it is 25Q16BVSIG 1120
Good light helps tremendously, glasses too. It is most probably B in this case.
I have downloaded the W25Q16BV chip datasheet. Does someone know if it is the same than the W25Q16 supported by flashrom?
Yes it is the same, the differences are not of concern to flashrom. You can pretty much forget the flash chip. It is well supported and wont be a problem for you, but the path between the host and the flash chip is/will.
Carl-Daniel: You are welcome to directly communicate with me if you have information to share concerning the superio chip.
He is very busy usually, but I'll try to poke him a bit regarding this.