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[commit] r655 - trunk
by svn＠flashrom.org 21 Jul '09

21 Jul '09

Author: libv Date: 2009-07-21 03:44:45 +0200 (Tue, 21 Jul 2009) New Revision: 655 Modified: trunk/board_enable.c Log: Board enable for Aopen VKM400 AM-S. This board is a VIA KM400 and VT8237 and IT8705F superio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Scott Johnson <scott(a)gnuveau.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-20 15:21:18 UTC (rev 654) +++ trunk/board_enable.c 2009-07-21 01:44:45 UTC (rev 655) @@ -636,10 +636,10 @@ /** * Suited for: - * - Biostar P4M80-M4: Intel P4 + VIA P4M800 + VT8237 - * - GIGABYTE GA-7VT600: AMD K7 + VIA KT600 + VT8237 + * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF + * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 */ -static int board_biostar_p4m80_m4(const char *name) +static int it8705_rom_write_enable(const char *name) { /* enter IT87xx conf mode */ enter_conf_mode_ite(0x2e); @@ -659,6 +659,24 @@ } /** + * Suited for A-Open vKM400 AM-S: VIA KM400 + VT8237 + IT8705F. + */ +static int board_aopen_vkm400(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); + return -1; + } + + vt823x_set_all_writes_to_lpc(dev); + + return it8705_rom_write_enable(name); +} + +/** * Winbond W83697HF Super I/O + VIA VT8235 southbridge * * Suited for: @@ -896,18 +914,19 @@ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400 AM-s", board_aopen_vkm400}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", board_biostar_p4m80_m4}, + {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, + {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},

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[commit] r654 - trunk
by svn＠flashrom.org 20 Jul '09

20 Jul '09

Author: hailfinger Date: 2009-07-20 17:21:18 +0200 (Mon, 20 Jul 2009) New Revision: 654 Modified: trunk/sst49lfxxxc.c Log: Reset SST49LF016C after erase to exit the read status register mode. Without this, all reads after erase will return 0x80 instead of the real memory contents. Thanks to Michael Melcher for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Michael Melcher <Michael.Melcher82(a)googlemail.com> Modified: trunk/sst49lfxxxc.c =================================================================== --- trunk/sst49lfxxxc.c 2009-07-14 10:26:56 UTC (rev 653) +++ trunk/sst49lfxxxc.c 2009-07-20 15:21:18 UTC (rev 654) @@ -91,6 +91,7 @@ return (-1); } } while (!(status & STATUS_WSMS)); + chip_writeb(RESET, bios); if (check_erased_range(flash, address, sector_size)) { fprintf(stderr, "ERASE FAILED!\n");

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Re: [flashrom] [PATCH] Reset SST49LF016C after erase
by Michael Melcher 20 Jul '09

20 Jul '09

On Mon, Jul 20, 2009 at 04:57:56PM +0200, Carl-Daniel Hailfinger wrote: > Reset SST49LF016C after erase to exit the read status register mode. > Without this, all reads after erase will return 0x80 instead of the real > memory contents. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested and verified. Acked-by Michael Melcher <Michael.Melcher82(a)googlemail.com>

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Info for supermicro x7dw-n
by Michael Melcher 20 Jul '09

20 Jul '09

# ../flashrom/flashrom -w real.rom flashrom v0.9.0-r653 No coreboot table found. Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address 0xffe00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: ERASE FAILED at 0x00000000! Expected=0xff, Read=0x80 ERASE FAILED! ERASE FAILED! Verifying flash... VERIFY FAILED at 0x00000000! Expected=0xf8, Read=0x80

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Re: [flashrom] bad flash ?
by Luc Verhaegen 17 Jul '09

17 Jul '09

On Fri, Jul 17, 2009 at 11:08:18PM +0200, Benjamin BELLEC wrote: > OK, it's now good, I have dl and install from the svn (flashrom > v0.9.0-r653) and it's works fine ! (Previously I used the Fedora > packages, I don't know which svn revision it was). > I'm now using the F8 BIOS ! > You can add this motherboard at the "approved" list. > > Thank you for your help. Great, Luc Verhaegen.

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IBM T30: UNTESTED though READ seems to work.
by Chet Johnson 17 Jul '09

17 Jul '09

I'm going to be slow about this as I don't want to brick my very useful notebook, but the bios read seemed to work successfully. Here is the output from the read operation. This is an old IBM T30 and it pretty much does everything I need as it stands. It does need an upgraded bios to accommodate some updated wifi features. I'm really concerned about performing the write operation. <------------> #sudo flashrom -r original.rom [sudo] password for <name> Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH3-M", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading flash... done. <-------------> This created the following file -rw-r--r-- 1 root root 1048576 2009-07-16 12:52 original.rom More when I ramp up my bravery (foolishness). Chet

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[RFC] More debugging for SB600/SB700 SPI
by Carl-Daniel Hailfinger 17 Jul '09

17 Jul '09

More debugging for SB600/SB700 SPI. Some of this should be conditional on SB700. Anyway, it should be harmless on SB600. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_sb600_sb700_debug/chipset_enable.c =================================================================== --- flashrom-spi_sb600_sb700_debug/chipset_enable.c (Revision 645) +++ flashrom-spi_sb600_sb700_debug/chipset_enable.c (Arbeitskopie) @@ -692,7 +692,9 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); - tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, AbortEnable=%i\n", + tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ @@ -704,6 +706,13 @@ /* The low bits of the SPI base address are used as offset into the mapped page */ sb600_spibar += tmp & 0xfff; + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); Index: flashrom-spi_sb600_sb700_debug/sb600spi.c =================================================================== --- flashrom-spi_sb600_sb700_debug/sb600spi.c (Revision 645) +++ flashrom-spi_sb600_sb700_debug/sb600spi.c (Arbeitskopie) @@ -117,13 +117,13 @@ if (readcnt > 8) { printf("%s, SB600 SPI controller can not receive %d bytes, " - "which is limited with 8 bytes\n", __func__, readcnt); + "it is limited to 8 bytes\n", __func__, readcnt); return 1; } if (writecnt > 8) { - printf("%s, SB600 SPI controller can not sent %d bytes, " - "which is limited with 8 bytes\n", __func__, writecnt); + printf("%s, SB600 SPI controller can not send %d bytes, " + "it is limited to 8 bytes\n", __func__, writecnt); return 1; } @@ -136,6 +136,7 @@ /* Send the write byte to FIFO. */ for (count = 0; count < writecnt; count++, writearr++) { printf_debug(" [%x]", *writearr); + /* FIXME: Can we rely on auto-posting these writes or do we have to issue a read afterwards? */ mmio_writeb(*writearr, sb600_spibar + 0xC); } printf_debug("\n"); @@ -153,19 +154,28 @@ * received byte. Here we just reset the FIFO pointer, skip the * writecnt, is there anyone who have anther method to replace it? */ + printf_debug("The FIFO pointer before reset is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); reset_internal_fifo_pointer(); for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the bytes we send. */ printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("The FIFO pointer after skipping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); } printf_debug("\n"); + printf_debug("The FIFO pointer after reading is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("Dumping everything that's left in the FIFO\n"); + for (count = 0; count < 8; count++) { + cmd = mmio_readb(sb600_spibar + 0xC); + printf_debug("[ %2x]", cmd); + } + printf_debug("The FIFO pointer after dumping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + return 0; } -- http://www.hailfinger.org/

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[PATCH] IT87* SPI unallocated port recovery
by Carl-Daniel Hailfinger 16 Jul '09

16 Jul '09

For Ward Vandewege. IT87* SPI unallocated port recovery. Some coreboot versions forget to set the correct SPI flash port. This in turn causes the port range to stay unallocated and thus not passed through to the device. Since the serial port at 0x3f8 is always enabled, disable the serial port, set its address to zero, then allow the user to set the SPI flash port to 0x3f8. Not intended for merging yet, we need a proper user interface for this How to use this: Boot a kernel with modular serial port, load the serial module and test it with minicom/whatever, run # lspci -nnvvvxxxx >lspci_loaded.txt # superiotool -d >superiotool_loaded.txt Unload the serial module, then run # lspci -nnvvvxxxx >lspci_unloaded.txt # superiotool -d >superiotool_unloaded.txt # flashrom -p it87spi=port=0x3f8 # lspci -nnvvvxxxx >lspci_modified.txt # superiotool -d >superiotool_modified.txt The above sequence needs to happen right after a cold boot and after testing the serial port. The flashrom step will alter some registers until the next cold boot, so running it twice will not yield useful results. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it87spi_emergency_serial_replacement/it87spi.c =================================================================== --- flashrom-it87spi_emergency_serial_replacement/it87spi.c (Revision 653) +++ flashrom-it87spi_emergency_serial_replacement/it87spi.c (Arbeitskopie) @@ -90,7 +90,7 @@ sio_write(port, 0x24, tmp); } printf("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); - /* LDN 0x7, reg 0x64/0x65 */ + /* LDN 0x7 */ sio_write(port, 0x07, 0x7); flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); @@ -102,6 +102,16 @@ if (it87opts && (portpos = strstr(it87opts, "port="))) { portpos += 5; flashport = strtol(portpos, (char **)NULL, 0); + tmp = sio_read(port, 0x2b); + printf("Logical block lock is %02x\n", tmp); + printf("Disabling serial port\n"); + /* LDN 0x1 */ + sio_write(port, 0x07, 0x1); + sio_write(port, 0x30, 0x00); + sio_write(port, 0x60, 0x00); + sio_write(port, 0x61, 0x00); + /* LDN 0x7 */ + sio_write(port, 0x07, 0x7); printf("Forcing serial flash port 0x%04x\n", flashport); sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); -- http://www.hailfinger.org/

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Re: [flashrom] FW: Asus A7V8X needs a board enable.
by Luc Verhaegen 15 Jul '09

15 Jul '09

On Wed, Jul 15, 2009 at 02:02:17AM +0000, Glenn Mueller wrote: > > Sure I can try but is my board or chipset supported at all by your program? Chipset; should be ok. Board; try and find out, but in general, very little boards actually need a board enable. And the board enable usually is the more tangible of issues we can fix :) Our big question here is, can we really support the flash part. And if we can, why didn't it work in the asus a7v8x? Luc Verhaegen.

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Asus A7V8X needs a board enable.
by Luc Verhaegen 14 Jul '09

14 Jul '09

Output from flashrom (from the .rar Glenn provided in a previous mail): Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. Found chip "SST SST49LF040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! Verifying flash... FAILED at 0x00000000! Expected=0x95, Read=0x49 Output from lspci -vnnxxx attached. Suggested ids: Host Bridge KT400: 0x1106, 0x3189, 0x1043, 0x807F ISA Bridge VT8235: 0x1106, 0x3177, 0x1043, 0x808C Board enable requires two things: io(0x370) &= ~0x02; io(PM_IO_Base + 0x2C) |= 0x01; The second scarily translates to: "Enable SMI generation". The first is (according to carldani) most likely an io range for the super io. The superio is probably an it8712, but we do not know for sure, but there is a good chance that this is about dropping a gpio line. We might then get lucky and might not need SMI at all. Glenn, please attach the output of superio -Vd, we cannot proceed without that. Luc Verhaegen.

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