flashrom

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9154 discussions

3COM NIC modification for >128kB flash.
by Marko Kraljevic 23 Aug '09

23 Aug '09

I was playing with modifying the supported 3COM NICs to support larger than 128kB chips. It's been a success so far, and seems to be functioning well with 256kB chips. I haven't tried with 4Mbit/512kB yet, and I don't remember the last time I've seen an 8Mbit [DIP] one. I need to add 28pin DIP and 32pin PLCC sockets yet - that should cover the whole 28F/29F family. It will need some work for the 512kB chips to work. On <512kB chips, pin 1 is either Vpp or /RST, so it has to be high. On the 512k chips, it's A18, so it has to change. For now, I have a pullup on it, and a switch to the bankswitching latch(A18). So when the switch is open, there is no support for 512k chips, but smaller should be fine... I should be able to take care of this in software though. I guess just have it turn the line on at init, and drop it if the probe determines a 512k+ chip. There's only a few bits of the latch used, so the others can be used for general purpose outputs. Right now I have two of the bits tied to LEDs, and the code set to turn on one or the other, depending whether it is in a write or read routine. With some hardware work, off the other outputs - I should be able to switch higher voltages to Vpp for the 27xxxx EPROM, I hope, but that's for another day. Here's a photo of the current card. Not very pretty, but once I get the kinks out, I should be able to get some (much smaller) add-on PCBs made, that will just plug into the stock plug on the NIC. http://electrontube.org/3com_mod/etherlink_mod.jpg Schematic, as is: http://electrontube.org/3com_mod/current_sm.png Schematic (minimalistic version): http://electrontube.org/3com_mod/minimal_sm.png Code changes: http://electrontube.org/3com_mod/3comhack.diff I think for the demo board, Maybe I'll add another decoder and an 8255.. then I'll have 3 bytes of GPIO - for whatever. Schematics, pictures, etc, related to this are CC-SA if you want them for anything. Anyways, any ideas, comments, criticism, etc, would be welcome :-) -Mark Oh yeah - one thing I've noticed, after read, write, or erase, the shutdown routine is called, but it *isn't* called after a probe. (on 3com NICs at least). Is that correct behaviour..? I noticed this, because the latch leaves LEDs on after a probe, but not after R/E/W (the shutdown function clears the bankswitching latch).

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flashrom success with MA790GP-DS4 motherboard.
by Ralph Loader 22 Aug '09

22 Aug '09

Hi, Just reporting successful flash upgrade of bios with flashrom for a board not listed on your website. Board is a Gigabyte MA790GP-DS4H (flashrom output says DS3H), with AMD 790GX / SB750 chipset, and Macronix MX25L8005 rom. Cheers, Ralph. # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "ATI(AMD) SB700", enabling flash write... OK. Found board "GIGABYTE GA-MA78G-DS3H", enabling flash write... Serial flash segment 0xfffe0000-0xffffffff disabled Serial flash segment 0x000e0000-0x000fffff disabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff disabled LPC write to serial flash disabled serial flash pin 29 FAILED! Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. No operations were specified.

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[RFC] Bad chips and boards policy
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

Hi, we desperately need a policy which states the exact requirements for listing a board or flash chip (or programmer) as known broken. This policy should include criteria for retesting as well. The following is what I came up with. Comments appreciated. Each known bad entry: - stores the flashrom revision used for the test - has a link to the mailing list post or mail address of reporter - has a reason why the board/chip does not work (e.g. chip region protection support incomplete, board enable missing, unknown) - is not a specific instance of a problem on another layer (e.g. do not list boards with chipset problems) If a chipset/programmer/flashchip is not supported at all, don't list it. If no effort was made to fix the problem, don't add an entry to the bad list because it wouldn't have any useful information. Do not add entries to the bad list unless the current svn version of flashrom was tested (exceptions apply if current svn is broken). After each release, ask people with broken boards/chipsets/flashchips to retest and update the bad entries with their new results, even if it's just that flashrom still does not work. If the last known state of a board is older than one release (e.g. pre-0.9.0 for the 0.9.1 release) and the reporter does not respond, mark the board as unknown. Reasons for the policy above: - Only track hardware where we have a chance to fix the problem. - Avoid accumulation of stale entries. - Give a better impression (loads of red with some green in between makes us look like incompetent developers). I noticed some press coverage about 0.9.0 where this was a problem. - Motivate people to contribute support for unsupported hardware instead of scaring them away with "doesn't work" if nobody didn't bother to add support yet. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> reported that flashrom didn't recognize her ICH9 LPC controller. According to http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was only used for an engineering sample. No intel doc mentions this ID at all. Anne, could you reply to this mail with "lspci -nnvvvxxx" as attachment? Thanks! This list accepts attachments. If the patch below is what you had in mind and detecting the chipset works for you, please reply with Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> This patch will also appear at the top of http://patchwork.coreboot.org/project/flashrom/list/ so if you have trouble extracting the patch from this mail, you can download it from there. Index: flashrom-ich9_engineeringsample/chipset_enable.c =================================================================== --- flashrom-ich9_engineeringsample/chipset_enable.c (Revision 695) +++ flashrom-ich9_engineeringsample/chipset_enable.c (Arbeitskopie) @@ -1012,6 +1012,7 @@ {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

bouncing this mail... On 21.08.2009 18:41, LE COQ ANNYVONNE wrote: > Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> > > Hi Carl-Daniel, > > It's the modification I've done to accept the ICH9, and it works fine. I just mention "ICH9" instead of "ICH9 Engineering Sample", but I don't think it's very important. > > My problem now is that the opcode 06 is unknown in the opcode table. > To continue my test, I replace one of unused opcode (0B9H) by 06 and it's better. But it's not a good solution... > Then, after that, I can only read, write and erase my flash till A000H. > I think it's because I use the ICH9 in descriptor mode. > I have the following fault: > ERROR at 0x0000a000: Expected=0xff, Read=0x00 > Have you got an idea about this issue ? > Thanks > Anne >

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

bouncing this mail... On 21.08.2009 18:55, LE COQ ANNYVONNE wrote: > Hello, > I have to leave my office now. I'll send the lspci result on Monday. > I'm working on an INTEL demo board called GreenCity: > 2 Nehalem processors, ICH9 + Tylersburg. > The problem is that I'm not able to flash a new BIOS ... > > I'm OK with the patch below, I've tested it on the GreenCity MotherBoard > Have a good week end > Anne > -- http://www.hailfinger.org/

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[commit] r696 - trunk
by svn＠flashrom.org 21 Aug '09

21 Aug '09

Author: hailfinger Date: 2009-08-21 19:26:13 +0200 (Fri, 21 Aug 2009) New Revision: 696 Modified: trunk/chipset_enable.c Log: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> reported that flashrom didn't recognize her ICH9 LPC controller on the Green City Intel Customer Reference Board with ICH9 + Tylersburg Chipset. According to http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was used for engineering samples. No intel doc mentions this ID at all. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-20 18:45:18 UTC (rev 695) +++ trunk/chipset_enable.c 2009-08-21 17:26:13 UTC (rev 696) @@ -1012,6 +1012,7 @@ {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

forwarding to list... -------- Original Message -------- Subject: RE: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables Date: Fri, 21 Aug 2009 18:41:36 +0200 From: LE COQ ANNYVONNE <Annyvonne.Le_Coq(a)alcatel-lucent.fr> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> References: <4A8EB02D.9000607(a)gmx.net> Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Hi Carl-Daniel, It's the modification I've done to accept the ICH9, and it works fine. I just mention "ICH9" instead of "ICH9 Engineering Sample", but I don't think it's very important. My problem now is that the opcode 06 is unknown in the opcode table. To continue my test, I replace one of unused opcode (0B9H) by 06 and it's better. But it's not a good solution... Then, after that, I can only read, write and erase my flash till A000H. I think it's because I use the ICH9 in descriptor mode. I have the following fault: ERROR at 0x0000a000: Expected=0xff, Read=0x00 Have you got an idea about this issue ? Thanks Anne

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bad flash ?
by Benjamin BELLEC 21 Aug '09

21 Aug '09

Hello, I have tried to flash the BIOS of my motherboard. It's a Gigabyte G33M-DS2R (ICH9R + SST SST25VF080B" (1024 KB)). [root@scarabee benjamin]# flashrom --version flashrom v0.9.0 (on Fedora 11 x86_64) Here is the log of the flash (my motherboard was previously in version F7) : flashrom --write ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and I check the BIOS : [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# flashrom --verify ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED at 0x00000000! Expected=0x00, Read=0x01 [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and when I try to erase it : [root@scarabee benjamin]# flashrom --erase Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Erasing flash chip... FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x01 [root@scarabee benjamin]# I can post the entire log (--write --verbose) if you want. What can I do, is my BIOS really write or not ? Can I reboot ? Thanks for your time. Benjamin (from France)

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Non-working board submission: Matsonic MS8308E
by Putlinuxonit 21 Aug '09

21 Aug '09

Hi, I've tested this board with flashrom-0.9.0-r695 as well as superiotool r4424. Also contained are dumps from* #lspci -vvnnxxxx*, *#dmidecode* and *#lshw*. As always, a lot of the info is probably duplicated but is provided for the sake of completeness. I'm available for further testing if required. Bios: AMI > Board: Matsonic MS8308E http://www.motherboard.cz/mb/matsonic/MS8308E.htm > Flash Chip: W49F002UP12B (PLCC) > Chipset: Sis 730 > Enjoy!, Udu E. Ogah .~~~~~~~~~~.

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