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[PATCH] Boards: Add ECS K7S6A.
by Luc Verhaegen 08 Dec '09

08 Dec '09

The nulled second set of subsystem ids is correct, and this seems to be a unique match. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 96d764f..b070960 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1144,6 +1144,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, + {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, "Elitegroup", "K7S6A", it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, -- 1.6.0.2 --UPT3ojh+0CqEDtpF--

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[PATCH] Boards: Tighten up ID match list.
by Luc Verhaegen 08 Dec '09

08 Dec '09

Tighten up board id match table in preparation of upcoming matching changes. Some boards are deliberately broken so that we will receive reports or can remove support later (for instance, for agami aruma, which, probably is no longer available in the wild). * Acorp 6A815EPD: make autodetectable. * Agami Aruma: remove bogus subsystem ids. Due to lacking secondary main id, this match will break soon. * GIGABYTE GA-2761GXDK: Add secondary main id. Subsystem ids are not possible as they are all copies of the main ids. Will still require -m. * GIGABYTE GA-M57SLI-S4: add full set of subsystem ids. Will keep match name for coreboot name matching. * GIGABYTE GA-M61P-S3: Add secondary main id. Remove name match. Probably has good subsystem ids, but no info was found. So deliberately broken match. * GIGABYTE GA-MA790FX-DQ6: pointless name match. * IBM x3455: add full ids, remove name match. * Kontron 986LCD-M: remove full id match as it is bogus. Kontron is an embedded vendor and does not bother with subsystem ids, so make this board name match only. * MSI MS-6590 (KT4 Ultra): remove name match. * MSI MS-7135 (K8N Neo3): add full id set, keep name match for coreboot. * VIA EPIA-N/NL: remove name match. * VIA PC3500G: remove name match. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 55 +++++++++++++++++++++++++++---------------------------- 1 files changed, 27 insertions(+), 28 deletions(-) diff --git a/board_enable.c b/board_enable.c index 96d764f..cfad812 100644 --- a/board_enable.c +++ b/board_enable.c @@ -385,10 +385,23 @@ static int board_asus_p5a(const char *name) return 0; } +/* + * Set GPIO lines in the Broadcom HT-1000 southbridge. + * + * It's not a Super I/O but it uses the same index/data port method. + */ +static int board_hp_dl145_g3_enable(const char *name) +{ + /* GPIO 0 reg from PM regs */ + /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ + sio_mask(0xcd6, 0x44, 0x24, 0x24); + + return 0; +} + static int board_ibm_x3455(const char *name) { - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - /* It's not a Super I/O but it uses the same index/data port method. */ + /* raise gpio13 */ sio_mask(0xcd6, 0x45, 0x20, 0x20); return 0; @@ -476,17 +489,6 @@ static int nvidia_mcp_gpio31_raise(const char *name) return nvidia_mcp_gpio_set(0x31, 0x01); } -static int board_hp_dl145_g3_enable(const char *name) -{ - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - /* GPIO 0 reg from PM regs */ - /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ - /* It's not a Super I/O but it uses the same index/data port method. */ - sio_mask(0xcd6, 0x44, 0x24, 0x24); - - return 0; -} - /** * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. */ @@ -1127,9 +1129,9 @@ static int board_asus_a7v600x(const char *name) struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, - {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, - {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, + {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, @@ -1148,28 +1150,25 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, - {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, + {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, - {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, - {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, + {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, + {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash}, - /* SB600 LPC, RD790 North. Neither are specific to the GA-MA790FX-DQ6. The coreboot ID is here to be able to trigger the board enable more easily. */ - {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, "gigabyte", "ma790fx-dq6", "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, + {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable}, - {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM", "x3455", board_ibm_x3455}, + {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, "IBM", "x3455", board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e}, - /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ - {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, - {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu}, - {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, - {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, @@ -1177,9 +1176,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */ + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n}, {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, - {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash}, + {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ }; -- 1.6.0.2 --8P1HSweYDcXXzwPJ--

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[PATCH] Chipset: remove sis630 chipset enable for sis540.
by Luc Verhaegen 07 Dec '09

07 Dec '09

SiS630 chipset enable is equal to sis540 plus superio "poking". Superio poking equals IT8705F flash write enable, which is currently dealt with on a board by board basis in board_enable.c. Not all 630 and newer based boards come with it8705/sis950 superios. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 2 + chipset_enable.c | 68 +++++++++++++---------------------------------------- 2 files changed, 19 insertions(+), 51 deletions(-) diff --git a/board_enable.c b/board_enable.c index 96d764f..fa50871 100644 --- a/board_enable.c +++ b/board_enable.c @@ -814,6 +814,8 @@ static int board_kontron_986lcd_m(const char *name) * Suited for: * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 + * + * SIS950 superio probably requires the same flash write enable. */ static int it8705_rom_write_enable(const char *name) { diff --git a/chipset_enable.c b/chipset_enable.c index 3be7763..b9fa474 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -225,40 +225,6 @@ static int enable_flash_sis540(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_sis630(struct pci_dev *dev, const char *name) -{ - uint8_t tmp; - uint16_t siobase; - int ret; - - ret = enable_flash_sis540(dev, name); - - /* The same thing on SiS 950 Super I/O side... */ - - /* First probe for Super I/O on config port 0x2e. */ - siobase = 0x2e; - enter_conf_mode_ite(siobase); - - if (INB(siobase + 1) != 0x87) { - /* If that failed, try config port 0x4e. */ - siobase = 0x4e; - enter_conf_mode_ite(siobase); - if (INB(siobase + 1) != 0x87) { - printf("Can not find SuperI/O.\n"); - return -1; - } - } - - /* Enable flash mapping. Works for most old ITE style SuperI/O. */ - tmp = sio_read(siobase, 0x24); - tmp |= 0xfc; - sio_write(siobase, 0x24, tmp); - - exit_conf_mode_ite(siobase); - - return ret; -} - /* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm @@ -1169,23 +1135,23 @@ const struct penable chipset_enables[] = { {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, - {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis630}, - {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis630}, - {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis630}, - {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis630}, - {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis630}, - {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis630}, - {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis630}, - {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis630}, - {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis630}, - {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis630}, - {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis630}, - {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis630}, - {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis630}, - {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis630}, - {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis630}, - {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis630}, - {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis630}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, + {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, + {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, + {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, + {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, -- 1.6.0.2 --GvXjxJ+pjyke8COw--

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[PATCH] Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.
by Luc Verhaegen 06 Dec '09

06 Dec '09

Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 181 ++++++++++++++---------------------------------------- chipset_enable.c | 7 ++ 2 files changed, 53 insertions(+), 135 deletions(-) diff --git a/board_enable.c b/board_enable.c index 96d764f..a6c5257 100644 --- a/board_enable.c +++ b/board_enable.c @@ -162,26 +162,40 @@ static void w836xx_memw_enable(uint16_t port) } /** - * Common routine for several VT823x based boards. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. */ -static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev) +static int w836xx_memw_enable_2e(const char *name) { - uint8_t val; + w836xx_memw_enable(0x2E); - /* All memory cycles, not just ROM ones, go to LPC. */ - val = pci_read_byte(dev, 0x59); - val &= ~0x80; - pci_write_byte(dev, 0x59, val); + return 0; } + /** * VT823x: Set one of the GPIO pins. */ -static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) +static int via_vt823x_gpio_set(uint8_t gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t val, bit; + dev = pci_dev_find_vendorclass(0x1106, 0x0601); + switch (dev->device_id) { + case 0x3177: /* VT8235 */ + case 0x3227: /* VT8237R */ + break; + default: + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + return -1; + } + if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); @@ -195,7 +209,7 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) } else { fprintf(stderr, "\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); - return; + return -1; } /* Now raise/drop the GPIO line itself. */ @@ -210,103 +224,44 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) else val &= ~bit; OUTB(val, base + 0x4D); -} - -/** - * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. - * - * We don't need to do this when using coreboot, GPIO15 is never lowered there. - */ -static int board_via_epia_m(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - - /* GPIO15 is connected to write protect. */ - vt823x_gpio_set(dev, 15, 1); return 0; } /** - * Suited for: - * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. + * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. + * + * We don't need to do this for EPIA M when using coreboot, GPIO15 is never + * lowered there. */ -static int board_asus_a7v8x_mx(const char *name) +static int via_vt823x_gpio15_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - w836xx_memw_enable(0x2E); - - return 0; -} - -/** - * Suited for VIAs EPIA SP and EPIA CN. - */ -static int board_via_epia_sp(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return 0; + return via_vt823x_gpio_set(15, 1); } /** * Suited for VIAs EPIA N & NL. */ -static int board_via_epia_n(const char *name) +static int via_vt823x_gpio9_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - /* All memory cycles, not just ROM ones, go to LPC */ - vt823x_set_all_writes_to_lpc(dev); - - /* GPIO9 -> output */ - vt823x_gpio_set(dev, 9, 1); - - return 0; + return via_vt823x_gpio_set(9, 1); } /** + * Winbond W83697HF Super I/O + VIA VT8235 southbridge + * * Suited for: - * - EPoX EP-8K5A2: VIA KT333 + VT8235. - * - Albatron PM266A Pro: VIA P4M266A + VT8235. - * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ -static int w836xx_memw_enable_2e(const char *name) +static int board_msi_kt4v(const char *name) { + int ret; + + ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E); - return 0; + return ret; } /** @@ -814,6 +769,7 @@ static int board_kontron_986lcd_m(const char *name) * Suited for: * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 + * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. */ static int it8705_rom_write_enable(const char *name) { @@ -835,49 +791,6 @@ static int it8705_rom_write_enable(const char *name) } /** - * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - */ -static int board_aopen_vkm400(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return it8705_rom_write_enable(name); -} - -/** - * Winbond W83697HF Super I/O + VIA VT8235 southbridge - * - * Suited for: - * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 - * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - */ -static int board_msi_kt4v(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - vt823x_gpio_set(dev, 12, 1); - w836xx_memw_enable(0x2E); - - return 0; -} - -/** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int board_soyo_sy_7vca(const char *name) @@ -1131,12 +1044,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, @@ -1174,11 +1087,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */ - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise}, /* TODO: remove coreboot ids */ {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ diff --git a/chipset_enable.c b/chipset_enable.c index 3be7763..1b16f65 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -656,6 +656,13 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return -1; } + if (dev->device_id == 0x3227) { /* VT8237 */ + /* All memory cycles, not just ROM ones, go to LPC. */ + val = pci_read_byte(dev, 0x59); + val &= ~0x80; + pci_write_byte(dev, 0x59, val); + } + return 0; } -- 1.6.0.2 --fUYQa+Pmc3FrFX/N--

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Board ASUS TUSL2-C not working
by Moritz Augsburger 06 Dec '09

06 Dec '09

Hi, I first didn't realize this is a mailing list, so my posts got stuck somewhere waiting for moderation - because of that here is a repost. Moritz

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Board ASUS TUSL2-C not working
by Moritz Augsburger 06 Dec '09

06 Dec '09

Hi, I first didn't realize this is a mailing list, so my posts got stuck somewhere waiting for moderation - because of that here is a repost. Moritz

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Board not working
by Moritz Augsburger 06 Dec '09

06 Dec '09

Hi, as requested all the data, for program outputs see the attached files. Board: ASUS TUSL2-C Flash Util http://dlcdnas.asus.com/pub/ASUS/mb/flash/aflash221.zip BIOS http://dlcdnas.asus.com/pub/ASUS/mb/sock370/815ep/tusl2-c/1014tc001.zip Information according to lshw *-core description: Motherboard product: TUSL2-C vendor: ASUSTeK Computer INC. physical id: 0 version: REV 1.xx serial: xxxxxxxxxxx *-firmware description: BIOS vendor: Award Software, Inc. physical id: 0 version: ASUS TUSL2-C ACPI BIOS Revision 1007.A (06/08/2001) size: 64KiB capacity: 192KiB capabilities: pci pnp apm upgrade shadowing escd cdboot bootselect socketedrom edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb agp ls120boot zipboot Couldn't find any revision printed on the board/a sticker. Greets Moritz

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flash write failed to SST49LF160C on jetway J7F2
by maarten van es 06 Dec '09

06 Dec '09

Hi all, I got an "sector erase FAILED, status =0x82" message when trying to flash a chip. This is not the original bios chip, so I am safe in that regard, but I would still like to get this chip to work. Could the chip be faulty or does anyone have suggestions why it might not work? some info: motherboard: Jetway J7F2 (VIA VT8237) (comes with a 4MBit chip) flash chip: SST49LF160C (16MBit) reading works fine (at least, no errors) flash write protect is disabled in BIOS setup, there are no (documented) jumpers for flash write protection Interestingly (?), if I run flashrom multiple times, it fails at different addresses. I have not tried flashing the original bios chip with a copy of itself, but would prefer to keep that chip in a known good state. Maarten

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Re: [flashrom] [commit] r759 - trunk
by Luc Verhaegen 06 Dec '09

06 Dec '09

On Sun, Nov 15, 2009 at 06:13:29PM +0100, svn(a)flashrom.org wrote: > Author: hailfinger > Date: 2009-11-15 18:13:29 +0100 (Sun, 15 Nov 2009) > New Revision: 759 > static int enable_flash_sis630(struct pci_dev *dev, const char *name) > /* First probe for Super I/O on config port 0x2e. */ > - OUTB(0x87, 0x2e); > - OUTB(0x01, 0x2e); > - OUTB(0x55, 0x2e); > - OUTB(0x55, 0x2e); > + siobase = 0x2e; > + enter_conf_mode_ite(siobase); > > - if (INB(0x2f) != 0x87) { > + if (INB(siobase + 1) != 0x87) { > /* If that failed, try config port 0x4e. */ > - OUTB(0x87, 0x4e); > - OUTB(0x01, 0x4e); > - OUTB(0x55, 0x4e); > - OUTB(0xaa, 0x4e); > - if (INB(0x4f) != 0x87) { > - printf("Can not access SiS 950\n"); > + siobase = 0x4e; > + enter_conf_mode_ite(siobase); > + if (INB(siobase + 1) != 0x87) { > + printf("Can not find SuperI/O.\n"); > return -1; > } > - OUTB(0x24, 0x4e); > - b = INB(0x4f) | 0xfc; > - OUTB(0x24, 0x4e); > - OUTB(b, 0x4f); > - OUTB(0x02, 0x4e); > - OUTB(0x02, 0x4f); > } > > - OUTB(0x24, 0x2e); > - printf_debug("2f is %#x\n", INB(0x2f)); > - b = INB(0x2f) | 0xfc; > - OUTB(0x24, 0x2e); > - OUTB(b, 0x2f); > + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ > + tmp = sio_read(siobase, 0x24); > + tmp |= 0xfc; > + sio_write(siobase, 0x24, tmp); > > - OUTB(0x02, 0x2e); > - OUTB(0x02, 0x2f); > + exit_conf_mode_ite(siobase); > > - return 0; > + return ret; > } Superio code in the chipset enable... Needs to be moved out, some VT823x based boards also require the same stuff. Maybe we need a superio_enable.c, which not only sets bits like that (some winbonds need the same) but which also contain the gpio specific routines. Luc Verhaegen.

1 2

I have problem making latest flashrom
by guy lacroix 05 Dec '09

05 Dec '09

Dear Sirs, i learned how to install libpcidev,(zlib1g-dev), libftdi-dev. That is done. I did not install subversion. Source code folder flashrom-0.9.1 is in /home/guy and there I type make flashrom. Then I get output as in included error make flashrom. When I type sudo make flasrom I get guy@asus-p4b:~/flashrom-0.9.1$ sudo make flashrom [sudo] password for guy: Checking for a C compiler... found. Checking for FTDI support... found. cc -Os -Wall -Werror -D'SERPROG_SUPPORT=1' -D'FT2232_SPI_SUPPORT=1' -D'FLASHROM_VERSION="0.9.1-r710"' -o physmap.o -c physmap.c cc1: warnings being treated as errors physmap.c: In function ‘rdmsr’: physmap.c:146: error: dereferencing type-punned pointer will break strict-aliasing rules make: *** [physmap.o] Fout 1 guy@asus-p4b:~/flashrom-0.9.1$ Thanks for your help! I'm learing something this way.

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