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[commit] r814 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: hailfinger Date: 2009-12-23 00:54:10 +0100 (Wed, 23 Dec 2009) New Revision: 814 Modified: trunk/spi.c Log: Add a few FIXME comments to the generic SPI code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-12-22 23:42:04 UTC (rev 813) +++ trunk/spi.c 2009-12-22 23:54:10 UTC (rev 814) @@ -807,6 +807,7 @@ int result; struct spi_command cmds[] = { { + /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ .writecnt = JEDEC_EWSR_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_EWSR }, .readcnt = 0, @@ -1059,6 +1060,7 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } + /* FIXME: This will fail on ICH/VIA SPI. */ result = spi_write_enable(); if (result) return result;

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[PATCH] Refactor ITE SuperI/O detection/access
by Carl-Daniel Hailfinger 22 Dec '09

22 Dec '09

Refactor ITE SuperI/O detection/access. The new code reduces duplications and paves the way for generic SuperI/O detection. Additional cost: We enter/exit the SuperI/O configuration mode twice. Once for detecting which SuperI/O it is, and once for actually changing the settings. Additional benefit: This has the potential of allowing some sort of primitive laptop detection (by way of checking whether an EC or a simple SuperI/O is present). I have added a call to a not yet implemented Winbond SuperI/O detection function inside #if 0 to make extension more straighforward. This affects most SiS chipsets and IT87 SPI translation, so tests in verbose mode would be appreciated. In theory, functionality should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-superio_ite_refactor/flash.h =================================================================== --- flashrom-superio_ite_refactor/flash.h (Revision 761) +++ flashrom-superio_ite_refactor/flash.h (Arbeitskopie) @@ -388,6 +388,11 @@ #endif /* internal.c */ +struct superio { + uint16_t vendor; + uint16_t port; + uint16_t model; +}; struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -395,6 +400,7 @@ uint16_t card_vendor, uint16_t card_device); void get_io_perms(void); void release_io_perms(void); +struct superio probe_superio(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -611,9 +617,12 @@ int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ +#define SUPERIO_VENDOR_NONE 0x0 +#define SUPERIO_VENDOR_ITE 0x1 extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); +struct superio probe_superio_ite(void); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-superio_ite_refactor/it87spi.c =================================================================== --- flashrom-superio_ite_refactor/it87spi.c (Revision 761) +++ flashrom-superio_ite_refactor/it87spi.c (Arbeitskopie) @@ -54,19 +54,56 @@ sio_write(port, 0x02, 0x02); } -static uint16_t find_ite_spi_flash_port(uint16_t port) +uint16_t probe_id_ite(uint16_t port) { - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t id, flashport = 0; + uint16_t id; enter_conf_mode_ite(port); - id = sio_read(port, CHIP_ID_BYTE1_REG) << 8; id |= sio_read(port, CHIP_ID_BYTE2_REG); + exit_conf_mode_ite(port); - /* TODO: Handle more IT87xx if they support flash translation */ - if (0x8716 == id || 0x8718 == id) { + return id; +} + +struct superio probe_superio_ite(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + i++; + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite(ret.port); + switch (ret.model >> 8) { + case 0x82: + case 0x86: + case 0x87: + printf_debug("Found ITE SuperI/O, id %04hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + switch (id) { + case 0x8716: + case 0x8718: + enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; printf("Serial flash segment 0x%08x-0x%08x %sabled\n", @@ -105,18 +142,26 @@ sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); } + exit_conf_mode_ite(port); + break; + /* TODO: Handle more IT87xx if they support flash translation */ + default: + printf("SuperI/O ID %04hx is not on the controller list.\n", id); } - exit_conf_mode_ite(port); return flashport; } int it87spi_common_init(void) { - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1); - if (!it8716f_flashport) - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2); + struct superio superio; + superio = probe_superio_ite(); + if (superio.vendor == SUPERIO_VENDOR_NONE) + return 1; + + it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); + if (it8716f_flashport) spi_controller = SPI_CONTROLLER_IT87XX; Index: flashrom-superio_ite_refactor/chipset_enable.c =================================================================== --- flashrom-superio_ite_refactor/chipset_enable.c (Revision 761) +++ flashrom-superio_ite_refactor/chipset_enable.c (Arbeitskopie) @@ -225,37 +225,40 @@ return ret; } -static int enable_flash_sis630(struct pci_dev *dev, const char *name) +static int enable_flash_decode_superio(void) { + int ret; uint8_t tmp; - uint16_t siobase; - int ret; + struct superio superio; - ret = enable_flash_sis540(dev, name); - - /* The same thing on SiS 950 Super I/O side... */ - - /* First probe for Super I/O on config port 0x2e. */ - siobase = 0x2e; - enter_conf_mode_ite(siobase); - - if (INB(siobase + 1) != 0x87) { - /* If that failed, try config port 0x4e. */ - siobase = 0x4e; - enter_conf_mode_ite(siobase); - if (INB(siobase + 1) != 0x87) { - printf("Can not find SuperI/O.\n"); - return -1; - } + superio = probe_superio(); + switch (superio.vendor) { + case SUPERIO_VENDOR_NONE: + ret = -1; + break; + case SUPERIO_VENDOR_ITE: + enter_conf_mode_ite(superio.port); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(superio.port, 0x24); + tmp |= 0xfc; + sio_write(superio.port, 0x24, tmp); + exit_conf_mode_ite(superio.port); + ret = 0; + break; + default: + printf_debug("Unhandled SuperI/O type!\n"); + ret = -1; + break; } + return ret; +} - /* Enable flash mapping. Works for most old ITE style SuperI/O. */ - tmp = sio_read(siobase, 0x24); - tmp |= 0xfc; - sio_write(siobase, 0x24, tmp); +static int enable_flash_sis630(struct pci_dev *dev, const char *name) +{ + int ret; - exit_conf_mode_ite(siobase); - + ret = enable_flash_sis540(dev, name); + ret |= enable_flash_decode_superio(); return ret; } Index: flashrom-superio_ite_refactor/internal.c =================================================================== --- flashrom-superio_ite_refactor/internal.c (Revision 761) +++ flashrom-superio_ite_refactor/internal.c (Arbeitskopie) @@ -122,6 +122,18 @@ #endif } +struct superio probe_superio(void) +{ + struct superio superio; + + superio = probe_superio_ite(); +#if 0 /* Winbond SuperI/O code is not yet available. */ + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_winbond(); +#endif + return superio; +} + int internal_init(void) { int ret = 0; -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

3 8

[commit] r813 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: hailfinger Date: 2009-12-23 00:42:04 +0100 (Wed, 23 Dec 2009) New Revision: 813 Modified: trunk/board_enable.c trunk/flash.h trunk/internal.c trunk/it87spi.c Log: SuperI/O detection now happens unconditionally and before the chipset enable. We could run it after chipset enable, but it definitely has to happen before board enable because the board enable usually accesses the SuperI/O. With this patch, it is possible to add a struct superio to the board enable table for more accurate matching in case subsystem IDs are ambiguous. This patch focuses on the generic infrastructure aspect and on support for IT8712F/IT8716F. Thanks go to Adrian Glaubitz and Ward Vandewege for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Adrian Glaubitz <glaubitz(a)physik.fu-berlin.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-22 22:15:33 UTC (rev 812) +++ trunk/board_enable.c 2009-12-22 23:42:04 UTC (rev 813) @@ -66,6 +66,35 @@ OUTB(tmp | (data & mask), port + 1); } +/* Not used yet. */ +#if 0 +static int enable_flash_decode_superio(void) +{ + int ret; + uint8_t tmp; + + switch (superio.vendor) { + case SUPERIO_VENDOR_NONE: + ret = -1; + break; + case SUPERIO_VENDOR_ITE: + enter_conf_mode_ite(superio.port); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(superio.port, 0x24); + tmp |= 0xfc; + sio_write(superio.port, 0x24, tmp); + exit_conf_mode_ite(superio.port); + ret = 0; + break; + default: + printf_debug("Unhandled SuperI/O type!\n"); + ret = -1; + break; + } + return ret; +} +#endif + /** * Winbond W83627HF: Raise GPIO24. * Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-12-22 22:15:33 UTC (rev 812) +++ trunk/flash.h 2009-12-22 23:42:04 UTC (rev 813) @@ -331,6 +331,14 @@ /* internal.c */ #if NEED_PCI == 1 +struct superio { + uint16_t vendor; + uint16_t port; + uint16_t model; +}; +extern struct superio superio; +#define SUPERIO_VENDOR_NONE 0x0 +#define SUPERIO_VENDOR_ITE 0x1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -340,6 +348,7 @@ void get_io_perms(void); void release_io_perms(void); #if INTERNAL_SUPPORT == 1 +void probe_superio(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -544,6 +553,7 @@ extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); +struct superio probe_superio_ite(void); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-12-22 22:15:33 UTC (rev 812) +++ trunk/internal.c 2009-12-22 23:42:04 UTC (rev 813) @@ -125,6 +125,17 @@ } #if INTERNAL_SUPPORT == 1 +struct superio superio = {}; + +void probe_superio(void) +{ + superio = probe_superio_ite(); +#if 0 /* Winbond SuperI/O code is not yet available. */ + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_winbond(); +#endif +} + int internal_init(void) { int ret = 0; @@ -142,6 +153,9 @@ */ coreboot_init(); + /* Probe for the SuperI/O chip and fill global struct superio. */ + probe_superio(); + /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-12-22 22:15:33 UTC (rev 812) +++ trunk/it87spi.c 2009-12-22 23:42:04 UTC (rev 813) @@ -54,19 +54,55 @@ sio_write(port, 0x02, 0x02); } -static uint16_t find_ite_spi_flash_port(uint16_t port) +uint16_t probe_id_ite(uint16_t port) { - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t id, flashport = 0; + uint16_t id; enter_conf_mode_ite(port); - id = sio_read(port, CHIP_ID_BYTE1_REG) << 8; id |= sio_read(port, CHIP_ID_BYTE2_REG); + exit_conf_mode_ite(port); - /* TODO: Handle more IT87xx if they support flash translation */ - if (0x8716 == id || 0x8718 == id) { + return id; +} + +struct superio probe_superio_ite(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite(ret.port); + switch (ret.model >> 8) { + case 0x82: + case 0x86: + case 0x87: + printf_debug("Found ITE SuperI/O, id %04hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + switch (id) { + case 0x8716: + case 0x8718: + enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; printf("Serial flash segment 0x%08x-0x%08x %sabled\n", @@ -105,17 +141,21 @@ sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); } + exit_conf_mode_ite(port); + break; + /* TODO: Handle more IT87xx if they support flash translation */ + default: + printf("SuperI/O ID %04hx is not on the controller list.\n", id); } - exit_conf_mode_ite(port); return flashport; } int it87spi_common_init(void) { - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1); + if (superio.vendor != SUPERIO_VENDOR_ITE) + return 1; - if (!it8716f_flashport) - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2); + it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); if (it8716f_flashport) spi_controller = SPI_CONTROLLER_IT87XX; @@ -129,6 +169,8 @@ int ret; get_io_perms(); + /* Probe for the SuperI/O chip and fill global struct superio. */ + probe_superio(); ret = it87spi_common_init(); if (!ret) { buses_supported = CHIP_BUSTYPE_SPI;

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[PATCH] Convert flashchips to use struct eraseblock - AMD
by Sean Nelson 22 Dec '09

22 Dec '09

After asking if page_size was equivalent to a chip's sector size, while I was verifying datasheets and our flashchip support table, Carl-Daniel suggested I convert all chips to use struct eraseblock. Starting from the top of the file and working down, this is the first of many patches. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 6

[commit] r812 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: hailfinger Date: 2009-12-22 23:15:33 +0100 (Tue, 22 Dec 2009) New Revision: 812 Modified: trunk/am29f040b.c trunk/chipdrivers.h trunk/flashchips.c trunk/jedec.c Log: Convert the following chips to use struct eraseblock: Am29F010A/B Am29F002(N)BB Am29F002(N)BT Am29F016D Am29F040B Am29F080B Am29LV040B Am29LV081B A29040B Pm29F002T Pm29F002B Change function signature of Am29 erase functions and JEDEC chip erase to be usable with block_erasers. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/am29f040b.c =================================================================== --- trunk/am29f040b.c 2009-12-22 13:04:53 UTC (rev 811) +++ trunk/am29f040b.c 2009-12-22 22:15:33 UTC (rev 812) @@ -22,9 +22,8 @@ /* FIMXE: check that the 2 second delay is really needed. Use erase_sector_jedec if not? */ -static int erase_sector_29f040b(struct flashchip *flash, unsigned long address) +int erase_sector_29f040b(struct flashchip *flash, unsigned int address, unsigned int blocklen) { - int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; chip_writeb(0xAA, bios + 0x555); @@ -39,13 +38,24 @@ /* wait for Toggle bit ready */ toggle_ready_jedec(bios + address); - if (check_erased_range(flash, address, page_size)) { + if (check_erased_range(flash, address, blocklen)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } return 0; } +/* erase chip with block_erase() prototype */ +int erase_chip_29f040b(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); + return -1; + } + return erase_29f040b(flash); +} + /* FIXME: use write_sector_jedec? */ static int write_sector_29f040b(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size) @@ -127,7 +137,7 @@ printf("Programming page "); for (i = 0; i < total_size / page_size; i++) { /* erase the page before programming */ - if (erase_sector_29f040b(flash, i * page_size)) { + if (erase_sector_29f040b(flash, i * page_size, page_size)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } Modified: trunk/chipdrivers.h =================================================================== --- trunk/chipdrivers.h 2009-12-22 13:04:53 UTC (rev 811) +++ trunk/chipdrivers.h 2009-12-22 22:15:33 UTC (rev 812) @@ -60,6 +60,8 @@ /* am29f040b.c */ int probe_29f040b(struct flashchip *flash); int erase_29f040b(struct flashchip *flash); +int erase_sector_29f040b(struct flashchip *flash, unsigned int blockaddr, unsigned int blocksize); +int erase_chip_29f040b(struct flashchip *flash, unsigned int blockaddr, unsigned int blocksize); int write_29f040b(struct flashchip *flash, uint8_t *buf); /* pm29f002.c */ @@ -83,6 +85,7 @@ int write_jedec_1(struct flashchip *flash, uint8_t *buf); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); +int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size); Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-12-22 13:04:53 UTC (rev 811) +++ trunk/flashchips.c 2009-12-22 22:15:33 UTC (rev 812) @@ -61,10 +61,20 @@ .model_id = AM_29F010B, /* Same as Am29F010A */ .total_size = 128, .page_size = 16 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_29f040b, .probe_timing = TIMING_ZERO, - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {16 * 1024, 8} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_pm29f002, .read = read_memmapped, }, @@ -80,7 +90,22 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, .write = write_jedec_1, .read = read_memmapped, }, @@ -93,10 +118,25 @@ .model_id = AM_29F002BT, .total_size = 256, .page_size = 256, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, .write = write_jedec_1, .read = read_memmapped, }, @@ -107,12 +147,22 @@ .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F016D, - .total_size = 2048, + .total_size = 2 * 1024, .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f040b, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -125,10 +175,20 @@ .model_id = AM_29F040B, .total_size = 512, .page_size = 64 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_29f040b, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -144,7 +204,17 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -160,7 +230,17 @@ .tested = TEST_UNTESTED, .probe = probe_29f040b, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -176,7 +256,17 @@ .tested = TEST_UNTESTED, .probe = probe_29f040b, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -770,7 +860,17 @@ .tested = TEST_OK_PR, .probe = probe_29f040b, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_29f040b, .read = read_memmapped, }, @@ -1768,32 +1868,62 @@ { .vendor = "PMC", - .name = "Pm29F0002T", + .name = "Pm29F002T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_29F002T, .total_size = 256, - .page_size = 8192, - .tested = TEST_OK_PREW, + .page_size = 8 * 1024, + .tested = TEST_OK_PRW, .probe = probe_29f040b, .probe_timing = TIMING_FIXME, - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_pm29f002, .read = read_memmapped, }, { .vendor = "PMC", - .name = "Pm29F0002B", + .name = "Pm29F002B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_29F002B, .total_size = 256, - .page_size = 8192, + .page_size = 8 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f040b, .probe_timing = TIMING_FIXME, - .erase = erase_29f040b, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 1}, + }, + .block_erase = erase_sector_29f040b, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_29f040b, + }, + }, .write = write_pm29f002, .read = read_memmapped, }, @@ -1949,7 +2079,7 @@ .manufacture_id = SST_ID, .model_id = SST_25VF040_REMS, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, .probe_timing = TIMING_ZERO, @@ -1965,7 +2095,7 @@ .manufacture_id = SST_ID, .model_id = SST_25VF040B_REMS, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, .probe_timing = TIMING_ZERO, @@ -3139,7 +3269,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V040A, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, @@ -3155,7 +3285,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V040B, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PR | TEST_BAD_ERASE | TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = 10, @@ -3171,7 +3301,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V040C, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_w39v040c, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v040c.c) */ @@ -3187,7 +3317,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V040FA, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, @@ -3203,7 +3333,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V080A, .total_size = 1024, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, @@ -3267,7 +3397,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V080FA, .total_size = 1024, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_winbond_fwhub, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v080fa.c) */ @@ -3283,7 +3413,7 @@ .manufacture_id = WINBOND_ID, .model_id = W_39V080FA_DM, .total_size = 512, - .page_size = 64*1024, + .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_winbond_fwhub, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v080fa.c) */ Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-12-22 13:04:53 UTC (rev 811) +++ trunk/jedec.c 2009-12-22 22:15:33 UTC (rev 812) @@ -245,6 +245,17 @@ return 0; } +/* erase chip with block_erase() prototype */ +int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr, unsigned int blocksize) +{ + if ((addr != 0) || (blocksize != flash->total_size * 1024)) { + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); + return -1; + } + return erase_chip_jedec(flash); +} + int erase_chip_jedec(struct flashchip *flash) { int total_size = flash->total_size * 1024;

1 0

Bios Update
by Bruno Vaillancourt 22 Dec '09

22 Dec '09

Trying to flash my bios and I get this message any idea what is the problem bruno@bruno-desktop:~/Desktop/BiosUpdate$ sudo flashrom -w A8N321303.ROM flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V080A" (1024 KB, LPC) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000008! Expected=0xff, Read=0x10, failed byte count from 0x00000000-0x000fffff: 0x8b465 ERASE FAILED! ERASE FAILED! FAILED!

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[commit] r811 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: hailfinger Date: 2009-12-22 14:04:53 +0100 (Tue, 22 Dec 2009) New Revision: 811 Modified: trunk/flash.h Log: Clarify comment about how to enter chip erase functions in struct block_eraser. Reported by Sean Nelson. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-12-22 13:04:13 UTC (rev 810) +++ trunk/flash.h 2009-12-22 13:04:53 UTC (rev 811) @@ -174,8 +174,8 @@ int (*erase) (struct flashchip *flash); /* - * Erase blocks and associated erase function. The default entry is a - * chip-sized virtual block together with the chip erase function. + * Erase blocks and associated erase function. Any chip erase function + * is stored as chip-sized virtual block together with said function. */ struct block_eraser { struct eraseblock{

1 0

[commit] r810 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: libv Date: 2009-12-22 14:04:13 +0100 (Tue, 22 Dec 2009) New Revision: 810 Modified: trunk/board_enable.c Log: Boards: Fix several issues with nvidia_mcp_gpio_set. - CK804, MCP04, MCP2 use the isa bridges.. - Newer nvidia mcp's do use the smbus controllers (Found by Michael Karcher). - gpio line check breaks EPoX EP-8RDA3+, and should be wider. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-21 15:30:46 UTC (rev 809) +++ trunk/board_enable.c 2009-12-22 13:04:13 UTC (rev 810) @@ -440,20 +440,30 @@ uint16_t base; uint8_t tmp; - if ((gpio < 0) || (gpio > 31)) { + if ((gpio < 0) || (gpio >= 0x40)) { fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + /* First, check the ISA Bridge */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: - fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); + /* Newer MCPs use the SMBus Controller */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0264: /* MCP51 */ + break; + default: + fprintf(stderr, + "\nERROR: no nVidia LPC/SMBus controller found.\n"); return -1; + } + break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */

1 0

Re: [flashrom] Is K7S6A supported by flashrom?
by Carl-Daniel Hailfinger 22 Dec '09

22 Dec '09

Hi Dave, On 19.12.2009 20:11, spirals wrote: > [...] no effect on my problem o/p when flashing my BIOS remains : > flashrom v0.9.1-r792 > No coreboot table found. > Found chipset "SiS 745", enabling flash write... FAILED! > This chipset supports the following protocols: Non-SPI. > Disabling flash write protection for board "Elitegroup K7S6A"... OK. > Calibrating delay loop... OK. > Found chip "SST SST39SF020A" (256 KB, Parallel) at physical address > 0xfffc0000. > > [...] patch is in but I still get Found chipset "SiS 745", enabling > flash write... FAILED! so write enable is NOT working. Brain is > slightly addled, (dja.) spirals. thanks for the report. I admit that the message is confusing. "enabling flash write... FAILED" does not mean that write enable failed, it just means that at least one of the expectations of the chipset write enable function was violated. And yes, we should fix that up. The problem is that we don't have any docs for this chipset and the code was just a guess. However, board the flash write enable function works fine as you can see from looking at the output: The flash chip is now found and it wasn't found before. > Carl-Daniel Hailfinger wrote: >> On 08.12.2009 11:41, Luc Verhaegen wrote: >>> http://patchwork.coreboot.org/patch/635/ >> >> And committed in r808 with some modifications. Unless you have problems writing to the chip, I think everything is OK. Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

Re: [flashrom] (update, update) Gigabyte GA-7ZXE v1.1
by Charles M 22 Dec '09

22 Dec '09

Oops, my bad, I was pretty sure the VIA chip was the Southbridge but I questioned my own logic when I saw it listed as a super i/o chip in the manual: Chipset: VT82C686B PCI Super-I/O Integrated Peripheral Controller (PSIPC) There's a chip just under the tail of the AGP slot that might be the super i/o chip... it's an ICS 94236AF but this is listed as the clock generator... So where is the super i/o chip usually located?

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