flashrom

flashrom@flashrom.org

1 participants
9182 discussions

flashrom-v1.2 tagged and released
by David Hendricks 17 Feb '20

17 Feb '20

Hello everyone, Flashrom v1.2 is out. A tarball has been added to download.flashrom.org/releases, and a new branch (1.2.x) and tag (v1.2) have been pushed. This release was rushed a bit so that we have a release that includes numerous build fixes that have been merged since v1.1. Fedora's build system started to encounter compilation issues that needed to be addressed for their upcoming release, so that became our canary in the coal mine this time around. Other highlights: - Meson support (hello fwupd!) - Layout improvements/fixes and many, many code cleanups. - New chips: MX25U25635F, MX25L51245G, GD25Q256D, M95M02-A125, N25Q/MT25Q variants, W25Q128JW_DTR, AT25SF321, S25FL512S - New programmers: National Instruments USB-845x, Tin Can Tools Flyswatter/Flyswatter 2, STLINK V3, more Intel PCHs (Apollo Lake, Cannon Lake variants, Ice Lake U) - Reduced dependency on libusb0 - Syntax: Added --flash-name and --flash-size arguments to print information about the flash chip Please report issues, and as always thanks to all who have contributed.

3 2

./flash command not found?
by df2100＠tutanota.com 14 Feb '20

14 Feb '20

Hello! I am attempting to install libreboot onto an old macbook while following a guide. I am having an issue where the ./flash command is giving me an error in terminal saying that it is not a valid command. Other commands I give to flashrom work fine, but ./flash does nothing. The command I am attempting to run is "sudo ./flash i945apple_firstflash 'path_to_my_rom_file'" and get back "sudo: ./flash: command not found" I am very new to linux so I'm probably missing something but any help would be greatly appreciated. Thanks! -- Sent securely via Tutanota email services

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Issue with AMD FP4
by Andreas Aßmann 13 Feb '20

13 Feb '20

Find both flashrom and lspci output attached to this message. Trying to determine the generation of the SPI interface... FCH device found but SMBus revision 0x59 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!.

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"Please report this to flashrom@flashrom.org"
by Pete French 09 Feb '20

09 Feb '20

Motherboard is MSI X370 XPOWER GAMING TITANIUM (MS-7A31) flashrom v1.1 on FreeBSD 12.1-STABLE (amd64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 4, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x59 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. pciconf -lv: hostb0@pci0:0:0:0: class=0x060000 card=0x7a311462 chip=0x14501022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Root Complex' class = bridge subclass = HOST-PCI none0@pci0:0:0:2: class=0x080600 card=0x14511022 chip=0x14511022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) I/O Memory Management Unit' class = base peripheral subclass = IOMMU hostb1@pci0:0:1:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI pcib1@pci0:0:1:3: class=0x060400 card=0x14531022 chip=0x14531022 rev=0x00 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) PCIe GPP Bridge' class = bridge subclass = PCI-PCI hostb2@pci0:0:2:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI hostb3@pci0:0:3:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI pcib9@pci0:0:3:1: class=0x060400 card=0x14531022 chip=0x14531022 rev=0x00 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) PCIe GPP Bridge' class = bridge subclass = PCI-PCI hostb4@pci0:0:4:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI hostb5@pci0:0:7:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI pcib10@pci0:0:7:1: class=0x060400 card=0x14541022 chip=0x14541022 rev=0x00 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B' class = bridge subclass = PCI-PCI hostb6@pci0:0:8:0: class=0x060000 card=0x00000000 chip=0x14521022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge' class = bridge subclass = HOST-PCI pcib11@pci0:0:8:1: class=0x060400 card=0x14541022 chip=0x14541022 rev=0x00 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B' class = bridge subclass = PCI-PCI intsmb0@pci0:0:20:0: class=0x0c0500 card=0x7a311462 chip=0x790b1022 rev=0x59 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'FCH SMBus Controller' class = serial bus subclass = SMBus isab0@pci0:0:20:3: class=0x060100 card=0x7a311462 chip=0x790e1022 rev=0x51 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'FCH LPC Bridge' class = bridge subclass = PCI-ISA hostb7@pci0:0:24:0: class=0x060000 card=0x00000000 chip=0x14601022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0' class = bridge subclass = HOST-PCI hostb8@pci0:0:24:1: class=0x060000 card=0x00000000 chip=0x14611022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1' class = bridge subclass = HOST-PCI hostb9@pci0:0:24:2: class=0x060000 card=0x00000000 chip=0x14621022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2' class = bridge subclass = HOST-PCI hostb10@pci0:0:24:3: class=0x060000 card=0x00000000 chip=0x14631022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3' class = bridge subclass = HOST-PCI hostb11@pci0:0:24:4: class=0x060000 card=0x00000000 chip=0x14641022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4' class = bridge subclass = HOST-PCI hostb12@pci0:0:24:5: class=0x060000 card=0x00000000 chip=0x14651022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5' class = bridge subclass = HOST-PCI hostb13@pci0:0:24:6: class=0x060000 card=0x00000000 chip=0x14661022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6' class = bridge subclass = HOST-PCI hostb14@pci0:0:24:7: class=0x060000 card=0x00000000 chip=0x14671022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7' class = bridge subclass = HOST-PCI xhci0@pci0:3:0:0: class=0x0c0330 card=0x11421b21 chip=0x43b91022 rev=0x02 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'X370 Series Chipset USB 3.1 xHCI Controller' class = serial bus subclass = USB ahci0@pci0:3:0:1: class=0x010601 card=0x10621b21 chip=0x43b51022 rev=0x02 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'X370 Series Chipset SATA Controller' class = mass storage subclass = SATA pcib2@pci0:3:0:2: class=0x060400 card=0x02011b21 chip=0x43b01022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'X370 Series Chipset PCIe Upstream Port' class = bridge subclass = PCI-PCI pcib3@pci0:32:0:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI pcib4@pci0:32:1:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI pcib5@pci0:32:2:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI pcib6@pci0:32:3:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI pcib7@pci0:32:4:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI pcib8@pci0:32:9:0: class=0x060400 card=0x33061b21 chip=0x43b41022 rev=0x02 hdr=0x01 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = '300 Series Chipset PCIe Port' class = bridge subclass = PCI-PCI igb0@pci0:33:0:0: class=0x020000 card=0x7a311462 chip=0x15398086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' device = 'I211 Gigabit Network Connection' class = network subclass = ethernet xhci1@pci0:38:0:0: class=0x0c0330 card=0x7a311462 chip=0x21421b21 rev=0x00 hdr=0x00 vendor = 'ASMedia Technology Inc.' device = 'ASM2142 USB 3.1 Host Controller' class = serial bus subclass = USB vgapci0@pci0:39:0:0: class=0x030000 card=0x3130103c chip=0x67591002 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD/ATI]' device = 'Turks PRO [Radeon HD 6570/7570/8550]' class = display subclass = VGA hdac0@pci0:39:0:1: class=0x040300 card=0xaa90103c chip=0xaa901002 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD/ATI]' device = 'Turks HDMI Audio [Radeon HD 6500/6600 / 6700M Series]' class = multimedia subclass = HDA none1@pci0:40:0:0: class=0x130000 card=0x145a1022 chip=0x145a1022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Zeppelin/Raven/Raven2 PCIe Dummy Function' class = non-essential instrumentation none2@pci0:40:0:2: class=0x108000 card=0x14561022 chip=0x14561022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) Platform Security Processor' class = encrypt/decrypt xhci2@pci0:40:0:3: class=0x0c0330 card=0x7a311462 chip=0x145c1022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) USB 3.0 Host Controller' class = serial bus subclass = USB none3@pci0:41:0:0: class=0x130000 card=0x14551022 chip=0x14551022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Zeppelin/Renoir PCIe Dummy Function' class = non-essential instrumentation ahci1@pci0:41:0:2: class=0x010601 card=0x7a311462 chip=0x79011022 rev=0x51 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'FCH SATA Controller [AHCI mode]' class = mass storage subclass = SATA hdac1@pci0:41:0:3: class=0x040300 card=0xda311462 chip=0x14571022 rev=0x00 hdr=0x00 vendor = 'Advanced Micro Devices, Inc. [AMD]' device = 'Family 17h (Models 00h-0fh) HD Audio Controller' class = multimedia subclass = HDA

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Flashrom report
by Dennis 04 Feb '20

04 Feb '20

Hi Please see the report below. I've tried flashing 2 eproms but get the same result. Any ideas? Thanks Dennis Calibrating delay loop... OK. Found Macronix flash chip "MX25U6435E/F" (8192 kB, SPI) on ch341a_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x00000010! Expected=0x5a, Found=0x5b, failed byte count from 0x00000000-0x007fffff: 0x332be2 Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

4 8

Add Mainboard Suport
by Jean Marques 03 Feb '20

03 Feb '20

Hi. I've built and ran the most recent version of flashrom, I can read the eeprom but I can't write or erase chips. It's possible to add suport? I have spare eeproms and a backup of my bios. I'm trying to do hotswap flashing. The motherboard is 775Twins-HDTV. I have a log atached. Thank you.

1 0

"pcidev.c: Factor out pcidev_validate() into pure fn" broke PCI programmers
by Carl-Daniel Hailfinger 31 Jan '20

31 Jan '20

Hi, commit e28d75ed7204d7fac2c0fac13978098530b0574e dropped some logic during refactoring. PCI-based programmers now fail to initialize IFF the desired PCI device not the last one enumerated by libpci. Given that this refactoring was done to make unit tests easier, I'd expect the unit tests to have caught that problem. This raises a few questions: - Why did unit tests not find that problem? - If there are no unit tests testing for such a problem, why was the code refactored in the first place? - Do we need CI tests with real hardware or at least with qemu to avoid such problems in the future? Regards, Carl-Daniel

5 4

Stepping Down as Flashrom Maintainer/Developer
by Nico Huber 30 Jan '20

30 Jan '20

Dear flashrom community, I regret to tell you that I won't do any further upstream flashrom work in the foreseeable future. Compared to the last few months that won't change much, as I didn't spend as much time on flashrom as I wanted to. TL;DR Maintaining flashrom was always a bit of a drag, mostly reviewing, organizing tests and releases, didn't leave much time for personal deve- lopment. Still, it was mostly fun. Until I flew too close to the sun and burned all my fuel that I had left for the project, trying to help converging the Chromium fork with upstream flashrom. I really hoped it wouldn't become another episode of "Nice! somebody else does the work". Not - a - chance. Upfront I was once told not to blame a company for the actions of individuals. However, there is forming a pattern, of people complaining to me how hard their job is; after I just did part of their job in my spare time! I don't think they are to blame, but they happen to all have the same employer. If we are pushed hard enough that we don't see anymore what we ask from one another, it's time to quit. At least regarding flash- rom I won't do any more work for them just because somebody said to be done in no time. What happened About half a year ago people started to push patches from Chromium upstream. I tried to welcome them and, as usual, to encouraged them to announce their plans on the mailing list so we could all work better together. Pipe dreams. Obviously they wanted a fast lane, so the fork wouldn't cause too much more friction (for them!). No time to wait for other patches (including conflicting ones) to be reviewed. No [...] to do it by themselves. There was a decision to be made, either they would have to wait and rebase or other contributors would have to wait even longer and rebase. I chose wrong, and feel sorry about it. I prioritized the upstreaming, did fewer reviews for other contributors, let my own patches rot, didn't invest in further flashrom releases. Around the same time, somebody (who happens to have administration rights) gave submit rights to the flashrom repository to one of them. I tried to stay calm and to be nice. (Edward, nothing personal, I actually was glad that it was you. I was just annoyed because of the way it happened, I had to dig up what is going on instead of reading it in a nice email.) Up to now, I guess roughly 40~50 patches landed upstream. Most of them in one of these categories: o New features o Flash chip support o Remaining diff between the branches The former turned out to be ok'ish, even though it's tedious to repeat every time that patches should be organized to ease review, and should have known issues fixed already. The flash chip additions started with a weird idea, sort the `flashchips.c` on both sides to make it easier comparable. I didn't want to squabble about other people's workflow and, in good faith, allowed it. The last category produced some odd patches with creative commit messages. It seems the idea was to diff individual files between the branches and if it was small enough to turn it into a commit. Now I have no idea how many sides their dice had that they used to decide which branch would be patched. The result was that I had to either complain about the commit message and hope to get answers (unlikely) or to dig into it by myself, spending hours staring at the history of the two branches to make some sense of it. I had to do exactly what the uploaders avoided to do because of their time constraints. Sometimes to find out that a commit effectively rever- ted good upstream work! If that wasn't discovered during review, that's the community's fault of course, and theirs to fix. The uploaders have no time; remember, their job is hard, yours is not. Regrets When I started maintaining flashrom, I set myself a rule: At least have a look at every patch that lands on Gerrit. I broke that rule at least with the patch train for AMD graphics cards, sorry Luc. Obviously I regret prioritizing Chromium patches, before they proved to be valuable community members. My biggest regret is the re-sorting of `flashchips.c`. Given the few patches in that area that landed, it didn't pan out. Also, it was a pure convenience stunt, one can as well re-sort on-the-fly for comparison. OTOH, it breaks the Git history, making it much harder to check for reasons, e.g. why is this feature set? which variants of this chip were really tested? If anybody wants to roll back master to fix that, you'd have my full support to make it happen without losing anything that was added after. Legacy I've left at least two of my patch trains rotting: A set to overhaul internal layout handling and one for IFWI layouts. I've seen that they were commented on eventually. Thank you Angel and David, and sorry in advance if I wasted your time in case the patches won't make it. The IFWI patches were written first, but they made me realize that layout changes are necessary and should come first. If I had spent more time on it, I would have rebased them accordingly. Future I'll have to maintain a flashrom branch for my employer. It might take some time before I rebase anything, but if anyone wants me to keep things published somewhere, I can arrange that. For upstream, future's all up to you! Thank you all for the time we spent together on the project! Nico

4 4

Re: How to add a new EEPROM/Flash chip into Flashrom
by Николай Николаев 30 Jan '20

30 Jan '20

Hello Thorsten. please find below the link for the details https://www.flashrom.org/Development_Guidelines#Patch_submission <https://www.flashrom.org/Development_Guidelines#Commit_message> <https://context.reverso.net/перевод/английский-русский/it%27s+about> <https://context.reverso.net/перевод/английский-русский/it%27s+about>it's about how to do patch -- With best regards Nikolay Nikolaev

1 0

Testing Flashrom on new board
by Vesely, Vojtech 29 Jan '20

29 Jan '20

Hi, I am working on bringing up new board and everything seems to work. I would like to test the functionality to make sure. There is https://www.flashrom.org/Board_Testing_HOWTO, but that is very general. Do you have some specific list of tests to run? Best, Vojtech Vesely Board Testing HOWTO - flashrom<https://www.flashrom.org/Board_Testing_HOWTO> This page gives you mainly hints on how to test flashrom support on mainboards. Testing for graphics / network / SATA cards and external programmer devices is similar but less dangerous. www.flashrom.org

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