flashrom

flashrom@flashrom.org

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9161 discussions

Hardware Sequencing vs Software Sequencing
by john warwick 01 Apr '10

01 Apr '10

Hi, I was looking through the code, and see that flashrom is using software sequencing. Is there any reason for software sequencing to be chosen instead of hardware sequencing? Are there any restrictions imposed for hardware sequencing? Rgds, John _________________________________________________________________ Hotmail: Trusted email with powerful SPAM protection. http://clk.atdmt.com/GBL/go/210850553/direct/01/

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[PATCH] Fix the delay loop
by Carl-Daniel Hailfinger 01 Apr '10

01 Apr '10

[Side note: This is not the big timing code rewrite I originally wanted to post. I decided to focus on readable code instead of clever code. My other rewrite is available on request if anyone is interested.] The current delay loop calculation is still from revision 1 of flashrom, and since then it had a logic bug which caused all delays to be twice as long as intended. Fix the delay duration. Protect against delay loop overflows. Detect a non-working delay loop. Change the delay loop itself to ensure clever compiler optimizers won't eliminate it (as happens with clang/llvm in the current code). Some people suggested machine-specific asm, but the empty asm statement with the loop counter as register/memory input has the benefit of being perfectly cross-platform and working in gcc and clang. If time goes backwards (catastrophical NTP time difference, manual time change), timing measurements were shot because the new-old time subtraction yielded negative numbers which weren't handled correctly because the variable is unsigned. Simply return 1 microsecond timing in that case. If time goes forward too fast, pick the biggest possible timing measurement with a guaranteed overflow avoidance for all timing calculations. Check four times if the calculated timing is at most 10% too fast. This addresses OS scheduler interactions, e.g. being scheduled out during measurement which inflates measurements. If the timing is off, recalculate the timer values up to four times before giving up. Avoid division by zero in rare cases where timing measurements for a 250 ms delay return 0 us elapsed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-delayloop_portable_fix/udelay.c =================================================================== --- flashrom-delayloop_portable_fix/udelay.c (Revision 988) +++ flashrom-delayloop_portable_fix/udelay.c (Arbeitskopie) @@ -24,13 +24,16 @@ #include <limits.h> #include "flash.h" -// count to a billion. Time it. If it's < 1 sec, count to 10B, etc. +/* loops per microsecond */ unsigned long micro = 1; -void myusec_delay(int usecs) +__attribute__ ((noinline)) void myusec_delay(int usecs) { - volatile unsigned long i; - for (i = 0; i < usecs * micro; i++) ; + unsigned long i; + for (i = 0; i < usecs * micro; i++) { + /* Make sure the compiler doesn't optimize the loop away. */ + asm volatile ("" : : "rm" (i) ); + } } unsigned long measure_delay(int usecs) @@ -43,30 +46,62 @@ gettimeofday(&end, 0); timeusec = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); + /* Protect against time going forward too much. */ + if ((end.tv_sec > start.tv_sec) && + ((end.tv_sec - start.tv_sec) >= LONG_MAX / 1000000 - 1)) + timeusec = LONG_MAX; + /* Protect against time going backwards during leap seconds. */ + if ((end.tv_sec < start.tv_sec) || (timeusec > LONG_MAX)) + timeusec = 1; return timeusec; } void myusec_calibrate_delay(void) { - int count = 1000; + unsigned long count = 1000; unsigned long timeusec; - int ok = 0; + int i, tries = 0; printf("Calibrating delay loop... "); - while (!ok) { +recalibrate: + while (1) { timeusec = measure_delay(count); + if (timeusec > 1000000 / 4) + break; + if (count >= ULONG_MAX / 2) { + msg_pinfo("timer loop overflow, reduced precision. "); + break; + } count *= 2; - if (timeusec < 1000000 / 4) - continue; - ok = 1; } + tries ++; - // compute one microsecond. That will be count / time - micro = count / timeusec; - msg_pdbg("%ldM loops per second, ", micro); + /* Avoid division by zero, but in that case the loop is shot anyway. */ + if (!timeusec) + timeusec = 1; + + /* Compute rounded up number of loops per microsecond. */ + micro = (count * micro) / timeusec + 1; + msg_pdbg("%luM loops per second, ", micro); + /* Did we try to recalibrate less than 5 times? */ + if (tries < 5) { + /* Recheck our timing to make sure we weren't just hitting + * a scheduler delay or something similar. + */ + for (i = 0; i < 4; i++) { + if (measure_delay(100) < 90) { + msg_pdbg("delay more than 10% too short, " + "recalculating... "); + goto recalibrate; + } + } + } else { + msg_perr("delay loop is unreliable, trying to continue "); + } + /* We're interested in the actual precision. */ timeusec = measure_delay(10); msg_pdbg("10 myus = %ld us, ", timeusec); -- http://www.hailfinger.org/

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[commit] r990 - trunk
by repository service 01 Apr '10

01 Apr '10

Author: hailfinger Date: Thu Apr 1 01:55:06 2010 New Revision: 990 URL: http://flashrom.org/trac/coreboot/changeset/990 Log: The current delay loop calculation is still from revision 1 of flashrom, and since then it had a logic bug which caused all delays to be twice as long as intended. Fix the delay duration. Protect against delay loop overflows. Detect a non-working delay loop. Change the delay loop itself to ensure clever compiler optimizers won't eliminate it (as happens with clang/llvm in the current code). Some people suggested machine-specific asm, but the empty asm statement with the loop counter as register/memory input has the benefit of being perfectly cross-platform and working in gcc and clang. If time goes backwards (catastrophical NTP time difference, manual time change), timing measurements were shot because the new-old time subtraction yielded negative numbers which weren't handled correctly because the variable is unsigned. Work around that issue (a fix is mathematically impossible). If time goes forward too fast, pick the biggest possible timing measurement with a guaranteed overflow avoidance for all timing calculations. Check four times if the calculated timing is at most 10% too fast. This addresses OS scheduler interactions, e.g. being scheduled out during measurement which inflates measurements. If the timing looks like garbage, recalculate the timer values up to four times before giving up. Avoid division by zero in rare cases where timing measurements for a 250 ms delay returned 0 us elapsed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Modified: trunk/udelay.c Modified: trunk/udelay.c ============================================================================== --- trunk/udelay.c Tue Mar 30 04:45:18 2010 (r989) +++ trunk/udelay.c Thu Apr 1 01:55:06 2010 (r990) @@ -24,13 +24,16 @@ #include <limits.h> #include "flash.h" -// count to a billion. Time it. If it's < 1 sec, count to 10B, etc. +/* loops per microsecond */ unsigned long micro = 1; -void myusec_delay(int usecs) +__attribute__ ((noinline)) void myusec_delay(int usecs) { - volatile unsigned long i; - for (i = 0; i < usecs * micro; i++) ; + unsigned long i; + for (i = 0; i < usecs * micro; i++) { + /* Make sure the compiler doesn't optimize the loop away. */ + asm volatile ("" : : "rm" (i) ); + } } unsigned long measure_delay(int usecs) @@ -43,29 +46,61 @@ gettimeofday(&end, 0); timeusec = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); + /* Protect against time going forward too much. */ + if ((end.tv_sec > start.tv_sec) && + ((end.tv_sec - start.tv_sec) >= LONG_MAX / 1000000 - 1)) + timeusec = LONG_MAX; + /* Protect against time going backwards during leap seconds. */ + if ((end.tv_sec < start.tv_sec) || (timeusec > LONG_MAX)) + timeusec = 1; return timeusec; } void myusec_calibrate_delay(void) { - int count = 1000; + unsigned long count = 1000; unsigned long timeusec; - int ok = 0; + int i, tries = 0; printf("Calibrating delay loop... "); - while (!ok) { +recalibrate: + while (1) { timeusec = measure_delay(count); + if (timeusec > 1000000 / 4) + break; + if (count >= ULONG_MAX / 2) { + msg_pinfo("timer loop overflow, reduced precision. "); + break; + } count *= 2; - if (timeusec < 1000000 / 4) - continue; - ok = 1; } + tries ++; - // compute one microsecond. That will be count / time - micro = count / timeusec; - msg_pdbg("%ldM loops per second, ", micro); + /* Avoid division by zero, but in that case the loop is shot anyway. */ + if (!timeusec) + timeusec = 1; + + /* Compute rounded up number of loops per microsecond. */ + micro = (count * micro) / timeusec + 1; + msg_pdbg("%luM loops per second, ", micro); + + /* Did we try to recalibrate less than 5 times? */ + if (tries < 5) { + /* Recheck our timing to make sure we weren't just hitting + * a scheduler delay or something similar. + */ + for (i = 0; i < 4; i++) { + if (measure_delay(100) < 90) { + msg_pdbg("delay more than 10% too short, " + "recalculating... "); + goto recalibrate; + } + } + } else { + msg_perr("delay loop is unreliable, trying to continue "); + } /* We're interested in the actual precision. */ timeusec = measure_delay(10);

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[PATCH] Intel 28F004/28F400 support
by Michael Karcher 01 Apr '10

01 Apr '10

This should also fix broken write for non-uniform sectored FWH-like chips. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- 82802ab.c | 85 +++++++++++++++++++++++++++++-------------- chipdrivers.h | 3 ++ flash.h | 2 +- flashchips.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 4 ++ 5 files changed, 175 insertions(+), 29 deletions(-) diff --git a/82802ab.c b/82802ab.c index aa7e45e..27acaa3 100644 --- a/82802ab.c +++ b/82802ab.c @@ -48,6 +48,12 @@ int probe_82802ab(struct flashchip *flash) chipaddr bios = flash->virtual_memory; uint8_t id1, id2; uint8_t flashcontent1, flashcontent2; + int id2_offset; + + if (flash->feature_bits & FEATURE_ADDR_SHIFTED) + id2_offset = 2; + else + id2_offset = 1; /* Reset to get a clean state */ chip_writeb(0xFF, bios); @@ -58,7 +64,7 @@ int probe_82802ab(struct flashchip *flash) programmer_delay(10); id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id2 = chip_readb(bios + id2_offset); /* Leave ID mode */ chip_writeb(0xFF, bios); @@ -72,7 +78,7 @@ int probe_82802ab(struct flashchip *flash) /* Read the product ID location again. We should now see normal flash contents. */ flashcontent1 = chip_readb(bios); - flashcontent2 = chip_readb(bios + 0x01); + flashcontent2 = chip_readb(bios + id2_offset); if (id1 == flashcontent1) msg_cdbg(", id1 is normal flash content"); @@ -177,41 +183,64 @@ void write_page_82802ab(chipaddr bios, uint8_t *src, int write_82802ab(struct flashchip *flash, uint8_t *buf) { - int i; - int total_size = flash->total_size * 1024; + int i, j, blocknum; + int blockoffset = 0; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; uint8_t *tmpbuf = malloc(page_size); + struct eraseblock * blocks; + int (*erase) (struct flashchip *flash, unsigned int blockaddr, + unsigned int blocklen); + + /* find first erase layout with a working erase function */ + for (i = 0; flash->block_erasers[i].block_erase == NULL && + i < NUM_ERASEFUNCTIONS; i++); + + if (i == NUM_ERASEFUNCTIONS) + { + msg_perr("No working erase function found - can't write\n"); + return -1; + } + msg_pdbg("Chosing block layout #%d\n", i); + blocks = flash->block_erasers[i].eraseblocks; + erase = flash->block_erasers[i].block_erase; if (!tmpbuf) { msg_cerr("Could not allocate memory!\n"); exit(1); } - msg_cinfo("Programming page: \n"); - for (i = 0; i < total_size / page_size; i++) { - msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - msg_cinfo("%04d at address: 0x%08x", i, i * page_size); - - /* Auto Skip Blocks, which already contain the desired data - * Faster, because we only write, what has changed - * More secure, because blocks, which are excluded - * (with the exclude or layout feature) - * or not erased and rewritten; their data is retained also in - * sudden power off situations - */ - chip_readn(tmpbuf, bios + i * page_size, page_size); - if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { - msg_cdbg("SKIPPED\n"); - continue; - } - - /* erase block by block and write block by block; this is the most secure way */ - if (erase_block_82802ab(flash, i * page_size, page_size)) { - msg_cerr("ERASE FAILED!\n"); - return -1; + msg_cinfo("Programming block: \n"); + blocknum = 0; + for (i = 0; blocks[i].size != 0; i++) { + for(j = 0; j < blocks[i].count; j++) { + msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b" + "\b\b\b\b\b\b\b\b\b\b\b"); + msg_cinfo("%04d at address: 0x%08x", blocknum, + blockoffset); + + /* Auto Skip Blocks, which already contain the + * desired data: + * Faster, because we only write, what has changed + * More secure, because blocks, which are excluded + * (with the exclude or layout feature) + * or not erased and rewritten; their data is + * retained also in sudden power off situations + */ + chip_readn(tmpbuf, bios + blockoffset, blocks[i].size); + if (!memcmp((void *)(buf + i * page_size), tmpbuf, + blocks[i].size)) { + msg_cdbg("SKIPPED\n"); + } else { + if (erase(flash, blockoffset, page_size)) { + msg_cerr("ERASE FAILED!\n"); + return -1; + } + write_page_82802ab(bios, buf + blockoffset, + bios + blockoffset, blocks[i].size); + } + blockoffset += blocks[i].size; + blocknum++; } - write_page_82802ab(bios, buf + i * page_size, - bios + i * page_size, page_size); } msg_cinfo("DONE!\n"); free(tmpbuf); diff --git a/chipdrivers.h b/chipdrivers.h index 6d5cef0..816088a 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -53,6 +53,9 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); +/* i28f00x.c */ +int write_28f00x(struct flashchip *flash, uint8_t *buf); + /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); int probe_82802ab(struct flashchip *flash); diff --git a/flash.h b/flash.h index aee95a3..0a74363 100644 --- a/flash.h +++ b/flash.h @@ -166,7 +166,7 @@ enum chipbustype { #define FEATURE_ADDR_MASK (3 << 2) #define FEATURE_ADDR_2AA (1 << 2) #define FEATURE_ADDR_AAA (2 << 2) -#define FEATURE_ADDR_SHIFTED 0 +#define FEATURE_ADDR_SHIFTED (1 << 5) struct flashchip { const char *vendor; diff --git a/flashchips.c b/flashchips.c index 2dbc1e0..f838ab2 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2385,6 +2385,116 @@ struct flashchip flashchips[] = { { .vendor = "Intel", + .name = "28F004BV/BE-B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F004BB, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 3}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F004BV/BE-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F004BT, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 3}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F400BV/CV/CE-B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F400BB, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .feature_bits = FEATURE_ADDR_SHIFTED, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 3}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F004BV/BE-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F400BT, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .feature_bits = FEATURE_ADDR_SHIFTED, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 3}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "82802AB", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, diff --git a/flashchips.h b/flashchips.h index 4337e52..b6c2e8b 100644 --- a/flashchips.h +++ b/flashchips.h @@ -259,6 +259,10 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F004BT 0x78 /* 28F004BV/BE-T */ +#define P28F004BB 0x79 /* 28F004BV/BE-B */ +#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ +#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ -- 1.7.0

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Re: [flashrom] [PATCH] Intel 28F004/28F400 support
by Michael Karcher 01 Apr '10

01 Apr '10

Am Donnerstag, den 01.04.2010, 00:42 +0200 schrieb Michael Karcher: > This should also fix broken write for non-uniform sectored FWH-like chips. Sorry, that patch was broken. Real patch follows. Regards, Michael Karcher

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[PATCH] Intel 28F004/28F400 support
by Michael Karcher 01 Apr '10

01 Apr '10

This should also fix broken write for non-uniform sectored FWH-like chips. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- Makefile | 2 +- chipdrivers.h | 3 +++ flashchips.c | 31 +++++++++++++++++++++++++++++++ flashchips.h | 2 ++ 4 files changed, 37 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index fa67b73..992397e 100644 --- a/Makefile +++ b/Makefile @@ -57,7 +57,7 @@ endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o i28f00x.o LIB_OBJS = layout.o diff --git a/chipdrivers.h b/chipdrivers.h index 6d5cef0..816088a 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -53,6 +53,9 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); +/* i28f00x.c */ +int write_28f00x(struct flashchip *flash, uint8_t *buf); + /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); int probe_82802ab(struct flashchip *flash); diff --git a/flashchips.c b/flashchips.c index 2dbc1e0..68f9ecd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2385,6 +2385,37 @@ struct flashchip flashchips[] = { { .vendor = "Intel", + .name = "28F004BV/BE-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F004BT, + .total_size = 512, + .page_size = 128 * 1024, /* for write_i28f00x: maximal block size */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .erase = NULL, + .block_erasers = + { + { + /* Keep this the first block_erasers + entry. The write functions spies here to + get the chip layout */ + .eraseblocks = { + {128 * 1024, 3}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_82802ab_block, + }, + }, + .write = write_28f00x, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "82802AB", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, diff --git a/flashchips.h b/flashchips.h index 4337e52..1cbb3c6 100644 --- a/flashchips.h +++ b/flashchips.h @@ -259,6 +259,8 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F004BT 0x78 /* 28F004BV/BE-T */ +#define P28F004BB 0x79 /* 28F004BV/BE-B */ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ -- 1.7.0

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HP dc5850 Dump Files
by Terminus Est 31 Mar '10

31 Mar '10

Flashrom doesnt read, write or erase on this mobo bios. I can't open my PC to clear the cmos settings, and don't remember the bios password. I need to access the bios to configure somethings. Maybe you have a tip, a clue? Thx in advance. -- Linux User nº 451568 Linux Mint Gloria KDE Edition running on Athlon 64 X2 4200+ 2Gb DDR-400 2x Maxtor 40Gb in RAID 0 SATA Samsung 160Gb A8N SLI Premium gForce 6800 GS Ultra - Deceased...

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Flashrom on Gigabyte GA-MA770-UD3 (rev 1.0) - works with little patch
by Vadim Girlin 30 Mar '10

30 Mar '10

Hello, Flashrom v0.9.1-r985 was unable to detect SPI flash chip (SST25VF080B) on Gigabyte GA-MA770-UD3 (rev 1.0) - http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI… First attachment contains the output of "flashrom -r -V". I've tried the following: Index: it87spi.c =================================================================== --- it87spi.c (revision 985) +++ it87spi.c (working copy) @@ -103,6 +103,7 @@ switch (id) { case 0x8716: case 0x8718: + case 0x8720: enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; After this patch flashrom detected the chip. Reading, erasing and writing also works. I attached the logs. Hope this helps. -- Best regards, Vadim Girlin

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[commit] r989 - trunk
by repository service 30 Mar '10

30 Mar '10

Author: hailfinger Date: Tue Mar 30 04:45:18 2010 New Revision: 989 URL: http://flashrom.org/trac/coreboot/changeset/989 Log: Add ITE IT8720 SPI support. Original patch by Vadim Girlin. Message printing updated by Carl-Daniel Hailfinger. Signed-off-by: Vadim Girlin <vadimgirlin(a)gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/it87spi.c Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Sun Mar 28 00:25:14 2010 (r988) +++ trunk/it87spi.c Tue Mar 30 04:45:18 2010 (r989) @@ -103,6 +103,7 @@ switch (id) { case 0x8716: case 0x8718: + case 0x8720: enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; @@ -159,7 +160,7 @@ break; /* TODO: Handle more IT87xx if they support flash translation */ default: - msg_pinfo("SuperI/O ID %04hx is not on the controller list.\n", id); + msg_pdbg("SuperI/O ID %04hx is not on the controller list.\n", id); } return flashport; } @@ -199,8 +200,11 @@ int ret; ret = it87spi_common_init(); - if (!ret) + if (!ret) { + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); buses_supported |= CHIP_BUSTYPE_SPI; + } return ret; }

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SST 49LF0008A - Erase problem (and solution)
by Panino ColSalame 29 Mar '10

29 Mar '10

Hello, I'm playing with flashrom on an ASEM Industrial PC based on an Atom Z530 and the US15W (Poulsbo) System Controller Hub. The BIOS flash is the SST 49LF0008A (Firmware Hub). After downloading the latest development code using git, flashrom was able to detect and read the flash, but the erase command failed. At first I've tried to increase the delay that is used by the toggle functions in jedec.c, passing from the default 8 to 80 (just for testing). At this point, the Erase command started to work properly. SST manual reads: The End-of-Write detection mode is incorporated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. So, I've set the delay for reading the toggle bit again to the default value of 8 and I've added an additional toggle bit check, in case the first one seems to be ok. It works! So, I'm able to Read, Write and Erase the chip. Best Regards Panino diff -Nur flashromold/jedec.c flashromnew/jedec.c --- flashromold/jedec.c 2010-03-08 14:07:23.000000000 +0100 +++ flashromnew/jedec.c 2010-03-08 13:29:30.000000000 +0100 @@ -50,7 +50,11 @@ programmer_delay(delay); tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { - break; + tmp1 = chip_readb(dst) & 0x40; + programmer_delay(delay); + tmp2 = chip_readb(dst) & 0x40; + if (tmp1 == tmp2) + break; } tmp1 = tmp2; } _________________________________________________________________ Personalizza il tuo Messenger con nuove e divertenti Emoticon http://www.pimpit.it/emoticon.html

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