flashrom

flashrom@flashrom.org

5 participants
9161 discussions

[commit] r1067 - trunk
by repository service 02 Jul '10

02 Jul '10

Author: hailfinger Date: Fri Jul 2 19:12:50 2010 New Revision: 1067 URL: http://flashrom.org/trac/coreboot/changeset/1067 Log: Add OpenBSD support. Add a requirements section to the man page which lists the needed access permissions for each programmer. This feature needs my pciutils/libpci 8/16-bit write emulation patch at http://marc.info/?l=openbsd-ports&m=127780030728045 titled [PATCH] Fix pciutils non-32bit PCI write on OpenBSD Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stuart Henderson <sthen(a)openbsd.org> Modified: trunk/Makefile trunk/README trunk/flashrom.8 trunk/hwaccess.c trunk/hwaccess.h trunk/physmap.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/Makefile Fri Jul 2 19:12:50 2010 (r1067) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,6 +263,10 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) +endif endif endif endif Modified: trunk/README ============================================================================== --- trunk/README Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/README Fri Jul 2 19:12:50 2010 (r1067) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/flashrom.8 Fri Jul 2 19:12:50 2010 (r1067) @@ -306,7 +306,7 @@ Example: .B "flashrom \-p dummy:lpc,fwh" .TP -.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii\ +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii \ " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -391,6 +391,51 @@ .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +.SH REQUIREMENTS +flashrom needs different access permissions for different programmers. +.sp +.B internal +needs raw memory access, PCI configuration space access, raw I/O port +access (x86) and MSR access (x86). +.sp +.B it87spi +needs raw I/O port access (x86). +.sp +.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " +need PCI configuration space read access and raw I/O port access. +.sp +.B atahpt +needs PCI configuration space access and raw I/O port access. +.sp +.BR gfxnvidia " and " drkaiser +need PCI configuration space access and raw memory access. +.sp +.B satasii +needs PCI configuration space read access and raw memory access. +.sp +.B serprog +needs TCP access to the network or userspace access to a serial port. +.sp +.B buspirate_spi +needs userspace access to a serial port. +.sp +.BR dediprog " and " ft2232_spi +need access to the USB device via libusb. +.sp +.B dummy +needs no access permissions at all. +.sp +.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " +.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +have to be run as superuser/root, and need additional raw access permission. +.sp +.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +can be run as normal user on most operating systems if appropriate device +permissions are set. +.sp +On OpenBSD, you can obtain raw access permission by setting +securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single +user mode. .SH BUGS Please report any bugs at .sp Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.c Fri Jul 2 19:12:50 2010 (r1067) @@ -57,6 +57,11 @@ #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); +#if defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); +#endif exit(1); } #endif Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.h Fri Jul 2 19:12:50 2010 (r1067) @@ -228,17 +228,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/physmap.c Fri Jul 2 19:12:50 2010 (r1067) @@ -229,6 +229,10 @@ msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#elif defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); #endif if (!mayfail) exit(3);

1 0

(no subject)
by Benjamin 02 Jul '10

02 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Studio XPS 1340" DMI string system-version: "A11" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: " " DMI string baseboard-version: "A11" DMI string chassis-type: "Portable" Found chipset "NVIDIA MCP79", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xf0600000, after clearing low bits BAR is at 0xf0600000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. LPC on this chipset is not supported yet. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 671M loops per second, 100 myus = 197 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

[PATCH] ICH9/10: display FRAP/FREGx access controls
by Joshua Roys 01 Jul '10

01 Jul '10

Hello, Attached is a patch to display the FRAP access controls on the FREGx regions of the flash chip. Also attached is the output from `flashrom -Vr foo.bin' on an ICH10 machine. Thanks, Josh

2 7

[commit] r1066 - trunk
by repository service 01 Jul '10

01 Jul '10

Author: hailfinger Date: Thu Jul 1 19:45:54 2010 New Revision: 1066 URL: http://flashrom.org/trac/coreboot/changeset/1066 Log: ICH9/10: display FRAP/FREGx access controls Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 1 13:16:28 2010 (r1065) +++ trunk/chipset_enable.c Thu Jul 1 19:45:54 2010 (r1066) @@ -430,6 +430,44 @@ return 0; } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | + ((ICH_BRRA(frap) & (1 << i)) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(spibar + offset), base, limit; + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { @@ -554,21 +592,15 @@ tmp = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); - msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); - msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); - msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - - msg_pdbg("0x54: 0x%08x (FREG0)\n", - mmio_readl(spibar + 0x54)); - msg_pdbg("0x58: 0x%08x (FREG1)\n", - mmio_readl(spibar + 0x58)); - msg_pdbg("0x5C: 0x%08x (FREG2)\n", - mmio_readl(spibar + 0x5C)); - msg_pdbg("0x60: 0x%08x (FREG3)\n", - mmio_readl(spibar + 0x60)); - msg_pdbg("0x64: 0x%08x (FREG4)\n", - mmio_readl(spibar + 0x64)); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n",

1 0

[PATCH] Support for HP DL165 G6
by Arne Georg Gleditsch 01 Jul '10

01 Jul '10

Hi, Attached is a patch to board_enable.c for the HP DL165 board. Apparently, the PCI signature of the DL165 is identical to the DL145, but the enable pins are placed differently... :/ I'm not sure what the best way to handle that is. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

3 9

[commit] r1065 - trunk
by repository service 01 Jul '10

01 Jul '10

Author: hailfinger Date: Thu Jul 1 13:16:28 2010 New Revision: 1065 URL: http://flashrom.org/trac/coreboot/changeset/1065 Log: Add support for the HP DL165 G6. Change the match for the HP DL145 G3 to avoid matching on the DL165 G6. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Jun 29 16:44:40 2010 (r1064) +++ trunk/board_enable.c Thu Jul 1 13:16:28 2010 (r1065) @@ -648,6 +648,20 @@ return 0; } +/* + * Set GPIO lines in the Broadcom HT-1000 southbridge. + * + * It's not a Super I/O but it uses the same index/data port method. + */ +static int board_hp_dl165_g6_enable(void) +{ + /* Variant of DL145, with slightly different pin placement. */ + sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */ + sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */ + + return 0; +} + static int board_ibm_x3455(void) { /* raise gpio13 */ @@ -1607,7 +1621,8 @@ {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},

1 0

Re: [flashrom] [coreboot] [PATCH] superiotool: libsuperiodetect
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

On 30.06.2010 14:51, Stefan Reinauer wrote: > On 6/30/10 2:35 PM, Carl-Daniel Hailfinger wrote: > >> Using the superiotool code to detect SuperI/O chips can be really useful >> even for applications besides superiotool, e.g. flashrom. >> The biggest hurdle right now is the excessive size of the superiotool >> binary (>2.2 MB) which is still ~15 kB after lzma compression. That's >> simply unacceptable for a library. >> >> > Why? There is no size constraints on libraries in Unix like systems. > Yes, but if I proposed to increase the size of the flashrom binary by over 2 MBytes, various people would ask if I'm crazy. > Assuming we're talking about a static library > >From my system: > > 20M /usr/lib64/libbfd.a > 20M /usr/lib64/libc.a > 11M /usr/lib64/libcrypto.a > 19M /usr/lib64/libdb-4.5.a > 3.9M /usr/lib64/libfreetype.a > 5.1M /usr/lib64/libgio-2.0.a > 3.6M /usr/lib64/libglib-2.0.a > 3.3M /usr/lib64/libgmp.a > 2.8M /usr/lib64/libm.a > 2.8M /usr/lib64/libncurses.a > 3.2M /usr/lib64/libncursesw.a > 4.9M /usr/lib64/libopcodes.a > 4.2M /usr/lib64/libruby-static.a > 3.0M /usr/lib64/libssl.a > 6.9M /usr/lib64/libxml2.a > > Also, keep in mind that the size of the library in the filesystem is not > the size increase when linking it. > However, if all objects in the library are used, the size increase of the binary is correlated closely to the linked static library size. > 15kb lzma compressed is nothing. > 8 kB more or less in a recovery payload of a coreboot image are not negligible IMHO. In normal OS environments people don't use compressed binaries, and there a 2 MB size increase for flashrom (98% of it for dead code which can't be optimized away by the compiler/linker) is definitely something people will object to. >> This minimally invasive patch makes all dumping code optional and >> reduces binary size for the probe-only case (libsuperiodetect) a lot. >> Binary sizes: >> 2268258 (before) >> 31600 (after) 98.6% reduction >> LZMA compressed and stripped binary sizes: >> 14778 (before) >> 6709 (after) 54.6% reduction >> >> > Not worth the additional unreadability of the code in my opinion > > >> To test compilation of superiotool with probe-only functionality, run >> make CONFIG_LIB=yes >> >> This patch is the first step towards libsuperiodetect, and more will >> have to follow. >> >> > I think the idea for libsuperio is great. > > I'll gladly ack this without the very intrusive "we save 6700 bytes" > part of the patch. > The patch is a pure size reduction. If I remove the size reduction part, the patch will be empty. I can reduce the number of #ifdefs, but that won't make the patch prettier. Will send the patch with less #ifdefs in a separate mail. >> IMHO the {EOT} markers should be killed in libsuperiodetect, at least >> for the LDNs. Such an operation would have increased the size of the >> patch and would have reduced readability as well. Due to that, I skipped >> it, but I plan to do that in a later operation. >> >> > What would you use instead? The array members all have different sizes > as far as I can tell, so some kind of end marker will be needed. > The libsuperiodetect case doesn't care about LDNs at all. Having exactly one LDN definition per Super I/O which is always EOT looks like dead code to me, especially if nothing is looking at the LDN. >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> >> >> > > >> /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. */ >> @@ -765,7 +803,9 @@ >> uint8_t revreg) >> { >> uint8_t id, rev; >> +#ifndef LIBSUPERIODETECT >> uint16_t runtime_base; >> +#endif /* ! LIBSUPERIODETECT */ >> >> > Maybe this could be moved downwards to where it is used, to save an ifndef? > IIRC this would break on some compilers which don't allow variable declarations in the middle of some code. >> Index: superiotool_libsuperiodetect/superiotool.h >> =================================================================== >> --- superiotool_libsuperiodetect/superiotool.h (Revision 5651) >> +++ superiotool_libsuperiodetect/superiotool.h (Arbeitskopie) >> @@ -98,12 +98,19 @@ >> struct superio_registers { >> int32_t superio_id; /* Signed, as we need EOT. */ >> const char *name; /* Super I/O name */ >> +#ifndef LIBSUPERIODETECT >> struct { >> int8_t ldn; >> const char *name; /* LDN name */ >> int16_t idx[IDXSIZE]; >> int16_t def[IDXSIZE]; >> } ldn[LDNSIZE]; >> +#else /* LIBSUPERIODETECT */ >> + /* Ugly hack to avoid messing with EOT markers. */ >> + struct { >> + int8_t dummy; >> + } dummy[1]; >> +#endif /* LIBSUPERIODETECT */ >> }; >> >> > hm ... the comment is very terse. > struct dummy is there to avoid putting all those LDN {EOT} markers inside #ifndef LIBSUPERIODETECT. It is a hack to allow compilation and make the patch less invasive than it would have been without struct dummy. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[PATCH] superiotool: libsuperiodetect
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

Using the superiotool code to detect SuperI/O chips can be really useful even for applications besides superiotool, e.g. flashrom. The biggest hurdle right now is the excessive size of the superiotool binary (>2.2 MB) which is still ~15 kB after lzma compression. That's simply unacceptable for a library. This minimally invasive patch makes all dumping code optional and reduces binary size for the probe-only case (libsuperiodetect) a lot. Binary sizes: 2268258 (before) 31600 (after) 98.6% reduction LZMA compressed and stripped binary sizes: 14778 (before) 6709 (after) 54.6% reduction To test compilation of superiotool with probe-only functionality, run make CONFIG_LIB=yes This patch is the first step towards libsuperiodetect, and more will have to follow. IMHO the {EOT} markers should be killed in libsuperiodetect, at least for the LDNs. Such an operation would have increased the size of the patch and would have reduced readability as well. Due to that, I skipped it, but I plan to do that in a later operation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: superiotool_libsuperiodetect/fintek.c =================================================================== --- superiotool_libsuperiodetect/fintek.c (Revision 5651) +++ superiotool_libsuperiodetect/fintek.c (Arbeitskopie) @@ -31,6 +31,7 @@ static const struct superio_registers reg_table[] = { {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ +#ifndef LIBSUPERIODETECT /* We assume reserved bits are read as 0. */ {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, @@ -75,11 +76,13 @@ {0xa, "PME, ACPI", {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ {EOT}}}, {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */ /* We assume reserved bits are read as 0. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, 0x2b,0x2c,0x2d,EOT}, @@ -121,9 +124,11 @@ {0xa, "PME, ACPI", {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, {0x00,0x00,0x01,0x06,0x1c,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0604, "F71805F/FG", { /* We assume reserved bits are read as 0. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT}, {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}}, @@ -150,6 +155,7 @@ {0xa, "PME", {0x30,0xf0,0xf1,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0581, "F8000", { /* Fintek/ASUS F8000 */ {EOT}}}, @@ -181,7 +187,9 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("Fintek", reg_table, port, did, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_winbond_fintek_ite_8787(port); } Index: superiotool_libsuperiodetect/winbond.c =================================================================== --- superiotool_libsuperiodetect/winbond.c (Revision 5651) +++ superiotool_libsuperiodetect/winbond.c (Arbeitskopie) @@ -40,6 +40,7 @@ {0x527, "W83977CTF", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x52f, "W83977EF/EG", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -78,10 +79,12 @@ 0xf0,0xf1,0xf3,0xf4,0xf6,0xf7,0xf9,0xfe,0xff,EOT}, {0x00,0x00,0x00,0x00,MISC,MISC,MISC,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x595, "W83627SF", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x601, "W83697HF/F/HG", { /* No G version? */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, 0x2a,EOT}, @@ -126,12 +129,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x610, "W83L517D/D-F", { {EOT}}}, {0x708, "W83637HF/HG", { {EOT}}}, {0x828, "W83627THF/THG", { /* We assume rev is bits 3..0 of 0x21. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -175,12 +180,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, #if 0 {0x85x, "W83687THF", { /* TODO: sensors-detect: 0x85 */ {EOT}}}, #endif {0xa02, "W83627DHG", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -232,6 +239,7 @@ EOT}, {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */ {EOT}}}, @@ -250,6 +258,7 @@ */ {EOT}}}, {0x9773, "W83977TF", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x2a,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -294,12 +303,14 @@ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, NANA,MISC,RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x9774, "W83977ATF", { {EOT}}}, /* ID only */ {0x52, "W83627HF/F/HG/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, 0x2a,0x2b,0x2c,0x2e,0x2f,EOT}, @@ -342,6 +353,7 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x68, "W83697SF/UF/UG", { /* ID: 0x68 (for W83697SF/UF/UG) @@ -349,6 +361,7 @@ * 0x0X (for W83697SF) -- sic! * 0x1X (for W83697UF/UG) */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, 0x2b,0x2c,EOT}, @@ -405,6 +418,7 @@ {0xf, "GPIO 8", {0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0xff,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x88, "W83627EHF/EF/EHG/EG", { /* @@ -414,6 +428,7 @@ * (W83627EHF) has an ID of 0x8854 (verified on hardware). * So we now assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -460,12 +475,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, /* ID[3..0] */ {0xa, "W83877F", { {EOT}}}, {0xb, "W83877AF", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -475,6 +492,7 @@ 0x1f,0x0c,0x28,0xa3,RSVD,RSVD,0x00,0x00,0x00,0x00, 0x00,0x00,0x0e,0x00,MISC,MISC,MISC,MISC,MISC,MISC, MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xc, "W83877TF", { {EOT}}}, @@ -483,6 +501,7 @@ {EOT} }; +#ifndef LIBSUPERIODETECT static const struct superio_registers hwm_table[] = { {0x828, "W83627THF/THG", { {NOLDN, NULL, @@ -531,6 +550,7 @@ {EOT}}}, {EOT} }; +#endif /* ! LIBSUPERIODETECT */ static void enter_conf_mode_winbond_88(uint16_t port) { @@ -550,7 +570,10 @@ static void probe_idregs_winbond_helper(const char *init, uint16_t port) { - uint16_t id, hwmport; + uint16_t id; +#ifndef LIBSUPERIODETECT + uint16_t hwmport; +#endif /* LIBSUPERIODETECT */ uint8_t devid, rev, olddevid; probing_for("Winbond", init, port); @@ -586,6 +609,7 @@ get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("Winbond", reg_table, port, id, LDN_SEL); if (extra_dump) { @@ -607,6 +631,7 @@ dump_superio("Winbond-HWM", hwm_table, hwmport, id, WINBOND_HWM_SEL); } +#endif /* ! LIBSUPERIODETECT */ } void probe_idregs_winbond(uint16_t port) @@ -631,5 +656,7 @@ void print_winbond_chips(void) { print_vendor_chips("Winbond", reg_table); +#ifndef LIBSUPERIODETECT print_vendor_chips("Winbond-HWM", hwm_table); +#endif /* ! LIBSUPERIODETECT */ } Index: superiotool_libsuperiodetect/ite.c =================================================================== --- superiotool_libsuperiodetect/ite.c (Revision 5651) +++ superiotool_libsuperiodetect/ite.c (Arbeitskopie) @@ -30,6 +30,7 @@ {0x8228, "IT8228E", { {EOT}}}, {0x8502, "IT8502E/TE/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -67,10 +68,12 @@ {0x17, "Power Channel 3", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8510, "IT8510E/TE/G", { {EOT}}}, {0x8511, "IT8511E/TE/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -101,8 +104,10 @@ {0x12, "Power Channel 2", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8512, "IT8512E/F/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -133,10 +138,12 @@ {0x12, "Power Channel 2", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8513, "IT8513E/F/G", { {EOT}}}, {0x8661, "IT8661F/IT8770F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, 0x23,0x24,EOT}, @@ -168,10 +175,12 @@ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8673, "IT8673F", { {EOT}}}, {0x8681, "IT8671F/IT8687R", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, 0x23,0x24,0x25,0x26,0x2e,0x2f,EOT}, @@ -211,8 +220,10 @@ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8701, "IT8703F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x26,0x29,0x2a,0x2b,EOT}, {0x87,0x00,0x00,0x80,0x00,0x00,0x7c,0xc0,EOT}}, @@ -253,10 +264,12 @@ {0xc, "GPIO set 5, 6 and 7", {0x30,0x60,0x61,0xf0,0xf3,0xf6,EOT}, {0x00,0x03,0x70,0x00,0xff,0xff,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8702, "IT8702F", { {EOT}}}, {0x8705, "IT8705F/AF / IT8700F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,EOT}, {0x87,0x05,0x00,0x00,NANA,EOT}}, @@ -303,11 +316,15 @@ {0x8, "MIDI port", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8706, "IT8706R", { /* TODO: Not yet in sensors-detect */ +#ifndef LIBSUPERIODETECT /* This is a "Special General Purpose I/O chip". */ +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8708, "IT8708F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2e,0x2f,EOT}, @@ -361,12 +378,14 @@ {0xa, "MIDI port", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8710, "IT8710F", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x8711, "IT8711F", { /* 0x8711 is a guess, not found in datasheet. */ {EOT}}}, {0x8712, "IT8712F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, @@ -416,8 +435,10 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8716, "IT8716F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x16,0x01,0x00,0x00,0x00,EOT}}, @@ -466,8 +487,10 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8718, "IT8718F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x18,0x01,0x00,0x00,0x00,EOT}}, @@ -514,6 +537,7 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8720, "IT8720F", { /* From sensors-detect */ {EOT}}}, @@ -521,6 +545,7 @@ {EOT}}}, {0x8726, "IT8726F", { /* Datasheet wrongly says that the ID is 0x8716. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x26,0x01,0x00,MISC,0x00,EOT}}, @@ -571,6 +596,7 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, @@ -579,6 +605,7 @@ {EOT} }; +#ifndef LIBSUPERIODETECT static const struct superio_registers ec_table[] = { {0x8716, "IT8716F", { {NOLDN, NULL, @@ -636,6 +663,7 @@ {EOT}}}, {EOT} }; +#endif /* ! LIBSUPERIODETECT */ /* Works for: IT8661F/IT8770F */ static const uint8_t initkey_it8661f[][4] = { @@ -712,7 +740,10 @@ static void probe_idregs_ite_helper(const char *init, uint16_t port) { - uint16_t id, chipver, ecport; + uint16_t id, chipver; +#ifndef LIBSUPERIODETECT + uint16_t ecport; +#endif /* ! LIBSUPERIODETECT */ probing_for("ITE", init, port); @@ -730,6 +761,7 @@ get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("ITE", reg_table, port, id, LDN_SEL); if (extra_dump) { @@ -745,6 +777,7 @@ printf("Environment controller (0x%04x)\n", ecport); dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL); } +#endif /* ! LIBSUPERIODETECT */ } void probe_idregs_ite(uint16_t port) @@ -783,5 +816,7 @@ void print_ite_chips(void) { print_vendor_chips("ITE", reg_table); +#ifndef LIBSUPERIODETECT print_vendor_chips("ITE-EC", ec_table); +#endif /* ! LIBSUPERIODETECT */ } Index: superiotool_libsuperiodetect/nsc.c =================================================================== --- superiotool_libsuperiodetect/nsc.c (Revision 5651) +++ superiotool_libsuperiodetect/nsc.c (Arbeitskopie) @@ -26,6 +26,7 @@ static const struct superio_registers reg_table[] = { {0xcf, "PC97307", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x27,EOT}, {0xcf,MISC,MISC,0x00,0x00,NANA,EOT}}, @@ -60,8 +61,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xd0, "PC87317", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,EOT}, {0xd0,MISC,MISC,0x00,0x00,0x00,EOT}}, @@ -96,8 +99,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xdf, "PC97317", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x27,EOT}, {0xdf,MISC,MISC,0x00,0x00,0x00,NANA,EOT}}, @@ -132,8 +137,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe0, "PC87309", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x27,0x2e,EOT}, {0xe0,MISC,0x00,NANA,RSVD,EOT}}, @@ -162,8 +169,10 @@ 0xf0,EOT}, {0x01,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04, 0x40,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe1, "PC87360", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,EOT}, @@ -206,8 +215,10 @@ {0xa, "Watchdog timer", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe2, "PC87351", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x27,0x2e,EOT}, {0xe2,0x11,0xa1,0x00,MISC,NANA,RSVD,EOT}}, @@ -240,6 +251,7 @@ {0x8, "Fan speed control", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe4, "PC87364", { {EOT}}}, @@ -248,6 +260,7 @@ {0xe8, "PC87363", { {EOT}}}, {0xe9, "PC87366", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x27,0x28,0x2a,0x2b, 0x2c,0x2d,0x2e,EOT}, @@ -304,10 +317,12 @@ {0xe, "Temperature sensor (TMS)", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ {0xea, "PC8739x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -344,12 +359,14 @@ 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,EOT}, {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xec, "PC87591x", { /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */ {EOT}}}, {0xee, "PC8741x", { /* SRID[7..5] is marked as "not applicable for the PC8741x". */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -397,10 +414,12 @@ 0xf1,0xf2,0xf3,EOT}, {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00, 0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf0, "PC87372", { {EOT}}}, {0x0f1, "PC8374L", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -441,8 +460,10 @@ {0x8, "Health management", {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8f1, "WPCD376I", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -480,9 +501,11 @@ 0xf2,0xf3,0xf8,EOT}, {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, 0x00,MISC,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf2, "PC87427", { /* SRID[7..5] is marked as "not applicable for the PC87427". */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x1d,0x20,0x21,0x22,0x23,0x24,0x25, 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, @@ -542,6 +565,7 @@ 0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, 0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf3, "PC87373", { {EOT}}}, @@ -592,8 +616,10 @@ get_superio_name(reg_table, magic), id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio(magic == 0x8f1 ? "Winbond" : "NSC", reg_table, port, magic, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ } void print_nsc_chips(void) Index: superiotool_libsuperiodetect/superiotool.c =================================================================== --- superiotool_libsuperiodetect/superiotool.c (Revision 5651) +++ superiotool_libsuperiodetect/superiotool.c (Arbeitskopie) @@ -81,6 +81,7 @@ return "<unknown>"; } +#ifndef LIBSUPERIODETECT static void dump_regs(const struct superio_registers reg_table[], int i, int j, uint16_t port, uint8_t ldn_sel) { @@ -170,6 +171,7 @@ printf("%02x ", INB(iobase + i)); printf("\n"); } +#endif /* ! LIBSUPERIODETECT */ void probing_for(const char *vendor, const char *info, uint16_t port) { @@ -189,9 +191,11 @@ for (i = 0; reg_table[i].superio_id != EOT; i++) { printf("%s %s", vendor, reg_table[i].name); +#ifndef LIBSUPERIODETECT /* Unless the ldn is empty, assume this chip has a dump. */ if (reg_table[i].ldn[0].ldn != EOT) printf(" (dump available)"); +#endif /* ! LIBSUPERIODETECT */ printf("\n"); } Index: superiotool_libsuperiodetect/ali.c =================================================================== --- superiotool_libsuperiodetect/ali.c (Revision 5651) +++ superiotool_libsuperiodetect/ali.c (Arbeitskopie) @@ -28,6 +28,7 @@ static const struct superio_registers reg_table[] = { /* TODO: M5113 doesn't seem to have ID registers? */ {0x5315, "M1535/M1535D/M1535+/M1535D+", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x1f,0x20,0x21,0x22,0x23,0x2c,0x2d,0x2e,EOT}, {NANA,0x53,0x15,0x00,0x00,RSVD,RSVD,RSVD,EOT}}, @@ -52,6 +53,7 @@ {0xc, "Hotkey", {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, {0x00,0x35,0x14,0x11,0x71,RSVD,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x2351, "M512x", { {EOT}}}, @@ -95,7 +97,9 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("ALi", reg_table, port, id, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_ali(port); } Index: superiotool_libsuperiodetect/smsc.c =================================================================== --- superiotool_libsuperiodetect/smsc.c (Revision 5651) +++ superiotool_libsuperiodetect/smsc.c (Arbeitskopie) @@ -30,6 +30,7 @@ static const struct superio_registers reg_table[] = { /* The following Super I/Os use the 0x20/0x21 ID registers. */ {0x02, "FDC37C932", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x2d,0x2e, 0x2f,EOT}, @@ -68,11 +69,13 @@ {0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00, 0x00,0x00,0x00,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, {0x0a, "FDC37N971", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -109,8 +112,10 @@ {0x9, "Mailbox", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0b, "FDC37N972", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -147,8 +152,10 @@ {0x9, "Mailbox", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0e, "LPC47N252", { /* From sensors-detect */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -188,12 +195,14 @@ {0xa, "LPC/8051 addressable GPIO (LGPIO)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x14, "LPC47M172", { {EOT}}}, {0x30, "FDC37C93xAPM", { {EOT}}}, {0x40, "FDC37C67x", { /* E.g. FDC37C672. Chiprev: 0x01 */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b,0x2c, 0x2d,0x2e,0x2f,EOT}, @@ -225,10 +234,12 @@ {0x00,NANA,NANA,NANA,NANA,0x06,0x03,NANA,NANA,NANA, 0x00,0x00,0x00,MISC,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD, EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x42, "FDC37B80x/FDC37M707", { {EOT}}}, {0x09, "FDC37N958FR", { /* Found in e.g. Dell Latitude CPi A366XT. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -270,10 +281,12 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x43, "FDC37B77x", { {EOT}}}, {0x44, "FDC37B78x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -315,12 +328,14 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x46, "FDC37M602", { /* Found in Biostar M6TLD. */ {EOT}}}, {0x47, "FDC37M60x", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x4c, "FDC37B72x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -357,8 +372,10 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x4d, "FDC37M81x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b,0x2c, 0x2d,0x2e,0x2f,EOT}, @@ -389,8 +406,10 @@ {0x00,NANA,NANA,NANA,NANA,0x02,0x01,NANA,NANA,NANA, NANA,NANA,NANA,NANA,0x00,0x00,0x00,0x00,RSVD,RSVD, RSVD,RSVD,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x51, "LPC47B27x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -424,10 +443,12 @@ {0xb, "MIDI port (MPU-401)", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x52, "LPC47B37x", { {EOT}}}, {0x54, "LPC47U33x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2a,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -459,12 +480,14 @@ {0xb, "SMBus", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x56, "LPC47B34x", { {EOT}}}, {0x57, "LPC47S42x", { {EOT}}}, {0x59, "LPC47M10x/112/13x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -498,12 +521,14 @@ {0xb, "MPU-401", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x5d, "LPC47B357", { /* From sensors-detect (no datasheet) */ {EOT}}}, {0x5f, "LPC47M14x", { {EOT}}}, {0x60, "LPC47M15x/192/997", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -535,6 +560,7 @@ {0xb, "MPU-401", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x62, "LPC47S45x", { {EOT}}}, @@ -550,6 +576,7 @@ {0x6f, "LPC47B397", { {EOT}}}, {0x74, "LPC47M182", { /* Only for LD_NUM = 0 */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27, 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -584,10 +611,12 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x76, "LPC47M584", { /* From sensors-detect (no datasheet) */ {EOT}}}, {0x77, "A8000", { /* ASUS A8000, a rebranded DME1737(?) */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -613,8 +642,10 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x78, "DME1737", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -640,6 +671,7 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x79, "SCH5504", { /* From sensors-detect (no datasheet) */ {EOT}}}, @@ -682,6 +714,7 @@ {EOT}}}, {0x28, "FDC37N769", { /* Init: 0x55. Exit: 0xaa. Ports: 0x3f0/0x370. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -693,12 +726,14 @@ NANA,NANA,NANA,0x03,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD, 0x80,0x00,0x3c,RSVD,RSVD,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,RSVD,0x00,0x00,0x03,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x29, "FDC37N3869/FDC37N869", { /* Init: 0x55. Exit: 0xaa. Ports: 0x3f0/0x370. */ {EOT}}}, {0x5a, "LPC47N227", { /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -712,9 +747,11 @@ RSVD,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x80,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x5b, "SIO10N268", { /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -734,6 +771,7 @@ 0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,0x50, NANA,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x01, 0x00,0x01,0x00,0x8c,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x65, "FDC37C665GT/IR", { /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. */ @@ -765,7 +803,9 @@ uint8_t revreg) { uint8_t id, rev; +#ifndef LIBSUPERIODETECT uint16_t runtime_base; +#endif /* ! LIBSUPERIODETECT */ const char *info = (idreg == 0x20) ? "(idregs=0x20/0x21) " : "(idregs=0x0d/0x0e) "; @@ -788,6 +828,7 @@ id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id, LDN_SEL); @@ -804,6 +845,7 @@ printf("No extra registers known for this chip.\n"); } } +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_smsc(port); } Index: superiotool_libsuperiodetect/superiotool.h =================================================================== --- superiotool_libsuperiodetect/superiotool.h (Revision 5651) +++ superiotool_libsuperiodetect/superiotool.h (Arbeitskopie) @@ -98,12 +98,19 @@ struct superio_registers { int32_t superio_id; /* Signed, as we need EOT. */ const char *name; /* Super I/O name */ +#ifndef LIBSUPERIODETECT struct { int8_t ldn; const char *name; /* LDN name */ int16_t idx[IDXSIZE]; int16_t def[IDXSIZE]; } ldn[LDNSIZE]; +#else /* LIBSUPERIODETECT */ + /* Ugly hack to avoid messing with EOT markers. */ + struct { + int8_t dummy; + } dummy[1]; +#endif /* LIBSUPERIODETECT */ }; /* pci.c */ Index: superiotool_libsuperiodetect/Makefile =================================================================== --- superiotool_libsuperiodetect/Makefile (Revision 5651) +++ superiotool_libsuperiodetect/Makefile (Arbeitskopie) @@ -32,6 +32,10 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) +ifeq ($(CONFIG_LIB), yes) +CFLAGS += -D'LIBSUPERIODETECT=1' +endif + OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o OS_ARCH = $(shell uname) -- http://www.hailfinger.org/

2 3

Re: [flashrom] Support of COM/LPT bit-bang SPI programmers in flashrom
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

On 29.06.2010 20:13, Andrew wrote: > 29.06.2010 20:18, Carl-Daniel Hailfinger пишет: >> would it be OK with you if I move this discussion to the flashrom >> mailing list? >> > Yes, it'll be good. Thanks. >> On 29.06.2010 19:11, Andrew wrote: >>> Is it possible to add support of some low-cost serial (for ex., >>> SI-Prog) >>> and parallel (for ex., Altera Byteblaster) SPI programming/interfacing >>> >> Yes. I have code for SPI bitbanging on the parallel port, but nobody has >> time to test. >> > I can test it in near future - I have some SPI flashes, and I have > 'universal' programmer (bunch of wires with protection resistors, 3.3V > power stabilizer and separate pins to connect to LPT holes - I use it > with SPIPGM; I assembled it when I need to program one SPI flash from MB) Oh, nice. I will update the SPIPGM support patch for flashrom and it would be great if you could test it. >>> devices? It'll be very useful (due to it's very simple schematic), and >>> IMHO it won't be much work to add them... >>> >> Sure. If someone sends me those devices, I can implement support for >> them. Or someone else uses my RayeR SPIPGM patch for flashrom and >> extends/changes it so it works with the Altera Byteblaster. >> > SPIPGM differs from ByteBlaster only by some LPT pins. + buffer. > Pinout for ByteBlasterMV: > JTAG (SPI) pins: > D0 -> TCK (SCK) > D1 -> TMS (CS-? or NC) > D6 -> TDI (SI) > Busy -> TDO (SO) > > Programmer pins (hardware detection): > D5 -> nACK > D7 -> PE (PaperEnd) via buffer (checking if buffer powered and > working) > nAutoFd -> buffer on (active in low) > nError -> pull-up to Vcc This can be supported easily by duplicating my SPIPGM driver. > For SI-Prog connection is also very simple: > SPI pins: > DSR -> SCK > DTR -> SI > CTS -> SO > > Programmer pins (hardware detection): > DSR -> RTS How does the SI-Prog handle CS? > About programmer detection pins - IMHO it'll be good to make hardware > detection, but just report hardware failure, not to break programming > process. Yes, a sanity check makes sense. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

Re: [flashrom] [PATCH] Check that the expected winbond Super I/O was found
by Carl-Daniel Hailfinger 29 Jun '10

29 Jun '10

On 29.06.2010 14:01, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom