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[PATCH] Safety checks for SPI bitbang init
by Carl-Daniel Hailfinger 18 Jul '10

18 Jul '10

Check during SPI bitbang init that SPI bitbang master configuration is correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_init_errorcheck/flash.h =================================================================== --- flashrom-bitbang_spi_init_errorcheck/flash.h (Revision 1091) +++ flashrom-bitbang_spi_init_errorcheck/flash.h (Arbeitskopie) @@ -128,7 +128,7 @@ void programmer_delay(int usecs); enum bitbang_spi_master_type { - BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ + BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ }; struct bitbang_spi_master { Index: flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c =================================================================== --- flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c (Revision 1091) +++ flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c (Arbeitskopie) @@ -54,6 +54,16 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { + /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, + * we catch it here. Same goes for missing initialization of bitbanging + * functions. + */ + if (!master || master->type == BITBANG_SPI_INVALID || !master->set_cs || + !master->set_sck || !master->set_mosi || !master->get_miso) { + msg_perr("Incomplete bitbanging SPI master setting! Please " + "report a bug at flashrom(a)flashrom.org\n"); + return 1; + } bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; -- http://www.hailfinger.org/

2 2

[commit] r1092 - trunk
by repository service 18 Jul '10

18 Jul '10

Author: hailfinger Date: Sun Jul 18 16:42:28 2010 New Revision: 1092 URL: http://flashrom.org/trac/coreboot/changeset/1092 Log: Check during SPI bitbang init that SPI bitbang master configuration is correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/bitbang_spi.c trunk/flash.h Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sun Jul 18 01:27:47 2010 (r1091) +++ trunk/bitbang_spi.c Sun Jul 18 16:42:28 2010 (r1092) @@ -54,6 +54,16 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { + /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, + * we catch it here. Same goes for missing initialization of bitbanging + * functions. + */ + if (!master || master->type == BITBANG_SPI_INVALID || !master->set_cs || + !master->set_sck || !master->set_mosi || !master->get_miso) { + msg_perr("Incomplete bitbanging SPI master setting! Please " + "report a bug at flashrom(a)flashrom.org\n"); + return 1; + } bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 01:27:47 2010 (r1091) +++ trunk/flash.h Sun Jul 18 16:42:28 2010 (r1092) @@ -128,7 +128,7 @@ void programmer_delay(int usecs); enum bitbang_spi_master_type { - BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ + BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ }; struct bitbang_spi_master {

1 0

[PATCH 3/3] kill central list of SPI programmers
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- buspirate_spi.c | 18 +++++++-- dediprog.c | 15 ++++++- dummyflasher.c | 18 +++++++-- flash.h | 49 ++--------------------- flashrom.c | 4 -- ft2232_spi.c | 11 +++++- ichspi.c | 56 +++++++++++++++++++-------- it87spi.c | 18 +++++++-- sb600spi.c | 17 ++++++-- spi.c | 115 +++++-------------------------------------------------- spi25.c | 4 +- wbsio_spi.c | 16 ++++++- 12 files changed, 146 insertions(+), 195 deletions(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index 55e71c2..36eaa9a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) #define sp_flush_incoming(...) 0 #endif +static const struct spi_programmer spi_programmer_buspirate; + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -210,7 +212,7 @@ int buspirate_spi_init(void) } buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + spi_programmer = &spi_programmer_buspirate; return 0; } @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_read_chunked(flash, buf, start, len, 12); } -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 12); } + +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = buspirate_spi_read, + .write_256 = buspirate_spi_write_256, +}; diff --git a/dediprog.c b/dediprog.c index 0b92983..c21c801 100644 --- a/dediprog.c +++ b/dediprog.c @@ -25,6 +25,7 @@ #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; +static const struct spi_programmer spi_programmer_dediprog; #if 0 /* Might be useful for other pieces of code as well. */ @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) } #endif -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); /* Chosen read length is 16 bytes for now. */ return spi_read_chunked(flash, buf, start, len, 16); } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -318,7 +319,7 @@ int dediprog_init(void) return 1; buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + spi_programmer = &spi_programmer_dediprog; /* RE leftover, leave in until the driver is complete. */ #if 0 @@ -394,3 +395,11 @@ int dediprog_shutdown(void) } return 0; } + +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = spi_chip_write_1_new, +}; diff --git a/dummyflasher.c b/dummyflasher.c index 241dcee..b1bbcf2 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -25,6 +25,8 @@ #include "flash.h" #include "chipdrivers.h" +static const struct spi_programmer spi_programmer_dummy; + static void tolower_string(char *str) { for (; *str != '\0'; str++) @@ -59,7 +61,7 @@ int dummy_init(void) } if (strstr(bustext, "spi")) { buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + spi_programmer = &spi_programmer_dummy; msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) return; } -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is unlimited, use 64kB. */ return spi_read_chunked(flash, buf, start, len, 64 * 1024); @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) * never be successful, and the current frontend refuses to write in that case. * Other frontends may allow writing even for non-detected chips, though. */ -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 256); } + +static const struct spi_programmer spi_programmer_dummy = { + .type = SPI_CONTROLLER_DUMMY, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dummy_spi_read, + .write_256 = dummy_spi_write_256, +}; diff --git a/flash.h b/flash.h index 8ebea29..fb06207 100644 --- a/flash.h +++ b/flash.h @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; #define FTDI_FT2232H 0x6010 #define FTDI_FT4232H 0x6011 int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); @@ -544,15 +537,10 @@ struct buspirate_spispeeds { }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ enum write_granularity { @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ enum spi_controller { - SPI_CONTROLLER_NONE, -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 SPI_CONTROLLER_FT2232, -#endif -#if CONFIG_DUMMY == 1 SPI_CONTROLLER_DUMMY, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 SPI_CONTROLLER_BUSPIRATE, -#endif -#if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, -#endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; -extern const int spi_programmer_count; + struct spi_command { unsigned int writecnt; unsigned int readcnt; @@ -660,6 +634,7 @@ struct spi_command { unsigned char *readarr; }; struct spi_programmer { + enum spi_controller type; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -669,8 +644,8 @@ struct spi_programmer { int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +const struct spi_programmer *spi_programmer; + int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, int ich_generation); int via_init_spi(struct pci_dev * dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); -int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); struct superio probe_superio_ite(void); int init_superio_ite(void); int it87spi_init(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ void sb600_probe_spi(struct pci_dev * dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* serprog.c */ int serprog_init(void); diff --git a/flashrom.c b/flashrom.c index fe173a7..dc262d5 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1354,10 +1354,6 @@ int selfcheck(void) msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; diff --git a/ft2232_spi.c b/ft2232_spi.c index c8711e9..b45ba42 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -45,6 +45,7 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 +static const struct spi_programmer spi_programmer_ft2232; static struct ftdi_context ftdic_context; static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) @@ -192,7 +193,7 @@ int ft2232_spi_init(void) // msg_pdbg("\nft2232 chosen\n"); buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + spi_programmer = &spi_programmer_ft2232; return 0; } @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l return spi_write_chunked(flash, buf, start, len, 256); } +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ft2232_spi_read, + .write_256 = ft2232_spi_write_256, +}; + #endif diff --git a/ichspi.c b/ichspi.c index 246f3ae..2627c60 100644 --- a/ichspi.c +++ b/ichspi.c @@ -234,7 +234,7 @@ static int generate_opcodes(OPCODES * op) return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -309,7 +309,7 @@ int program_opcodes(OPCODES * op) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: REGWRITE16(ICH7_REG_PREOP, preop); @@ -337,7 +337,7 @@ int program_opcodes(OPCODES * op) */ void ich_set_bbar(uint32_t minaddr) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: mmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); @@ -448,19 +448,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, switch (ich_generation) { case 7: buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; + spi_programmer = &spi_programmer_ich7; spibar_offset = 0x3020; break; case 8: buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3800; break; } @@ -471,7 +471,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -600,7 +600,7 @@ int via_init_spi(struct pci_dev * dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + spi_programmer = &spi_programmer_via; ich_init_opcodes(); return 0; @@ -848,7 +848,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -881,27 +881,27 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_read_chunked(flash, buf, start, len, maxdata); } -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_write_chunked(flash, buf, start, len, maxdata); } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -966,7 +966,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: if (addr < ichspi_bbar) { @@ -1001,7 +1001,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1071,4 +1071,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) return ret; } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + #endif diff --git a/it87spi.c b/it87spi.c index cf3d3b9..dddb5a9 100644 --- a/it87spi.c +++ b/it87spi.c @@ -34,6 +34,8 @@ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +static const struct spi_programmer spi_programmer_it87xx; + uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ static int fast_spi = 1; @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; + spi_programmer = &spi_programmer_it87xx; buses_supported |= CHIP_BUSTYPE_SPI; return 0; } @@ -227,7 +229,7 @@ int it87spi_init(void) * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int total_size = 1024 * flash->total_size; fast_spi = 0; @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + #endif diff --git a/sb600spi.c b/sb600spi.c index e42b20b..866e309 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -41,6 +41,7 @@ */ static uint8_t *sb600_spibar = NULL; +static const struct spi_programmer spi_programmer_sb600; void sb600_probe_spi(struct pci_dev * dev) { @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) return; buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + spi_programmer = &spi_programmer_sb600; } -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is 8 bytes. */ return spi_read_chunked(flash, buf, start, len, 8); } -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 5); } @@ -144,7 +145,7 @@ static void execute_command(void) ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = sb600_spi_read, + .write_256 = sb600_spi_write_256, +}; + #endif diff --git a/spi.c b/spi.c index 2b64463..dc4da9f 100644 --- a/spi.c +++ b/spi.c @@ -27,129 +27,34 @@ #include "chipdrivers.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - void spi_prettyprint_status_register(struct flashchip *flash); -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ -}; - -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].read(flash, buf, start, len); + return spi_programmer->read(flash, buf, start, len); } /* @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* Wrapper function until the generic code is converted to partial writes. */ @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: diff --git a/spi25.c b/spi25.c index 32bb73c..d9dae35 100644 --- a/spi25.c +++ b/spi25.c @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: diff --git a/wbsio_spi.c b/wbsio_spi.c index b8f8b38..6288340 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -28,6 +28,7 @@ #define WBSIO_PORT2 0x4e static uint16_t wbsio_spibase = 0; +static const struct spi_programmer spi_programmer_wbsio; static uint16_t wbsio_get_spibase(uint16_t port) { @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + spi_programmer = &spi_programmer_wbsio; msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); } +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1_new, +}; + + #endif -- 1.7.1

1 0

[PATCH 2/3] Move SB600 SPI initialization to sb600spi.c
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 79 ++--------------------------------------------------- flash.h | 2 +- sb600spi.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 80 insertions(+), 78 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 7434d65..ad3b732 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -683,10 +683,8 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, prot; + uint32_t prot; uint8_t reg; - struct pci_dev *smbus_dev; - int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -710,80 +708,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } - /* Read SPI_BaseAddr */ - tmp = pci_read_long(dev, 0xa0); - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - msg_pdbg("SPI base address is at 0x%x\n", tmp); - - /* If the BAR has address 0, it is unlikely SPI is used. */ - if (!tmp) - has_spi = 0; - - if (has_spi) { - /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); - /* The low bits of the SPI base address are used as offset into - * the mapped page. - */ - sb600_spibar += tmp & 0xfff; - - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - } - - /* Look for the SMBus device. */ - smbus_dev = pci_dev_find(0x1002, 0x4385); - - if (has_spi && !smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - has_spi = 0; - } - if (has_spi) { - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ - reg = pci_read_byte(smbus_dev, 0xAB); - reg &= 0xC0; - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); - if (reg != 0x00) - has_spi = 0; - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ - reg = pci_read_byte(smbus_dev, 0x83); - reg &= 0xC0; - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); - /* SPI_HOLD is not used on all boards, filter it out. */ - if ((reg & 0x80) != 0x00) - has_spi = 0; - /* GPIO47/SPI_CLK status */ - reg = pci_read_byte(smbus_dev, 0xA7); - reg &= 0x40; - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); - if (reg != 0x00) - has_spi = 0; - } - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; - if (has_spi) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; - } + + sb600_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); diff --git a/flash.h b/flash.h index a8ca6d7..8ebea29 100644 --- a/flash.h +++ b/flash.h @@ -702,11 +702,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +void sb600_probe_spi(struct pci_dev * dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -extern uint8_t *sb600_spibar; /* wbsio_spi.c */ int wbsio_check_for_spi(void); diff --git a/sb600spi.c b/sb600spi.c index caf1a99..e42b20b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -40,7 +40,82 @@ *}; */ -uint8_t *sb600_spibar = NULL; +static uint8_t *sb600_spibar = NULL; + +void sb600_probe_spi(struct pci_dev * dev) +{ + struct pci_dev *smbus_dev; + uint32_t tmp; + uint8_t reg; + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ + msg_pdbg("SPI base address is at 0x%x\n", tmp); + + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + return; + + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return; + } + + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) + return; + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + /* SPI_HOLD is not used on all boards, filter it out. */ + if ((reg & 0x80) != 0x00) + return; + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) + return; + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_SB600; +} int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { -- 1.7.1

1 0

[PATCH 1/3] Move Intel SPI initialisation to ichspi.c
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 202 +-------------------------------------------------- flash.h | 6 +- ichspi.c | 214 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 218 insertions(+), 204 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index dc0e55f..7434d65 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -417,69 +417,15 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - uint32_t mmio_base; - /* Do we really need no write enable? */ - mmio_base = (pci_read_long(dev, 0xbc)) << 8; - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(ich_spibar + 0x6c)); - - /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; - ich_init_opcodes(); - - return 0; -} - -#define ICH_BMWAG(x) ((x >> 24) & 0xff) -#define ICH_BMRAG(x) ((x >> 16) & 0xff) -#define ICH_BRWA(x) ((x >> 8) & 0xff) -#define ICH_BRRA(x) ((x >> 0) & 0xff) - -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - -static void do_ich9_spi_frap(uint32_t frap, int i) -{ - const char *access_names[4] = { - "locked", "read-only", "write-only", "read-write" - }; - const char *region_names[5] = { - "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" - }; - uint32_t base, limit; - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | - (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset); - - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", - offset, freg, i, region_names[i]); - - base = ICH_FREG_BASE(freg); - limit = ICH_FREG_LIMIT(freg); - if (base == 0x1fff && limit == 0) { - /* this FREG is disabled */ - msg_pdbg("%s region is unused.\n", region_names[i]); - return; - } - - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + return via_init_spi(dev); } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { - int ret, i; - uint8_t old, new, bbs, buc; - uint16_t spibar_offset, tmp2; + int ret; + uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line @@ -518,147 +464,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, return ret; } - switch (ich_generation) { - case 7: - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; - spibar_offset = 0x3020; - break; - case 8: - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3020; - break; - case 9: - case 10: - default: /* Future version might behave the same */ - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3800; - break; - } - - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); - - /* Assign Virtual Address */ - ich_spibar = rcrb + spibar_offset; - - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(ich_spibar + 0)); - msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(ich_spibar + 2)); - msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(ich_spibar + 4)); - for (i = 0; i < 8; i++) { - int offs; - offs = 8 + (i * 8); - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(ich_spibar + offs + 4), i); - } - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x54)); - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x56)); - msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x58)); - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { - int offs; - offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - } - msg_pdbg("\n"); - if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - - tmp = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); - - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - default: - /* Nothing */ - break; - } - - old = pci_read_byte(dev, 0xdc); - msg_pdbg("SPI Read Configuration: "); - new = (old >> 2) & 0x3; - switch (new) { - case 0: - case 1: - case 2: - msg_pdbg("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", - (new & 0x1) ? "dis" : "en"); - break; - default: - msg_pdbg("invalid prefetching/caching settings, "); - break; - } - + ich_init_spi(dev, tmp, rcrb, ich_generation); return ret; } diff --git a/flash.h b/flash.h index c3302c4..a8ca6d7 100644 --- a/flash.h +++ b/flash.h @@ -680,10 +680,10 @@ int default_spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ -extern int ichspi_lock; extern uint32_t ichspi_bbar; -extern void *ich_spibar; -int ich_init_opcodes(void); +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, + int ich_generation); +int via_init_spi(struct pci_dev * dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); diff --git a/ichspi.c b/ichspi.c index d6f9118..246f3ae 100644 --- a/ichspi.c +++ b/ichspi.c @@ -101,11 +101,11 @@ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ -int ichspi_lock = 0; +static int ichspi_lock = 0; uint32_t ichspi_bbar = 0; -void *ich_spibar = NULL; +static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode @@ -364,7 +364,7 @@ void ich_set_bbar(uint32_t minaddr) * * It should be called before ICH sends any spi command. */ -int ich_init_opcodes(void) +static int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; @@ -398,6 +398,214 @@ int ich_init_opcodes(void) } } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(ich_spibar + offset); + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, + int ich_generation) +{ + int i; + uint8_t old, new; + uint16_t spibar_offset, tmp2; + uint32_t tmp; + + switch (ich_generation) { + case 7: + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH7; + spibar_offset = 0x3020; + break; + case 8: + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3020; + break; + case 9: + case 10: + default: /* Future version might behave the same */ + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3800; + break; + } + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); + + /* Assign Virtual Address */ + ich_spibar = rcrb + spibar_offset; + + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + msg_pdbg("0x00: 0x%04x (SPIS)\n", + mmio_readw(ich_spibar + 0)); + msg_pdbg("0x02: 0x%04x (SPIC)\n", + mmio_readw(ich_spibar + 2)); + msg_pdbg("0x04: 0x%08x (SPIA)\n", + mmio_readl(ich_spibar + 4)); + for (i = 0; i < 8; i++) { + int offs; + offs = 8 + (i * 8); + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + mmio_readl(ich_spibar + offs + 4), i); + } + ichspi_bbar = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0x54: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x54)); + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x56)); + msg_pdbg("0x58: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x58)); + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x5c)); + for (i = 0; i < 4; i++) { + int offs; + offs = 0x60 + (i * 4); + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + } + msg_pdbg("\n"); + if (mmio_readw(ich_spibar) & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + case SPI_CONTROLLER_ICH9: + tmp2 = mmio_readw(ich_spibar + 4); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + + tmp = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + + msg_pdbg("0x74: 0x%08x (PR0)\n", + mmio_readl(ich_spibar + 0x74)); + msg_pdbg("0x78: 0x%08x (PR1)\n", + mmio_readl(ich_spibar + 0x78)); + msg_pdbg("0x7C: 0x%08x (PR2)\n", + mmio_readl(ich_spibar + 0x7C)); + msg_pdbg("0x80: 0x%08x (PR3)\n", + mmio_readl(ich_spibar + 0x80)); + msg_pdbg("0x84: 0x%08x (PR4)\n", + mmio_readl(ich_spibar + 0x84)); + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", + mmio_readl(ich_spibar + 0x90)); + msg_pdbg("0x94: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x94)); + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x96)); + msg_pdbg("0x98: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x98)); + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0xB0: 0x%08x (FDOC)\n", + mmio_readl(ich_spibar + 0xB0)); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + default: + /* Nothing */ + break; + } + + old = pci_read_byte(dev, 0xdc); + msg_pdbg("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + msg_pdbg("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", + (new & 0x1) ? "dis" : "en"); + break; + default: + msg_pdbg("invalid prefetching/caching settings, "); + break; + } +} + +int via_init_spi(struct pci_dev * dev) +{ + uint32_t mmio_base; + + mmio_base = (pci_read_long(dev, 0xbc)) << 8; + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", + mmio_readw(ich_spibar + 0x6c)); + + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_VIA; + ich_init_opcodes(); + + return 0; +} + static int ich7_run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data, int maxdata) { -- 1.7.1

1 0

i think i made a mistake
by Antoine Visier 18 Jul '10

18 Jul '10

Hello. Sorry for my stupidity, and my english, i don't speak very well. Today, i tryed to update the bios of my computer. I used flashrom. I 've probably made a mistake and now i got an error message. My computer is the MP945-X The bios version i used is R1.14 and the release date is 4/25/2007 I followed this page : http://doc.ubuntu-fr.org/flasher_le_bios I download the latest version of the bios located on the Aopen download website. http://download.aopen.com.tw/userdownload_List.aspx?RecNo=11314&Model=2210 I unzip the wiab1e.zip and i used the file named IAB1E.BIN (i don't use the two other .exe files) After the first error message, i tried to return to the inital bios (i've got two backup, called* *backup.bin and A7Tversion.ROM) I put the file i used attached to this mail. I 've typed those commands : @a-desktop:~$* sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ *sudo flashrom* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. No operations were specified. a@a-desktop:~$ *sudo flashrom -r backup.bin* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Reading flash... done. a@a-desktop:~$ sudo dmidecode -s bios-version i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ *sudo flashrom -w IAB1E.BIN * flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo flashrom -w backup.bin* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$* sudo flashrom -w A7Tversion.ROM * flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ sudo flashrom -w IAB1E.BIN flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. Thanks for any help. I keep my computer on Antoine ---- Attachments have been stripped: "IAB1E.BIN", "backup.bin", "A7Tversion.ROM"

2 1

Re: [flashrom] [PATCH] Use struct pointer instead of enum to set bitbang adapter
by Carl-Daniel Hailfinger 18 Jul '10

18 Jul '10

On 18.07.2010 01:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for the patch. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1091 - trunk
by repository service 18 Jul '10

18 Jul '10

Author: mkarcher Date: Sun Jul 18 01:27:47 2010 New Revision: 1091 URL: http://flashrom.org/trac/coreboot/changeset/1091 Log: Use struct pointer instead of enum to set bitbang adapter Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/bitbang_spi.c trunk/flash.h trunk/flashrom.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/bitbang_spi.c Sun Jul 18 01:27:47 2010 (r1091) @@ -29,45 +29,34 @@ /* Length of half a clock period in usecs. */ static int bitbang_spi_half_period; -static enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; - -static const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { - {}, /* This entry corresponds to BITBANG_SPI_INVALID. */ -}; - -const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table); +static const struct bitbang_spi_master *bitbang_spi_master = NULL; /* Note that CS# is active low, so val=0 means the chip is active. */ static void bitbang_spi_set_cs(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_cs(val); + bitbang_spi_master->set_cs(val); } static void bitbang_spi_set_sck(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_sck(val); + bitbang_spi_master->set_sck(val); } static void bitbang_spi_set_mosi(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_mosi(val); + bitbang_spi_master->set_mosi(val); } static int bitbang_spi_get_miso(void) { - return bitbang_spi_master_table[bitbang_spi_master].get_miso(); + return bitbang_spi_master->get_miso(); } -int bitbang_spi_init(enum bitbang_spi_master master, int halfperiod) +int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - if (bitbang_spi_master == BITBANG_SPI_INVALID) { - msg_perr("Invalid bitbang SPI master. \n" - "Please report a bug at flashrom(a)flashrom.org\n"); - return 1; - } bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/flash.h Sun Jul 18 01:27:47 2010 (r1091) @@ -127,13 +127,14 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); -enum bitbang_spi_master { - BITBANG_SPI_INVALID /* This must always be the last entry. */ +enum bitbang_spi_master_type { + BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ }; -extern const int bitbang_spi_master_count; +struct bitbang_spi_master { + enum bitbang_spi_master_type type; -struct bitbang_spi_master_entry { + /* Note that CS# is active low, so val=0 means the chip is active. */ void (*set_cs) (int val); void (*set_sck) (int val); void (*set_mosi) (int val); @@ -531,7 +532,7 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ -int bitbang_spi_init(enum bitbang_spi_master master, int halfperiod); +int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/flashrom.c Sun Jul 18 01:27:47 2010 (r1091) @@ -1358,12 +1358,6 @@ msg_gerr("SPI programmer table miscompilation!\n"); ret = 1; } -#if CONFIG_BITBANG_SPI == 1 - if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { - msg_gerr("Bitbanging SPI master table miscompilation!\n"); - ret = 1; - } -#endif for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1;

1 0

[PATCH] Print supported flash chips as narrow as possible
by Carl-Daniel Hailfinger 18 Jul '10

18 Jul '10

Print supported flash chips as narrow as possible. Fix a bug where 4 GB of spaces would be printed per line if a vendor name was longer than 10 chars. This patch (or a smaller version) is needed to commit MoselVitelic chip support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-chiplist_narrow/print.c =================================================================== --- flashrom-chiplist_narrow/print.c (Revision 1087) +++ flashrom-chiplist_narrow/print.c (Arbeitskopie) @@ -76,26 +76,33 @@ static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; + int maxchiplen = 0, maxvendorlen = 0; struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { - if (GENERIC_DEVICE_ID == f->model_id) + /* Ignore "unknown XXXX SPI chip" entries. */ + if (!strncmp(f->name, "unknown", 7)) continue; - okcol = max(okcol, strlen(f->vendor) + 1 + strlen(f->name)); + chipcount++; + maxvendorlen = max(maxvendorlen, strlen(f->vendor)); + maxchiplen = max(maxchiplen, strlen(f->name)); } - okcol = (okcol + 7) & ~7; + maxvendorlen++; + maxchiplen++; + okcol = maxvendorlen + maxchiplen; - for (f = flashchips; f->name != NULL; f++) - chipcount++; - printf("\nSupported flash chips (total: %d):\n\n", chipcount); - POS_PRINT("Vendor: Device:"); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); - } + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + printf("Device"); + for (i = strlen("Device"); i < maxchiplen; i++) + printf(" "); - printf("Tested OK:\tKnown BAD: Size/KB: Type:\n\n"); + printf("Tested Known Size/KB: Type:\n"); + for (i = 0; i < okcol; i++) + printf(" "); + printf("OK Broken\n\n"); printf("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); for (f = flashchips; f->name != NULL; f++) { @@ -104,15 +111,13 @@ continue; printf("%s", f->vendor); - for (i = 0; i < 10 - strlen(f->vendor); i++) + for (i = strlen(f->vendor); i < maxvendorlen; i++) printf(" "); printf("%s", f->name); + for (i = strlen(f->name); i < maxchiplen; i++) + printf(" "); - pos = 10 + strlen(f->name); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); - } + pos = maxvendorlen + maxchiplen; if ((f->tested & TEST_OK_MASK)) { if ((f->tested & TEST_OK_PROBE)) POS_PRINT("P "); @@ -124,21 +129,25 @@ POS_PRINT("W "); } while (pos < okcol + 9) { - printf("\t"); - pos += 8 - (pos % 8); + printf(" "); + pos++; } if ((f->tested & TEST_BAD_MASK)) { if ((f->tested & TEST_BAD_PROBE)) - printf("P "); + POS_PRINT("P "); if ((f->tested & TEST_BAD_READ)) - printf("R "); + POS_PRINT("R "); if ((f->tested & TEST_BAD_ERASE)) - printf("E "); + POS_PRINT("E "); if ((f->tested & TEST_BAD_WRITE)) - printf("W "); + POS_PRINT("W "); } - printf("\t %d", f->total_size); + while (pos < okcol + 18) { + printf(" "); + pos++; + } + printf("%d", f->total_size); for (i = 0; i < 10 - digits(f->total_size); i++) printf(" "); printf("%s\n", flashbuses_to_text(f->bustype)); -- http://www.hailfinger.org/

2 2

[commit] r1090 - trunk
by repository service 18 Jul '10

18 Jul '10

Author: hailfinger Date: Sun Jul 18 01:21:12 2010 New Revision: 1090 URL: http://flashrom.org/trac/coreboot/changeset/1090 Log: Print supported flash chips as narrow as possible. Fix a bug where 4 GB of spaces would be printed per line if a vendor name was longer than 10 chars. This patch is needed to commit MoselVitelic chip support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print.c Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 18 00:42:33 2010 (r1089) +++ trunk/print.c Sun Jul 18 01:21:12 2010 (r1090) @@ -76,26 +76,33 @@ static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; + int maxchiplen = 0, maxvendorlen = 0; struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { - if (GENERIC_DEVICE_ID == f->model_id) + /* Ignore "unknown XXXX SPI chip" entries. */ + if (!strncmp(f->name, "unknown", 7)) continue; - okcol = max(okcol, strlen(f->vendor) + 1 + strlen(f->name)); - } - okcol = (okcol + 7) & ~7; - - for (f = flashchips; f->name != NULL; f++) chipcount++; - - printf("\nSupported flash chips (total: %d):\n\n", chipcount); - POS_PRINT("Vendor: Device:"); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); + maxvendorlen = max(maxvendorlen, strlen(f->vendor)); + maxchiplen = max(maxchiplen, strlen(f->name)); } + maxvendorlen++; + maxchiplen++; + okcol = maxvendorlen + maxchiplen; - printf("Tested OK:\tKnown BAD: Size/KB: Type:\n\n"); + printf("\nSupported flash chips (total: %d):\n\n", chipcount); + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + printf("Device"); + for (i = strlen("Device"); i < maxchiplen; i++) + printf(" "); + + printf("Tested Known Size/KB: Type:\n"); + for (i = 0; i < okcol; i++) + printf(" "); + printf("OK Broken\n\n"); printf("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); for (f = flashchips; f->name != NULL; f++) { @@ -104,15 +111,13 @@ continue; printf("%s", f->vendor); - for (i = 0; i < 10 - strlen(f->vendor); i++) + for (i = strlen(f->vendor); i < maxvendorlen; i++) printf(" "); printf("%s", f->name); + for (i = strlen(f->name); i < maxchiplen; i++) + printf(" "); - pos = 10 + strlen(f->name); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); - } + pos = maxvendorlen + maxchiplen; if ((f->tested & TEST_OK_MASK)) { if ((f->tested & TEST_OK_PROBE)) POS_PRINT("P "); @@ -124,21 +129,25 @@ POS_PRINT("W "); } while (pos < okcol + 9) { - printf("\t"); - pos += 8 - (pos % 8); + printf(" "); + pos++; } if ((f->tested & TEST_BAD_MASK)) { if ((f->tested & TEST_BAD_PROBE)) - printf("P "); + POS_PRINT("P "); if ((f->tested & TEST_BAD_READ)) - printf("R "); + POS_PRINT("R "); if ((f->tested & TEST_BAD_ERASE)) - printf("E "); + POS_PRINT("E "); if ((f->tested & TEST_BAD_WRITE)) - printf("W "); + POS_PRINT("W "); } - printf("\t %d", f->total_size); + while (pos < okcol + 18) { + printf(" "); + pos++; + } + printf("%d", f->total_size); for (i = 0; i < 10 - digits(f->total_size); i++) printf(" "); printf("%s\n", flashbuses_to_text(f->bustype));

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