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[PATCH] Initial ITE IT8500 EC support
by Donald.Huang＠ite.com.tw 09 Aug '10

09 Aug '10

The attached patch adds generalized support for IT8500/IT8502 embedded controllers. The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc. Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) Signed-off by: Yung-chieh Lo (yjlou(a)google.com) Signed-off by: David Hendricks (dhendrix(a)google.com)

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[PATCH 05/11] Rebased Board Enable Patch: A8JM board_enable patch (was Re: A8JM flashrom unable to erase)
by Sean Nelson 09 Aug '10

09 Aug '10

This patch replaces the earlier one sent, and adds A8JM (and possibly all A8J series) support, and additionally adds DMI detection of A8J, after the r896 fix to dmi detection. Signed-off-by: James Lancaster <deathstalker(a)gmail.com> The DMI identification triggers on either the 2nd or 5th dmi strings, which are both "A8J" followed by different numbers of spaces. Combined with the PCI IDs, it might work on any of the A8J series seeing that the main difference in all but the A8JS is the video card/screen (possibly that too, while there they did add sata in place of IDE). I believe (based on having a video card that was supposed to only be on the A8JS, that it has a different device number (1232), that the A8JS will not be picked up.) I've tested this on my own computer, it picks it up and appears to flash just fine. I think I probably should have added Acked by as it works, but I'll be conservative on the issue. --- board_enable.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 36bf6e4..89dad8a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -910,26 +910,34 @@ static int intel_ich_gpio_set(int gpio, int raise) return 0; } /** * Suited for Abit IP35: Intel P35 + ICH9R. * Suited for Abit IP35 Pro: Intel P35 + ICH9R. */ static int intel_ich_gpio16_raise(const char *name) { return intel_ich_gpio_set(16, 1); } /** + * Suited for ASUS A8JM: Intel 945 + ICH7 + */ +static int intel_ich_gpio34_raise(const char *name) +{ + return intel_ich_gpio_set(34, 1); +} + +/** * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ static int intel_ich_gpio19_raise(const char *name) { return intel_ich_gpio_set(19, 1); } /** * Suited for: * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ @@ -1290,26 +1298,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, @@ -1323,27 +1332,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, -- 1.6.6

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[PATCH] Board enable for ASUS A8N-LA (HP NAGAMI)
by Sean Nelson 09 Aug '10

09 Aug '10

Reversed-engineered board enable for the ASUS A8N-LA. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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[PATCH] Board enable for Asus P4S800-MX
by David Borg 08 Aug '10

08 Aug '10

Tested and works. Thanks to Carl-Daniel Hailfinger for simplifying the chipset enable for this board! Index: board_enable.c =================================================================== --- board_enable.c (revision 1127) +++ board_enable.c (working copy) @@ -352,7 +352,9 @@ } /** - * w83627: Enable MEMW# and set ROM size to max. + * Enable MEMW# and set ROM size to max. + * Supported chips: + * W83L517D, W83697HF/F/HG, W83697SF/UF/UG */ static void w836xx_memw_enable(uint16_t port) { @@ -1715,6 +1717,7 @@ {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, + {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x0003, 0, 0, "^P4S800-MX$", NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, Signed-off-by: David Borg <borg.db(a)gmail.com> On 28 July 2010 03:06, David Borg <borg.db(a)gmail.com> wrote: > > Updated the patch to remove anything related to chip (un)locking, as there is no way to unlock the superio except by a cold reset. > > Logs for the different flashrom runs and the outputs of lspci -nnvvvxxx and superiotool -deV are also attached. > > w836xx_memw_enable will work for this board, however i'd still like to see the function corrected for completeness sake. I haven't yet found a datasheet for a superio in the w83627 family where the function is correct, and the supported superio's all work with sio_mask(port, 0x24, 0x28, 0x38); Perhaps it should be fixed in a separate patch? > > Regards, > David > > On 1 July 2010 11:50, David Borg <borg.db(a)gmail.com> wrote: >> >> Patch to add support for the Asus P4S800-MX motherboard and SIS 963 >> chipset. Invalidates previous patch: [PATCH] add support for SIS963 >> >> If anyone has the output of superiotool -deV for the following working >> boards, please forward them, so I can merge the functions >> w836xx_unlock_memw_enable_2e and w836xx_memw_enable_2e, and maybe fix >> the function w836xx_memw_enable which I believe has a typo, such that >> sio_mask(port, 0x24, 0x28, 0x28); >> becomes : sio_mask(port, 0x24, 0x28, 0x38); >> >> Motherboards: >> Albatron - PM266A Pro >> ASUS - A7V8X-MX SE >> EPoX - EP-8K5A2 >> Shuttle - AK31 >> Tyan - S2498 (Tomcat K7M) >> Termtek - TK-3370 (Rev:2.5B) >> MSI - MS-6590 (KT4 Ultra) >> MSI - MS-6712 (KT4V) >> MSI - MS-7005 (651M-L) >> >> Signed-off-by: David Borg <borg.db(a)gmail.com> >> >> Regards, >> David > > > > -- > David Borg -- David Borg

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Re: [flashrom] [PATCH] Add dmidecode quirk workaround
by Michael Karcher 08 Aug '10

08 Aug '10

[I put the list back into Cc:] Am Sonntag, den 08.08.2010, 11:06 -0700 schrieb Sean Nelson: > > Upcoming Fedora 14 doesn't have this problem, but the patch doesn't > > hurt either. So, this is > > Acked-by: Sean Nelson <audiohacked(a)gmail.com> > I should clearify my previous message in that MY fedora system doesn't > show the problem. If you don't have the problem, most likely your SMBIOS does not declare a version number above 2.6. I clarified the comment to state the fact. No problem, thanks for the Ack. committed in r1136. Regards, Michael Karcher

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[commit] r1136 - trunk
by repository service 08 Aug '10

08 Aug '10

Author: mkarcher Date: Sun Aug 8 23:56:52 2010 New Revision: 1136 URL: http://flashrom.org/trac/coreboot/changeset/1136 Log: Add dmidecode quirk workaround dmidecode emits a warning message about unsupported SMBIOS versions to stdout before the information asked for when using "-s". I consider this behaviour broken, but we still need to workaround it as e.g. Fedora currently distributes an dmidecode with this behaviour. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/dmi.c Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Sun Aug 8 19:04:21 2010 (r1135) +++ trunk/dmi.c Sun Aug 8 23:56:52 2010 (r1136) @@ -76,15 +76,24 @@ msg_perr("DMI pipe open error\n"); return NULL; } - if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { - if(ferror(dmidecode_pipe)) { - msg_perr("DMI pipe read error\n"); - pclose(dmidecode_pipe); - return NULL; - } else { - answerbuf[0] = 0; /* Hit EOF */ + + /* Kill lines starting with '#', as recent dmidecode versions + have the quirk to emit a "# SMBIOS implementations newer..." + message even on "-s" if the SMBIOS declares a + newer-than-supported version number, while it *should* only print + the requested string. */ + do { + if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { + if(ferror(dmidecode_pipe)) { + msg_perr("DMI pipe read error\n"); + pclose(dmidecode_pipe); + return NULL; + } else { + answerbuf[0] = 0; /* Hit EOF */ + } } - } + } while(answerbuf[0] == '#'); + /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent deadlock on pclose. */ while (!feof(dmidecode_pipe))

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MSI Neo4-F/Neo4/Neo4 Platinum clarification (Re: Scary error message)
by Uwe Hermann 08 Aug '10

08 Aug '10

Hi folks, (I'm deliberately breaking the thread otherwise most people will probably miss this as the original thread is from Nov 2009) On Wed, Dec 23, 2009 at 04:08:10AM +0100, Luc Verhaegen wrote: > On Mon, Nov 09, 2009 at 08:45:45PM -0800, Fraser Hanson wrote: > > Hi, > > > > I flashed my bios with flashrom tonight and got the scary warning > > message saying "erase failed" and "do not reboot". > > > > I haven't rebooted. > > > > As far as I can tell from using flashrom itself, everything is > > actually fine. The erase appears to have failed at physical address 0, > > which I would guess means that nothing actually happened. > > > > I had taken a dump of the original bios before starting, and "flashrom > > -v" now verifies that it is identical. > > > > Furthermore, a new dump of the bios matches the original dump from > > before I tried to write the bios. > > > > My board is an MSI K8N Neo4 Platinum. > > > > Output from my dump attempt and subsequent messing around follows. > > > > Do I have your blessing to reboot my machine? > > > > --Fraser > > -> r816. > > Luc Verhaegen. I'm browsing some old board reports on the mailing list and stumbled upon this one here. What we have right now in svn trunk is this: * Suited for: * - MSI K8N Neo4: NVIDIA CK804 [...] {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, I.e., the comment talks about "MSI K8N Neo4" while the name in the board-enable is "MSI K8N Neo4-F" (note the added -F). However, in http://www.flashrom.org/pipermail/flashrom/2009-November/000889.html the user reported that the board is a "K8N Neo4 Platinum (PCB 1.0)" from http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=165 On the MSI page, searching for "neo4" I can see: K8N Neo4 Platinum (PCB 1.0) K8N Neo4 Platinum (PCB 3.0) K8N Neo4-F (PCB 1.0) K8N Neo4-F (PCB 3.0) K8N Neo4-FI (PCB 1.0) K8N Neo4-FX (PCB 1.0) So there are two Neo4-F versions (probably differing hardware) and two Neo4-F versions (also potentially differing hardware). I cannot spot any pure "Neo4" board without any suffix on the current website. Fraser, could you please use the latest flashrom from svn and send us the following info: * flashrom -V * lspci -nnvvvxxx * superiotool -deV Also, can you confirm that the board you have is indeed "K8N Neo4 Platinum (PCB 1.0)"? It's probably best to check what is actually printed on the board itself, I wouldn't entirely trust dmidecode or similar tools. We should fix the board name in the code in one direction or the other. It would also be nice to get a report of whether the current board-enable for the mainboard works (this requires a write or erase test), I think we never got a report, so we should probably mark the board-enable as untested for now. Thanks, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1134 - trunk
by repository service 08 Aug '10

08 Aug '10

Author: uwe Date: Sun Aug 8 19:01:18 2010 New Revision: 1134 URL: http://flashrom.org/trac/coreboot/changeset/1134 Log: Various cosmetic and coding-style fixes (trivial). - Fix incorrect whitespace, indentation, and coding style in some places. - Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use it, the comments are useless as we don't have any Doxygen markup in there. - Use consistent vendor name spelling as per current website (NVIDIA, abit, GIGABYTE). - Use consistent / common format for "Suited for:" lines in board_enable.c. - Add some missing 'void's in functions taking no arguments. - Add missing fullstops in sentences, remove them from non-sentences (lists). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/flashrom.8 trunk/flashrom.c trunk/mcp6x_spi.c trunk/print.c trunk/programmer.h Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/board_enable.c Sun Aug 8 19:01:18 2010 (r1134) @@ -96,7 +96,7 @@ } #endif -/** +/* * SMSC FDC37B787: Raise GPIO50 */ static int fdc37b787_gpio50_raise(uint16_t port) @@ -127,8 +127,9 @@ return 0; } -/** - * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 +/* + * Suited for: + * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 */ static int fdc37b787_gpio50_raise_3f0(void) { @@ -226,37 +227,40 @@ {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf}, }; -/* Detects which Winbond Super I/O is responding at the given base - address, but takes no effort to make sure the chip is really a - Winbond Super I/O */ - -static const struct winbond_chip * winbond_superio_detect(uint16_t base) +/* + * Detects which Winbond Super I/O is responding at the given base address, + * but takes no effort to make sure the chip is really a Winbond Super I/O. + */ +static const struct winbond_chip *winbond_superio_detect(uint16_t base) { uint8_t chipid; - const struct winbond_chip * chip = NULL; + const struct winbond_chip *chip = NULL; int i; w836xx_ext_enter(base); chipid = sio_read(base, 0x20); - for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) - if (winbond_chips[i].device_id == chipid) - { + + for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) { + if (winbond_chips[i].device_id == chipid) { chip = &winbond_chips[i]; break; } - + } + w836xx_ext_leave(base); return chip; } -/* The chipid parameter goes away as soon as we have Super I/O matching in the - board enable table. The call to winbond_superio_detect goes away as - soon as we have generic Super I/O detection code. */ +/* + * The chipid parameter goes away as soon as we have Super I/O matching in the + * board enable table. The call to winbond_superio_detect() goes away as + * soon as we have generic Super I/O detection code. + */ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, int pin, int raise) { - const struct winbond_chip * chip = NULL; - const struct winbond_port * gpio; + const struct winbond_chip *chip = NULL; + const struct winbond_port *gpio; int port = pin / 10; int bit = pin % 10; @@ -286,18 +290,18 @@ w836xx_ext_enter(base); - /* Select logical device */ + /* Select logical device. */ sio_write(base, 0x07, gpio->ldn); /* Activate logical device. */ sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit); - /* Select GPIO function of that pin */ + /* Select GPIO function of that pin. */ if (gpio->mux && gpio->mux[bit].reg) sio_mask(base, gpio->mux[bit].reg, gpio->mux[bit].data, gpio->mux[bit].mask); - sio_mask(base, gpio->base + 0, 0, 1 << bit); /* make pin output */ + sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */ sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ sio_mask(base, gpio->base + 1, raise << bit, 1 << bit); @@ -306,66 +310,65 @@ return 0; } -/** +/* * Winbond W83627HF: Raise GPIO24. * * Suited for: * - Agami Aruma * - IWILL DK8-HTX */ -static int w83627hf_gpio24_raise_2e() +static int w83627hf_gpio24_raise_2e(void) { return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1); } -/** +/* * Winbond W83627HF: Raise GPIO25. * * Suited for: * - MSI MS-6577 */ -static int w83627hf_gpio25_raise_2e() +static int w83627hf_gpio25_raise_2e(void) { return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1); } -/** +/* * Winbond W83627EHF: Raise GPIO24. * * Suited for: - * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51. + * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51 */ -static int w83627ehf_gpio24_raise_2e() +static int w83627ehf_gpio24_raise_2e(void) { return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1); } -/** +/* * Winbond W83627THF: Raise GPIO 44. * * Suited for: * - MSI K8T Neo2-F */ -static int w83627thf_gpio44_raise_2e() +static int w83627thf_gpio44_raise_2e(void) { return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1); } -/** +/* * Winbond W83627THF: Raise GPIO 44. * * Suited for: * - MSI K8N Neo3 */ -static int w83627thf_gpio44_raise_4e() +static int w83627thf_gpio44_raise_4e(void) { return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1); } -/** +/* * Enable MEMW# and set ROM size to max. - * Supported chips: - * W83L517D, W83697HF/F/HG, W83697SF/UF/UG + * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG */ static void w836xx_memw_enable(uint16_t port) { @@ -377,13 +380,13 @@ w836xx_ext_leave(port); } -/** +/* * Suited for: - * - EPoX EP-8K5A2: VIA KT333 + VT8235. - * - Albatron PM266A Pro: VIA P4M266A + VT8235. - * - Shuttle AK31 (all versions): VIA KT266 + VT8233. - * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. + * - EPoX EP-8K5A2: VIA KT333 + VT8235 + * - Albatron PM266A Pro: VIA P4M266A + VT8235 + * - Shuttle AK31 (all versions): VIA KT266 + VT8233 + * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237 */ static int w836xx_memw_enable_2e(void) { @@ -392,9 +395,9 @@ return 0; } -/** +/* * Suited for: - * - Termtek TK-3370 (rev. 2.5b) + * - Termtek TK-3370 (rev. 2.5b) */ static int w836xx_memw_enable_4e(void) { @@ -403,7 +406,7 @@ return 0; } -/** +/* * Suited for all boards with ITE IT8705F. * The SIS950 Super I/O probably requires a similar flash write enable. */ @@ -494,46 +497,46 @@ static int pc87360_gpio_set(uint8_t gpio, int raise) { - static const int bankbase[] = {0, 4, 8, 10, 12}; - int gpio_bank = gpio / 8; - int gpio_pin = gpio % 8; - uint16_t baseport; - uint8_t id, val; - - if (gpio_bank > 4) { - msg_perr("PC87360: Invalid GPIO %d\n", gpio); - return -1; - } + static const int bankbase[] = {0, 4, 8, 10, 12}; + int gpio_bank = gpio / 8; + int gpio_pin = gpio % 8; + uint16_t baseport; + uint8_t id, val; - id = sio_read(0x2E, 0x20); - if (id != 0xE1) { - msg_perr("PC87360: unexpected ID %02x\n", id); - return -1; - } + if (gpio_bank > 4) { + msg_perr("PC87360: Invalid GPIO %d\n", gpio); + return -1; + } - sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */ - baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); - if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { - msg_perr("PC87360: invalid GPIO base address %04x\n", - baseport); - return -1; - } - sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */ - sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); - sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */ - - val = INB(baseport + bankbase[gpio_bank]); - if (raise) - val |= 1 << gpio_pin; - else - val &= ~(1 << gpio_pin); - OUTB(val, baseport + bankbase[gpio_bank]); + id = sio_read(0x2E, 0x20); + if (id != 0xE1) { + msg_perr("PC87360: unexpected ID %02x\n", id); + return -1; + } - return 0; + sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */ + baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { + msg_perr("PC87360: invalid GPIO base address %04x\n", + baseport); + return -1; + } + sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */ + sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); + sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */ + + val = INB(baseport + bankbase[gpio_bank]); + if (raise) + val |= 1 << gpio_pin; + else + val &= ~(1 << gpio_pin); + OUTB(val, baseport + bankbase[gpio_bank]); + + return 0; } -/** - * VT823x: Set one of the GPIO pins. +/* + * VIA VT823x: Set one of the GPIO pins. */ static int via_vt823x_gpio_set(uint8_t gpio, int raise) { @@ -588,8 +591,9 @@ return 0; } -/** - * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F +/* + * Suited for: + * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F */ static int via_vt823x_gpio5_raise(void) { @@ -597,16 +601,18 @@ return via_vt823x_gpio_set(5, 1); } -/** - * Suited for VIA EPIA EK & N & NL. +/* + * Suited for: + * - VIA EPIA EK & N & NL */ static int via_vt823x_gpio9_raise(void) { return via_vt823x_gpio_set(9, 1); } -/** - * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs. +/* + * Suited for: + * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs) * * We don't need to do this for EPIA M when using coreboot, GPIO15 is never * lowered there. @@ -616,12 +622,12 @@ return via_vt823x_gpio_set(15, 1); } -/** +/* * Winbond W83697HF Super I/O + VIA VT8235 southbridge * * Suited for: - * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 - * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ static int board_msi_kt4v(void) { @@ -633,8 +639,9 @@ return ret; } -/** - * Suited for ASUS P5A. +/* + * Suited for: + * - ASUS P5A * * This is rather nasty code, but there's no way to do this cleanly. * We're basically talking to some unknown device on SMBus, my guess @@ -712,7 +719,7 @@ /* * Set GPIO lines in the Broadcom HT-1000 southbridge. * - * It's not a Super I/O but it uses the same index/data port method. + * It's not a Super I/O but it uses the same index/data port method. */ static int board_hp_dl145_g3_enable(void) { @@ -726,7 +733,7 @@ /* * Set GPIO lines in the Broadcom HT-1000 southbridge. * - * It's not a Super I/O but it uses the same index/data port method. + * It's not a Super I/O but it uses the same index/data port method. */ static int board_hp_dl165_g6_enable(void) { @@ -739,14 +746,15 @@ static int board_ibm_x3455(void) { - /* raise gpio13 */ + /* Raise GPIO13. */ sio_mask(0xcd6, 0x45, 0x20, 0x20); return 0; } -/** - * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4). +/* + * Suited for: + * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4) */ static int board_shuttle_fn25(void) { @@ -764,7 +772,7 @@ return 0; } -/** +/* * Very similar to AMD 8111 IO Hub. */ static int nvidia_mcp_gpio_set(int gpio, int raise) @@ -837,110 +845,121 @@ return 0; } -/** - * Suited for ASUS A8N-LA: nVidia MCP51. - * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51. +/* + * Suited for: + * - ASUS A8N-LA: NVIDIA MCP51 + * - ASUS M2NBP-VM CSM: NVIDIA MCP51 */ static int nvidia_mcp_gpio0_raise(void) { return nvidia_mcp_gpio_set(0x00, 1); } -/** - * Suited for Abit KN8 Ultra: nVidia CK804. +/* + * Suited for: + * - abit KN8 Ultra: NVIDIA CK804 */ static int nvidia_mcp_gpio2_lower(void) { return nvidia_mcp_gpio_set(0x02, 0); } -/** - * Suited for MSI K8N Neo4: NVIDIA CK804. - * Suited for MSI K8N GM2-L: NVIDIA MCP51. +/* + * Suited for: + * - MSI K8N Neo4: NVIDIA CK804 + * - MSI K8N GM2-L: NVIDIA MCP51 */ static int nvidia_mcp_gpio2_raise(void) { return nvidia_mcp_gpio_set(0x02, 1); } - -/** - * Suited for HP xw9400 (Tyan S2915-E OEM): Dual(!) nVidia MCP55. - * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that - * board. We can't tell the SMBus logical devices apart, but we - * can tell the LPC bridge functions apart. - * We need to choose the SMBus bridge next to the LPC bridge with - * ID 0x364 and the "LPC bridge" class. - * b) #TBL is hardwired on that board to a pull-down. It can be - * overridden by connecting the two solder points next to F2. +/* + * Suited for: + * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55 + * + * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that + * board. We can't tell the SMBus logical devices apart, but we + * can tell the LPC bridge functions apart. + * We need to choose the SMBus bridge next to the LPC bridge with + * ID 0x364 and the "LPC bridge" class. + * b) #TBL is hardwired on that board to a pull-down. It can be + * overridden by connecting the two solder points next to F2. */ static int nvidia_mcp_gpio5_raise(void) { return nvidia_mcp_gpio_set(0x05, 1); } -/** - * Suited for Abit NF7-S: NVIDIA CK804. +/* + * Suited for: + * - abit NF7-S: NVIDIA CK804 */ static int nvidia_mcp_gpio8_raise(void) { return nvidia_mcp_gpio_set(0x08, 1); } -/** - * Suited for MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8. +/* + * Suited for: + * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8 */ static int nvidia_mcp_gpio0c_raise(void) { return nvidia_mcp_gpio_set(0x0c, 1); } -/** - * Suited for abit NF-M2 nView: Socket AM2 + NVIDIA MCP51. +/* + * Suited for: + * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51 */ static int nvidia_mcp_gpio4_lower(void) { return nvidia_mcp_gpio_set(0x04, 0); } -/** - * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. +/* + * Suited for: + * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04 */ static int nvidia_mcp_gpio10_raise(void) { return nvidia_mcp_gpio_set(0x10, 1); } -/** - * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. +/* + * Suited for: + * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F */ static int nvidia_mcp_gpio21_raise(void) { return nvidia_mcp_gpio_set(0x21, 0x01); } -/** - * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. +/* + * Suited for: + * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2 */ static int nvidia_mcp_gpio31_raise(void) { return nvidia_mcp_gpio_set(0x31, 0x01); } -/** - * Suited for Artec Group DBE61 and DBE62. +/* + * Suited for: + * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) { #define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015 -#define DBE6x_PRI_BOOT_LOC_SHIFT (2) -#define DBE6x_BOOT_OP_LATCHED_SHIFT (8) -#define DBE6x_SEC_BOOT_LOC_SHIFT (10) +#define DBE6x_PRI_BOOT_LOC_SHIFT 2 +#define DBE6x_BOOT_OP_LATCHED_SHIFT 8 +#define DBE6x_SEC_BOOT_LOC_SHIFT 10 #define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT) #define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT) #define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT) -#define DBE6x_BOOT_LOC_FLASH (2) -#define DBE6x_BOOT_LOC_FWHUB (3) +#define DBE6x_BOOT_LOC_FLASH 2 +#define DBE6x_BOOT_LOC_FWHUB 3 msr_t msr; unsigned long boot_loc; @@ -968,7 +987,7 @@ return 0; } -/** +/* * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) @@ -983,20 +1002,20 @@ return -1; } - /* sanity check */ + /* Sanity check. */ if (gpo > 30) { msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); return -1; } - /* these are dual function pins which are most likely in use already */ + /* These are dual function pins which are most likely in use already. */ if (((gpo >= 1) && (gpo <= 7)) || ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); return -1; } - /* dual function that need special enable. */ + /* Dual function that need special enable. */ if ((gpo >= 22) && (gpo <= 26)) { tmp = pci_read_long(dev, 0xB0); /* GENCFG */ switch (gpo) { @@ -1040,23 +1059,25 @@ return 0; } -/** - * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. +/* + * Suited for: + * - EPoX EP-BX3 */ static int board_epox_ep_bx3(void) { return intel_piix4_gpo_set(22, 1); } -/** - * Suited for Intel SE440BX-2 +/* + * Suited for: + * - Intel SE440BX-2 */ static int intel_piix4_gpo27_lower(void) { - return intel_piix4_gpo_set(27, 0); + return intel_piix4_gpo_set(27, 0); } -/** +/* * Set a GPIO line on a given Intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1129,12 +1150,14 @@ return -1; } - /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1 - strapped to zero. From some mobile ICH9 version on, this becomes - 6:1. The mask below catches all. */ + /* + * According to the datasheets, all Intel ICHs have the GPIO bar 5:1 + * strapped to zero. From some mobile ICH9 version on, this becomes + * 6:1. The mask below catches all. + */ base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; - /* check whether the line is allowed */ + /* Check whether the line is allowed. */ if (gpio < 32) allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; else if (gpio < 64) @@ -1152,7 +1175,7 @@ raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { - /* Set line to GPIO */ + /* Set line to GPIO. */ tmp = INL(base); /* ICH/ICH0 multiplexes 27/28 on the line set. */ if ((gpio == 28) && @@ -1174,12 +1197,12 @@ } } - /* Set GPIO to OUTPUT */ + /* Set GPIO to OUTPUT. */ tmp = INL(base + 0x04); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x04); - /* Raise GPIO line */ + /* Raise GPIO line. */ tmp = INL(base + 0x0C); if (raise) tmp |= 1 << gpio; @@ -1189,7 +1212,7 @@ } else if (gpio < 64) { gpio -= 32; - /* Set line to GPIO */ + /* Set line to GPIO. */ tmp = INL(base + 0x30); tmp |= 1 << gpio; OUTL(tmp, base + 0x30); @@ -1206,12 +1229,12 @@ } } - /* Set GPIO to OUTPUT */ + /* Set GPIO to OUTPUT. */ tmp = INL(base + 0x34); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x34); - /* Raise GPIO line */ + /* Raise GPIO line. */ tmp = INL(base + 0x38); if (raise) tmp |= 1 << gpio; @@ -1221,7 +1244,7 @@ } else { gpio -= 64; - /* Set line to GPIO */ + /* Set line to GPIO. */ tmp = INL(base + 0x40); tmp |= 1 << gpio; OUTL(tmp, base + 0x40); @@ -1233,12 +1256,12 @@ return -1; } - /* Set GPIO to OUTPUT */ + /* Set GPIO to OUTPUT. */ tmp = INL(base + 0x44); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x44); - /* Raise GPIO line */ + /* Raise GPIO line. */ tmp = INL(base + 0x48); if (raise) tmp |= 1 << gpio; @@ -1250,55 +1273,59 @@ return 0; } -/** - * Suited for Abit IP35: Intel P35 + ICH9R. - * Suited for Abit IP35 Pro: Intel P35 + ICH9R. +/* + * Suited for: + * - abit IP35: Intel P35 + ICH9R + * - abit IP35 Pro: Intel P35 + ICH9R */ static int intel_ich_gpio16_raise(void) { return intel_ich_gpio_set(16, 1); } -/** - * Suited for HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6. +/* + * Suited for: + * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6 */ static int intel_ich_gpio18_raise(void) { return intel_ich_gpio_set(18, 1); } -/** - * Suited for ASUS A8JM: Intel 945 + ICH7 +/* + * Suited for: + * - ASUS A8JM: Intel 945 + ICH7 */ static int intel_ich_gpio34_raise(void) { return intel_ich_gpio_set(34, 1); } -/** - * Suited for MSI MS-7046: LGA775 + 915P + ICH6. +/* + * Suited for: + * - MSI MS-7046: LGA775 + 915P + ICH6 */ static int intel_ich_gpio19_raise(void) { return intel_ich_gpio_set(19, 1); } -/** +/* * Suited for: - * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. - * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5. - * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. - * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5. - * - Samsung Polaris 32: socket478 + 865P + ICH5. + * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2 + * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5 + * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R + * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5 + * - Samsung Polaris 32: socket478 + 865P + ICH5 */ static int intel_ich_gpio21_raise(void) { return intel_ich_gpio_set(21, 1); } -/** +/* * Suited for: - * - ASUS P4B266: socket478 + Intel 845D + ICH2. + * - ASUS P4B266: socket478 + Intel 845D + ICH2 * - ASUS P4B533-E: socket478 + 845E + ICH4 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 */ @@ -1307,58 +1334,62 @@ return intel_ich_gpio_set(22, 1); } -/** - * Suited for HP Vectra VL400: 815 + ICH + PC87360. +/* + * Suited for: + * - HP Vectra VL400: 815 + ICH + PC87360 */ - static int board_hp_vl400(void) { - int ret; - ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ - if (!ret) - ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ - if (!ret) - ret = pc87360_gpio_set(0x27, 1); /* #TBL */ - return ret; + int ret; + ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ + if (!ret) + ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ + if (!ret) + ret = pc87360_gpio_set(0x27, 1); /* #TBL */ + return ret; } -/** - * Suited for: - * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R. - * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. - * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5. +/* + * Suited for: + * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R + * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R + * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5 */ static int intel_ich_gpio23_raise(void) { return intel_ich_gpio_set(23, 1); } -/** - * Suited for GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2. +/* + * Suited for: + * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2 */ static int intel_ich_gpio25_raise(void) { return intel_ich_gpio_set(25, 1); } -/** - * Suited for IBase MB899: i945GM + ICH7. +/* + * Suited for: + * - IBASE MB899: i945GM + ICH7 */ static int intel_ich_gpio26_raise(void) { return intel_ich_gpio_set(26, 1); } -/** - * Suited for P4SD-LA (HP OEM): i865 + ICH5 +/* + * Suited for: + * - P4SD-LA (HP OEM): i865 + ICH5 */ static int intel_ich_gpio32_raise(void) { return intel_ich_gpio_set(32, 1); } -/** - * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. +/* + * Suited for: + * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2 */ static int board_acorp_6a815epd(void) { @@ -1372,8 +1403,9 @@ return ret; } -/** - * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. +/* + * Suited for: + * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R */ static int board_kontron_986lcd_m(void) { @@ -1386,8 +1418,9 @@ return ret; } -/** - * Suited for Soyo SY-7VCA: Pro133A + VT82C686. +/* + * Suited for: + * - Soyo SY-7VCA: Pro133A + VT82C686 */ static int via_apollo_gpo_set(int gpio, int raise) { @@ -1438,29 +1471,33 @@ return 0; } -/** - * Suited for Abit VT6X4: Pro133x + VT82C686A +/* + * Suited for: + * - abit VT6X4: Pro133x + VT82C686A */ static int via_apollo_gpo4_lower(void) { return via_apollo_gpo_set(4, 0); } -/** - * Suited for Soyo SY-7VCA: Pro133A + VT82C686. +/* + * Suited for: + * - Soyo SY-7VCA: Pro133A + VT82C686 */ static int via_apollo_gpo0_lower(void) { return via_apollo_gpo_set(0, 0); } -/** +/* * Enable some GPIO pin on SiS southbridge. - * Suited for MSI 651M-L: SiS651 / SiS962 + * + * Suited for: + * - MSI 651M-L: SiS651 / SiS962 */ static int board_msi_651ml(void) { - struct pci_dev *dev; + struct pci_dev *dev; uint16_t base, temp; dev = pci_dev_find(0x1039, 0x0962); @@ -1469,7 +1506,7 @@ return 1; } - /* Registers 68 and 64 seem like bitmaps */ + /* Registers 68 and 64 seem like bitmaps. */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ @@ -1484,7 +1521,7 @@ return 0; } -/** +/* * Find the runtime registers of an SMSC Super I/O, after verifying its * chip ID. * @@ -1518,8 +1555,8 @@ return rt_port; } -/** - * Disable write protection on the Mitac 6513WU. WP# on the FWH is +/* + * Disable write protection on the Mitac 6513WU. WP# on the FWH is * connected to GP30 on the Super I/O, and TBL# is always high. */ static int board_mitac_6513wu(void) @@ -1551,15 +1588,16 @@ return 0; } -/** - * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A +/* + * Suited for: + * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F */ static int board_asus_a7v8x(void) { uint16_t id, base; uint8_t tmp; - /* find the IT8703F */ + /* Find the IT8703F. */ w836xx_ext_enter(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); w836xx_ext_leave(0x2E); @@ -1569,7 +1607,7 @@ return -1; } - /* Get the GP567 IO base */ + /* Get the GP567 I/O base. */ w836xx_ext_enter(0x2E); sio_write(0x2E, 0x07, 0x0C); base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); @@ -1606,11 +1644,11 @@ /* Check line */ if ((port > 4) || /* also catches unsigned -1 */ ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); + msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line); return -1; } - /* find the IT8712F */ + /* Find the IT8712F. */ enter_conf_mode_ite(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); exit_conf_mode_ite(0x2E); @@ -1643,7 +1681,7 @@ return 0; } -/** +/* * Suited for: * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F @@ -1655,7 +1693,7 @@ #endif -/** +/* * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1699,14 +1737,14 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) - {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, - {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "Abit", "IC7", 0, NT, intel_ich_gpio23_raise}, - {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, - {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, - {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, - {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "Abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, - {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, + {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, + {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, + {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, + {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, @@ -1748,7 +1786,7 @@ {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, @@ -1781,7 +1819,7 @@ { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -/** +/* * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ @@ -1834,7 +1872,7 @@ return NULL; } -/** +/* * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ @@ -1895,19 +1933,19 @@ if (!board) board = board_match_pci_card_ids(); - if (board && board->status == NT) { - if (!force_boardenable) { - msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" - "code has not been tested, and thus will not not be executed by default.\n" - "Depending on your hardware environment, erasing, writing or even probing\n" - "can fail without running the board specific code.\n\n" - "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" - "\"internal programmer\") for details.\n", - board->vendor_name, board->board_name); - board = NULL; - } else { - msg_pinfo("NOTE: Running an untested board enable procedure.\n" - "Please report success/failure to flashrom(a)flashrom.org.\n"); + if (board && board->status == NT) { + if (!force_boardenable) { + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + "code has not been tested, and thus will not not be executed by default.\n" + "Depending on your hardware environment, erasing, writing or even probing\n" + "can fail without running the board specific code.\n\n" + "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" + "\"internal programmer\") for details.\n", + board->vendor_name, board->board_name); + board = NULL; + } else { + msg_pinfo("NOTE: Running an untested board enable procedure.\n" + "Please report success/failure to flashrom(a)flashrom.org.\n"); } } @@ -1918,8 +1956,8 @@ if (board->enable != NULL) { msg_pinfo("Disabling flash write protection for " - "board \"%s %s\"... ", board->vendor_name, - board->board_name); + "board \"%s %s\"... ", board->vendor_name, + board->board_name); ret = board->enable(); if (ret) Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/chipset_enable.c Sun Aug 8 19:01:18 2010 (r1134) @@ -609,7 +609,7 @@ return 0; } -/** +/* * Geode systems write protect the BIOS via RCONFs (cache settings similar * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. * @@ -868,7 +868,7 @@ return 0; } -/** +/* * The MCP6x/MCP7x code is based on cleanroom reverse engineering. * It is assumed that LPC chips need the MCP55 code and SPI chips need the * code provided in enable_flash_mcp6x_7x_common. @@ -945,7 +945,7 @@ return 0; } -/** +/* * Usually on the x86 architectures (and on other PC-like platforms like some * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD * Elan SC520 only a small piece of the system flash is mapped there, but the Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/flashrom.8 Sun Aug 8 19:01:18 2010 (r1134) @@ -351,7 +351,7 @@ syntax where .B model can be any of -.BR 2232H ", "JTAGkey ", or " 4232H +.BR 2232H ", " JTAGkey ", or " 4232H and .B interface can be any of Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/flashrom.c Sun Aug 8 19:01:18 2010 (r1134) @@ -98,7 +98,7 @@ /* Supported buses for the current programmer. */ enum chipbustype buses_supported; -/** +/* * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ @@ -685,7 +685,7 @@ return ret; } -/** +/* * @cmpbuf buffer to compare against, cmpbuf[0] is expected to match the flash content at location start * @start offset to the base address of the flash chip @@ -765,7 +765,7 @@ return ret; } -/** +/* * Check if the buffer @have can be programmed to the content of @want without * erasing. This is only possible if all chunks of size @gran are either kept * as-is or changed from an all-ones state to any other state. Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/mcp6x_spi.c Sun Aug 8 19:01:18 2010 (r1134) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller. +/* Driver for the NVIDIA MCP6x/MCP7x MCP6X_SPI controller. * Based on clean room reverse engineered docs from * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html * created by Michael Karcher. @@ -165,7 +165,7 @@ return 0; } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544); + mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); #if 0 /* FIXME: Run the physunmap in a shutdown function. */ Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/print.c Sun Aug 8 19:01:18 2010 (r1134) @@ -257,13 +257,13 @@ #endif #if CONFIG_FT2232_SPI+CONFIG_DEDIPROG >= 1 - printf("\nSupported USB devices flashrom can use " - "as programmer:\n\n"); + printf("\nSupported USB devices flashrom can use " + "as programmer:\n\n"); #endif #if CONFIG_FT2232_SPI == 1 print_supported_usbdevs(devs_ft2232spi); -#endif +#endif } #if CONFIG_INTERNAL == 1 @@ -278,15 +278,15 @@ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), - B("Abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), - B("Abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), - B("Abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), - B("Abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), - B("Abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), - B("Abit", "IS-10", 0, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), - B("Abit", "NF-M2 nView", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), - B("Abit", "NF7-S", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), - B("Abit", "VT6X4", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), + B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), + B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), + B("abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), + B("abit", "IS-10", 0, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("abit", "NF-M2 nView", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), + B("abit", "NF7-S", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), + B("abit", "VT6X4", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), B("Acorp", "6A815EPD", 1, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL), B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", 1, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Aug 8 18:05:23 2010 (r1133) +++ trunk/programmer.h Sun Aug 8 19:01:18 2010 (r1134) @@ -399,11 +399,11 @@ /* ft2232_spi.c */ #if CONFIG_FT2232_SPI == 1 struct usbdev_status { -uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; + uint16_t vendor_id; + uint16_t device_id; + int status; + const char *vendor_name; + const char *device_name; }; int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);

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Re: [flashrom] [PATCH] Add dmidecode quirk workaround
by Sean Nelson 08 Aug '10

08 Aug '10

On 08/08/2010 02:24 AM, Michael Karcher wrote: > dmidecode emits a warning message about unsupported SMBIOS versions > to stdout before the information asked for when using "-s". I consider > this behaviour broken, but we still need to workaround it as e.g. Fedora > currently distributes an dmidecode with this behaviour. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > dmi.c | 24 ++++++++++++++++-------- > 1 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/dmi.c b/dmi.c > index cf459ec..98d595c 100644 > --- a/dmi.c > +++ b/dmi.c > @@ -76,15 +76,23 @@ static char *get_dmi_string(const char *string_name) > msg_perr("DMI pipe open error\n"); > return NULL; > } > - if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { > - if(ferror(dmidecode_pipe)) { > - msg_perr("DMI pipe read error\n"); > - pclose(dmidecode_pipe); > - return NULL; > - } else { > - answerbuf[0] = 0; /* Hit EOF */ > + > + /* Kill lines starting with '#', as recent dmidecode versions > + have the quirk to emit a "# SMBIOS implementations newer..." > + message even on "-s", when it *should* only print the > + requested string. */ > + do { > + if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { > + if(ferror(dmidecode_pipe)) { > + msg_perr("DMI pipe read error\n"); > + pclose(dmidecode_pipe); > + return NULL; > + } else { > + answerbuf[0] = 0; /* Hit EOF */ > + } > } > - } > + } while(answerbuf[0] == '#'); > + > /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent > deadlock on pclose. */ > while (!feof(dmidecode_pipe)) Upcoming Fedora 14 doesn't have this problem, but the patch doesn't hurt either. So, this is Acked-by: Sean Nelson <audiohacked(a)gmail.com>

1 0

New supported board: 939A785GMH/128M
by Lennart Sauerbeck 08 Aug '10

08 Aug '10

Hi all, I just tried flashrom 0.9.2 with my mainboard [1] and everything I tested worked fine. Since it is not listed as supported mainboard in the wiki here's what I did: - Reading my current BIOS. - Writing my current BIOS to the chip. - Verifying the content of the chip against the read binary. Attached are the outputs of "flashrom -V" (flashrom_V) and of "lspci -vvvnnxxx" (lspci). I checked back with the IRC channel, but if you still need the output of "superiotool -deV" or any other information let me know. Regards, Lennart Sauerbeck [1] http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939

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