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9161 discussions

[PATCH] SST49FL040B: add unlocking
by Joshua Roys 17 Aug '10

17 Aug '10

Hello all, A bit of poking around revealed the possible reason this chip wasn't getting written to... both the datasheet and linux mtd twiddle some registers in the 4Mbit area before the flash chip in a manner identical to the 82802ab unlock function. Attached is a patch to hook it up. Thanks, Josh

2 2

[commit] r1144 - trunk
by repository service 17 Aug '10

17 Aug '10

Author: mkarcher Date: Tue Aug 17 00:12:39 2010 New Revision: 1144 URL: http://flashrom.org/trac/coreboot/changeset/1144 Log: SST49FL040B: add unlocking The datasheet says there's a set of registers in the 4Mbit before the flash memory. The block locking registers are aligned on 64K boundaries, plus 2. Write/erase sucessful on a system it failed before: http://www.flashrom.org/pipermail/flashrom/2010-August/004432.html Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon Aug 16 00:43:23 2010 (r1143) +++ trunk/flashchips.c Tue Aug 17 00:12:39 2010 (r1144) @@ -5651,8 +5651,8 @@ .model_id = SST_49LF040B, .total_size = 512, .page_size = 64 * 1024, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -5668,6 +5668,7 @@ .block_erase = NULL, } }, + .unlock = unlock_82802ab, .write = write_jedec_1, .read = read_memmapped, },

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SST25VF016B verbose output
by Veres, Greg 16 Aug '10

16 Aug '10

I noticed that the erase fails on the SST25VF016B. Attached is the log file for burning a portion of the bios file. Greg

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[PATCH] Test patch for patchwork experiments
by Carl-Daniel Hailfinger 16 Aug '10

16 Aug '10

This patch is here to allow testing state changes, user permissions and have fun with. No signoff because the patch is not for flashrom. --- 1 2010-08-16 20:30:44.000000000 +0200 +++ 2 2010-08-16 20:30:47.000000000 +0200 @@ -1 +1 @@ -foo +bar -- http://www.hailfinger.org/

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ERROR
by Jason Cochrane 16 Aug '10

16 Aug '10

ran this command: sudo flashrom -w ~/Downloads/P4P81019.rom and got this output: flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: ERASE FAILED at 0x00004ec0! Expected=0xff, Read=0x24, failed byte count from 0x00000000-0x0000ffff: 0xb06d ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF!

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[PATCH] MSI MS-6787 board enable
by Jon Shadow 16 Aug '10

16 Aug '10

Here's a patch that should make swiftgeek's board work. Signed-off-by: Sergey A Lichack <shadowpilot34(a)gmail.com>

2 1

[PATCH] Board enable for Abit VA6
by Mattias Mattsson 16 Aug '10

16 Aug '10

Hi, This adds board enable for Abit VA6. I'm not sure if the DMI matching here is good enough, maybe we should require the -m option. There is support in flashrom for a similar abit board (VT6X4) which currently requires this. -mattias

2 3

[commit] r1143 - trunk
by repository service 16 Aug '10

16 Aug '10

Author: mkarcher Date: Mon Aug 16 00:43:23 2010 New Revision: 1143 URL: http://flashrom.org/trac/coreboot/changeset/1143 Log: Add board enable for Abit VA6 lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-August/004440.html Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Aug 16 00:35:31 2010 (r1142) +++ trunk/board_enable.c Mon Aug 16 00:43:23 2010 (r1143) @@ -1489,6 +1489,7 @@ /* * Suited for: * - abit VT6X4: Pro133x + VT82C686A + * - abit VA6: Pro133x + VT82C686A */ static int via_apollo_gpo4_lower(void) { @@ -1759,6 +1760,7 @@ {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Aug 16 00:35:31 2010 (r1142) +++ trunk/print.c Mon Aug 16 00:43:23 2010 (r1143) @@ -288,6 +288,7 @@ B("abit", "KN8 Ultra", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "NF-M2 nView", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), B("abit", "NF7-S", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), + B("abit", "VA6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), B("abit", "VT6X4", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), B("Acorp", "6A815EPD", 1, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL), B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL),

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[PATCH] Check availability of GPO lines on Intel PIIX4
by Mattias Mattsson 16 Aug '10

16 Aug '10

Hi, I'm not a skilled programmer so this patch may look rather ugly. (Suggestions to improve it are very welcome.) Anyways, this changes the intel_piix4_gpo_set() function to always check the GENCFG and XBCS register for the availability of the requested GPO line (unless called with safe=0) before raising/lowering it. This behaviour was suggested by Michael Karcher on the flashrom mailing list and this is an attempt implementing it. Also adds a board enable for Asus P2B-N. Probe/Read/Write/Erease tested and works with this board. Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: board_enable.c =================================================================== --- board_enable.c (revision 1091) +++ board_enable.c (working copy) @@ -947,13 +947,67 @@ } /** + * Helper function to check if a given gpo line is available on Intel PIIX4{,E,M}. + */ +static int intel_piix4_gpo_available(unsigned int gpo, struct pci_dev *pci_dev) +{ + + uint32_t gencfg; + uint16_t xbcs; + + gencfg = pci_read_long(pci_dev, 0xB0); /* GENCFG */ + xbcs = pci_read_word(pci_dev, 0x4E); /* XBCS */ + + if ((gpo == 0)) { + return 1; /* GPO0 is always available */ + + } else if ((gpo >= 1) && (gpo <= 7)) { + return ((gencfg & 1) == 0); /* GENCFG bit 0 */ + + } else if ((gpo == 8)) { + return -1; /* GPO8 is never available */ + + } else if ((gpo >= 9) && (gpo <= 11)) { + return ((gencfg & (1 << (gpo - 1))) == 0); /* GENCFG bit 8-10 */ + + } else if ((gpo >= 12) && (gpo <= 14)) { + return ((xbcs & (1 << 8)) == 0); /* XBCS bit 8 */ + + } else if ((gpo >= 15) && (gpo <= 16)) { + return ((gencfg & (1 << 17)) == 1); /* GENCFG bit 17 */ + + } else if ((gpo >= 17) && (gpo <= 21)) { + return ((gencfg & (1 << (gpo + 1))) == 1); /* GENCFG bit 18-22 */ + + } else if ((gpo >= 22) && (gpo <= 23)) { + return ((gencfg & (1 << 28)) == 1); /* GENCFG bit 28 */ + + } else if ((gpo >= 24) && (gpo <= 26)) { + return ((gencfg & (1 << (gpo + 5))) == 1); /* GENCFG bit 29-31 */ + + } else if ((gpo >= 27) && (gpo <= 28)) { + return 1; /* GPO27-28 is always available */ + + } else if ((gpo == 29)) { + return ((xbcs & (1 << 8)) == 0); /* XBCS bit 8 */ + + } else if ((gpo == 30)) { + return 1; /* GPO30 is always available */ + + } else { + return -1; + } +} + +/** * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ -static int intel_piix4_gpo_set(unsigned int gpo, int raise) +static int intel_piix4_gpo_set(unsigned int gpo, int raise, int safe) { unsigned int gpo_byte, gpo_bit; struct pci_dev *dev; uint32_t tmp, base; + uint16_t tmp2; dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { @@ -967,36 +1021,86 @@ return -1; } - /* these are dual function pins which are most likely in use already */ - if (((gpo >= 1) && (gpo <= 7)) || - ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); - return -1; - } + if (safe) { + if (intel_piix4_gpo_available(gpo, dev) == -1) { + msg_perr("\nERROR: Intel PIIX4 GPO%d not available.\n", gpo); + return -1; + } + } else { + /* dual function that need special enable. */ - /* dual function that need special enable. */ - if ((gpo >= 22) && (gpo <= 26)) { - tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + tmp2 = pci_read_word(dev, 0x4E); /* XBCS */ switch (gpo) { - case 22: /* XBUS: XDIR#/GPO22 */ - case 23: /* XBUS: XOE#/GPO23 */ - tmp |= 1 << 28; + case 0: break; - case 24: /* RTCSS#/GPO24 */ - tmp |= 1 << 29; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + tmp &= ~(1 << 0); /* GENCFG bit 0: 0 = GPI0+GPO1-7 / 1 = IOCHK#+LA17-23 */ break; - case 25: /* RTCALE/GPO25 */ - tmp |= 1 << 30; + case 8: break; - case 26: /* KBCSS#/GPO26 */ - tmp |= 1 << 31; + case 9: + tmp &= ~(1 << 8); /* GENCFG bit 8: 0 = GPI2+GPO9 / 1 = PC/PCI REQA+GNTA */ break; - } - pci_write_long(dev, 0xB0, tmp); - } + case 10: + tmp &= ~(1 << 9); /* GENCFG bit 9: 0 = GPI3+GPO10 / 1 = PC/PCI REQB+GNTB */ + break; + case 11: + tmp &= ~(1 << 10); /* GENCFG bit 10: 0 = GPI4+GPO11 / 1 = PC/PCI REQC+GNTC */ + break; + case 12: + case 13: + case 14: + case 29: + tmp2 &= ~(1 << 8); /* XBCS bit 8: 0 = GPI5+GPO12-14+GPO29 / 1 = APIC Chip select */ + break; + case 15: + case 16: + tmp |= 1 << 17; /* GENCFG bit 17: 0 = SUSB#+SUSC# / 1 = GPO15+GPO16 */ + break; + case 17: + tmp |= 1 << 18; /* GENCFG bit 18: 0 = CPU_STP# / 1 = GPO17 */ + break; + case 18: + tmp |= 1 << 19; /* GENCFG bit 19: 0 = PCI_STP# / 1 = GPO18 */ + break; + case 19: + tmp |= 1 << 20; /* GENCFG bit 20: 0 = ZZ / 1 = GPO19 */ + break; + case 20: + tmp |= 1 << 21; /* GENCFG bit 21: 0 = SUS_STAT1# / 1 = GPO20 */ + break; + case 21: + tmp |= 1 << 22; /* GENCFG bit 22: 0 = SUS_STAT2# / 1 = GPO21 */ + break; + case 22: + case 23: + tmp |= 1 << 28; /* GENCFG bit 28: 0 = XDIR#+XDIR# / 1 = GPO22+GPO23 */ + break; + case 24: + tmp |= 1 << 29; /* GENCFG bit 29: 0 = RTCSS# / 1 = GPO24 */ + break; + case 25: + tmp |= 1 << 30; /* GENCFG bit 30: 0 = RTCALE / 1 = GPO25 */ + break; + case 26: + tmp |= 1 << 31; /* GENCFG bit 31: 0 = KBCSS# / 1 = GPO26 */ + break; + case 27: + case 28: + case 30: + break; + } + pci_write_long(dev, 0xB0, tmp); + pci_write_word(dev, 0x4E, tmp2); + } - /* GPO {0,8,27,28,30} are always available. */ - dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); @@ -1023,15 +1127,23 @@ */ static int board_epox_ep_bx3(void) { - return intel_piix4_gpo_set(22, 1); + return intel_piix4_gpo_set(22, 1, 1); } /** + * Suited for Asus P2B-N + */ +static int intel_piix4_gpo18_lower(void) +{ + return intel_piix4_gpo_set(18, 0, 1); +} + +/** * Suited for Intel SE440BX-2 */ static int intel_piix4_gpo27_lower(void) { - return intel_piix4_gpo_set(27, 0); + return intel_piix4_gpo_set(27, 0, 1); } /** @@ -1672,6 +1784,7 @@ {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7191, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},

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[commit] r1142 - trunk
by repository service 16 Aug '10

16 Aug '10

Author: mkarcher Date: Mon Aug 16 00:35:31 2010 New Revision: 1142 URL: http://flashrom.org/trac/coreboot/changeset/1142 Log: Check availability of GPO lines on Intel PIIX4 This patch changes the intel_piix4_gpo_set() function to always check the GENCFG and XBCS registers for the availability of the requested GPO line before raising/lowering it and fails otherwise. It makes no attempt to bypass the values in these configuration registers. The old flashrom code did consider it safe to reprogram (multiplexed) GPO:s 22-26 without checking the value of the controlling register (GENCFG). I do not really know why. I have tested this patch on an Asus P2B-N (needs GPO18 low) and MSI MS-6163 Pro (needs GPO14 high). The information for these registers are from the Intel "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" datasheet available here: http://www.intel.com/design/intarch/datashts/29056201.pdf Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Aug 15 17:26:30 2010 (r1141) +++ trunk/board_enable.c Mon Aug 16 00:35:31 2010 (r1142) @@ -997,6 +997,43 @@ struct pci_dev *dev; uint32_t tmp, base; + static const uint32_t nonmuxed_gpos = 0x58000101; /* GPPO {0,8,27,28,30} are always available */ + + static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { + {0}, + {0xB0, 0x0001, 0x0000}, /* GPO1... */ + {0xB0, 0x0001, 0x0000}, + {0xB0, 0x0001, 0x0000}, + {0xB0, 0x0001, 0x0000}, + {0xB0, 0x0001, 0x0000}, + {0xB0, 0x0001, 0x0000}, + {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ + {0}, + {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ + {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ + {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ + {0x4E, 0x0100, 0x0000}, /* GPO12... */ + {0x4E, 0x0100, 0x0000}, + {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ + {0xB2, 0x0002, 0x0002}, /* GPO15... */ + {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ + {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ + {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ + {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ + {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ + {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ + {0xB2, 0x1000, 0x1000}, /* GPO22... */ + {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ + {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ + {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ + {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ + {0}, + {0}, + {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ + {0} + }; + + dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); @@ -1009,36 +1046,12 @@ return -1; } - /* These are dual function pins which are most likely in use already. */ - if (((gpo >= 1) && (gpo <= 7)) || - ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); - return -1; + if ( (((1 << gpo) & nonmuxed_gpos) == 0) && + (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) { + msg_perr("\nERROR: PIIX4 GPO\%d not programmed for output.\n", gpo); + return -1; } - /* Dual function that need special enable. */ - if ((gpo >= 22) && (gpo <= 26)) { - tmp = pci_read_long(dev, 0xB0); /* GENCFG */ - switch (gpo) { - case 22: /* XBUS: XDIR#/GPO22 */ - case 23: /* XBUS: XOE#/GPO23 */ - tmp |= 1 << 28; - break; - case 24: /* RTCSS#/GPO24 */ - tmp |= 1 << 29; - break; - case 25: /* RTCALE/GPO25 */ - tmp |= 1 << 30; - break; - case 26: /* KBCSS#/GPO26 */ - tmp |= 1 << 31; - break; - } - pci_write_long(dev, 0xB0, tmp); - } - - /* GPO {0,8,27,28,30} are always available. */ - dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); @@ -1064,7 +1077,7 @@ * Suited for: * - EPoX EP-BX3 */ -static int board_epox_ep_bx3(void) +static int intel_piix4_gpo22_raise(void) { return intel_piix4_gpo_set(22, 1); } @@ -1778,7 +1791,7 @@ {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, - {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, + {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},

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