flashrom

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No luck with a Marvell 88SX7042 (Adaptec 1430SA)
by Tim Small 25 Jul '11

25 Jul '11

Hi, The Adaptec 1430SA is a Marvell 88SX7042 based controller. It has a different vendor/device ID pair when using the Adaptec firmware, so I added this in: --- satamv.c (revision 1364) +++ satamv.c (working copy) @@ -30,6 +30,7 @@ const struct pcidev_status satas_mv[] = { /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + {0x9005, 0x0243, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II (Adaptec 1430SA)"}, {}, }; ... but it doesn't seem to work on the Adaptec card: flashrom -p satamv:pci=06:00.0 flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found "Marvell 88SX7042 PCI-e 4-port SATA-II (Adaptec 1430SA)" (9005:0243, BDF 06:00.0). Warning! Either the straps are incorrect or you have no flash or someone overwrote the strap values! No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. The eeprom on the card is an AMD Am29LV004BT (which is supported for probing). Cheers, Tim. -- South East Open Source Solutions Limited Registered in England and Wales with company number 06134732. Registered Office: 2 Powell Gardens, Redhill, Surrey, RH1 1TQ VAT number: 900 6633 53 http://seoss.co.uk/ +44-(0)1273-808309

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Re: [flashrom] [PATCH] Add support for the GIGABYTE GA-8SIMLH board.
by Stefan Tauner 25 Jul '11

25 Jul '11

On Sun, 24 Jul 2011 20:47:12 +0200 Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> wrote: > The usage of the GPIO output register as bitmap can be confirmed from the > vendor board enable code, so the comment has been deleted. It really is > (1<<gpionumber). > > lspci: http://paste.flashrom.org/view.php?id=729 > superiotool: http://paste.flashrom.org/view.php?id=730 > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> since it has apparently worked (http://paste.flashrom.org/view.php?id=733) and looks fine otherwise, this is Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> two minor nitpicks: > + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7012, 0x1458, 0xa002, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, the second device is the sound card, which could presumably be disabled. there is only one other device with a gigabyte vendor id: 1458:5004 (usb2.0 controller). not sure if that would be better, just wanted to mention it. > B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), > + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), > B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), P < S, so the new one should be below the GA-8PE667. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1385 - trunk
by repository service 25 Jul '11

25 Jul '11

Author: mkarcher Date: Mon Jul 25 19:25:24 2011 New Revision: 1385 URL: http://flashrom.org/trac/flashrom/changeset/1385 Log: Add support for the GIGABYTE GA-8SIMLH board. The usage of the GPIO output register as bitmap can be confirmed from the vendor board enable code, so the comment has been deleted. It really is (1<<gpionumber). flashrom -V: http://paste.flashrom.org/view.php?id=728 lspci: http://paste.flashrom.org/view.php?id=729 superiotool: http://paste.flashrom.org/view.php?id=730 test report: http://paste.flashrom.org/view.php?id=733 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Jul 25 00:21:57 2011 (r1384) +++ trunk/board_enable.c Mon Jul 25 19:25:24 2011 (r1385) @@ -1725,12 +1725,13 @@ } /* - * Enable some GPIO pin on SiS southbridge. + * Enable some GPIO pin on SiS southbridge and enables SIO flash writes. * * Suited for: * - MSI 651M-L: SiS651 / SiS962 + * - GIGABYTE GA-8SIMLH */ -static int board_msi_651ml(void) +static int sis_gpio0_raise_and_w836xx_memw(void) { struct pci_dev *dev; uint16_t base, temp; @@ -1741,7 +1742,6 @@ return 1; } - /* Registers 68 and 64 seem like bitmaps. */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ @@ -2035,6 +2035,7 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, @@ -2063,7 +2064,7 @@ {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jul 25 00:21:57 2011 (r1384) +++ trunk/print.c Mon Jul 25 19:25:24 2011 (r1385) @@ -534,6 +534,7 @@ B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL),

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Re: [flashrom] [Patch] Add support for EN25Q series SPI flash chips
by Stefan Tauner 25 Jul '11

25 Jul '11

On Wed, 22 Jun 2011 16:04:42 -0700 David Hendricks <dhendrix(a)google.com> wrote: > Thanks for the review! I've attached an updated patch to address your > comments. > > I'm still not sure what the best course of action is for dealing with the > D16 versus Q16 evil twin scenario. Let's see if Carl-Daniel has further > comments. > > New patch is: > Signed-off-by: David Hendricks <dhendrix(a)google.com> since carl-daniel wants to push 0.9.4 soon (no, really! ;) i have committed your patch with some small changes which i think make it better (including the D16 -> Q16 rename) in r1384. thank you! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1384 - trunk
by repository service 25 Jul '11

25 Jul '11

Author: stefanct Date: Mon Jul 25 00:21:57 2011 New Revision: 1384 URL: http://flashrom.org/trac/flashrom/changeset/1384 Log: add support for EN25Q(H) series SPI flash chips - EN25Q40 - EN25Q80 - EN25Q16 (half-evil twin of already supported EN25D16, hence merged) - EN25Q32(A/B) - EN25Q64 - EN25Q128 - EN25QH16 Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jul 24 20:41:13 2011 (r1383) +++ trunk/flashchips.c Mon Jul 25 00:21:57 2011 (r1384) @@ -2923,42 +2923,6 @@ { .vendor = "Eon", - .name = "EN25D16", - .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = EON_ID_NOPREFIX, - .model_id = EON_EN25D16, - .total_size = 2048, - .page_size = 256, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "Eon", .name = "EN25F05", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = EON_ID_NOPREFIX, @@ -3205,6 +3169,259 @@ }, { + .vendor = "Eon", + .name = "EN25Q40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q40, + .total_size = 512, + .page_size = 256, + /* TODO: chip features 256-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q80(A)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q80, + .total_size = 1024, + .page_size = 256, + /* TODO: chip features 256-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + /* Note: EN25D16 is an evil twin which shares the model ID + but has different write protection capabilities */ + .vendor = "Eon", + .name = "EN25Q16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q16, + .total_size = 2048, + .page_size = 256, + /* TODO: EN25D16 features 512-byte one-time programmable region, + * EN25Q16 features a 128-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + /* not supported by Q16 version */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q32(A/B)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q32, + .total_size = 4096, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q64", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q64, + .total_size = 8192, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q128", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q128, + .total_size = 16384, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25QH16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH16, + .total_size = 2048, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region + * and supports SFDP. + */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 2048, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 2048, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { .vendor = "Eon", .name = "EN29F010", .bustype = CHIP_BUSTYPE_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jul 24 20:41:13 2011 (r1383) +++ trunk/flashchips.h Mon Jul 25 00:21:57 2011 (r1384) @@ -232,7 +232,6 @@ #define EON_EN25B64 0x2017 /* Same as P64 */ #define EON_EN25B64T 0x46 #define EON_EN25B64B 0x36 -#define EON_EN25D16 0x3015 #define EON_EN25F05 0x3110 #define EON_EN25F10 0x3111 #define EON_EN25F20 0x3112 @@ -240,6 +239,13 @@ #define EON_EN25F80 0x3114 #define EON_EN25F16 0x3115 #define EON_EN25F32 0x3116 +#define EON_EN25Q40 0x3013 +#define EON_EN25Q80 0x3014 +#define EON_EN25Q16 0x3015 /* Same as EN25D16 */ +#define EON_EN25Q32 0x3016 /* Same as EN25Q32A and EN25Q32B */ +#define EON_EN25Q64 0x3017 +#define EON_EN25Q128 0x3018 +#define EON_EN25QH16 0x7015 #define EON_EN29F512 0x7F21 #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04

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Asus_EEE_PC_1201N_flashrom_v0.9.3-r1383
by Filatov Sergey Dmitrievich 24 Jul '11

24 Jul '11

-- Regards, Sergey Filatov

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[PATCH] Man page fixes: dummy, satamv, it87
by Carl-Daniel Hailfinger 24 Jul '11

24 Jul '11

Man page fixes: - Add dummy programmer flash chip emulation - Add satamv programmer - Merge it87spi programmer into internal section - Correct formatting of pci= parameter Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-manpage_dummy_satamv_it87spi/flashrom.8 =================================================================== --- flashrom-manpage_dummy_satamv_it87spi/flashrom.8 (Revision 1380) +++ flashrom-manpage_dummy_satamv_it87spi/flashrom.8 (Arbeitskopie) @@ -168,7 +168,7 @@ .sp .BR "* internal" " (default, for in-system flashing in the mainboard)" .sp -.BR "* dummy" " (just prints all operations and accesses)" +.BR "* dummy" " (prints all operations and accesses, can emulate flash chips)" .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp @@ -192,9 +192,6 @@ .sp .BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ -translation unit)" -.sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer)" .sp @@ -286,17 +283,17 @@ .B " flashrom \-p internal:boardmismatch=force" .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus -translation, flashrom should autodetect that configuration. You can use the +translation, flashrom should autodetect that configuration. If you want to +set the I/O base port of the IT87 series SPI controller manually instead of +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp -syntax as explained in the -.B it87spi -programmer section to use a non-default port for controlling the IT87 series -Super I/O. In the unlikely case flashrom doesn't detect an active -IT87 LPC<->SPI bridge, you can try to force recognition by using the -.B it87spi -programmer. +syntax where +.B portnum +is the I/O port number (must be a multiple of 8). In the unlikely case +flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug +report so we can diagnose the problem. .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -322,7 +319,9 @@ .BR "dummy " programmer An optional parameter specifies the bus types it should support. For that you have to use the -.B "flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp +.B " flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp syntax where .B type can be @@ -332,6 +331,51 @@ .sp Example: .B "flashrom \-p dummy:bus=lpc+fwh" +.sp +The dummy programmer supports flash chip emulation for automated self-tests +without hardware access. If you want to emulate a flash chip, use the +.sp +.B " flashrom \-p dummy:emulate=chip" +.sp +syntax where +.B chip +is one of the following chips (please specify only the chip name, not the +vendor): +.sp +.RB "* ST " M25P10.RES " SPI flash chip (RES, page write)" +.sp +.RB "* SST " SST25VF040.REMS " SPI flash chip (REMS, byte write)" +.sp +.RB "* SST " SST25VF032B " SPI flash chip (RDID, AAI write)" +.sp +Example: +.B "flashrom -p dummy:emulate=SST25VF040.REMS" +.sp +If you use flash chip emulation, flash image persistence is available as well +by using the +.sp +.B " flashrom \-p dummy:emulate=chip,image=image.rom" +.sp +syntax where +.B image.rom +is the file where the simulated chip contents are read on flashrom startup and +where the chip contents on flashrom shutdown are written to. +.sp +Example: +.B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.sp +If you use SPI flash chip emulation for a chip which supports SPI page write +with the default opcode, you can set the maximum allowed write chunk size with +the +.sp +.B " flashrom \-p dummy:emulate=chip,spi_write_256_chunksize=size" +.sp +syntax where +.B size +is the number of bytes (min. 1, max. 256). +.sp +Example: +.B "flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" .TP .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ @@ -339,7 +383,9 @@ These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is -.BR "flashrom \-p xxxx:pci=bb:dd.f" , +.sp +.BR " flashrom \-p xxxx:pci=bb:dd.f" , +.sp where .B xxxx is the name of the programmer @@ -353,19 +399,6 @@ Example: .B "flashrom \-p nic3com:pci=05:04.0" .TP -.BR "it87spi " programmer -An optional -.B it87spiport -parameter sets the I/O base port of the IT87 series SPI controller -interface to the port specified in the parameter instead of using the port -address set by the BIOS. For that you have to use the -.sp -.B " flashrom \-p it87spi:it87spiport=portnum" -.sp -syntax where -.B portnum -is an I/O port number which must be a multiple of 8. -.TP .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -487,9 +520,6 @@ needs raw memory access, PCI configuration space access, raw I/O port access (x86) and MSR access (x86). .sp -.B it87spi -needs raw I/O port access (x86). -.sp .BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " need PCI configuration space read access and raw I/O port access. .sp @@ -505,6 +535,10 @@ .B satasii needs PCI configuration space read access and raw memory access. .sp +.B satamv +needs PCI configuration space read access, raw I/O port access and raw memory +access. +.sp .B serprog needs TCP access to the network or userspace access to a serial port. .sp @@ -517,8 +551,8 @@ .B dummy needs no access permissions at all. .sp -.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " -.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +.BR internal ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " nicnatsemi ", " +.BR gfxnvidia" ", " drkaiser ", " satasii ", " satamv " and " atahpt have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi -- http://www.hailfinger.org/

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Asus EEE PC 1201N netbook
by Filatov Sergey Dmitrievich 24 Jul '11

24 Jul '11

flashrom log in attachment. -- Regards, Sergey Filatov

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Gigabyte
by halloaron＠web.de 24 Jul '11

24 Jul '11

http://www.flashrom.org/pipermail/flashrom/2011-July/007348.html Its works. Acked. ___________________________________________________________ Schon gehört? WEB.DE hat einen genialen Phishing-Filter in die Toolbar eingebaut! http://produkte.web.de/go/toolbar

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[PATCH] Add support for the GIGABYTE GA-8SIMLH board.
by Michael Karcher 24 Jul '11

24 Jul '11

The usage of the GPIO output register as bitmap can be confirmed from the vendor board enable code, so the comment has been deleted. It really is (1<<gpionumber). lspci: http://paste.flashrom.org/view.php?id=729 superiotool: http://paste.flashrom.org/view.php?id=730 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 9 +++++---- print.c | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board_enable.c b/board_enable.c index b3dc58e..1a2c108 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1725,12 +1725,13 @@ static int via_apollo_gpo0_lower(void) } /* - * Enable some GPIO pin on SiS southbridge. + * Enable some GPIO pin on SiS southbridge and enables SIO flash writes. * * Suited for: * - MSI 651M-L: SiS651 / SiS962 + * - GIGABYTE GA-8SIMLH */ -static int board_msi_651ml(void) +static int sis_gpio0_raise_and_w836xx_memw(void) { struct pci_dev *dev; uint16_t base, temp; @@ -1741,7 +1742,6 @@ static int board_msi_651ml(void) return 1; } - /* Registers 68 and 64 seem like bitmaps. */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ @@ -2035,6 +2035,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7012, 0x1458, 0xa002, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, @@ -2063,7 +2064,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, diff --git a/print.c b/print.c index 0db0339..2cf89f1 100644 --- a/print.c +++ b/print.c @@ -532,6 +532,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), -- 1.7.5.4

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