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[PATCH 1/1] Introduce ERROR_FATAL in chipset enables
by Tadas Slotkus 06 Sep '11

06 Sep '11

Currently we are continuing even if chipset enable has failed. Some chipset enables do exits, so to kill those exits I have prepared one sneaky check :) Errors are negative there, so I have chosen this constant. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- chipset_enable.c | 4 ++++ flash.h | 3 ++- internal.c | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 687682a..f6c5d81 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1289,6 +1289,10 @@ int chipset_flash_enable(void) msg_pinfo("OK.\n"); else if (ret == ERROR_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); + else if (ret == ERROR_FATAL) { + msg_perr("FATAL ERROR!\n") + return ret; + } } s = flashbuses_to_text(buses_supported); diff --git a/flash.h b/flash.h index 3d47a16..7386ecb 100644 --- a/flash.h +++ b/flash.h @@ -224,8 +224,9 @@ int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filena #define OK 0 #define NT 1 /* Not tested */ -/* Something happened that shouldn't happen, but we can go on */ +/* Something happened that shouldn't happen, but we can go on, or not */ #define ERROR_NONFATAL 0x100 +#define ERROR_FATAL -0xEE /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ diff --git a/internal.c b/internal.c index 846cf1e..46836b7 100644 --- a/internal.c +++ b/internal.c @@ -268,7 +268,8 @@ int internal_init(void) if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); - } + } else if (ret == ERROR_FATAL) + return ret; #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for IT87* LPC->SPI translation and for -- 1.7.6

3 9

[commit] r1429 - trunk
by repository service 06 Sep '11

06 Sep '11

Author: uwe Date: Tue Sep 6 20:49:31 2011 New Revision: 1429 URL: http://flashrom.org/trac/flashrom/changeset/1429 Log: Kill all exit() calls in chipset_enable.c. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Sep 6 20:17:02 2011 (r1428) +++ trunk/chipset_enable.c Tue Sep 6 20:49:31 2011 (r1429) @@ -343,10 +343,7 @@ msg_perr("Error: fwh_idsel= specified, but no value given.\n"); idsel_garbage_out: free(idsel); - /* FIXME: Return failure here once internal_init() starts - * to care about the return value of the chipset enable. - */ - exit(1); + return ERROR_FATAL; } free(idsel); @@ -489,6 +486,8 @@ /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); + if (ret == ERROR_FATAL) + return ret; /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; @@ -894,7 +893,7 @@ if (!smbusdev) { msg_perr("ERROR: SMBus device not found. Aborting.\n"); - exit(1); + return ERROR_FATAL; } /* Enable some SMBus stuff. */

1 0

[commit] r1428 - trunk
by repository service 06 Sep '11

06 Sep '11

Author: uwe Date: Tue Sep 6 20:17:02 2011 New Revision: 1428 URL: http://flashrom.org/trac/flashrom/changeset/1428 Log: Fix linux_spi.c build on 32bit systems. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Sat Sep 3 20:37:52 2011 (r1427) +++ trunk/linux_spi.c Tue Sep 6 20:17:02 2011 (r1428) @@ -107,11 +107,11 @@ { struct spi_ioc_transfer msg[2] = { { - .tx_buf = (uint64_t)txbuf, + .tx_buf = (uint64_t)(ptrdiff_t)txbuf, .len = writecnt, }, { - .rx_buf = (uint64_t)rxbuf, + .rx_buf = (uint64_t)(ptrdiff_t)rxbuf, .len = readcnt, }, };

1 0

NVIDIA MCP67 chipset in HP DV9820US running flashrom -V results
by Jon Jensen 06 Sep '11

06 Sep '11

Here is the output when I ran "sudo flashrom -V" on my HP DV9820US laptop under 64-bit Ubuntu 10.04.3 LTS Lucid Lynx: http://h10025.www1.hp.com/ewfrf/wc/searchResults?product=3689897&tmp_qt=dri… http://h10025.www1.hp.com/ewfrf/wc/product?product=3689897&lc=en&cc=us&dlc=… --------------BEGIN QUOTED flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv9700 Notebook PC " DMI string system-version: "Rev 1" DMI string baseboard-manufacturer: "Quanta" DMI string baseboard-product-name: "30D1" DMI string baseboard-version: "85.26" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "NVIDIA MCP67", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:0542 at 00:01:1 SPI BAR is at 0xf2300000, after clearing low bits BAR is at 0xf2300000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 97M loops per second, 100 myus = 34 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x02, id2 0x01, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x02, id2 0x01 Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x02, id2 0x01 Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x02, id2 0x01, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ---------------------------END QUOTED

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Flashrom 0.9.4-r1395 compiled, running, detected Flash modchip on Xbox running Linux
by Matt Falcon 06 Sep '11

06 Sep '11

Here's a curiosity of the day... :) I knew my Xbox used an LPC Flash ROM for its modchip, and that it could flash its own ROMs once a chip is installed. And I had restored a bad BIOS onto a PC*. Lack of an LPC-compatible board, and failure in my serprog+Arduino endeavors, I was kinda looking for anything. So, putting these things together, I thought I'd try getting Flashrom working inside XDSL. Most of the work was done through VNC, as jerking around with an on-screen keyboard and the Xbox controller was hardly rewarding... * -Flashrom seems to have some "read" bugs - it's bricked 2 different PCs so far by restoring a backup it made - the file was mostly correct, but uniformly-but-lightly littered with "p____________" ("p" followed by about 24 0x00 bytes) garbage data - found out after-the-fact when looking back at the backup data! As you can see in the photo (attached), it runs, but doesn't detect the chipset (though it somehow detects the flash - weird!). This is properly identified as well, and that's even going through an LPC adapter chip of some sort (Xilinx something-or-other on the modchip, a Duo X2). I hadn't tested read/write, since that wasn't the chip I needed to flash. Sadly, if I hot-swap the chip into the Xbox while it's booted, it craps out and freezes. I can only do it in a tiny 3-4 second window after powering it on, while the Xbox animation is playing (presumably it's already loaded the ROM into memory). That works, but I haven't been able to get it to detect the chip yet. I still get the same chipset error, but it doesn't detect the SST49LF020 chip I'm trying to test with (ultimately I have a SST49LF040B that I need to program). But anywho, I figured this might be some useful, or at least entertaining, information. Yup, Flashrom runs on an Xbox. :) - Matt

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 05 Sep '11

05 Sep '11

On Mon, 5 Sep 2011 10:00:24 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi Stefan, > > today I loaded the sources again and I got the R1427. > > The patches do not work on this. > > So: What revision will I have to check out? Which revision are the patches for? > i have answered this multiple times already e.g. in http://www.flashrom.org/pipermail/flashrom/2011-August/007751.html you have even quoted it below your message: > i am not using svn but i think the right command to fetch the correct version of source for those patches is: > svn update -r 1421 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Paul Menzel 05 Sep '11

05 Sep '11

Dear Thomas, Am Montag, den 05.09.2011, 10:00 +0200 schrieb Frei, Thomas (GE Germany): > today I loaded the sources again and I got the R1427. > > The patches do not work on this. > > So: What revision will I have to check out? Which revision are the patches for? we asked you several times to paste your steps/commands into the message. Please do as we ask you to as otherwise it is very time consuming to help you. Thanks, Paul PS: Are you subscribed to the list? Do I have to put your address into CC?

1 0

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 05 Sep '11

05 Sep '11

On Thu, 1 Sep 2011 15:28:42 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > I tried to clean the build environment (make clean), and reloaded the sources. > > With this clean base I started step by step to patch: > > Make -> PASS > Patch < 0001....patch -> PASS > Make -> PASS > Patch < 0002....patch -> ERROR!!! > > --- snip --- > (Stripping trailing CRs from patch) > patching file cli_classic.c > Hunk #1 FAILED at 226. > Hunk #2 FAILED at 318. > 2 out of 2 hunks FAILED -- saving rejects to cli_classic.c.rej > (Stripping trailing CRs from patch) > patching file flash.h > Hunk #1 FAILED at 255. > 1 out of 1 hunk FAILED -- saving rejects to flash.h.rej > (Stripping trailing CRs from patch) > patching file layout.c > --- snip --- > > Am I doinf wrong, or what else can be? > you are using the wrong revision of source code (probably the most current one?) imo. the patches encode differences of files. when the files change too much 'patch' is not able to find the right spots to insert the hunks of code in the patches... i am not using svn but i think the right command to fetch the correct version of source for those patches is: svn update -r 1421 i am not sure if that eliminates all of your local changes though. please check with svn st and revert them with svn revert or something similar before you try. of course i could be wrong too. if the above does not work please post the commands used and complete outputs. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] spi25: get rid of unneccessary line breaks (on failed probes)
by Uwe Hermann 04 Sep '11

04 Sep '11

On Mon, Aug 22, 2011 at 01:07:50PM +0200, Stefan Tauner wrote: > --- > not sure if this is correct for all execution paths, but it fixes the > output of a probe on my thinkpad. i have looked a bit around to find > examples of code that this patch would break and found none though. > > without this patch: > Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. > > Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. > > Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. > > Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > > with this patch: > Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. > Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. > Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. > Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Untested, but I can't see any obvious problems either. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Re: [flashrom] [PATCH 1/8] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger 04 Sep '11

04 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptor sections that are > cached/mapped by the chipset (and which are therefore reachable via > FDOC/FDOD registers). > > this includes the following: > - content section: > describes the image and some generic properties (number of > sections, offset of sections, PCH/ICH and MCH/PROC strap > offsets and lengths) > - component section: > identify the different SPI flash chips and their capabilities. > - region section > similarly to a partition table this describes the different regions. > the content of FLREG* is derived from this section. > - master section > defines SPI master (host, ME, GbE) access rights of the > individual regions. the content of PR* is derived from this section. > > this is only a part of the data included in the descriptor. other > information can be retrieved from a complete binary dump of the > descriptor region only. > > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: there are two of them: lower and > upper. they describe the properties of the address space divided by > FPBA (which allows to use multiple flash chips or partitions with > different properties). the properties of all supported flash chips > (together with their RDIDs) are stored in the same format in table > in a descriptor section (which is used by the ME apparently). a > later patch will use the macros outside of ichspi.c which is the > reason why the prettyprinting function and the register bit macros > are not defined in ichspi.c but ich_descriptors.h (else they would > be moved in the follow-up patch). > > because this patch relies on (compiler) implementation-specific > layouting of bit-fields, it checks for basic compiler support in the > makefile and for correct layout before taking any action on runtime. > Checking for presence of bitfield support in the compiler is the way to madness. Next we have to test for C99 capability and other fun stuff. Just assume that bitfields are supported, otherwise compilation will blow up or the runtime checks will catch a miscompilation. That compile-time check (including the #if BITFIELDS) is nacked. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > Makefile | 25 +++++- > ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 60 +++++++++-- > 4 files changed, 622 insertions(+), 12 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index 26f978f..247a60c 100644 > --- a/Makefile > +++ b/Makefile > @@ -340,9 +340,11 @@ endif > > ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > @@ -635,6 +637,19 @@ int main(int argc, char **argv) > endef > export UTSNAME_TEST > > +define BITFIELDS_TEST > +#include "ich_descriptors.h" > +int main(int argc, char **argv) > +{ > + struct ich_descriptors desc; > + (void) argc; > + (void) argv; > + desc.region.FLREGs[4] = 0x5aa5a55a; > + return desc.region.reg4_base; > +} > +endef > +export BITFIELDS_TEST > + > features: compiler > @echo "FEATURES := yes" > .features.tmp > ifeq ($(CONFIG_FT2232_SPI), yes) > @@ -649,6 +664,14 @@ endif > @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ > ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ > ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) > +# ugly hack to get a logical AND *sigh* > +ifeq ($(CONFIG_INTERNAL)$(ARCH), yes"x86") > + @printf "Checking if bit-fields support is sufficient... " > + @echo "$$BITFIELDS_TEST" > .featuretest.c > + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ > + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ > + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) > +endif > @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features > @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) > > That Makefile change needs to be dropped except for the PROGRAMMER_OBJS addition. > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..ce40d9f > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,288 @@ > [...] > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) > +{ > + uint8_t i; > + uint8_t nr; > + struct ich_desc_region *r = &desc->region; > + > The snippet below needs to be in its own function named selfcheck_bitfields(), and that function should live in flashrom.c (or any other reasonably central place) and be called in the initial selfcheck() function. We want to know where this explodes, even if the functionality would not be necessary. > + /* Test if bit-fields are working as expected */ > + for (i = 0; i < 4; i++) > + desc->region.FLREGs[i] = 0x5A << (i * 8); > + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || > + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || > + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || > + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { > + msg_pdbg("The combination of compiler and CPU architecture used" > + "does not lay out bit-fields as expected, sorry.\n"); > + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); > + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); > + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); > + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); > + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); > + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); > + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); > + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); > + return RET_ERR; > + } > Snippet ends here. If you want, I can send my own bitfield checker code to the list so you can compare both implementations. > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..b1da914 > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,261 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +#define RET_OK 0 > +#define RET_ERR -1 > +#define RET_WARN -2 > +#define RET_PARAM -3 > +#define RET_OOB -4 > Too generic names. > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum ich_chipset { > + CHIPSET_ICH_UNKNOWN, > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); > + > +#if BITFIELDS == 1 > +struct ich_desc_content { > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8, /* Flash Component Base Address */ > + NC :2, /* Number Of Components */ > + :6, > + FRBA :8, /* Flash Region Base Address */ > + NR :3, /* Number Of Regions */ > + :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8, /* Flash Master Base Address */ > + NM :3, /* Number Of Masters */ > + :5, > + FISBA :8, /* Flash ICH Strap Base Address */ > + ISL :8; /* ICH Strap Length */ > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ > + MSL :8, /* MCH Strap Length */ > + :16; > + }; > + }; > +}; > + > +struct ich_desc_component { > + union { /* 0x00 */ > + uint32_t FLCOMP; /* Flash Components Register */ > + struct { > + uint32_t comp1_density :3, > + comp2_density :3, > + :11, > + freq_read :3, > + fastread :1, > + freq_fastread :3, > + freq_write :3, > + freq_read_id :3, > + :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; /* Flash Invalid Instructions Register */ > + struct { > + uint32_t invalid_instr0 :8, > + invalid_instr1 :8, > + invalid_instr2 :8, > + invalid_instr3 :8; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; /* Flash Partition Boundary Register */ > + struct { > + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ > + :19; > + }; > + }; > +}; > + > +struct ich_desc_region { > + union { > + uint32_t FLREGs[5]; > + struct { > + struct { /* FLREG0 Flash Descriptor */ > + uint32_t reg0_base :13, > + :3, > + reg0_limit :13, > + :3; > + }; > + struct { /* FLREG1 BIOS */ > + uint32_t reg1_base :13, > + :3, > + reg1_limit :13, > + :3; > + }; > + struct { /* FLREG2 ME */ > + uint32_t reg2_base :13, > + :3, > + reg2_limit :13, > + :3; > + }; > + struct { /* FLREG3 GbE */ > + uint32_t reg3_base :13, > + :3, > + reg3_limit :13, > + :3; > + }; > + struct { /* FLREG4 Platform */ > + uint32_t reg4_base :13, > + :3, > + reg4_limit :13, > + :3; > + }; > + }; > + }; > +}; > + > +struct ich_desc_master { > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16, > + BIOS_descr_r :1, > + BIOS_BIOS_r :1, > + BIOS_ME_r :1, > + BIOS_GbE_r :1, > + BIOS_plat_r :1, > + :3, > + BIOS_descr_w :1, > + BIOS_BIOS_w :1, > + BIOS_ME_w :1, > + BIOS_GbE_w :1, > + BIOS_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16, > + ME_descr_r :1, > + ME_BIOS_r :1, > + ME_ME_r :1, > + ME_GbE_r :1, > + ME_plat_r :1, > + :3, > + ME_descr_w :1, > + ME_BIOS_w :1, > + ME_ME_w :1, > + ME_GbE_w :1, > + ME_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16, > + GbE_descr_r :1, > + GbE_BIOS_r :1, > + GbE_ME_r :1, > + GbE_GbE_r :1, > + GbE_plat_r :1, > + :3, > + GbE_descr_w :1, > + GbE_BIOS_w :1, > + GbE_ME_w :1, > + GbE_GbE_w :1, > + GbE_plat_w :1, > + :3; > + }; > + }; > +}; > + > +struct ich_descriptors { > + struct ich_desc_content content; > + struct ich_desc_component component; > + struct ich_desc_region region; > + struct ich_desc_master master; > +}; > + > +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); > + > +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); > +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > + > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > + > +#endif /* BITFIELDS == 1 */ > +#endif /* __ICH_DESCRIPTORS_H__ */ > +#endif /* defined(__i386__) || defined(__x86_64__) */ > diff --git a/ichspi.c b/ichspi.c > index 8b4210e..09af2b3 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > How does FDOVR (or whatever the correct acronym for Flash Descriptor Override is) relate to this? > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1308,12 +1318,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > mmio_readl(ich_spibar + ICH9_REG_OPMENU)); > msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); > - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > - msg_pdbg("0xA0: 0x%08x (BBAR)\n", > - ichspi_bbar); > - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + if (ich_generation == 8) { > + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); > + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); > + msg_pdbg("VSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + } else { > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > + msg_pdbg("0xA0: 0x%08x (BBAR)\n", > + ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + } > > + msg_pdbg("\n"); > +#if BITFIELDS == 1 > + if (ichspi_desc) { > + struct ich_descriptors desc = {{ 0 }}; > + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > + RET_OK) > + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > + &desc); > + } > +#endif /* BITFIELDS == 1 */ > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

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