flashrom

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[commit] r1538 - trunk
by repository service 16 May '12

16 May '12

Author: stefanct Date: Wed May 16 02:15:53 2012 New Revision: 1538 URL: http://flashrom.org/trac/flashrom/changeset/1538 Log: Remove sharplhf00l04.c. The currently unreferenced function in sharplhf00l04.c does a standard FWH block protection reset (writes 0 to the protection register) and a standard FWH block erase. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Deleted: trunk/sharplhf00l04.c Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 16 00:58:19 2012 (r1537) +++ trunk/Makefile Wed May 16 02:15:53 2012 (r1538) @@ -260,7 +260,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o \ a25.o at25.o opaque.o sfdp.o en29lv640b.o LIB_OBJS = layout.o

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Re: [flashrom] [PATCH] ft2232_spi.c: add frequency divider parameter.
by Samir Ibradžić 16 May '12

16 May '12

On 2012年02月28日 10:48, Stefan Tauner wrote: > This adds an extra argument when using the ft2232_spi programmer to set > the frequency divider. The valid values for the divider is any even integer > between 2 and 131072. > > Signed-off-by: Samir Ibradžić<sibradzic(a)gmail.com> > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > > --- > this was totally broken even without Samir's version of the patch applied. > it might be a better idea to let the user specify the actual frequency instead of > the divisor like some other programmers do (serprog and buspirate). Well, it may be more clear to specify exact frequencies, but we may end up with weird set of frequencies for all these large dividers. Maybe it would be better to support a limited set of "standard" dividers and their corresponding frequencies, like: divider | freq --------+-------- 2 | 30MHz 4 | 15MHz 6 | 10MHz 8 | 7.5MHz 10 | 6MHz 12 | 5MHz 20 | 3MHz 30 | 2MHz 60 | 1MHz 80 | 750KHz 100 | 600KHz 120 | 500KHz 150 | 400KHz 200 | 300KHz 300 | 200KHz 600 | 100KHz 800 | 75KHz 1000 | 60KHz 1200 | 50KHz 1500 | 40KHz 2000 | 30KHz 3000 | 20KHz 6000 | 10KHz 8000 | 7.5KHz (and so on) But i vote for supporting specific divider after all, one can never know if there is some obscure device out there in the wild that supports only 6365372Hz. > TODO: man page > --- > ft2232_spi.c | 54 +++++++++++++++++++++++++++++++++++++----------------- > 1 files changed, 37 insertions(+), 17 deletions(-) > > diff --git a/ft2232_spi.c b/ft2232_spi.c > index 122866f..7d598b1 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -64,17 +64,8 @@ const struct usbdev_status devs_ft2232spi[] = { > {}, > }; > > -/* > - * The 'H' chips can run internally at either 12MHz or 60MHz. > - * The non-H chips can only run at 12MHz. > - */ > -static uint8_t clock_5x = 1; > > -/* > - * In either case, the divisor is a simple integer clock divider. > - * If clock_5x is set, this divisor divides 30MHz, else it divides 6MHz. > - */ > -#define DIVIDE_BY 3 /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */ > +#define DEFAULT_DIVISOR 2 > > #define BITMODE_BITBANG_NORMAL 1 > #define BITMODE_BITBANG_SPI 2 > @@ -162,12 +153,28 @@ static const struct spi_programmer spi_programmer_ft2232 = { > /* Returns 0 upon success, a negative number upon errors. */ > int ft2232_spi_init(void) > { > - int f, ret = 0; > + int ret = 0; > struct ftdi_context *ftdic =&ftdic_context; > unsigned char buf[512]; > int ft2232_vid = FTDI_VID; > int ft2232_type = FTDI_FT4232H_PID; > enum ftdi_interface ft2232_interface = INTERFACE_B; > + /* > + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, > + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 > + * prescaler on the former to run on the same speed. > + */ > + uint8_t clock_5x = 1; > + /* In addition to the prescaler mentioned above there is also another > + * configurable one on all versions of the chips. Its divisor div can be > + * set by a 16 bit value x according to the following formula: > + * div = (1 + x) * 2<-> x = div / 2 - 1 > + * Hence the expressible divisors are all even numbers between 2 and > + * 2^17 (=131072) resulting in SCK frequencies of 2 MHz down to about > + * 92 Hz for 12 MHz inputs. > + */ > + uint32_t divisor = DEFAULT_DIVISOR; > + int f; > char *arg; > double mpsse_clk; > > @@ -243,6 +250,21 @@ int ft2232_spi_init(void) > } > } > free(arg); > + arg = extract_programmer_param("divisor"); > + if (arg&& strlen(arg)) { > + unsigned int temp = 0; > + char *endptr; > + temp = strtoul(arg,&endptr, 10); > + if (*endptr || temp< 2 || temp> 131072 || temp& 0x1) { > + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" > + "Valid are even values between 2 and 131072.\n", arg); > + free(arg); > + return -2; > + } else { > + divisor = (uint32_t)temp; > + } > + } > + free(arg); > msg_pdbg("Using device type %s %s ", > get_ft2232_vendorname(ft2232_vid, ft2232_type), > get_ft2232_devicename(ft2232_vid, ft2232_type)); > @@ -303,17 +325,15 @@ int ft2232_spi_init(void) > > msg_pdbg("Set clock divisor\n"); > buf[0] = 0x86; /* command "set divisor" */ > - /* valueL/valueH are (desired_divisor - 1) */ > - buf[1] = (DIVIDE_BY - 1)& 0xff; > - buf[2] = ((DIVIDE_BY - 1)>> 8)& 0xff; > if (send_buf(ftdic, buf, 3)) { > ret = -6; > goto ftdi_err; > } > + buf[1] = (divisor / 2 - 1)& 0xff; > + buf[2] = ((divisor / 2 - 1)>> 8)& 0xff; > > - msg_pdbg("MPSSE clock: %f MHz divisor: %d " > - "SPI clock: %f MHz\n", mpsse_clk, DIVIDE_BY, > - (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2))); > + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", > + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); > > /* Disconnect TDI/DO to TDO/DI for loopback. */ > msg_pdbg("No loopback of TDI/DO TDO/DI\n");

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[commit] r1537 - trunk
by repository service 16 May '12

16 May '12

Author: stefanct Date: Wed May 16 00:58:19 2012 New Revision: 1537 URL: http://flashrom.org/trac/flashrom/changeset/1537 Log: ft2232_spi.c: add frequency divisor parameter. This adds an optional argument when using the ft2232_spi programmer to set the frequency divisor. The valid values for the divisor is any even integer between 2 and 131072. Signed-off-by: Samir Ibradžić <sibradzic(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/ft2232_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Tue May 15 00:54:58 2012 (r1536) +++ trunk/flashrom.8 Wed May 16 00:58:19 2012 (r1537) @@ -549,6 +549,17 @@ .B 4232H and the default interface is .BR B . +.sp +All models supported by the ft2232_spi driver can configure the SPI clock rate by setting a divisor. The +expressible divisors are all even numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of +6 MHz down to about 92 Hz for 12 MHz inputs. The default divisor is set to 2, but you can use another one by +specifying the optional +.B divisor +parameter with the +.sp +.B " flashrom \-p ft2232_spi:divisor=div" +.sp +syntax. .SS .BR "serprog " programmer A mandatory parameter specifies either a serial Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Tue May 15 00:54:58 2012 (r1536) +++ trunk/ft2232_spi.c Wed May 16 00:58:19 2012 (r1537) @@ -64,17 +64,8 @@ {}, }; -/* - * The 'H' chips can run internally at either 12MHz or 60MHz. - * The non-H chips can only run at 12MHz. - */ -static uint8_t clock_5x = 1; -/* - * In either case, the divisor is a simple integer clock divider. - * If clock_5x is set, this divisor divides 30MHz, else it divides 6MHz. - */ -#define DIVIDE_BY 3 /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */ +#define DEFAULT_DIVISOR 2 #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 @@ -162,12 +153,28 @@ /* Returns 0 upon success, a negative number upon errors. */ int ft2232_spi_init(void) { - int f, ret = 0; + int ret = 0; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; int ft2232_vid = FTDI_VID; int ft2232_type = FTDI_FT4232H_PID; enum ftdi_interface ft2232_interface = INTERFACE_B; + /* + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 + * prescaler on the former to run on the same speed. + */ + uint8_t clock_5x = 1; + /* In addition to the prescaler mentioned above there is also another + * configurable one on all versions of the chips. Its divisor div can be + * set by a 16 bit value x according to the following formula: + * div = (1 + x) * 2 <-> x = div / 2 - 1 + * Hence the expressible divisors are all even numbers between 2 and + * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about + * 92 Hz for 12 MHz inputs. + */ + uint32_t divisor = DEFAULT_DIVISOR; + int f; char *arg; double mpsse_clk; @@ -243,6 +250,21 @@ } } free(arg); + arg = extract_programmer_param("divisor"); + if (arg && strlen(arg)) { + unsigned int temp = 0; + char *endptr; + temp = strtoul(arg, &endptr, 10); + if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" + "Valid are even values between 2 and 131072.\n", arg); + free(arg); + return -2; + } else { + divisor = (uint32_t)temp; + } + } + free(arg); msg_pdbg("Using device type %s %s ", get_ft2232_vendorname(ft2232_vid, ft2232_type), get_ft2232_devicename(ft2232_vid, ft2232_type)); @@ -303,17 +325,15 @@ msg_pdbg("Set clock divisor\n"); buf[0] = 0x86; /* command "set divisor" */ - /* valueL/valueH are (desired_divisor - 1) */ - buf[1] = (DIVIDE_BY - 1) & 0xff; - buf[2] = ((DIVIDE_BY - 1) >> 8) & 0xff; if (send_buf(ftdic, buf, 3)) { ret = -6; goto ftdi_err; } + buf[1] = (divisor / 2 - 1) & 0xff; + buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; - msg_pdbg("MPSSE clock: %f MHz divisor: %d " - "SPI clock: %f MHz\n", mpsse_clk, DIVIDE_BY, - (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2))); + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); /* Disconnect TDI/DO to TDO/DI for loopback. */ msg_pdbg("No loopback of TDI/DO TDO/DI\n");

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Chipset A49LF040A : Alix 1D --- Warning report and lspci report
by Joao Bonina 15 May '12

15 May '12

Alix 1D Url: http://pcengines.ch/alix1d.htm root@nst100:/boot# flashrom -p internal:laptop=this_is_not_a_laptop flashrom v0.9.5.2-r1517 on Linux 2.6.38-bpo.2-486 (i586), built with libpci 3.1.9, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. ======================================================================== WARNING! You may be running flashrom on an unsupported laptop. We could not detect this for sure because your vendor has not setup the SMBIOS tables correctly. You can enforce execution by adding '-p internal:laptop=this_is_not_a_laptop' to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "AMD CS5536". Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. No operations were specified. root@nst100:/boot# lspci 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block 00:0c.0 Multimedia audio controller: VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller (rev 01) 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.4 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)

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Re: [flashrom] Test report Biostar M7VIQ - Chip now detected, reading works
by Carl-Daniel Hailfinger 15 May '12

15 May '12

Am 15.05.2012 01:53 schrieb Gurken Papst: > On Mon, May 7, 2012 at 2:52 AM, Stefan Tauner > <stefan.tauner(a)student.tuwien.ac.at> wrote: >> > if you like please test the current svn HEAD flashrom on all boards with >> > a winbond superio and send us the usual flashrom -V output, thanks! > Ok, here is the new result. I suppose the line "Found Winbond Super > I/O, id 60" is telling me detection is working as expected? > > flashrom v0.9.5.2-r1534 on Linux 3.2.0-23-generic-pae (i686), built > with libpci 3.0.0, GCC 4.4.3, little endian > Calibrating delay loop... OS timer resolution is 1 usecs, 820M loops > per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 985 us, > 10000 myus = 9857 us, 4 myus = 4 us, OK. > Initializing internal programmer > DMI string baseboard-product-name: "KM266-8235" > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found Winbond Super I/O, id 60 Excellent, I can work with that. Expect an updated patch in the next few days. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Using flashrom with EliteGroup ECS GF8200A motherboard
by Stefan Tauner 15 May '12

15 May '12

On Sun, 6 May 2012 21:46:07 -0300 Denilson Figueiredo de Sá <denilsonsa(a)gmail.com> wrote: > Today I updated the BIOS of my EliteGroup ECS GF8200A motherboard. > […] > Following help from carldani and twice11, I tried flashing again the > new firmware. This time it worked and gave me no errors. The output is > also attached. thanks for the mail. since flashrom works in general on that board i have added it to our list of supported boards. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Flashrom -V Report for motherboard Asustek M4N68T-V2
by Stefan Tauner 15 May '12

15 May '12

On Sat, 12 May 2012 14:25:00 +0200 Jean-Christophe CHARRON <jeanchristophe.charron(a)gmail.com> wrote: > Thanks Stefan ,working well with 0.9.5 version. Thanks for your report! I have added the board to our list and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] test Asus P8H61 B3
by Stefan Tauner 15 May '12

15 May '12

On Wed, 9 May 2012 23:47:18 +0200 Laure-Hélène Bruneton <laure.helene.bruneton(a)gmail.com> wrote: > Could you tell me if it's okay to use flashrom to upgrade my BIOS please? at least there is no clear indication that it would not work. you have to try to be sure. if you do, please report back, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Test report Biostar M7VIQ - Chip now detected, reading works
by Stefan Tauner 15 May '12

15 May '12

On Tue, 15 May 2012 01:53:53 +0200 Gurken Papst <gurken.papst(a)gmail.com> wrote: > Ok, here is the new result. I suppose the line "Found Winbond Super > I/O, id 60" is telling me detection is working as expected? thanks! i don't know if it is working as expected (i haven't looked at the code), but that's the interesting part of the output, yes. we want to finally integrate a log file functionality into flashrom soon, so it is possible that the next version of the superio patch will take a while. but afaict carl-daniel is quite interesting in improving that part, so there surely will be some progress :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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DQ965GF
by gabris 15 May '12

15 May '12

Hello, as written in flashrom I'm sending verbose log which is from Intel DQ965GF motherboard running Q965, Mandriva 2010.2 as OS. it has SST25VF016B Bioschip. flashrom v0.9.5.2-r1515 on Linux 2.6.33.7-desktop-2mnb (i686), built with libpci 3.1.7, GCC 4.6.1 20110627 (Mandriva), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1852M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1004 us, 10000 myus = 10143 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ965GF" DMI string baseboard-version: "AAD41676-400" DMI string chassis-type: "Desktop" Found chipset "Intel ICH8DO" with PCI ID 8086:2814. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa WARNING: Setting 0xdc from 0xa to 0xb on ICH8DO failed. New value is 0xa. Root Complex Register Block address = 0xfed1c000 GCS = 0x464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x01ff0120 FREG1: BIOS region (0x00120000-0x001fffff) is read-write. 0x5C: 0x011f0003 FREG2: WARNING: Management Engine region (0x00003000-0x0011ffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x00000000 FREG4: WARNING: Platform Data region (0x00000000-0x00000fff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0x004200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x0008 (OPTYPE) 0x98: 0x0000ab9f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xC1: 0xffffffff (VSCC) VSCC: BES=0x3, WG=1, WSR=1, WEWS=1, EO=0xff, VCL=1 Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 2048 kB. There is only one partition containing the whole address space (0x000000 - 0x1fffff). There are 512 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (2048 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x4b, id2 0x93, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x4b, id2 0x93, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x4b, id2 0x93, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x0c, id2 0xe1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x4b, id2 0x93, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x4b, id2 0x93, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x5a, id2 0x47, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (2048 kB, Programmer-specific). No operations were specified. Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

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