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[PATCH 0/3] rayer_spi: Add support for Willem EPROM programmer SPI
by Ondrej Zary 16 Mar '13

16 Mar '13

This patch series adds support for SPI socket on Willem EPROM programmer to rayer_spi driver. Tested with PCB4.0 with W25X16 chip (which is not supported by the original Windows-only software). This patch series require 2013-03-06 rayer_spi patches by Kyösti Mälkki. P.S. As the rayer_spi driver becomes more generic, it should probably be renamed (e.g. lpt_spi). -- Ondrej Zary

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[PATCH 3/3] rayer_spi: add pinout for Willem EPROM programmer SPI
by Ondrej Zary 16 Mar '13

16 Mar '13

Add support for Willem EPROM programmer SPI socket. Tested on PCB4.0. Signed-off-by: Ondrej Zary <linux(a)rainbow-software.org> --- a/rayer_spi.c 2013-03-16 23:13:31.000000000 +0100 +++ b/rayer_spi.c 2013-03-16 23:13:39.000000000 +0100 @@ -124,6 +124,22 @@ static struct rayer_pinout wiggler_lpt = .miso_inverted = 1, }; +static void willem_preinit(void *); +static int willem_shutdown(void *); + +static struct rayer_pinout willem = { + .cs_bit = 3, /* SELIN */ + .cs_reg = 2, /* control register */ + .cs_inverted = 1, + .sck_bit = 1, /* D1 */ + .mosi_bit = 0, /* D0 */ + .mosi_inverted = 1, + .miso_bit = 7, /* BUSY */ + .miso_inverted = 1, + .preinit = willem_preinit, + .shutdown = willem_shutdown, +}; + struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, @@ -131,6 +147,7 @@ struct rayer_programmer rayer_spi_types[ {"byteblaster", NT, "Altera ByteBlaster", &altera_byteblaster}, {"stk200", NT, "Atmel STK200/300 adapter", &atmel_stk200}, {"wiggler", NT, "Wiggler LPT", &wiggler_lpt}, + {"willem", NT, "Willem EPROM Programmer SPI", &willem}, {0}, }; @@ -305,6 +322,21 @@ static int stk200_shutdown(void *data) { return 0; } +static void willem_preinit(void *data) { + msg_pdbg("willem_init\n"); + /* Disable VPP, enable VCC and OE. */ + lpt_outbyte[2] = (1 << 2) | (1 << 1) | (1 << 0); + OUTB(lpt_outbyte[2], lpt_iobase + 2); +} + +static int willem_shutdown(void *data) { + msg_pdbg("willem_shutdown\n"); + /* Disable VPP, VCC and OE. */ + lpt_outbyte[2] = (1 << 0); + OUTB(lpt_outbyte[2], lpt_iobase + 2); + return 0; +} + #else #error PCI port I/O access is not supported on this architecture yet. #endif -- Ondrej Zary

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[PATCH 2/3] rayer_spi: add control register support
by Ondrej Zary 16 Mar '13

16 Mar '13

Allow using control register (in addition to data register) for all output signals. Signed-off-by: Ondrej Zary <linux(a)rainbow-software.org> --- a/rayer_spi.c 2013-03-16 23:13:02.000000000 +0100 +++ b/rayer_spi.c 2013-03-16 23:13:09.000000000 +0100 @@ -58,6 +58,9 @@ struct rayer_pinout { int sck_inverted; int mosi_inverted; int miso_inverted; + int cs_reg; + int sck_reg; + int mosi_reg; void (*preinit)(void *); int (*shutdown)(void *); }; @@ -136,33 +139,33 @@ struct rayer_pinout *pinout = NULL; static uint16_t lpt_iobase; /* Cached value of last byte sent. */ -static uint8_t lpt_outbyte; +static uint8_t lpt_outbyte[3]; static void rayer_bitbang_set_cs(int val) { if (pinout->cs_inverted) val = !val; - lpt_outbyte &= ~(1 << pinout->cs_bit); - lpt_outbyte |= (val << pinout->cs_bit); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[pinout->cs_reg] &= ~(1 << pinout->cs_bit); + lpt_outbyte[pinout->cs_reg] |= (val << pinout->cs_bit); + OUTB(lpt_outbyte[pinout->cs_reg], lpt_iobase + pinout->cs_reg); } static void rayer_bitbang_set_sck(int val) { if (pinout->sck_inverted) val = !val; - lpt_outbyte &= ~(1 << pinout->sck_bit); - lpt_outbyte |= (val << pinout->sck_bit); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[pinout->sck_reg] &= ~(1 << pinout->sck_bit); + lpt_outbyte[pinout->sck_reg] |= (val << pinout->sck_bit); + OUTB(lpt_outbyte[pinout->sck_reg], lpt_iobase + pinout->sck_reg); } static void rayer_bitbang_set_mosi(int val) { if (pinout->mosi_inverted) val = !val; - lpt_outbyte &= ~(1 << pinout->mosi_bit); - lpt_outbyte |= (val << pinout->mosi_bit); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[pinout->mosi_reg] &= ~(1 << pinout->mosi_bit); + lpt_outbyte[pinout->mosi_reg] |= (val << pinout->mosi_bit); + OUTB(lpt_outbyte[pinout->mosi_reg], lpt_iobase + pinout->mosi_reg); } static int rayer_bitbang_get_miso(void) @@ -245,7 +248,8 @@ int rayer_spi_init(void) return 1; /* Get the initial value before writing to any line. */ - lpt_outbyte = INB(lpt_iobase); + lpt_outbyte[0] = INB(lpt_iobase); + lpt_outbyte[2] = INB(lpt_iobase + 2); if (pinout->shutdown) register_shutdown(pinout->shutdown, (void*)pinout); @@ -261,15 +265,15 @@ int rayer_spi_init(void) static void dlc5b_preinit(void * data) { msg_pdbg("dlc5b_preinit\n"); /* Assert pin 6 to receive MISO. */ - lpt_outbyte |= (1<<4); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[0] |= (1<<4); + OUTB(lpt_outbyte[0], lpt_iobase); } static int dlc5b_shutdown(void * data) { msg_pdbg("dlc5b_shutdown\n"); /* De-assert pin 6 to force MISO low. */ - lpt_outbyte &= ~(1<<4); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[0] &= ~(1<<4); + OUTB(lpt_outbyte[0], lpt_iobase); return 0; } @@ -289,15 +293,15 @@ static int byteblaster_shutdown(void * d static void stk200_preinit(void *data) { msg_pdbg("stk200_init\n"); /* Assert #EN signals, set LED signal. */ - lpt_outbyte = (1 << 6) ; - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[0] = (1 << 6) ; + OUTB(lpt_outbyte[0], lpt_iobase); } static int stk200_shutdown(void *data) { msg_pdbg("stk200_shutdown\n"); /* Assert #EN signals, clear LED signal. */ - lpt_outbyte = (1 << 2) | (1 << 3); - OUTB(lpt_outbyte, lpt_iobase); + lpt_outbyte[0] = (1 << 2) | (1 << 3); + OUTB(lpt_outbyte[0], lpt_iobase); return 0; } -- Ondrej Zary

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[PATCH 1/3] rayer_spi: add signal inversion support
by Ondrej Zary 16 Mar '13

16 Mar '13

Add signal inversion support for all signals and remove the bit 7 hack in rayer_bitbang_get_miso(). Signed-off-by: Ondrej Zary <linux(a)rainbow-software.org> --- a/rayer_spi.c 2013-03-16 23:11:57.000000000 +0100 +++ b/rayer_spi.c 2013-03-16 23:12:06.000000000 +0100 @@ -54,6 +54,10 @@ struct rayer_pinout { int sck_bit; int mosi_bit; int miso_bit; + int cs_inverted; + int sck_inverted; + int mosi_inverted; + int miso_inverted; void (*preinit)(void *); int (*shutdown)(void *); }; @@ -92,6 +96,7 @@ static struct rayer_pinout altera_bytebl .sck_bit = 0, .mosi_bit = 6, .miso_bit = 7, + .miso_inverted = 1, .preinit = byteblaster_preinit, .shutdown = byteblaster_shutdown, }; @@ -113,6 +118,7 @@ static struct rayer_pinout wiggler_lpt = .sck_bit = 2, .mosi_bit = 3, .miso_bit = 7, + .miso_inverted = 1, }; struct rayer_programmer rayer_spi_types[] = { @@ -134,6 +140,8 @@ static uint8_t lpt_outbyte; static void rayer_bitbang_set_cs(int val) { + if (pinout->cs_inverted) + val = !val; lpt_outbyte &= ~(1 << pinout->cs_bit); lpt_outbyte |= (val << pinout->cs_bit); OUTB(lpt_outbyte, lpt_iobase); @@ -141,6 +149,8 @@ static void rayer_bitbang_set_cs(int val static void rayer_bitbang_set_sck(int val) { + if (pinout->sck_inverted) + val = !val; lpt_outbyte &= ~(1 << pinout->sck_bit); lpt_outbyte |= (val << pinout->sck_bit); OUTB(lpt_outbyte, lpt_iobase); @@ -148,6 +158,8 @@ static void rayer_bitbang_set_sck(int va static void rayer_bitbang_set_mosi(int val) { + if (pinout->mosi_inverted) + val = !val; lpt_outbyte &= ~(1 << pinout->mosi_bit); lpt_outbyte |= (val << pinout->mosi_bit); OUTB(lpt_outbyte, lpt_iobase); @@ -157,8 +169,10 @@ static int rayer_bitbang_get_miso(void) { uint8_t tmp; - tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted + tmp = INB(lpt_iobase + 1); tmp = (tmp >> pinout->miso_bit) & 0x1; + if (pinout->miso_inverted) + tmp = !tmp; return tmp; } -- Ondrej Zary

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Re: [flashrom] [PATCH] Fix evil twins of Macronix MX25L1605, MX25L3205, MX25L6405.
by Stefan Tauner 15 Mar '13

15 Mar '13

On Sun, 3 Feb 2013 08:40:08 +0100 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Similarly to the previous patch this one updates the chips identified as above > with references to and data about their respective twins. Unlike previously this > one deals with the more evil details. > > Helge Wagner from GE discovered some problems with chips sharing IDs > and proposed a patch to tackle (some of) them, see: > http://patchwork.coreboot.org/patch/3709/ > That patch was bitrotting in our mailboxes for a long time and it is still not > ready for merge, but we increasingly get reports about problems (e.g. > http://paste.flashrom.org/view.php?id=1525) regarding these chips and > hence must act to ensure users' safety. > > This patch splits the chip definitions of evil twins into separate ones which > correctly declare the respective attributes (the main problems are the erase > block sizes for the 0x20 opcode and hence my changes combine different > chips with partly different attributes apart from their names as long as the > erasers layout it the same). This forces the user to select the (right) chip > definition with the -c/--chip parameter and hence will break a number of > previously perfectly working environments. > > 0x2015 is used by and split to > - MX25L1605 (64kB sectors in 0x20 erases) > - MX25L1605A (4kB in 0x20 erases and an additional 0x52 opcode with 64kB blocks) > - MX25L1605D/MX25L1608D (4k sectors in 0x20 erases) > > 0x2016 is used by and split to > - MX25L3205, MX25L3205A (64kB 0x20) > - MX25L3205D/MX25L3208D (4kB 0x20) > - MX25L3206E (4k 0x20, 64k 0x52) > > 0x2017 is used by and split to > - MX25L6405 MX25L6405D (64k 0x20) > - MX25L6406E/MX25L6436E (4k 0x20) > - MX25L6445E (4k 0x20, 64k 0x52) > > Bonus: add some minor details to MX25L1635D, MX25L1635E, MX25L3235D, > MX25L12805D. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> self-acked and committed in r1657. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1657 - trunk
by repository service 15 Mar '13

15 Mar '13

Author: stefanct Date: Sat Mar 16 02:22:12 2013 New Revision: 1657 URL: http://flashrom.org/trac/flashrom/changeset/1657 Log: Fix evil twins of Macronix MX25L1605, MX25L3205, MX25L6405. Similarly to the patch in r1647 this one updates the chips identified as above with references to and data about their respective twins. Unlike previously this one deals with the more evil details. Helge Wagner from GE discovered some problems with chips sharing IDs and proposed a patch to tackle (some of) them, see: http://patchwork.coreboot.org/patch/3709/ That patch was bitrotting in our mailboxes for a long time and it is still not ready for merge, but we increasingly get reports about problems (e.g. http://paste.flashrom.org/view.php?id=1525) regarding these chips and hence must act to ensure users' safety. This patch splits the chip definitions of evil twins into separate ones which correctly declare the respective attributes (the main problems are the erase block sizes for the 0x20 opcode and hence my changes combine different chips with partly different attributes apart from their names as long as the erasers layout it the same). This forces the user to select the (right) chip definition with the -c/--chip parameter and hence will break a number of previously perfectly working environments. 0x2015 is used by and split to - MX25L1605 (64kB sectors in 0x20 erases) - MX25L1605A/MX25L1606E (4kB in 0x20 erases and an additional 0x52 opcode with 64kB blocks) - MX25L1605D/MX25L1608D (4k sectors in 0x20 erases) 0x2016 is used by and split to - MX25L3205/MX25L3205A (64kB 0x20) - MX25L3205D/MX25L3208D (4kB 0x20) - MX25L3206E (4k 0x20, 64k 0x52) 0x2017 is used by and split to - MX25L6405/MX25L6405D (64k 0x20) - MX25L6406E/MX25L6436E (4k 0x20) - MX25L6445E (4k 0x20, 64k 0x52) Bonus: add some minor details to MX25L1635D, MX25L1635E, MX25L3235D, MX25L12805D. Tested with MX25L3206E, MX25L64036E. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Mar 15 04:12:29 2013 (r1656) +++ trunk/flashchips.c Sat Mar 16 02:22:12 2013 (r1657) @@ -5273,10 +5273,46 @@ .block_erasers = { { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605A/MX25L1606E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 (MX25L1606E only) */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ + .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 32} }, @@ -5289,10 +5325,45 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* MX25L1605A bp2 only */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605D/MX25L1608D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: Continously Program (CP) mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5304,7 +5375,8 @@ .model_id = MACRONIX_MX25L1635D, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5324,10 +5396,10 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -5339,7 +5411,8 @@ .model_id = MACRONIX_MX25L1635E, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5359,16 +5432,16 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L3205", + .name = "MX25L3205(A)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L3205, @@ -5381,12 +5454,87 @@ .block_erasers = { { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3205D/MX25L3208D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: CP mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3206E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { @@ -5394,10 +5542,10 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5409,7 +5557,8 @@ .model_id = MACRONIX_MX25L3235D, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 256B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5429,7 +5578,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5438,13 +5587,14 @@ { .vendor = "Macronix", - .name = "MX25L6405", + .name = "MX25L6405(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L6405, .total_size = 8192, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L6405D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5464,7 +5614,43 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 has different meanings */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L6406E/MX25L6436E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* OTP: 06E 64B/36E 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 for 36E is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5473,13 +5659,54 @@ { .vendor = "Macronix", - .name = "MX25L12805", + .name = "MX25L6445E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L12805(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L12805, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5499,10 +5726,10 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* MX25L12805D: Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Fri Mar 15 04:12:29 2013 (r1656) +++ trunk/flashchips.h Sat Mar 16 02:22:12 2013 (r1657) @@ -397,10 +397,10 @@ #define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ #define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ -#define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ -#define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D}, MX25L6406E, MX25L6436E */ -#define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ +#define MACRONIX_MX25L1605 0x2015 /* MX25L1605 (64k 0x20); MX25L1605A/MX25L1606E (4k 0x20, 64k 0x52); MX25L1605D/MX25L1608D (4k 0x20) */ +#define MACRONIX_MX25L3205 0x2016 /* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L12805 0x2018 /* Same as MX25L12805D */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX25U1635E 0x2535

1 0

Intel QM67 - Macronix MX25L6405 flash read problem
by George Ciobanu 15 Mar '13

15 Mar '13

Hello, I've tried to read the contents of the memory in the subject, but it failed. I'm using a Panasonic CF-53 Toughbook and I have attached the verbose output. Do you think that I will be able to read the memory using serprog and an Arduino, unsoldering it from the motherboard or will flashrom just give the same error? Thanks for the great software and support! George

1 0

Supermicro X9SCM-F - not supported yet?
by Alexander List 15 Mar '13

15 Mar '13

Hi, according to your website my board (Supermicro X9SCM-F) is not supported yet. http://www.supermicro.com/products/motherboard/xeon/c202_c204/x9scm-f.cfm I wonder what's faster - me figuring out how to get a PXE boot environment up and running here at home so I can boot a FreeDOS HDD image via the net, or me helping you support this type of board ;) output of flashrom -V attached, as well as dmidecode. cheers Alex PS: You can find me on freenode as #alexlist - around the ubuntu channels ... just ping me if I can help you support this board.

2 3

Re: [flashrom] [coreboot] IMC on persimmon (was: Flashrom erase failure)
by Wolfgang Kamp - datakamp 15 Mar '13

15 Mar '13

Hi Marc, first I have to do some rework on my flashrom patches, after easter I will send them to you. Wolfgang -----Ursprüngliche Nachricht----- Von: Marc Jones [mailto:marc.jones@se-eng.com] Gesendet: Donnerstag, 14. März 2013 16:11 An: flashrom(a)flashrom.org Cc: Wolfgang Kamp - datakamp; Martin Roth; bruce.griffith(a)se-eng.com Betreff: Re: [flashrom] [coreboot] IMC on persimmon (was: Flashrom erase failure) On Thu, Mar 14, 2013 at 2:55 AM, Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > On Mon, 4 Mar 2013 13:43:14 +0100 > Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > >> On Mon, 4 Mar 2013 09:42:43 +0100 >> Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: >> >> > Hi, >> > >> > recently I had the same problems to get Flashrom working on an embedded platform with AMD G-series processor similar to Persimmon. >> > I did all the patches to get Flashrom working but actually I'm not able to commit to flashrom.org. >> > If there is interest I would send the necessary files to someone who can do that for me. >> >> Hello Wolfgang, >> >> you can/should send any flashrom-related patches to >> flashrom(a)flashrom.org. . > > ping > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom I'm not sure if Stefan was volunteering to do that, but Sage can help handle patches if you send them. Marc

1 0

[commit] r1656 - trunk
by repository service 14 Mar '13

14 Mar '13

Author: stefanct Date: Fri Mar 15 04:12:29 2013 New Revision: 1656 URL: http://flashrom.org/trac/flashrom/changeset/1656 Log: Add support for Intel Lynx Point low-power and Wellsburg. New IDs taken from Intel's patches for the Linux kernel. Also, refine original Lynx Point naming etc. Based on the chromiumos patch Change-Id: I303a05baa80e4449e70d20adf78ebc7128b88d8e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/programmer.h Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Mar 15 03:03:16 2013 (r1655) +++ trunk/chipset_enable.c Fri Mar 15 04:12:29 2013 (r1656) @@ -512,6 +512,8 @@ static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; + static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch8_lp[] = { "SPI", "LPC", "unknown", "unknown" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { @@ -534,6 +536,15 @@ case CHIPSET_7_SERIES_PANTHER_POINT: straps_names = straps_names_pch567; break; + case CHIPSET_8_SERIES_LYNX_POINT: + straps_names = straps_names_pch8; + break; + case CHIPSET_8_SERIES_LYNX_POINT_LP: + straps_names = straps_names_pch8_lp; + break; + case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet + straps_names = straps_names_unknown; + break; default: msg_gerr("%s: unknown ICH generation. Please report!\n", __func__); @@ -557,7 +568,18 @@ msg_pdbg("GCS = 0x%x: ", gcs); msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); - bbs = (gcs >> 10) & 0x3; + + switch (ich_generation) { + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet + /* Lynx Point LP uses a single bit for GCS */ + bbs = (gcs >> 10) & 0x1; + break; + default: + /* Older chipsets use two bits for GCS */ + bbs = (gcs >> 10) & 0x3; + break; + } msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); @@ -635,6 +657,18 @@ return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT); } +/* Lynx Point aka. 8 series low-power */ +static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT_LP); +} + +/* Wellsburg (for Haswell-EP Xeons) */ +static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_WELLSBURG); +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1468,37 +1502,73 @@ {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c41, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c42, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Engineering Sample", enable_flash_pch8}, + {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Engineering Sample", enable_flash_pch8}, {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c44, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c44, NT, "Intel", "Z87", enable_flash_pch8}, {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c46, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c49, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4a, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4b, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4c, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, + {0x8086, 0x8c4a, NT, "Intel", "H87", enable_flash_pch8}, + {0x8086, 0x8c4b, NT, "Intel", "HM87", enable_flash_pch8}, + {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4e, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4f, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c50, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, + {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, + {0x8086, 0x8c50, NT, "Intel", "B85", enable_flash_pch8}, {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c52, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c54, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c56, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5c, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Engineering Sample", enable_flash_pch8_lp}, + {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, + {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, + {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, + {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, #endif {0}, }; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Mar 15 03:03:16 2013 (r1655) +++ trunk/programmer.h Fri Mar 15 04:12:29 2013 (r1656) @@ -547,7 +547,9 @@ CHIPSET_5_SERIES_IBEX_PEAK, CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, - CHIPSET_8_SERIES_LYNX_POINT + CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_8_SERIES_LYNX_POINT_LP, + CHIPSET_8_SERIES_WELLSBURG, }; /* ichspi.c */

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