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[PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 18 Jul '14

18 Jul '14

This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 5 seconds for writes of 32 kB chips. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Hello Ricardo, the patch is not merged yet but I think the final version is attached below (applicable to r1830). We have integrated proper support for EEPROM semantics in r1822 which is used in this patch. This allows flashrom to write without prior erases which were implicitly scheduled without said patch unnecessarily on EEPROMs. Maybe this even speeds up things a bit. I'll commit the patch as soon as it got tested. Thanks again for the initial patch, all the testing and also your patience with us ;) Makefile | 14 +++ flashrom.8.tmpl | 16 ++- flashrom.c | 12 ++ nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 5 files changed, 379 insertions(+), 3 deletions(-) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 7a48889..64798c9 100644 --- a/Makefile +++ b/Makefile @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0b4867d..153591a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -225,6 +225,8 @@ bitbanging adapter) .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ For more information please see .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory diff --git a/flashrom.c b/flashrom.c index 4f41bf4..f7d1803 100644 --- a/flashrom.c +++ b/flashrom.c @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..b03899f --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_programmer opaque_programmer_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_programmer(&opaque_programmer_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index b0df2ba..83a05b9 100644 --- a/programmer.h +++ b/programmer.h @@ -84,6 +84,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- Kind regards, Stefan Tauner

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Re: [flashrom] ft2232_spi:type=jtagkey
by Stefan Tauner 16 Jul '14

16 Jul '14

On Thu, 5 Jun 2014 12:26:58 +0700 Alfin Cahya <alfincp(a)gmail.com> wrote: > Uh oh. Erase/write failed. Checking if anything has changed. > Reading current flash chip contents... done. > Apparently at least some data has changed. > Your flash chip is in an unknown state. That still looks to me like a floating write protection (or hold) pin. Sorry for the late reply... did you manage to get it to work eventually? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add new programmer for EEPROMs attached to Intel 82580 NICs.
by Ricardo Ribalda Delgado 15 Jul '14

15 Jul '14

Hi Is this currently merged into some branch? Regards On Tue, Jun 17, 2014 at 1:24 AM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This patch lets you read and write the EEPROM on 82580-based gigabit NIC > cards. So far it has been tested on copper NICs only, but other variants > employing this controller should work too. > It is a nice substitution for the official eeupdate tool. > > Speed is quite decent: > > root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -E > flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. > Erasing and writing flash chip... Erase/write done. > > real 0m4.699s > user 0m4.676s > sys 0m0.024s > > root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -w original.kk > flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFIED. > > real 0m3.533s > user 0m3.516s > sys 0m0.018s > > Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > Makefile | 9 ++ > flashrom.8.tmpl | 13 ++- > flashrom.c | 12 ++ > nicintel_eeprom.c | 334 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > programmer.h | 9 ++ > 5 files changed, 376 insertions(+), 1 deletion(-) > create mode 100644 nicintel_eeprom.c > > diff --git a/Makefile b/Makefile > index 7a48889..b47b644 100644 > --- a/Makefile > +++ b/Makefile > @@ -426,6 +426,9 @@ CONFIG_NICINTEL ?= yes > # Always enable SPI on Intel NICs for now. > CONFIG_NICINTEL_SPI ?= yes > > +# Always enable EEPROM on Intel NICs for now. > +CONFIG_NICINTEL_EEPROM ?= yes > + > # Always enable SPI on OGP cards for now. > CONFIG_OGP_SPI ?= yes > > @@ -626,6 +629,12 @@ PROGRAMMER_OBJS += nicintel_spi.o > NEED_PCI := yes > endif > > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' > +PROGRAMMER_OBJS += nicintel_eeprom.o > +NEED_PCI := yes > +endif > + > ifeq ($(CONFIG_OGP_SPI), yes) > FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' > PROGRAMMER_OBJS += ogp_spi.o > diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl > index 0b4867d..d3000c2 100644 > --- a/flashrom.8.tmpl > +++ b/flashrom.8.tmpl > @@ -225,6 +225,8 @@ bitbanging adapter) > .sp > .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" > .sp > +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" > +.sp > Some programmers have optional or mandatory parameters which are described > in detail in the > .B PROGRAMMER SPECIFIC INFO > @@ -591,7 +593,7 @@ syntax where > .B content > is an 8-bit hexadecimal value. > .SS > -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ > +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ > , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ > , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers > These programmers have an option to specify the PCI address of the card > @@ -625,6 +627,14 @@ For more information please see > .nh > .B http://flashrom.org/VT6421A > .SS > +.BR "nicintel_eeprom " programmer > +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs > +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their > +size nor allow to be identified, the controller relies on correct size values written to predefined addresses > +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed > +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) > +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. > +.SS > .BR "ft2232_spi " programmer > An optional parameter specifies the controller > type and channel/interface/port it should support. For that you have to use the > @@ -903,6 +913,7 @@ flashrom exits with 0 on success, 1 on most failures but with 3 if a call to mma > .SH REQUIREMENTS > flashrom needs different access permissions for different programmers. > .sp > +.\" FIXME: nicintel* > .B internal > needs raw memory access, PCI configuration space access, raw I/O port > access (x86) and MSR access (x86). > diff --git a/flashrom.c b/flashrom.c > index 408c555..7375b2e 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { > }, > #endif > > +#if CONFIG_NICINTEL_EEPROM == 1 > + { > + .name = "nicintel_eeprom", > + .type = PCI, > + .devs.dev = nics_intel_ee, > + .init = nicintel_ee_init, > + .map_flash_region = fallback_map, > + .unmap_flash_region = fallback_unmap, > + .delay = internal_delay, > + }, > +#endif > + > #if CONFIG_OGP_SPI == 1 > { > .name = "ogp_spi", > diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c > new file mode 100644 > index 0000000..48fac4a > --- /dev/null > +++ b/nicintel_eeprom.c > @@ -0,0 +1,334 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S > + * Copyright (C) 2011, 2014 Stefan Tauner > + * > + * Based on nicinctel_spi.c and ichspi.c > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see http://www.gnu.org/licenses/. > + */ > + > +/* > + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet > + * 3.3.1.4: General EEPROM Software Access > + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) > + * 7.4: Register Descriptions > + */ > + > +#include <stdlib.h> > +#include <unistd.h> > +#include "flash.h" > +#include "spi.h" > +#include "programmer.h" > +#include "hwaccess.h" > + > +#define PCI_VENDOR_ID_INTEL 0x8086 > +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ > + > +#define EEC 0x10 /* EEPROM/Flash Control Register */ > +#define EERD 0x14 /* EEPROM Read Register */ > + > +/* EPROM/Flash Control Register bits */ > +#define EE_SCK 0 > +#define EE_CS 1 > +#define EE_SI 2 > +#define EE_SO 3 > +#define EE_REQ 6 > +#define EE_GNT 7 > +#define EE_PRES 8 > +#define EE_SIZE 11 > +#define EE_SIZE_MASK 0xf > + > +/* EEPROM Read Register bits */ > +#define EERD_START 0 > +#define EERD_DONE 1 > +#define EERD_ADDR 2 > +#define EERD_DATA 16 > + > +#define BIT(x) (1<<x) > +#define PAGE_MASK 0x3f > + > +static uint8_t *nicintel_eebar; > +static struct pci_dev *nicintel_pci; > + > +#define UNPROG_DEVICE 0x1509 > + > +const struct dev_entry nics_intel_ee[] = { > + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, > + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, > + {0}, > +}; > + > +static int nicintel_ee_probe(struct flashctx *flash) > +{ > + if (nicintel_pci->device_id == UNPROG_DEVICE) > + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ > + else { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); > + switch (tmp) { > + case 7: > + flash->chip->total_size = 16; > + break; > + case 8: > + flash->chip->total_size = 32; > + break; > + default: > + msg_cerr("Unsupported chip size 0x%x\n", tmp); > + return 0; > + } > + } > + > + flash->chip->page_size = PAGE_MASK + 1; > + flash->chip->tested = TEST_OK_PREW; > + /* FIXME: Due to the write_granularity set below we do 0xFF dummy writes to fake erases on every write > + * which is completely pointless and potentially even harmful for the hardware. Programmers/devices > + * should be able to indicate that erases are not needed for writes. */ > + flash->chip->gran = write_gran_1byte; > + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); > + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); > + > + return 1; > +} > + > +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) > +{ > + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); > + pci_mmio_writel(tmp, nicintel_eebar + EERD); > + > + /* Poll done flag. 10.000.000 cycles seem to be enough. */ > + uint32_t i; > + for (i = 0; i < 10000000; i++) { > + tmp = pci_mmio_readl(nicintel_eebar + EERD); > + if (tmp & BIT(EERD_DONE)) { > + *word = (tmp >> EERD_DATA) & 0xffff; > + return 0; > + } > + } > + > + return -1; > +} > + > +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + uint16_t word; > + > + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address > + * explicitly at the start (and also at the end in the loop below). */ > + if (addr & 1) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + } > + > + while (len > 0) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + if (len > 0) { > + *buf++ = (word >> 8) & 0xff; > + addr++; > + len--; > + } > + } > + > + return 0; > +} > + > +static int nicintel_ee_bitset(int reg, int bit, bool val) > +{ > + uint32_t tmp; > + > + tmp = pci_mmio_readl(nicintel_eebar + reg); > + if (val) > + tmp |= BIT(bit); > + else > + tmp &= ~BIT(bit); > + pci_mmio_writel(tmp, nicintel_eebar + reg); > + > + return -1; > +} > + > +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ > +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) > +{ > + uint8_t out = 0x0; > + > + int i; > + for (i = 7; i >= 0; i--) { > + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); > + nicintel_ee_bitset(EEC, EE_SCK, 1); > + if (miso != NULL) { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (tmp & BIT(EE_SO)) > + out |= BIT(i); > + } > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + } > + > + if (miso != NULL) > + *miso = out; > + > + return 0; > +} > + > +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ > +static int nicintel_ee_ready(void) > +{ > + unsigned int i; > + for (i = 0; i < 1000; i++) { > + nicintel_ee_bitset(EEC, EE_CS, 0); > + > + nicintel_ee_bitbang(JEDEC_RDSR, NULL); > + uint8_t rdsr; > + nicintel_ee_bitbang(0x00, &rdsr); > + > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (!(rdsr & SPI_SR_WIP)) { > + return 0; > + } > + } > + return -1; > +} > + > +/* Requests direct access to the SPI pins. */ > +static int nicintel_ee_req(void) > +{ > + uint32_t tmp; > + nicintel_ee_bitset(EEC, EE_REQ, 1); > + > + tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (!(tmp & BIT(EE_GNT))) { > + msg_perr("Enabling eeprom access failed.\n"); > + return 1; > + } > + > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + return 0; > +} > + > +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + if (nicintel_ee_req()) > + return -1; > + > + int ret = -1; > + if (nicintel_ee_ready()) > + goto out; > + > + while (len > 0) { > + /* WREN */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_WREN, NULL); > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + > + /* data */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); > + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); > + nicintel_ee_bitbang(addr & 0xff, NULL); > + while (len > 0) { > + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); > + len--; > + addr++; > + if (!(addr & PAGE_MASK)) > + break; > + } > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (nicintel_ee_ready()) > + goto out; > + } > + ret = 0; > +out: > + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ > + return ret; > +} > + > +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) > +{ > + return nicintel_ee_write(flash, NULL, addr, len); > +} > + > +static const struct opaque_programmer opaque_programmer_nicintel_ee = { > + .probe = nicintel_ee_probe, > + .read = nicintel_ee_read, > + .write = nicintel_ee_write, > + .erase = nicintel_ee_erase, > +}; > + > +static int nicintel_spi_shutdown(void *eecp) > +{ > + uint32_t old_eec = *(uint32_t *)eecp; > + /* Request bitbanging and unselect the chip first to be safe. */ > + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) > + return -1; > + > + /* Try to restore individual bits we care about. */ > + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); > + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); > + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); > + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ > + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); > + > + free(eecp); > + return ret; > +} > + > +int nicintel_ee_init(void) > +{ > + if (rget_io_perms()) > + return 1; > + > + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); > + if (!dev) > + return 1; > + > + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); > + if (!io_base_addr) > + return 1; > + > + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); > + nicintel_pci = dev; > + if (dev->device_id != UNPROG_DEVICE) { > + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); > + > + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), > + * and 3.3.1.7 for possible recovery. */ > + if (!(eec & BIT(EE_PRES))) { > + msg_perr("Controller reports no EEPROM is present.\n"); > + return 1; > + } > + > + uint32_t *eecp = malloc(sizeof(uint32_t)); > + if (eecp == NULL) > + return 1; > + *eecp = eec; > + > + if (register_shutdown(nicintel_spi_shutdown, eecp)) > + return 1; > + } > + > + return register_opaque_programmer(&opaque_programmer_nicintel_ee); > +} > diff --git a/programmer.h b/programmer.h > index b0df2ba..83a05b9 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -84,6 +84,9 @@ enum programmer { > #if CONFIG_NICINTEL_SPI == 1 > PROGRAMMER_NICINTEL_SPI, > #endif > +#if CONFIG_NICINTEL_EEPROM == 1 > + PROGRAMMER_NICINTEL_EEPROM, > +#endif > #if CONFIG_OGP_SPI == 1 > PROGRAMMER_OGP_SPI, > #endif > @@ -416,6 +419,12 @@ int nicintel_spi_init(void); > extern const struct dev_entry nics_intel_spi[]; > #endif > > +/* nicintel_eeprom.c */ > +#if CONFIG_NICINTEL_EEPROM == 1 > +int nicintel_ee_init(void); > +extern const struct dev_entry nics_intel_ee[]; > +#endif > + > /* ogp_spi.c */ > #if CONFIG_OGP_SPI == 1 > int ogp_spi_init(void); > -- > Kind regards, Stefan Tauner > -- Ricardo Ribalda

1 0

[commit] r1830 - trunk
by repository service 15 Jul '14

15 Jul '14

Author: stefanct Date: Tue Jul 15 15:50:58 2014 New Revision: 1830 URL: http://flashrom.org/trac/flashrom/changeset/1830 Log: Add support for AMD Bolton chipset. SPI controller on the bolton chipset uses the same 3-bit speed settings as Yangtze, but is otherwise the same as the Hudson chips. Note that the Bolton RRG doesn't specify a speed setting for the bit setting of 0b111, so I'm assuming that it's the same setting as Yangtze. Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/sb600spi.c Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jul 15 15:50:17 2014 (r1829) +++ trunk/sb600spi.c Tue Jul 15 15:50:58 2014 (r1830) @@ -51,6 +51,7 @@ CHIPSET_SB7XX, /* SP5100 too */ CHIPSET_SB89XX, /* Hudson-1 too */ CHIPSET_HUDSON234, + CHIPSET_BOLTON, CHIPSET_YANGTZE, }; static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; @@ -137,6 +138,9 @@ if (rev >= 0x11 && rev <= 0x15) { amd_gen = CHIPSET_HUDSON234; msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev == 0x16) { + amd_gen = CHIPSET_BOLTON; + msg_pdbg("Bolton detected.\n"); } else if (rev >= 0x39 && rev <= 0x3A) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); @@ -409,23 +413,11 @@ } /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used. - * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 bolton/yangtze * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] */ - if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); - msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); - if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; - if (tmp == 0) { - msg_perr("Enabling Spi100 failed.\n"); - return 1; - } - msg_pdbg("Enabling Spi100 succeeded.\n"); - } - + if (amd_gen >= CHIPSET_BOLTON) { static const char *spireadmodes[] = { "Normal (up to 33 MHz)", /* 0 */ "Reserved", /* 1 */ @@ -434,7 +426,7 @@ "Dual IO (1-2-2)", /* 4 */ "Quad IO (1-4-4)", /* 5 */ "Normal (up to 66 MHz)", /* 6 */ - "Fast Read", /* 7 */ + "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; tmp = mmio_readl(sb600_spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); @@ -448,11 +440,25 @@ msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ - msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); - msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); - msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); - msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + if (amd_gen >= CHIPSET_YANGTZE) { + tmp = mmio_readb(sb600_spibar + 0x20); + msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + if ((tmp & 0x1) == 0) { + rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + if (tmp == 0) { + msg_perr("Enabling Spi100 failed.\n"); + return 1; + } + msg_pdbg("Enabling Spi100 succeeded.\n"); + } + + tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); + msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); + msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); + msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;

1 0

[commit] r1829 - trunk
by repository service 15 Jul '14

15 Jul '14

Author: stefanct Date: Tue Jul 15 15:50:17 2014 New Revision: 1829 URL: http://flashrom.org/trac/flashrom/changeset/1829 Log: Refine messages regarding AMD FCH flash protections. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jul 14 20:04:15 2014 (r1828) +++ trunk/chipset_enable.c Tue Jul 15 15:50:17 2014 (r1829) @@ -999,20 +999,23 @@ /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n", - (prot & 0x1) ? "write " : "", + msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...", (prot & 0x2) ? "read " : "", + (prot & 0x1) ? "write " : "", (prot & 0xfffff800), (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); prot &= 0xfffffffc; rpci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); - if (prot & 0x3) - msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n", - (prot & 0x1) ? "write " : "", + if ((prot & 0x3) != 0) { + msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n", (prot & 0x2) ? "read " : "", + (prot & 0x1) ? "write " : "", (prot & 0xfffff800), (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); + continue; + } + msg_pdbg("done.\n"); } internal_buses_supported = BUS_LPC | BUS_FWH;

1 0

test report for GD25Q16(B)
by YounJaeRho 15 Jul '14

15 Jul '14

programmar : raspberry pichip : GD25Q16BSIG operation : read(success), write(fail) I attached log file, thx for developing good program :)

2 3

New motherboard
by Dima Veselov 14 Jul '14

14 Jul '14

Hello, I have an Asus Barebone system, called Asus Vintage 2 PH1. SVN-trunk flashrom version won't flash it initially, but I found a way to do it. Few words about it: Barebone has its own story, own BIOSes to download, but it looks in strange way: some soft think its Asus P5KPML motherboard, BIOS says its P5LD2-VM, flashrom show P5LD2-MQ. Motherboard tag says "DP_MB/V2-PH1<GA>" Anyway, it has same problem as P5LD2, but a bit different hardware. So I added motherboard to a copy of trunk version and flashed it successfully. I attach diff file and put log files to download: http://kab00m.ru/temp/flashrom.txz Hope this will help. -- Sincerelly yours

2 3

[commit] r1828 - trunk
by repository service 14 Jul '14

14 Jul '14

Author: stefanct Date: Mon Jul 14 20:04:15 2014 New Revision: 1828 URL: http://flashrom.org/trac/flashrom/changeset/1828 Log: Add Board Enable for ASUS Vintage 2 PH1 (P5LD2-MQ). ASUS Vintage 2 PH1 barebone systems have a mainboard from the P5LD2 series, namely the P5LD2-MQ (although it is labeled V2-PH1). Pin 16 GPIO needs to be raised to enable write/erase like on other boards of the series. NB: it uses a ICH7DH southbridge and hence requires different PCI IDs. Signed-off-by: Dima Veselov <kab00m(a)lich.phys.spbu.ru> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Jul 14 01:53:40 2014 (r1827) +++ trunk/board_enable.c Mon Jul 14 20:04:15 2014 (r1828) @@ -1663,6 +1663,7 @@ * - abit IP35: Intel P35 + ICH9R * - abit IP35 Pro: Intel P35 + ICH9R * - ASUS P5LD2 + * - ASUS P5LD2-MQ * - ASUS P5LD2-VM * - ASUS P5LD2-VM DH */ @@ -2374,6 +2375,7 @@ {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise}, {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jul 14 01:53:40 2014 (r1827) +++ trunk/print.c Mon Jul 14 20:04:15 2014 (r1828) @@ -749,6 +749,7 @@ B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", NT, NULL, "Untested board enable."), + B("ASUS", "P5LD2-MQ", OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&o…", "Found in ASUS Vintage-PH2 barebones."), B("ASUS", "P5LD2-VM", NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."), B("ASUS", "P5LD2-VM DH", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL), B("ASUS", "P5LP-LE (Lithium-UL8E)", OK, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP."),

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Re: [flashrom] [PATCH] Improve messages on failed erases with default verbosity.
by Stefan Tauner 14 Jul '14

14 Jul '14

On Sun, 1 Jun 2014 03:38:29 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > From: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > Without this... > Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09 > ERASE FAILED! > Reading current flash chip contents... done. > <loooooong break while the next eraser and writing is tried> > Erase/write done. > Verifying flash... VERIFIED. > > Even if there is not a long temporal pause, it is very confusing for > the user to first see a failed erase, followed by a read, a done > message and eventually the verification message. > This patch inserts "Looking for another erase function." where there is > just a silent break above. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1827. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1827 - trunk
by repository service 14 Jul '14

14 Jul '14

Author: stefanct Date: Mon Jul 14 01:53:40 2014 New Revision: 1827 URL: http://flashrom.org/trac/flashrom/changeset/1827 Log: Improve messages on failed erases with default verbosity. Without this... Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09 ERASE FAILED! Reading current flash chip contents... done. <loooooong break while the next eraser and writing is tried> Erase/write done. Verifying flash... VERIFIED. Even if there is not a long temporal pause, it is very confusing for the user to first see a failed erase, followed by a read, a done message and eventually the verification message. This patch inserts "Looking for another erase function." where there is just a silent pause above. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 13 19:06:11 2014 (r1826) +++ trunk/flashrom.c Mon Jul 14 01:53:40 2014 (r1827) @@ -1463,9 +1463,9 @@ for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { if (k != 0) - msg_cdbg("Looking for another erase function.\n"); + msg_cinfo("Looking for another erase function.\n"); if (!usable_erasefunctions) { - msg_cdbg("No usable erase functions left.\n"); + msg_cinfo("No usable erase functions left.\n"); break; } msg_cdbg("Trying erase function %i... ", k);

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