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Missing chip definition for ZD25WQ80Y
by a.b.c＠ntlworld.com 12 Aug '23

12 Aug '23

ZD25WQ80Y Hope this info is of use

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Re: HP 11 G5 EE - WP disable failure
by Peter Marheine 10 Aug '23

10 Aug '23

You don't need to cut any tracks, and that might not even do what you want because there probably isn't a pull-up or -down on the WP signal so it would be left floating in an indeterminate state. It looks like your Meep uses battery presence for WP, so disconnecting the battery should be all you need to do in order to temporarily disable hardware write protection. On Thu, Aug 10, 2023 at 11:16 AM E239 76BF <e23976bf(a)gmail.com> wrote: > I think the apparent thin link might be on the other side of the board. I > need to extract the board to confirm this, cut it and try again. > I'm a hardware tech with 40 yrs experience, so no issue. Just > unfamiliar with ChromeOS. > Need to remove the board. But it's the only IT platform I have. > Learned ChromeOS, Time to go back to linux. > > > On Thu, 10 Aug 2023 at 13:01, Peter Marheine <pmarheine(a)chromium.org> > wrote: > >> > Note: hardware status register protection is enabled. The chip's WP# >> pin must be set to an inactive voltage level to be able to change the WP >> settings. >> >> You need to disable hardware write protect: >> https://chromium.googlesource.com/chromiumos/docs/+/master/write_protection… >> >> On Tue, Aug 8, 2023 at 1:02 PM E239 76BF <e23976bf(a)gmail.com> wrote: >> >>> Glenn in Wellington, New Zealand >>> I know little about ChromeOS, but am moderately comfortable with Linux. >>> Got this machine two months ago (because I lost all my gear in a big >>> fire 11 weeks ago) and having learned ChromeOS, I'm now ready to return to >>> the comfort of a linux environment. >>> >>> Verbose output : >>> >>> # flashrom --wp-disable -V >>> flashrom 68022911 on Linux 4.14.313-20323-gc32c2d54e434 (x86_64) >>> flashrom is free software, get the source code at https://flashrom.org >>> >>> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). >>> flashrom was built with LLVM Clang 16.0.0 >>> (/var/tmp/portage/sys-devel/llvm-16.0_pre484197_p20230405-r7/work/llvm-16.0_pre484197_p20230405/clang >>> 2916b99182752b1aece8cc4479d8d6a20b5e02da), little endian >>> Command line (2 args): flashrom --wp-disable -V >>> Using default programmer "internal" with arguments "". >>> Acquiring lock (timeout=180 sec)... >>> Opened file lock "/run/lock/firmware_utility_lock" >>> Lock acquired. >>> Initializing internal programmer >>> /sys/class/mtd/mtd0 does not exist >>> Found candidate at: 00000500-00000528 >>> Found coreboot table at 0x00000500. >>> Found candidate at: 00000000-000005cc >>> Found coreboot table at 0x00000000. >>> coreboot table found at 0x79b2a000. >>> coreboot header(24) checksum: a42a table(1460) checksum: c446 entries: 45 >>> Vendor ID: Google, part ID: Meep >>> Using Internal DMI decoder. >>> DMI string chassis-type: "Laptop" >>> Laptop detected via DMI. >>> DMI string system-manufacturer: "HP" >>> DMI string system-product-name: "Meep" >>> DMI string system-version: "rev7" >>> DMI string baseboard-manufacturer: "HP" >>> DMI string baseboard-product-name: "Meep" >>> DMI string baseboard-version: "rev7" >>> Found chipset "Intel Gemini Lake" with PCI ID 8086:3197. >>> This chipset is marked as untested. If you are using an up-to-date >>> version >>> of flashrom *and* were (not) able to successfully update your firmware >>> with it, >>> then please email a report to flashrom(a)flashrom.org including a verbose >>> (-V) log. >>> Thank you! >>> Enabling flash write... BIOS_SPI_BC = 0x9: BIOS Interface Lock-Down: >>> disabled, Boot BIOS Straps: 0x0 (SPI) >>> Top Swap: not enabled >>> SPI Read Configuration: prefetching enabled, caching enabled, >>> BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled >>> SPIBAR = 0x00007bd11ce10000 (phys = 0xc1121000) >>> 0x04: 0x6000 (HSFS) >>> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, >>> FLOCKDN=0 >>> Programming OPCODES... done >>> 0x06: 0x020c (HSFC) >>> HSFC: FGO=0, FCYCLE=2, FDBC=2, SME=0 >>> 0x0c: 0x00000000 (DLOCK) >>> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, >>> PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, >>> PR4_LOCKDN=0, >>> SSEQ_LOCKDN=0 >>> 0x50: 0x000042c3 (FRAP) >>> BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc3 >>> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) >>> is read-only. >>> 0x58: 0x0f7e0001 FREG1: BIOS region (0x00001000-0x00f7efff) is >>> read-write. >>> 0x68: 0x0fff0f7f FREG5: Device Expansion region (0x00f7f000-0x00ffffff) >>> is locked. >>> 0x7C: 0x7fff7fff FREG10: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0x80: 0x7fff7fff FREG11: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE0: 0x7fff7fff FREG12: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE4: 0x7fff7fff FREG13: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE8: 0x7fff7fff FREG14: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xEC: 0x7fff7fff FREG15: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> Not all flash regions are freely accessible by flashrom. This is most >>> likely >>> due to an active ME. Please see https://flashrom.org/ME for details. >>> At least some flash regions are read protected. You have to use a flash >>> layout and include only accessible regions. For write operations, you'll >>> additionally need the --noverify-all switch. See manpage for more >>> details. >>> 0xa0: 0xc0 (SSFS) >>> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 >>> 0xa1: 0xfe0000 (SSFC) >>> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 >>> 0xa4: 0x5006 (PREOP) >>> 0xa6: 0x463b (OPTYPE) >>> 0xa8: 0x05200302 (OPMENU) >>> 0xac: 0xc79f0190 (OPMENU+4) >>> 0xc4: 0xb1d82024 (LVSCC) >>> LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 >>> 0xc8: 0x00002000 (UVSCC) >>> UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 >>> Enabling hardware sequencing by default for >>> Apollo/Gemini/Jasper/Elkhart/Meteor Lake. >>> OK. >>> The following protocols are supported: Programmer-specific. >>> Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing >>> reports 1 attached SPI flash chip with a density of 16384 kB. >>> HSFC: FGO=1, FCYCLE=2, FDBC=2, SME=0 >>> Chip identified: GD25LQ128C/GD25LQ128D/GD25LQ128E >>> Added layout entry 00000000 - 00ffffff named complete flash >>> Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 >>> kB, Programmer-specific) on internal. >>> Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 >>> kB, Programmer-specific). >>> This chip may contain one-time programmable memory. flashrom cannot read >>> and may never be able to write it, hence it may not be able to completely >>> clone the contents of this chip (see man page for details). >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Writing status register >>> HSFC: FGO=1, FCYCLE=3, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> write_wp_bits: wp_verify failed: reg:1 actual:0xb4 expected:0x34 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Failed to apply new WP settings: unexpected WP configuration read back >>> from chip >>> Note: hardware status register protection is enabled. The chip's WP# pin >>> must be set to an inactive voltage level to be able to change the WP >>> settings. >>> Restoring MMIO space at 0x7bd11ce10084 >>> Restoring MMIO space at 0x7bd11ce100ac >>> Restoring MMIO space at 0x7bd11ce100a8 >>> Restoring MMIO space at 0x7bd11ce100a6 >>> Restoring MMIO space at 0x7bd11ce100a4 >>> _______________________________________________ >>> flashrom mailing list -- flashrom(a)flashrom.org >>> To unsubscribe send an email to flashrom-leave(a)flashrom.org >>> >>

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HP 11 G5 EE - WP disable failure
by E239 76BF 10 Aug '23

10 Aug '23

Glenn in Wellington, New Zealand I know little about ChromeOS, but am moderately comfortable with Linux. Got this machine two months ago (because I lost all my gear in a big fire 11 weeks ago) and having learned ChromeOS, I'm now ready to return to the comfort of a linux environment. Verbose output : # flashrom --wp-disable -V flashrom 68022911 on Linux 4.14.313-20323-gc32c2d54e434 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). flashrom was built with LLVM Clang 16.0.0 (/var/tmp/portage/sys-devel/llvm-16.0_pre484197_p20230405-r7/work/llvm-16.0_pre484197_p20230405/clang 2916b99182752b1aece8cc4479d8d6a20b5e02da), little endian Command line (2 args): flashrom --wp-disable -V Using default programmer "internal" with arguments "". Acquiring lock (timeout=180 sec)... Opened file lock "/run/lock/firmware_utility_lock" Lock acquired. Initializing internal programmer /sys/class/mtd/mtd0 does not exist Found candidate at: 00000500-00000528 Found coreboot table at 0x00000500. Found candidate at: 00000000-000005cc Found coreboot table at 0x00000000. coreboot table found at 0x79b2a000. coreboot header(24) checksum: a42a table(1460) checksum: c446 entries: 45 Vendor ID: Google, part ID: Meep Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "HP" DMI string system-product-name: "Meep" DMI string system-version: "rev7" DMI string baseboard-manufacturer: "HP" DMI string baseboard-product-name: "Meep" DMI string baseboard-version: "rev7" Found chipset "Intel Gemini Lake" with PCI ID 8086:3197. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... BIOS_SPI_BC = 0x9: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007bd11ce10000 (phys = 0xc1121000) 0x04: 0x6000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x020c (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=2, SME=0 0x0c: 0x00000000 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0, SSEQ_LOCKDN=0 0x50: 0x000042c3 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc3 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0f7e0001 FREG1: BIOS region (0x00001000-0x00f7efff) is read-write. 0x68: 0x0fff0f7f FREG5: Device Expansion region (0x00f7f000-0x00ffffff) is locked. 0x7C: 0x7fff7fff FREG10: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0x80: 0x7fff7fff FREG11: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE0: 0x7fff7fff FREG12: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE4: 0x7fff7fff FREG13: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE8: 0x7fff7fff FREG14: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xEC: 0x7fff7fff FREG15: unknown region (0x07fff000-0x07ffffff) has unknown permissions. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0xa0: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x5006 (PREOP) 0xa6: 0x463b (OPTYPE) 0xa8: 0x05200302 (OPMENU) 0xac: 0xc79f0190 (OPMENU+4) 0xc4: 0xb1d82024 (LVSCC) LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake. OK. The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. HSFC: FGO=1, FCYCLE=2, FDBC=2, SME=0 Chip identified: GD25LQ128C/GD25LQ128D/GD25LQ128E Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 kB, Programmer-specific) on internal. Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Writing status register HSFC: FGO=1, FCYCLE=3, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify failed: reg:1 actual:0xb4 expected:0x34 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Failed to apply new WP settings: unexpected WP configuration read back from chip Note: hardware status register protection is enabled. The chip's WP# pin must be set to an inactive voltage level to be able to change the WP settings. Restoring MMIO space at 0x7bd11ce10084 Restoring MMIO space at 0x7bd11ce100ac Restoring MMIO space at 0x7bd11ce100a8 Restoring MMIO space at 0x7bd11ce100a6 Restoring MMIO space at 0x7bd11ce100a4

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flashrom meeting notes 03.08.2023
by Anastasia Klimchuk 03 Aug '23

03 Aug '23

# 3th August 2023, 6.00-7.00am UTC+0 Attendees: Stefan, Carl-Daniel, Anastasia ## Decision summary * 3 developers get submit rights: Joursoir (Alexander Goncharov), Peter Marheine, Nikolai Artemiev * document the process of getting commit rights and send for review (todo aklm) ## Agenda * [aklm] I would like to nominate 3 developers to get submit rights: Joursoir (Alexander Goncharov) [authored](https://review.coreboot.org/q/owner:chat@joursoir.net), [reviewed](https://review.coreboot.org/q/reviewer:chat@joursoir.net), Peter Marheine [authored](https://review.coreboot.org/q/owner:pmarheine@chromium.org), [reviewed](https://review.coreboot.org/q/reviewer:pmarheine@chromium.org), Nikolai Artemiev [authored](https://review.coreboot.org/q/owner:nartemiev@google.com), [reviewed](https://review.coreboot.org/q/reviewer:nartemiev@google.com). They all made valuable contributions to flashrom, are on the project for a while already: 1-2-3.... years, currently active, are respected members of the dev community. To be more specific, and formal: we now have the duties documented [https://www.flashrom.org/about_flashrom/team.html](https://www.flashrom.org… and all of them agreed to do the duties. * all approved! * [aklm] ongoing item: "We need to figure out criteria to give people submit rights." Is it done with the Team page describing duties? A missing piece is to describe the process (which currently is: someone nominates you and adds an item to the meeting agenda in advance. whoever comes to the meeting, discusses and decides). So maybe document the process and ongoing item solved? * yes, document the process, send for review (todo aklm) * we can remove ongoing item * the process can be improved later, if any issues are observed. As of today, the process has been working for >1yr, everything seems to go well. * [Carl-Daniel] subject line for meeting notes email says "dev meeting", but there are various questions discussed, not only dev, but also organisational and any misc stuff. * [aklm] we can drop "dev"? that would be "flashrom meeting notes DD.MM.YYYY" * sounds good, drop "dev" from subject line -- Anastasia.

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MCIX MX25L6406E M2I-12G (Acer DAFT3L-Kelia MB 12088-1M)
by Shizeeg Unadequatov 31 Jul '23

31 Jul '23

Board: Acer DAFT3L-Kelia MB 12088-1M Programmer: CH431 (CH341B) OS: NixOS 23.05 (Linux-6.1.39 x86_64) flashrom: v1.3.0 ```sh # command-line: % flashrom -p ch341a_spi -c "MX25L6406E/MX25L6408E" -w 12088-1M\ 48.3KN02.01M\ DAFT3L-KELIA\ MB.BIN ```

1 0

(no subject)
by vanniealdamar 31 Jul '23

31 Jul '23

Unknown flash Chip detected ( eon en25qx128a ) on ch341a bios programmer...any update for this thanks Sent from vivo smartphone

1 0

New flashrom website
by Anastasia Klimchuk 28 Jul '23

28 Jul '23

Good day everyone, Good news for the good day: we are launching the new flashrom website! doc.flashrom.org At the moment it is available by the address doc.flashrom.org, but in the very near future (think of a few weeks) it will move to primary flashrom.org. The reason for this few weeks' interval is to check everything looks good and fix small things. After the new website moves to the primary address, the old wiki website moves to wiki.flashrom.org and will be locked for editing. Wiki will be available as view-only until we migrate all the content. New website is generated by sphinx from sources that are in the tree under doc/ directory. To add or update documentation, you need to send a patch as per usual dev process. Separate wiki account is no longer needed to update the documentation. Everything is set up so that after the patch is merged into documentation, it will appear on the website shortly after. There is a doc on how to add docs with more details: https://doc.flashrom.org/how_to_add_docs.html As you can see, the new website doesn't have all of the pages migrated from the old wiki yet. This is by the plan, we will migrate the pages gradually, hopefully within this year. Everyone is very welcome to join migrating the wiki pages to doc/ files! Especially if there is a page in wiki that you own and can verify the correctness of content. Thanks a lot to everyone who was working on the new website! The idea has been around for a while, and it is so cool to see it happening! -- Anastasia.

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flashrom dev meeting notes 20.07.2023
by Anastasia Klimchuk 28 Jul '23

28 Jul '23

# 20th July 2023, 6.00-7.00am UTC+0 Attendees: Stefan, Edward, Anastasia ## Decision summary * flashrom.org is new, wiki.flashrom.org is old (will be a dedicated post on the ML) ## Agenda * New website: let's do it right now! * Done: flashrom.org is new, wiki.flashrom.org is old, and old one is locked for editing (no edit button anymore) * one thing left: put a red banner on old wiki which says it is retired and locked for editing * aklm to post news on mailing list * Code of conduct patch [https://review.coreboot.org/c/flashrom/+/76455](https://review.coreboot.org… * maybe coreboot can help in the beginning? but longer term we need our own. -- Anastasia.

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new unsupported motherboard
by shandower＠gmx.de 23 Jul '23

23 Jul '23

flashrom v1.3.0 on FreeBSD 13.2-RELEASE-p1 (amd64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 4, resolution: 70ns). flashrom was built with LLVM Clang 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c), little endian Command line (3 args): flashrom --programmer internal -VV Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Wortmann_AG" DMI string system-product-name: "1009663;2120131" DMI string system-version: "AX370M;2120131" DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "AX370M-DS3H-CF" DMI string baseboard-version: "Default string" Found ITE Super I/O, ID 0x8686 on port 0x2e Found chipset "AMD FP4" with PCI ID 1022:790e. Enabling flash write... SPI base address is at 0xfec10000 Trying to determine the generation of the SPI interface... FCH device found but SMBus revision 0x59 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.ROM strap override is not active PROBLEMS, continuing anyway No IT87* serial flash segment enabled. The following protocols are supported: LPC, FWH. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel AT82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xf8, id2 0x67, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10ms/40us. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xf8, id2 0x67, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xf8, id2 0x67, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xf8, id2 0x67, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. lspci output below: 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Flags: fast devsel 00: 22 10 50 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 50 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] Flags: bus master, fast devsel, latency 0, IRQ 255 Bus: primary=00, secondary=01, subordinate=07, sec-latency=0 I/O behind bridge: 0000f000-0000ffff [size=4K] [32-bit] Memory behind bridge: fe600000-fe7fffff [size=2M] [32-bit] Prefetchable memory behind bridge: 0000001ffff00000-0000001fffffffff [size=1M] [64-bit] Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services Capabilities: [370] L1 PM Substates Capabilities: [3c4] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?> 00: 22 10 53 14 07 00 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 07 00 f1 f1 00 20 20: 60 fe 70 fe f1 ff f1 ff 1f 00 00 00 1f 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 10 00 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] Flags: bus master, fast devsel, latency 0, IRQ 255 Bus: primary=00, secondary=08, subordinate=08, sec-latency=0 I/O behind bridge: 0000e000-0000efff [size=4K] [32-bit] Memory behind bridge: fe900000-fe9fffff [size=1M] [32-bit] Prefetchable memory behind bridge: 00000000e0000000-00000000efffffff [size=256M] [64-bit] Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services Capabilities: [370] L1 PM Substates Capabilities: [3c4] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?> 00: 22 10 53 14 07 00 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 08 08 00 e1 e1 00 20 20: 90 fe 90 fe 01 e0 f1 ef 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 18 00 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] Flags: bus master, fast devsel, latency 0, IRQ 255 Bus: primary=00, secondary=09, subordinate=09, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: fe300000-fe5fffff [size=3M] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot-), MSI 00 Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services 00: 22 10 54 14 07 00 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 09 09 00 f1 01 00 00 20: 30 fe 50 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 ff 01 10 00 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] Flags: bus master, fast devsel, latency 0, IRQ 255 Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: fe800000-fe8fffff [size=1M] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot-), MSI 00 Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [c0] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services 00: 22 10 54 14 07 00 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 0a 0a 00 f1 01 00 00 20: 80 fe 80 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 ff 01 10 00 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 59) Subsystem: Gigabyte Technology Co., Ltd Device [1458:5001] Flags: 66MHz, medium devsel 00: 22 10 0b 79 03 04 20 02 59 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 01 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: Gigabyte Technology Co., Ltd Device [1458:5001] Flags: bus master, 66MHz, medium devsel, latency 0 00: 22 10 0e 79 0f 00 20 02 51 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 01 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] Flags: fast devsel 00: 22 10 60 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] Flags: fast devsel 00: 22 10 61 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] Flags: fast devsel 00: 22 10 62 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] Flags: fast devsel 00: 22 10 63 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] Flags: fast devsel 00: 22 10 64 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] Flags: fast devsel 00: 22 10 65 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] Flags: fast devsel 00: 22 10 66 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] Flags: fast devsel 00: 22 10 67 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset USB 3.1 xHCI Controller [1022:43b9] (rev 02) (prog-if 30 [XHCI]) Subsystem: ASMedia Technology Inc. Device [1b21:1142] Flags: bus master, fast devsel, latency 0, IRQ 32 Memory at fe7a0000 (64-bit, non-prefetchable) Capabilities: [50] MSI: Enable+ Count=1/8 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Legacy Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [300] Latency Tolerance Reporting Capabilities: [400] L1 PM Substates 00: 22 10 b9 43 06 04 10 00 02 30 03 0c 10 00 80 00 10: 04 00 7a fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 21 1b 42 11 30: 00 00 00 00 50 00 00 00 00 00 00 00 20 01 00 00 01:00.1 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset SATA Controller [1022:43b5] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. Device [1b21:1062] Flags: bus master, fast devsel, latency 0, IRQ 33 Memory at fe780000 (32-bit, non-prefetchable) Expansion ROM at fe700000 [disabled] Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Legacy Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting 00: 22 10 b5 43 06 04 10 00 02 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 78 fe 00 00 00 00 21 1b 62 10 30: 00 00 70 fe 50 00 00 00 00 00 00 00 21 02 00 00 01:00.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset PCIe Upstream Port [1022:43b0] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:0201] Flags: bus master, fast devsel, latency 0, IRQ 34 Bus: primary=01, secondary=02, subordinate=07, sec-latency=0 I/O behind bridge: 0000f000-0000ffff [size=4K] [32-bit] Memory behind bridge: fe600000-fe6fffff [size=1M] [32-bit] Prefetchable memory behind bridge: 0000001ffff00000-0000001fffffffff [size=1M] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Upstream Port, MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:0201] Capabilities: [100] Advanced Error Reporting 00: 22 10 b0 43 07 00 10 00 02 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 01 02 07 00 f1 f1 00 00 20: 60 fe 60 fe f1 ff f1 ff 1f 00 00 00 1f 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 22 03 10 00 02:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:3306] Flags: bus master, fast devsel, latency 0, IRQ 32 Bus: primary=02, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: [disabled] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Downstream Port (Slot+), MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:3306] Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [400] L1 PM Substates 00: 22 10 b4 43 07 00 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 20 01 10 00 02:01.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:3306] Flags: bus master, fast devsel, latency 0, IRQ 33 Bus: primary=02, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-0000ffff [size=4K] [32-bit] Memory behind bridge: fe600000-fe6fffff [size=1M] [32-bit] Prefetchable memory behind bridge: 0000001ffff00000-0000001fffffffff [size=1M] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Downstream Port (Slot+), MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:3306] Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [400] L1 PM Substates 00: 22 10 b4 43 07 00 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 04 04 00 f1 f1 00 00 20: 60 fe 60 fe f1 ff f1 ff 1f 00 00 00 1f 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 21 01 10 00 02:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:3306] Flags: bus master, fast devsel, latency 0, IRQ 34 Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: [disabled] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Downstream Port (Slot+), MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:3306] Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [400] L1 PM Substates 00: 22 10 b4 43 07 00 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 05 05 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 22 01 10 00 02:03.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:3306] Flags: bus master, fast devsel, latency 0, IRQ 35 Bus: primary=02, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: [disabled] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Downstream Port (Slot+), MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:3306] Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [400] L1 PM Substates 00: 22 10 b4 43 07 00 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 23 01 10 00 02:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Subsystem: ASMedia Technology Inc. Device [1b21:3306] Flags: bus master, fast devsel, latency 0, IRQ 32 Bus: primary=02, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: [disabled] [32-bit] Memory behind bridge: [disabled] [32-bit] Prefetchable memory behind bridge: [disabled] [64-bit] Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Power Management version 3 Capabilities: [80] Express Downstream Port (Slot+), MSI 00 Capabilities: [c0] Subsystem: ASMedia Technology Inc. Device [1b21:3306] Capabilities: [100] Advanced Error Reporting Capabilities: [200] Secondary PCI Express Capabilities: [400] L1 PM Substates 00: 22 10 b4 43 07 00 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff 00 00 00 50 00 00 00 00 00 00 00 20 01 10 00 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 0c) Subsystem: Gigabyte Technology Co., Ltd Onboard Ethernet [1458:e000] pcilib: 0000:04:00.0 64-bit device address ignored. Flags: bus master, fast devsel, latency 0, IRQ 33 I/O ports at f000 Memory at fe600000 (64-bit, non-prefetchable) Memory at <unassigned> (64-bit, prefetchable) I/O ports at 0000 Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [70] Express Endpoint, MSI 01 Capabilities: [b0] MSI-X: Enable+ Count=4 Masked- Capabilities: [d0] Vital Product Data Capabilities: [100] Advanced Error Reporting Capabilities: [140] Virtual Channel Capabilities: [160] Device Serial Number 01-00-00-00-68-4c-e0-00 Capabilities: [170] Latency Tolerance Reporting 00: ec 10 68 81 07 04 10 00 0c 00 00 02 10 00 00 00 10: 01 f0 00 00 00 00 00 00 04 00 60 fe 00 00 00 00 20: 0c 00 f0 ff 1f 00 00 00 00 00 00 00 58 14 00 e0 30: 00 00 00 00 40 00 00 00 00 00 00 00 21 01 00 00 08:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Pitcairn PRO [Radeon HD 7850 / R7 265 / R9 270 1024SP] [1002:6819] (prog-if 00 [VGA controller]) Subsystem: PC Partner Limited / Sapphire Technology Radeon HD 7850 2GB GDDR5 DVI-I/DVI-D/HDMI/DP [174b:e221] Flags: bus master, fast devsel, latency 0, IRQ 54 Memory at e0000000 (64-bit, prefetchable) Memory at fe900000 (64-bit, non-prefetchable) I/O ports at e000 Expansion ROM at fe940000 [disabled] Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [58] Express Legacy Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2b0] Address Translation Service (ATS) Capabilities: [2c0] Page Request Interface (PRI) Capabilities: [2d0] Process Address Space ID (PASID) 00: 02 10 19 68 07 04 10 00 00 00 00 03 10 00 80 00 10: 0c 00 00 e0 00 00 00 00 04 00 90 fe 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 4b 17 21 e2 30: 00 00 94 fe 48 00 00 00 00 00 00 00 36 01 00 00 08:00.1 Audio device [0403]: Advanced Micro Devices, Inc. [AMD/ATI] Oland/Hainan/Cape Verde/Pitcairn HDMI Audio [Radeon HD 7000 Series] [1002:aab0] Subsystem: PC Partner Limited / Sapphire Technology Device [174b:aab0] Flags: bus master, fast devsel, latency 0, IRQ 55 Memory at fe960000 (64-bit, non-prefetchable) Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [58] Express Legacy Endpoint, MSI 00 Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting 00: 02 10 b0 aa 07 04 10 00 00 00 03 04 10 00 80 00 10: 04 00 96 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 b0 aa 30: 00 00 00 00 48 00 00 00 00 00 00 00 37 02 00 00 09:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Flags: bus master, fast devsel, latency 0, IRQ 255 Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services 00: 22 10 5a 14 07 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 5a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 09:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor (PSP) 3.0 Device [1022:1456] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor (PSP) 3.0 Device [1022:1456] Flags: bus master, fast devsel, latency 0, IRQ 36 Memory at fe400000 (32-bit, non-prefetchable) Memory at fe500000 (32-bit, non-prefetchable) Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [a0] MSI: Enable- Count=1/2 Maskable- 64bit+ Capabilities: [c0] MSI-X: Enable- Count=2 Masked- Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [2a0] Access Control Services 00: 22 10 56 14 07 00 10 00 00 00 80 10 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 40 fe 00 00 00 00 20: 00 00 00 00 00 00 50 fe 00 00 00 00 22 10 56 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 24 02 00 00 09:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) USB 3.0 Host Controller [1022:145c] (prog-if 30 [XHCI]) Subsystem: Gigabyte Technology Co., Ltd Device [1458:5007] Flags: bus master, fast devsel, latency 0, IRQ 37 Memory at fe300000 (64-bit, non-prefetchable) Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/8 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [2a0] Access Control Services 00: 22 10 5c 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 30 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 50 30: 00 00 00 00 48 00 00 00 00 00 00 00 25 03 00 00 0a:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Flags: bus master, fast devsel, latency 0, IRQ 255 Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] Secondary PCI Express Capabilities: [2a0] Access Control Services 00: 22 10 55 14 07 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 55 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 0a:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) Subsystem: Gigabyte Technology Co., Ltd Device [1458:b002] Flags: bus master, fast devsel, latency 0, IRQ 42 Memory at fe808000 (32-bit, non-prefetchable) Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=16/16 Maskable- 64bit+ Capabilities: [d0] SATA HBA v1.0 Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [2a0] Access Control Services 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 80 80 fe 00 00 00 00 58 14 02 b0 30: 00 00 00 00 48 00 00 00 00 00 00 00 2a 02 00 00 0a:00.3 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) HD Audio Controller [1022:1457] Subsystem: Gigabyte Technology Co., Ltd Device [1458:a182] Flags: bus master, fast devsel, latency 0, IRQ 43 Memory at fe800000 (32-bit, non-prefetchable) Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [64] Express Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [2a0] Access Control Services 00: 22 10 57 14 07 04 10 00 00 00 03 04 10 00 80 00 10: 00 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 82 a1 30: 00 00 00 00 48 00 00 00 00 00 00 00 2b 03 00 00

1 0

UC25HQ64
by Toy Lim 22 Jul '23

22 Jul '23

Attached is the output for the Flash IC with label: UC25HQ64 flashrom -VV -p ch341a_spi >> chip_id.txt

1 0

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