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[PATCH] Add Altera USB Blaster SPI programmer
by James Laird 29 Oct '12

29 Oct '12

Adds support for the Altera USB Blaster programming dongle in SPI mode. It has only been tested against a cheap clone ($10, unclear origin), and so is marked as not tested. It should also support several variants which are present on Altera dev boards (PID 6002,6003...), although I believe these are hardwired to their targets. Signed-off-by: James Laird <jhl(a)mafipulation.org> Index: Makefile =================================================================== --- Makefile (revision 1548) +++ Makefile (working copy) @@ -84,7 +84,7 @@ else override CONFIG_SERPROG = no endif -# Dediprog and FT2232 are not supported under DOS (missing USB support). +# Dediprog, FT2232 and USB Blaster are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -95,7 +95,12 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no endif +endif # FIXME: Should we check for Cygwin/MSVC as well? ifeq ($(TARGET_OS), MinGW) @@ -196,7 +201,7 @@ else override CONFIG_SERPROG = no endif -# Dediprog and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, FT2232 and USB Blaster are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -207,7 +212,12 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no endif +endif ifneq ($(TARGET_OS), Linux) ifeq ($(CONFIG_LINUX_SPI), yes) @@ -344,6 +354,9 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +# Always enable USB Blaster SPI for now. +CONFIG_USBBLASTER_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -430,14 +443,31 @@ NEED_PCI := yes endif +# This is a totally ugly hack. +WANT_LIBFTDI := no +HAVE_LIBFTDI := $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && echo "yes") ifeq ($(CONFIG_FT2232_SPI), yes) -FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") -# This is a totally ugly hack. -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'CONFIG_FT2232_SPI=1'") -FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") -PROGRAMMER_OBJS += ft2232_spi.o + WANT_LIBFTDI := yes + ifeq ($(HAVE_LIBFTDI), yes) + FEATURE_CFLAGS += -DCONFIG_FT2232_SPI=1 + PROGRAMMER_OBJS += ft2232_spi.o + endif endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) + WANT_LIBFTDI := yes + ifeq ($(HAVE_LIBFTDI), yes) + FEATURE_CFLAGS += -DCONFIG_USBBLASTER_SPI=1 + PROGRAMMER_OBJS += usbblaster_spi.o + endif +endif +ifeq ($(WANT_LIBFTDI), yes) + ifeq ($(WANT_LIBFTDI), yes) + FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") + FEATURE_LIBS += $(FTDILIBS) + endif +endif + ifeq ($(CONFIG_DUMMY), yes) FEATURE_CFLAGS += -D'CONFIG_DUMMY=1' PROGRAMMER_OBJS += dummyflasher.o @@ -700,7 +730,7 @@ features: compiler @echo "FEATURES := yes" > .features.tmp -ifeq ($(CONFIG_FT2232_SPI), yes) +ifeq ($(WANT_LIBFTDI), yes) @printf "Checking for FTDI support... " @echo "$$FTDI_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ Index: README =================================================================== --- README (revision 1548) +++ README (working copy) @@ -45,8 +45,8 @@ To build flashrom you need to install the following software: * pciutils+libpci (if you want support for mainboard or PCI device flashing) - * libusb (if you want FT2232 or Dediprog support) - * libftdi (if you want FT2232 support) + * libusb (if you want FT2232, Dediprog or USB Blaster support) + * libftdi (if you want FT2232 or USB Blaster support) Linux et al: Index: usbblaster_spi.c =================================================================== --- usbblaster_spi.c (revision 0) +++ usbblaster_spi.c (working copy) @@ -0,0 +1,258 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2012 James Laird <jhl(a)mafipulation.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Device should be connected as per "active serial" mode: + * + * +---------+------+-----------+ + * | SPI | Pin | Altera | + * +---------+------+-----------+ + * | SCLK | 1 | DCLK | + * | GND | 2,10 | GND | + * | VCC | 4 | VCC(TRGT) | + * | MISO | 7 | ASDO | + * | /CS | 8 | nCS | + * | MOSI | 9 | ASDI | + * +---------+------+-----------+ + */ + +#if CONFIG_USBBLASTER_SPI == 1 + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" +#include "programmer.h" +#include "spi.h" +#include <ftdi.h> + +/* Please keep sorted by vendor ID, then device ID. */ + +#define ALTERA_VID 0x09fb +#define ALTERA_USBBLASTER_PID 0x6001 + +const struct usbdev_status devs_usbblasterspi[] = { + {ALTERA_VID, ALTERA_USBBLASTER_PID, NT, "Altera", "USB Blaster"}, + {}, +}; + +static const struct spi_programmer spi_programmer_usbblaster; + +static struct ftdi_context ftdic; + +// command bytes +#define BIT_BYTE (1<<7) // byte mode (rather than bitbang) +#define BIT_READ (1<<6) // read request + +#define BIT_LED (1<<5) +#define BIT_CS (1<<3) +#define BIT_CLK (1<<0) +#define BIT_TMS (1<<1) + +#define BITS_OTHER 0 + +// The programmer shifts bits in the wrong order for SPI. +static unsigned char reverse[] = { + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + + +/* Returns 0 upon success, a negative number upon errors. */ +int usbblaster_spi_init(void) +{ + if (ftdi_init(&ftdic) < 0) + return -1; + + if (ftdi_usb_open(&ftdic, ALTERA_VID, ALTERA_USBBLASTER_PID) < 0) { + msg_perr("Failed to open USB Blaster: %s\n", ftdic.error_str); + return -1; + } + + if (ftdi_usb_reset(&ftdic) < 0) { + msg_perr("Blaster reset failed\n"); + return -1; + } + + if (ftdi_set_latency_timer(&ftdic, 2) < 0) { + msg_perr("Blaster set latency timer failed\n"); + return -1; + } + + if (ftdi_write_data_set_chunksize(&ftdic, 4096) < 0 || + ftdi_read_data_set_chunksize(&ftdic, 64) < 0) { + msg_perr("Blaster set chunk size failed\n"); + return -1; + } + unsigned char buf[65]; + memset(buf, 0, sizeof(buf)); + buf[sizeof(buf)-1] = BIT_LED | BITS_OTHER | BIT_CS; + if (ftdi_write_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("Blaster reset write failed\n"); + return -1; + } + if (ftdi_read_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("Blaster reset read failed\n"); + return -1; + } + + register_spi_programmer(&spi_programmer_usbblaster); + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int usbblaster_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned char cmd; + unsigned char buf[64]; + unsigned char tms_state = 0; + int i; + // assert /CS + cmd = BIT_LED | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + + while (writecnt) { + unsigned int n_write = writecnt; + if (n_write > 63) + n_write = 63; + + msg_pspew("writing %d-byte packet\n", n_write); + + cmd = BIT_BYTE | (unsigned char)n_write; + buf[0] = cmd; + for (i=0; i<n_write; i++) { + buf[i+1] = reverse[writearr[i]]; + } + if (ftdi_write_data(&ftdic, buf, n_write+1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_LED | BITS_OTHER | (tms_state ^= BIT_TMS); + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + writearr += n_write; + writecnt -= n_write; + } + + unsigned int n_readout = readcnt; + while (readcnt) { + unsigned int n_read = readcnt; + if (n_read > 63) + n_read = 63; + + cmd = BIT_BYTE | BIT_READ | (unsigned char)n_read; + buf[0] = cmd; + if (ftdi_write_data(&ftdic, buf, n_read + 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_LED | BITS_OTHER | (tms_state ^= BIT_TMS); + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + readcnt -= n_read; + msg_pspew("reading %d-byte packet\n", n_read); + }; + + unsigned int n_read = n_readout; + while (n_read) { + int ret = ftdi_read_data(&ftdic, readarr, n_read); + if (ret < 0) { + msg_perr("Blaster read failed\n"); + return -1; + } + for (i=0; i<ret; i++) { + readarr[i] = reverse[readarr[i]]; + } + n_read -= ret; + readarr += ret; + } + + cmd = BIT_LED | BIT_CS | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_CS | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + return 0; +} + + +static const struct spi_programmer spi_programmer_usbblaster = { + .type = SPI_CONTROLLER_USBBLASTER, + .max_data_read = 4096, + .max_data_write = 256, + .command = usbblaster_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +#endif Index: programmer.h =================================================================== --- programmer.h (revision 1548) +++ programmer.h (working copy) @@ -87,6 +87,9 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +#if CONFIG_USBBLASTER_SPI == 1 + PROGRAMMER_USBBLASTER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -433,6 +436,11 @@ void print_supported_usbdevs(const struct usbdev_status *devs); #endif +/* usbblaster_spi.c */ +#if CONFIG_USBBLASTER_SPI == 1 +int usbblaster_spi_init(void); +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -514,6 +522,9 @@ #if CONFIG_SERPROG == 1 SPI_CONTROLLER_SERPROG, #endif +#if CONFIG_USBBLASTER_SPI == 1 + SPI_CONTROLLER_USBBLASTER, +#endif }; #define MAX_DATA_UNSPECIFIED 0 Index: print.c =================================================================== --- print.c (revision 1548) +++ print.c (working copy) @@ -538,6 +538,12 @@ programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif +#if CONFIG_USBBLASTER_SPI == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_USBBLASTER_SPI].name); + /* FIXME */ + msg_ginfo("Altera USB Blaster cable\n"); +#endif } #if CONFIG_INTERNAL == 1 Index: flashrom.c =================================================================== --- flashrom.c (revision 1548) +++ flashrom.c (working copy) @@ -262,6 +262,16 @@ }, #endif +#if CONFIG_USBBLASTER_SPI == 1 + { + .name = "usbblaster_spi", + .init = usbblaster_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ };

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[commit] r1620 - trunk
by repository service 28 Oct '12

28 Oct '12

Author: stefanct Date: Sun Oct 28 02:50:08 2012 New Revision: 1620 URL: http://flashrom.org/trac/flashrom/changeset/1620 Log: Add support for Winbond W39F010/W39L010/W39L020. W39F010 is a 128kB parallel 5V flash chip, 16k bootblocks. W39L010 is a 128kB parallel 3.3V flash chip, 8k bootblocks. W39L020 is a 256kB parallel 3.3V flash chip, 64k/16k bootblocks. The W39F010 code was tested with a satasii programmer. The first write attempt after an erase returned with verify failure, but the second write attempt was succesful: http://paste.flashrom.org/view.php?id=1418 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h trunk/w39.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sat Oct 27 17:36:56 2012 (r1619) +++ trunk/chipdrivers.h Sun Oct 28 02:50:08 2012 (r1620) @@ -143,6 +143,9 @@ int unlock_sst_fwhub(struct flashctx *flash); /* w39.c */ +int printlock_w39f010(struct flashctx * flash); +int printlock_w39l010(struct flashctx * flash); +int printlock_w39l020(struct flashctx * flash); int printlock_w39l040(struct flashctx * flash); int printlock_w39v040a(struct flashctx *flash); int printlock_w39v040b(struct flashctx *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Oct 27 17:36:56 2012 (r1619) +++ trunk/flashchips.c Sun Oct 28 02:50:08 2012 (r1620) @@ -9436,6 +9436,93 @@ { .vendor = "Winbond", + .name = "W39F010", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39F010, + .total_size = 128, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39f010, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, + }, + + { + .vendor = "Winbond", + .name = "W39L010", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L010, + .total_size = 128, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l010, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W39L020", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L020, + .total_size = 256, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l020, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Winbond", .name = "W39L040", .bustype = BUS_PARALLEL, .manufacture_id = WINBOND_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat Oct 27 17:36:56 2012 (r1619) +++ trunk/flashchips.h Sun Oct 28 02:50:08 2012 (r1620) @@ -653,6 +653,7 @@ #define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ #define WINBOND_W29C040 0x46 /* Same as W29C040P */ #define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */ +#define WINBOND_W39F010 0xA1 #define WINBOND_W39L010 0x31 #define WINBOND_W39L020 0xB5 #define WINBOND_W39L040 0xB6 Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Sat Oct 27 17:36:56 2012 (r1619) +++ trunk/w39.c Sun Oct 28 02:50:08 2012 (r1620) @@ -115,6 +115,15 @@ return 0; } +static int printlock_w39_single_bootblock(uint8_t lock, uint16_t kB) +{ + msg_cdbg("Software %d kB bootblock locking is %sactive.\n", kB, (lock & 0x03) ? "" : "not "); + if (lock & 0x03) + return -1; + + return 0; +} + static int printlock_w39_bootblock_64k16k(uint8_t lock) { msg_cdbg("Software 64 kB bootblock locking is %sactive.\n", @@ -160,6 +169,54 @@ return 0; } +int printlock_w39f010(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_single_bootblock(lock, 16); + + lock = w39_idmode_readb(flash, 0x1fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_single_bootblock(lock, 16); + + return ret; +} + +int printlock_w39l010(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_single_bootblock(lock, 8); + + lock = w39_idmode_readb(flash, 0x1fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_single_bootblock(lock, 8); + + return ret; +} + +int printlock_w39l020(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_64k16k(lock); + + lock = w39_idmode_readb(flash, 0x3fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_bootblock_64k16k(lock); + + return ret; +} + int printlock_w39l040(struct flashctx *flash) { uint8_t lock;

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[PATCH] Add chips Winbond W39F010/L010/L020
by Kyösti Mälkki 28 Oct '12

28 Oct '12

W39F010 is 128kB parallel 5V flash chip, 16k bootblocks. W39L010 is 128kB parallel 3V flash chip, 8k bootblocks. W39L020 is 256kB parallel 3V flash chip, 64k/16k bootblocks. Considering the test of W39F010, on the platform [1] the first write attempt after erase returned with verify failure. Second write attempt and following read-verify was succesful. [1] "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 07:04.0). Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> diff --git a/chipdrivers.h b/chipdrivers.h index b43e16e..854269d 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -137,6 +137,9 @@ int printlock_sst_fwhub(struct flashctx *flash); int unlock_sst_fwhub(struct flashctx *flash); /* w39.c */ +int printlock_w39f010(struct flashctx * flash); +int printlock_w39l010(struct flashctx * flash); +int printlock_w39l020(struct flashctx * flash); int printlock_w39l040(struct flashctx * flash); int printlock_w39v040a(struct flashctx *flash); int printlock_w39v040b(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 1afed36..56333eb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9102,6 +9102,93 @@ const struct flashchip flashchips[] = { { .vendor = "Winbond", + .name = "W39F010", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39F010, + .total_size = 128, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39f010, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, + }, + + { + .vendor = "Winbond", + .name = "W39L010", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L010, + .total_size = 128, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l010, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W39L020", + .bustype = BUS_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L020, + .total_size = 256, + .page_size = 4 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l020, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Winbond", .name = "W39L040", .bustype = BUS_PARALLEL, .manufacture_id = WINBOND_ID, diff --git a/flashchips.h b/flashchips.h index e6c74c4..3a8e655 100644 --- a/flashchips.h +++ b/flashchips.h @@ -648,6 +648,7 @@ #define WINBOND_W29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ #define WINBOND_W29C040 0x46 /* Same as W29C040P */ #define WINBOND_W29C512A 0xC8 /* Same as W29EE512 */ +#define WINBOND_W39F010 0xA1 #define WINBOND_W39L010 0x31 #define WINBOND_W39L020 0xB5 #define WINBOND_W39L040 0xB6 diff --git a/w39.c b/w39.c index da61d23..d6504ff 100644 --- a/w39.c +++ b/w39.c @@ -115,6 +115,26 @@ static int printlock_w39_tblwp(uint8_t lock) return 0; } +static int printlock_w39_bootblock_8k(uint8_t lock) +{ + msg_cdbg("Software 8 kB bootblock locking is %sactive.\n", + (lock & 0x03) ? "" : "not "); + if (lock & 0x03) + return -1; + + return 0; +} + +static int printlock_w39_bootblock_16k(uint8_t lock) +{ + msg_cdbg("Software 16 kB bootblock locking is %sactive.\n", + (lock & 0x03) ? "" : "not "); + if (lock & 0x03) + return -1; + + return 0; +} + static int printlock_w39_bootblock_64k16k(uint8_t lock) { msg_cdbg("Software 64 kB bootblock locking is %sactive.\n", @@ -160,6 +180,54 @@ static int unlock_w39_fwh(struct flashctx *flash) return 0; } +int printlock_w39f010(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_16k(lock); + + lock = w39_idmode_readb(flash, 0x1fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_bootblock_16k(lock); + + return ret; +} + +int printlock_w39l010(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_8k(lock); + + lock = w39_idmode_readb(flash, 0x1fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_bootblock_8k(lock); + + return ret; +} + +int printlock_w39l020(struct flashctx *flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_64k16k(lock); + + lock = w39_idmode_readb(flash, 0x3fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_bootblock_64k16k(lock); + + return ret; +} + int printlock_w39l040(struct flashctx *flash) { uint8_t lock;

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Micro-Star International (MSI) G33M (MS-7357) mainboard sucsessfully flashed with flashrom v0.9.6.1-r1564
by alex 28 Oct '12

28 Oct '12

Micro-Star International (MSI) G33M (MS-7357) mainboard sucsessfully readed, tested & flashed with flashrom v0.9.6.1-r1564

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Re: [flashrom] ft2232: TI Stellaris DevKit / Dediprog SF100 IF / SPI Chip
by Stefan Tauner 27 Oct '12

27 Oct '12

Hello Philipp, thanks for sharing. On Sat, 27 Oct 2012 15:44:51 +0200 Philipp Wiesner <wiesnerph(a)fh-bingen.de> wrote: > I had to make > some customizations to ft2232.c add support for this programmer. I had to > build a cable which connects the JTAG interface with the on-board SF100 > interface. But it is just a plain cable without logic, i presume i.e. there are no hardware modifications necessary for the TI board nor the iEi mainboard, right? > I like to share as much of the knowledge I acquired as possible with the > community. The least thing I can do is send a patch with my modifications > for the TI development board. I still need to read the instructions on how > to prepare and send patches as I haven't done this in a long time. How did you obtain the flashrom source (file archive, subversion, git...)? Depending on that the way to obtain a usable diff/patch vary a lot. If you need further help you can also ask us on our IRC channel, #flashrom on freenode, available also via this website: http://webchat.freenode.net/?channels=flashrom&uio=d4 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/3] Do not read the flash chip twice in verification mode.
by Carl-Daniel Hailfinger 27 Oct '12

27 Oct '12

Am 23.07.2012 15:33 schrieb Stefan Tauner: > Kyösti Mälkki noticed that we unnecessarily read the flash chip twice when > called with --verify. The first one is the mandatory read before everything > (to be able to detect the seriousness of errors), but the second one is not > necessary because we can just use the former for the comparison. Indeed. > This introduces a small output change: previously we printed ERASE or > VERIFY depending on the callee. This special case has been dropped > because it is unnecessary to print it (and wrong for the verification > function to need to know why it is verifying exactly). > If an erase fails we mention that fact explicitly already, similar for verify. I'm not convinced yet. I'll try to compare the failure output with and without this patch before I ack. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flash.h | 2 +- > flashrom.c | 86 +++++++++++++++++++++++++++--------------------------------- > jedec.c | 2 +- > 3 files changed, 41 insertions(+), 49 deletions(-) > > diff --git a/flash.h b/flash.h > index d669512..5bb1211 100644 > --- a/flash.h > +++ b/flash.h > @@ -241,7 +241,7 @@ int min(int a, int b); > int max(int a, int b); > void tolower_string(char *str); > char *extract_param(char **haystack, const char *needle, const char *delim); > -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); > +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len); > int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran); > char *strcat_realloc(char *dest, const char *src); > void print_version(void); > diff --git a/flashrom.c b/flashrom.c > index fc52c4a..70687ff 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -548,6 +548,26 @@ static unsigned int count_usable_erasers(const struct flashctx *flash) > return usable_erasefunctions; > } > > +int compare_range(uint8_t *wantbuf, uint8_t *havebuf, unsigned int start, unsigned int len) Make this function static? > +{ > + int ret = 0, failcount = 0; > + unsigned int i; > + for (i = 0; i < len; i++) { > + if (wantbuf[i] != havebuf[i]) { > + /* Only print the first failure. */ > + if (!failcount++) > + msg_cerr("FAILED at 0x%08x! Expected=0x%02x, Found=0x%02x,", > + start + i, wantbuf[i], havebuf[i]); > + } > + } > + if (failcount) { > + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", > + start, start + len - 1, failcount); > + ret = -1; > + } > + return ret; > +} > + > /* start is an offset to the base address of the flash chip */ > int check_erased_range(struct flashctx *flash, unsigned int start, > unsigned int len) > @@ -560,7 +580,7 @@ int check_erased_range(struct flashctx *flash, unsigned int start, > exit(1); > } > memset(cmpbuf, 0xff, len); > - ret = verify_range(flash, cmpbuf, start, len, "ERASE"); > + ret = verify_range(flash, cmpbuf, start, len); > free(cmpbuf); > return ret; > } > @@ -570,15 +590,12 @@ int check_erased_range(struct flashctx *flash, unsigned int start, > * flash content at location start > * @start offset to the base address of the flash chip > * @len length of the verified area > - * @message string to print in the "FAILED" message > * @return 0 for success, -1 for failure > */ > -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > - unsigned int len, const char *message) > +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len) > { > - unsigned int i; > uint8_t *readbuf = malloc(len); > - int ret = 0, failcount = 0; > + int ret = 0; > > if (!len) > goto out_free; > @@ -599,8 +616,6 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > ret = -1; > goto out_free; > } > - if (!message) > - message = "VERIFY"; > > ret = flash->read(flash, readbuf, start, len); > if (ret) { > @@ -609,22 +624,7 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > return ret; > } > > - for (i = 0; i < len; i++) { > - if (cmpbuf[i] != readbuf[i]) { > - /* Only print the first failure. */ > - if (!failcount++) > - msg_cerr("%s FAILED at 0x%08x! " > - "Expected=0x%02x, Read=0x%02x,", > - message, start + i, cmpbuf[i], > - readbuf[i]); > - } > - } > - if (failcount) { > - msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", > - start, start + len - 1, failcount); > - ret = -1; > - } > - > + ret = compare_range(cmpbuf, readbuf, start, len); Good idea to refactor this. > out_free: > free(readbuf); > return ret; > @@ -1060,21 +1060,6 @@ notfound: > return flash - flashchips; > } > > -int verify_flash(struct flashctx *flash, uint8_t *buf) > -{ > - int ret; > - unsigned int total_size = flash->total_size * 1024; > - > - msg_cinfo("Verifying flash... "); > - > - ret = verify_range(flash, buf, 0, total_size, NULL); > - > - if (!ret) > - msg_cinfo("VERIFIED. \n"); > - > - return ret; > -} I believe that this hunk conflicts with some of your layout patches. Maybe not a direct patch hunk conflict, but having a standalone function which verifies the flash chip according to some layout rules is a good thing. I'd keep verify_flash for now. OTOH, the hunk below makes it painfully obvious that the current verify_flash abstraction is not the right abstraction. Two functions compare_all_ranges() defaulting to a full chip range and verify_all_ranges() with similar characteristics would IMHO be a good abstraction, especially in light of the pending improved layout support. > - > int read_buf_from_file(unsigned char *buf, unsigned long size, > const char *filename) > { > @@ -1838,15 +1823,22 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > } > > if (verify_it) { > - /* Work around chips which need some time to calm down. */ > - if (write_it) > + msg_cinfo("Verifying flash... "); > + > + if (write_it) { > + /* Work around chips which need some time to calm down. */ > programmer_delay(1000*1000); > - ret = verify_flash(flash, newcontents); > - /* If we tried to write, and verification now fails, we > - * might have an emergency situation. > - */ > - if (ret && write_it) > - emergency_help_message(); > + ret = verify_range(flash, newcontents, 0, size); > + /* If we tried to write, and verification now fails, we > + * might have an emergency situation. > + */ > + if (ret) > + emergency_help_message(); > + } else { > + ret = compare_range(newcontents, oldcontents, 0, size); > + } > + if (!ret) > + msg_cinfo("VERIFIED.\n"); > } > > out: > diff --git a/jedec.c b/jedec.c > index 69c0c0c..1fa1a10 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -409,7 +409,7 @@ retry: > > dst = d; > src = s; > - failed = verify_range(flash, src, start, page_size, NULL); > + failed = verify_range(flash, src, start, page_size); > > if (failed && tried++ < MAX_REFLASH_TRIES) { > msg_cerr("retrying.\n"); I agree with the direction of the patch, I'm just not yet sure about the implementation. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Add support for Atmel AT26DF041.
by Stefan Tauner 27 Oct '12

27 Oct '12

On Sun, 7 Oct 2012 06:23:26 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Wicked chip: > No WRSR, no write enable command, auto-erasing page write (but even > without that page writes are recommended to write the whole page > i.e. operate on a completely erased page), mad requirements on block > refreshments if only partly written. > > Found on my Intel D946GZIS and tested with my serprog in situ. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> committed in r1616. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] serprog: add opcode to control the programmer's output drivers.
by Stefan Tauner 27 Oct '12

27 Oct '12

On Wed, 10 Oct 2012 08:08:36 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Also, move the macro list to its own file. i have splitted the previous patch into two and committed them in r1617 and r1618. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1619 - trunk
by repository service 27 Oct '12

27 Oct '12

Author: stefanct Date: Sat Oct 27 17:36:56 2012 New Revision: 1619 URL: http://flashrom.org/trac/flashrom/changeset/1619 Log: Do not read the flash chip twice in verification mode. Kyösti Mälkki noticed that we unnecessarily read the flash chip twice when called with --verify. The first one is the mandatory read before everything (to be able to detect the seriousness of errors), but the second one is not necessary because we can just use the former for the comparison. This introduces a small output change: previously we printed ERASE or VERIFY depending on the callee. This special case has been dropped because it is unnecessary to print it (and wrong for the verification function to need to know why it is verifying exactly). If an erase fails we mention that fact explicitly already, similar for verify. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flash.h trunk/flashrom.c trunk/jedec.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sat Oct 27 02:34:23 2012 (r1618) +++ trunk/flash.h Sat Oct 27 17:36:56 2012 (r1619) @@ -231,7 +231,7 @@ int max(int a, int b); void tolower_string(char *str); char *extract_param(char **haystack, const char *needle, const char *delim); -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len); int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Oct 27 02:34:23 2012 (r1618) +++ trunk/flashrom.c Sat Oct 27 17:36:56 2012 (r1619) @@ -544,6 +544,26 @@ return usable_erasefunctions; } +int compare_range(uint8_t *wantbuf, uint8_t *havebuf, unsigned int start, unsigned int len) +{ + int ret = 0, failcount = 0; + unsigned int i; + for (i = 0; i < len; i++) { + if (wantbuf[i] != havebuf[i]) { + /* Only print the first failure. */ + if (!failcount++) + msg_cerr("FAILED at 0x%08x! Expected=0x%02x, Found=0x%02x,", + start + i, wantbuf[i], havebuf[i]); + } + } + if (failcount) { + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", + start, start + len - 1, failcount); + ret = -1; + } + return ret; +} + /* start is an offset to the base address of the flash chip */ int check_erased_range(struct flashctx *flash, unsigned int start, unsigned int len) @@ -556,7 +576,7 @@ exit(1); } memset(cmpbuf, 0xff, len); - ret = verify_range(flash, cmpbuf, start, len, "ERASE"); + ret = verify_range(flash, cmpbuf, start, len); free(cmpbuf); return ret; } @@ -566,15 +586,12 @@ * flash content at location start * @start offset to the base address of the flash chip * @len length of the verified area - * @message string to print in the "FAILED" message * @return 0 for success, -1 for failure */ -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, - unsigned int len, const char *message) +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len) { - unsigned int i; uint8_t *readbuf = malloc(len); - int ret = 0, failcount = 0; + int ret = 0; if (!len) goto out_free; @@ -595,8 +612,6 @@ ret = -1; goto out_free; } - if (!message) - message = "VERIFY"; ret = flash->chip->read(flash, readbuf, start, len); if (ret) { @@ -605,22 +620,7 @@ return ret; } - for (i = 0; i < len; i++) { - if (cmpbuf[i] != readbuf[i]) { - /* Only print the first failure. */ - if (!failcount++) - msg_cerr("%s FAILED at 0x%08x! " - "Expected=0x%02x, Read=0x%02x,", - message, start + i, cmpbuf[i], - readbuf[i]); - } - } - if (failcount) { - msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", - start, start + len - 1, failcount); - ret = -1; - } - + ret = compare_range(cmpbuf, readbuf, start, len); out_free: free(readbuf); return ret; @@ -1054,21 +1054,6 @@ return chip - flashchips; } -int verify_flash(struct flashctx *flash, uint8_t *buf) -{ - int ret; - unsigned int total_size = flash->chip->total_size * 1024; - - msg_cinfo("Verifying flash... "); - - ret = verify_range(flash, buf, 0, total_size, NULL); - - if (!ret) - msg_cinfo("VERIFIED. \n"); - - return ret; -} - int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename) { @@ -1424,10 +1409,8 @@ { msg_gerr("Your flash chip is in an unknown state.\n" "Get help on IRC at chat.freenode.net (channel #flashrom) or\n" - "mail flashrom(a)flashrom.org with the subject " - "\"FAILED: <your board name>\"!\n" - "-------------------------------------------------------------" - "------------------\n" + "mail flashrom(a)flashrom.org with the subject \"FAILED: <your board name>\"!\n" + "-------------------------------------------------------------------------------\n" "DO NOT REBOOT OR POWEROFF!\n"); } @@ -1860,15 +1843,22 @@ } if (verify_it) { - /* Work around chips which need some time to calm down. */ - if (write_it) + msg_cinfo("Verifying flash... "); + + if (write_it) { + /* Work around chips which need some time to calm down. */ programmer_delay(1000*1000); - ret = verify_flash(flash, newcontents); - /* If we tried to write, and verification now fails, we - * might have an emergency situation. - */ - if (ret && write_it) - emergency_help_message(); + ret = verify_range(flash, newcontents, 0, size); + /* If we tried to write, and verification now fails, we + * might have an emergency situation. + */ + if (ret) + emergency_help_message(); + } else { + ret = compare_range(newcontents, oldcontents, 0, size); + } + if (!ret) + msg_cinfo("VERIFIED.\n"); } out: Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sat Oct 27 02:34:23 2012 (r1618) +++ trunk/jedec.c Sat Oct 27 17:36:56 2012 (r1619) @@ -410,7 +410,7 @@ dst = d; src = s; - failed = verify_range(flash, src, start, page_size, NULL); + failed = verify_range(flash, src, start, page_size); if (failed && tried++ < MAX_REFLASH_TRIES) { msg_cerr("retrying.\n");

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ft2232: TI Stellaris DevKit / Dediprog SF100 IF / SPI Chip
by Philipp Wiesner 27 Oct '12

27 Oct '12

Hi I had to flash a BIOS chip via SPI. The board i was flashing was the mainboard of a 'iEi TANK-800-D525' computer (it's a rugged industrial sff computer). I don't have access to the machine ATM so I can't tell what the exact name of the board is, but it's a custom mainboard only used in this computer AFAIK. It has a SST25VF016B BIOS-chip (which is well supported) and an interface designed for the Dediprog SF100 programmer, which essentially is a SPI interface with an optional IO line. (Documentation is available online, for users as well as for hardware developers, so the interface is well documented). The programmer I used was a Texas Instruments DK-LM3S9B96 Stellaris development kit. It has a JTAG-Interface, which is externally accessable via pin header. The interface is provided by a FTDI ft2232 chip together with some glue logic (essentially bus buffers, some logic). I had to make some customizations to ft2232.c add support for this programmer. I had to build a cable which connects the JTAG interface with the on-board SF100 interface. Needless to say, I was successful. I like to share as much of the knowledge I acquired as possible with the community. The least thing I can do is send a patch with my modifications for the TI development board. I still need to read the instructions on how to prepare and send patches as I haven't done this in a long time. IMHO other TI Stellaris development boards share the same JTAG interface concept, but I can't name them. If someone has suggestions, I could check those boards for compatibility (by schematics). BTW, vid=0x0403 (FTDI default), pid=0xbcd9. In fact, a lot of USB-JTAG-Interfaces on development boards should be capable of doing this. The board needs to be flashed while completely off. At least I was not successful using the optional IO-line to claim exclusive access to the chip while in standby/running. I'm going to send a follow-up if I have specific questions. In the meantime you can ask questions if you think anything I did can be useful for you / for everyone. Kind regards, P. Wiesner

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[commit] r1616 - trunk
by repository service 27 Oct '12

27 Oct '12

Author: stefanct Date: Sat Oct 27 02:06:02 2012 New Revision: 1616 URL: http://flashrom.org/trac/flashrom/changeset/1616 Log: Add support for Atmel AT26DF041. Wicked chip: No WRSR, no write enable command (but swallows our default one without a problem), supports an auto-erasing page write (but even without that page writes are recommended to write the whole page i.e. operate on a completely erased page), mad requirements on block refreshments if only partly written. Found on my Intel D946GZIS and tested with my serprog in situ. Using the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using the spi_chip_write_256 command greatly improves performance and works flawlessly. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/spi.h trunk/spi25.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/chipdrivers.h Sat Oct 27 02:06:02 2012 (r1616) @@ -41,7 +41,9 @@ int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/flashchips.c Sat Oct 27 02:06:02 2012 (r1616) @@ -1795,18 +1795,24 @@ .total_size = 512, .page_size = 256, /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { + .eraseblocks = { {256, 2048} }, + .block_erase = spi_block_erase_81, + }, { + .eraseblocks = { {2 * 1024, 256} }, + .block_erase = spi_block_erase_50, + }, { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, } - }, - .write = NULL /* Incompatible Page write */, - .read = spi_chip_read, + }, /* Supports also an incompatible page write (of exactly 256 B) and an auto-erasing write. */ + .write = spi_chip_write_1, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, /* 3.0-3.6V for higher speed, 2.7-3.6V normal */ }, Modified: trunk/spi.h ============================================================================== --- trunk/spi.h Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/spi.h Sat Oct 27 02:06:02 2012 (r1616) @@ -76,11 +76,21 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 +/* Block Erase 0x50 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_50 0x50 +#define JEDEC_BE_50_OUTSIZE 0x04 +#define JEDEC_BE_50_INSIZE 0x00 + /* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 +/* Block Erase 0x81 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_81 0x81 +#define JEDEC_BE_81_OUTSIZE 0x04 +#define JEDEC_BE_81_INSIZE 0x00 + /* Block Erase 0xd8 is supported by EON/Macronix chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/spi25.c Sat Oct 27 02:06:02 2012 (r1616) @@ -741,6 +741,86 @@ return 0; } +int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_50_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_50, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 10 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_81_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_81, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 8 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen) {

2 1

[commit] r1618 - in trunk: . Documentation
by repository service 27 Oct '12

27 Oct '12

Author: stefanct Date: Sat Oct 27 02:34:23 2012 New Revision: 1618 URL: http://flashrom.org/trac/flashrom/changeset/1618 Log: serprog: add opcode to control the programmer's output drivers. This allowed me to let the clips remain attached on my D946GZIS while playing with coreboot/serialice. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Documentation/serprog-protocol.txt trunk/serprog.c trunk/serprog.h Modified: trunk/Documentation/serprog-protocol.txt ============================================================================== --- trunk/Documentation/serprog-protocol.txt Sat Oct 27 02:34:18 2012 (r1617) +++ trunk/Documentation/serprog-protocol.txt Sat Oct 27 02:34:23 2012 (r1618) @@ -34,6 +34,7 @@ 0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK + slen bytes of data 0x14 Set SPI clock frequency in Hz 32-bit requested frequency ACK + 32-bit set frequency / NAK +0x15 Toggle flash chip pin drivers 8-bit (0 disable, else enable) ACK / NAK 0x?? unimplemented command - invalid. @@ -82,6 +83,12 @@ lower than the one requested. If there is no lower frequency available the lowest possible should be used. The value chosen is sent back in the reply with an ACK. + 0x15 (S_CMD_S_PIN_STATE): + Sets the state of the pin drivers connected to the flash chip. Disabling them allows other + devices (e.g. a mainboard's chipset) to access the chip. This way the serprog controller can + remain attached to the flash chip even when the board is running. The user is responsible to + NOT connect VCC and other permanently externally driven signals to the programmer as needed. + If the value is 0, then the drivers should be disabled, otherwise they should be enabled. About mandatory commands: The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, but one can't really do anything with these commands. Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sat Oct 27 02:34:18 2012 (r1617) +++ trunk/serprog.c Sat Oct 27 02:34:23 2012 (r1618) @@ -664,6 +664,15 @@ sp_device_opbuf_size); } + if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { + uint8_t en = 1; + if (sp_docommand(S_CMD_S_PIN_STATE, 1, &en, 0, NULL) != 0) { + msg_perr("Error: could not enable output buffers\n"); + return 1; + } else + msg_pdbg(MSGHEADER "Output drivers enabled\n"); + } else + msg_pdbg(MSGHEADER "Warning: Programmer does not support toggling its output drivers\n"); sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; @@ -736,9 +745,15 @@ static int serprog_shutdown(void *data) { - msg_pspew("%s\n", __func__); if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) sp_execute_opbuf(); + if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { + uint8_t dis = 0; + if (sp_docommand(S_CMD_S_PIN_STATE, 1, &dis, 0, NULL) == 0) + msg_pdbg(MSGHEADER "Output drivers disabled\n"); + else + msg_perr(MSGHEADER "%s: Warning: could not disable output buffers\n", __func__); + } /* FIXME: fix sockets on windows(?), especially closing */ serialport_shutdown(&sp_fd); if (sp_max_write_n) Modified: trunk/serprog.h ============================================================================== --- trunk/serprog.h Sat Oct 27 02:34:18 2012 (r1617) +++ trunk/serprog.h Sat Oct 27 02:34:23 2012 (r1618) @@ -22,3 +22,4 @@ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ #define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ #define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ +#define S_CMD_S_PIN_STATE 0x15 /* Enable/disable output drivers */

1 0

[commit] r1617 - in trunk: . Documentation
by repository service 27 Oct '12

27 Oct '12

Author: stefanct Date: Sat Oct 27 02:34:18 2012 New Revision: 1617 URL: http://flashrom.org/trac/flashrom/changeset/1617 Log: serprog: move the macro list to its own header file. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Added: trunk/serprog.h (contents, props changed) Modified: trunk/Documentation/serprog-protocol.txt trunk/serprog.c Modified: trunk/Documentation/serprog-protocol.txt ============================================================================== --- trunk/Documentation/serprog-protocol.txt Sat Oct 27 02:06:02 2012 (r1616) +++ trunk/Documentation/serprog-protocol.txt Sat Oct 27 02:34:18 2012 (r1617) @@ -92,28 +92,4 @@ In addition, support for these commands is recommended: S_CMD_Q_PGMNAME, S_CMD_Q_BUSTYPE, S_CMD_Q_CHIPSIZE (if parallel). - -This define listing should help C coders - (it's here to be the single source for copying - will be a .h someday i think) -#define S_ACK 0x06 -#define S_NAK 0x15 -#define S_CMD_NOP 0x00 /* No operation */ -#define S_CMD_Q_IFACE 0x01 /* Query interface version */ -#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ -#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ -#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ -#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ -#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ -#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ -#define S_CMD_R_BYTE 0x09 /* Read a single byte */ -#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ -#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ -#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ -#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ -#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ -#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ -#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ -#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ -#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ -#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ -#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ +See also serprog.h. Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sat Oct 27 02:06:02 2012 (r1616) +++ trunk/serprog.c Sat Oct 27 02:34:18 2012 (r1617) @@ -38,6 +38,7 @@ #include "flash.h" #include "programmer.h" #include "chipdrivers.h" +#include "serprog.h" #define MSGHEADER "serprog: " @@ -48,30 +49,6 @@ */ static int serprog_shutdown(void *data); -#define S_ACK 0x06 -#define S_NAK 0x15 -#define S_CMD_NOP 0x00 /* No operation */ -#define S_CMD_Q_IFACE 0x01 /* Query interface version */ -#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ -#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ -#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ -#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ -#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ -#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum length */ -#define S_CMD_R_BYTE 0x09 /* Read a single byte */ -#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ -#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ -#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ -#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ -#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ -#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ -#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ -#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ -#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ -#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ -#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ - static uint16_t sp_device_serbuf_size = 16; static uint16_t sp_device_opbuf_size = 300; /* Bitmap of supported commands */ Added: trunk/serprog.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/serprog.h Sat Oct 27 02:34:18 2012 (r1617) @@ -0,0 +1,24 @@ +/* According to Serial Flasher Protocol Specification - version 1 */ +#define S_ACK 0x06 +#define S_NAK 0x15 +#define S_CMD_NOP 0x00 /* No operation */ +#define S_CMD_Q_IFACE 0x01 /* Query interface version */ +#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ +#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ +#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ +#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ +#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ +#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ +#define S_CMD_R_BYTE 0x09 /* Read a single byte */ +#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ +#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ +#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ +#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ +#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ +#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ +#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ +#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ +#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ +#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */

1 0

[commit] r1615 - trunk
by repository service 26 Oct '12

26 Oct '12

Author: stefanct Date: Fri Oct 26 18:49:15 2012 New Revision: 1615 URL: http://flashrom.org/trac/flashrom/changeset/1615 Log: Add support for Numonyx N25Q016 and N25Q032. The 32Mb version has 1.8V and 3.0V versions, the smaller one 1.8V only (or Numonyx/Micron forgot to publish it). Another difference is that the 16Mb chip has 32 kB subsectors (erase opcode 0x52). As long as there are no funky configurations like for the 128Mb chips, we got the smaller parts covered with this change. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Oct 23 15:06:46 2012 (r1614) +++ trunk/flashchips.c Fri Oct 26 18:49:15 2012 (r1615) @@ -5587,6 +5587,108 @@ { .vendor = "Numonyx", + .name = "N25Q016", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q016__1E, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Numonyx", + .name = "N25Q032..1E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q032__1E, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Numonyx", + .name = "N25Q032..3E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q032__3E, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", .name = "N25Q064..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -5614,7 +5716,7 @@ }, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, }, @@ -5647,7 +5749,7 @@ }, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Oct 23 15:06:46 2012 (r1614) +++ trunk/flashchips.h Fri Oct 26 18:49:15 2012 (r1615) @@ -591,8 +591,11 @@ #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 -#define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, 64KB/4KB blocks/sectors */ -#define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, 64KB/4KB blocks/sectors */ +#define ST_N25Q016__1E 0xBB15 /* N25Q016, 1.8V, (uniform sectors expected) */ +#define ST_N25Q032__3E 0xBA16 /* N25Q032, 3.0V, (uniform sectors expected) */ +#define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ +#define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ +#define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ #define MVC_V29C51000T 0x00

1 0

[PATCH] Remove exit calls from print_supported_chips
by Niklas Söderlund 23 Oct '12

23 Oct '12

Propagate the error code using return values instead. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- cli_classic.c | 3 +-- flash.h | 2 +- print.c | 14 +++++++++----- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index 4ae375c..7bcd4a6 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -363,8 +363,7 @@ int main(int argc, char *argv[]) #endif if (list_supported) { - print_supported(); - ret = 0; + ret = print_supported(); goto out; } diff --git a/flash.h b/flash.h index 4913536..0bb6c2b 100644 --- a/flash.h +++ b/flash.h @@ -214,7 +214,7 @@ void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); -void print_supported(void); +int print_supported(void); void print_supported_wiki(void); /* flashrom.c */ diff --git a/print.c b/print.c index eb99c07..49e9441 100644 --- a/print.c +++ b/print.c @@ -58,7 +58,7 @@ char *flashbuses_to_text(enum chipbustype bustype) return ret; } -static void print_supported_chips(void) +static int print_supported_chips(void) { const char *delim = "/"; const int mintoklen = 5; @@ -182,7 +182,7 @@ static void print_supported_chips(void) tmpven = malloc(strlen(chip->vendor) + 1); if (tmpven == NULL) { msg_gerr("Out of memory!\n"); - exit(1); + return 1; } strcpy(tmpven, chip->vendor); @@ -206,7 +206,7 @@ static void print_supported_chips(void) tmpdev = malloc(strlen(chip->name) + 1); if (tmpdev == NULL) { msg_gerr("Out of memory!\n"); - exit(1); + return 1; } strcpy(tmpdev, chip->name); @@ -320,6 +320,8 @@ static void print_supported_chips(void) } msg_ginfo("\n"); } + + return 0; } #if CONFIG_INTERNAL == 1 @@ -431,9 +433,10 @@ static void print_supported_boards_helper(const struct board_info *boards, } #endif -void print_supported(void) +int print_supported(void) { - print_supported_chips(); + if (print_supported_chips()) + return 1; msg_ginfo("\nSupported programmers:\n"); list_programmers_linebreak(0, 80, 0); @@ -547,6 +550,7 @@ void print_supported(void) programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif + return 0; } #if CONFIG_INTERNAL == 1 -- 1.7.12.3

2 1

[commit] r1614 - trunk
by repository service 23 Oct '12

23 Oct '12

Author: stefanct Date: Tue Oct 23 15:06:46 2012 New Revision: 1614 URL: http://flashrom.org/trac/flashrom/changeset/1614 Log: Remove exit calls from print_supported_chips. Propagate the error code using return values instead, but let cli_classic.c still decide the ultimate return value of the process. Also, remove setting the ret value again after print_supported_wiki() - success is the default. Signed-off-by: Niklas Söderlund <niso(a)kth.se> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cli_classic.c trunk/flash.h trunk/print.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sat Oct 20 11:13:16 2012 (r1613) +++ trunk/cli_classic.c Tue Oct 23 15:06:46 2012 (r1614) @@ -357,14 +357,13 @@ #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { print_supported_wiki(); - ret = 0; goto out; } #endif if (list_supported) { - print_supported(); - ret = 0; + if (print_supported()) + ret = 1; goto out; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sat Oct 20 11:13:16 2012 (r1613) +++ trunk/flash.h Tue Oct 23 15:06:46 2012 (r1614) @@ -214,7 +214,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); -void print_supported(void); +int print_supported(void); void print_supported_wiki(void); /* flashrom.c */ Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Oct 20 11:13:16 2012 (r1613) +++ trunk/print.c Tue Oct 23 15:06:46 2012 (r1614) @@ -58,7 +58,7 @@ return ret; } -static void print_supported_chips(void) +static int print_supported_chips(void) { const char *delim = "/"; const int mintoklen = 5; @@ -182,7 +182,7 @@ tmpven = malloc(strlen(chip->vendor) + 1); if (tmpven == NULL) { msg_gerr("Out of memory!\n"); - exit(1); + return 1; } strcpy(tmpven, chip->vendor); @@ -206,7 +206,7 @@ tmpdev = malloc(strlen(chip->name) + 1); if (tmpdev == NULL) { msg_gerr("Out of memory!\n"); - exit(1); + return 1; } strcpy(tmpdev, chip->name); @@ -320,6 +320,8 @@ } msg_ginfo("\n"); } + + return 0; } #if CONFIG_INTERNAL == 1 @@ -431,9 +433,10 @@ } #endif -void print_supported(void) +int print_supported(void) { - print_supported_chips(); + if (print_supported_chips()) + return 1; msg_ginfo("\nSupported programmers:\n"); list_programmers_linebreak(0, 80, 0); @@ -547,6 +550,7 @@ programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif + return 0; } #if CONFIG_INTERNAL == 1

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[PATCH] Enable VX855 chipset
by John Schmerge 21 Oct '12

21 Oct '12

This patch adds support for the Via VX855 chipset

4 8

CHIPSET: TYAN Thunder K8WE S2895
by Tony Freeman 21 Oct '12

21 Oct '12

*Hello,* * * *As per output from the program:* *=========================* [root@monarch ~]# flashrom --programmer internal flashrom v0.9.6.1-r1613 on Linux 2.6.32-279.11.1.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA CK804". Enabling flash write... OK. WARNING: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. No operations were specified. *And here's the lspci:* *================* [root@monarch ~]# lspci 00:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a3) 00:01.0 ISA bridge: NVIDIA Corporation CK804 ISA Bridge (rev a3) 00:01.1 SMBus: NVIDIA Corporation CK804 SMBus (rev a2) 00:02.0 USB controller: NVIDIA Corporation CK804 USB Controller (rev a2) 00:02.1 USB controller: NVIDIA Corporation CK804 USB Controller (rev a3) 00:04.0 Multimedia audio controller: NVIDIA Corporation CK804 AC'97 Audio Controller (rev a2) 00:06.0 IDE interface: NVIDIA Corporation CK804 IDE (rev a2) 00:07.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev a3) 00:08.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev a3) 00:09.0 PCI bridge: NVIDIA Corporation CK804 PCI Bridge (rev a2) 00:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev a3) 00:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:05.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] 02:00.0 VGA compatible controller: NVIDIA Corporation NV45 [GeForce 6800 GTO] (rev a2) 08:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 08:0a.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 08:0b.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 08:0b.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 80:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a3) 80:01.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a3) 80:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev a3) 80:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3)

1 0

[commit] r1613 - trunk
by repository service 20 Oct '12

20 Oct '12

Author: stefanct Date: Sat Oct 20 11:13:16 2012 New Revision: 1613 URL: http://flashrom.org/trac/flashrom/changeset/1613 Log: Add a bunch of new/tested stuff and various small changes 15. Tested Mainboards: OK: - Foxconn P55MX http://www.flashrom.org/pipermail/flashrom/2012-October/010002.html Tested flash chips: - Eon EN25F64 to PR (+PR) http://paste.flashrom.org/view.php?id=1426 - Macronix MX25L1005 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-October/010004.html - Set SST39VF512 to PREW (+W) http://www.flashrom.org/pipermail/flashrom/2012-September/009958.html Tested chipsets: - Z77 (only reading was really tested) Miscellaneous: - Fix ft2232_spi's parameter parsing. - Fix nicrealtek's init (always segfaulted since r1586 oops). - Add another T60 variant to the laptop whitelist. - Improve message shown when image file size does not match flash chip - Refine messages regarding the flash descriptor override strap according to the findings by Vladislav Bykov on his P55MX. - Fix the ID of EN25F64. - Demote and clarify debug message in serprog_delay(). - Minor other cleanups. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/flashchips.c trunk/flashrom.c trunk/ft2232_spi.c trunk/ichspi.c trunk/nicrealtek.c trunk/print.c trunk/serprog.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/board_enable.c Sat Oct 20 11:13:16 2012 (r1613) @@ -2407,10 +2407,11 @@ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, - {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, + {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/chipset_enable.c Sat Oct 20 11:13:16 2012 (r1613) @@ -1406,7 +1406,7 @@ {0x8086, 0x1c5c, OK, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_pch6}, {0x8086, 0x1d41, OK, "Intel", "X79", enable_flash_pch6}, - {0x8086, 0x1e44, NT, "Intel", "Z77", enable_flash_pch7}, + {0x8086, 0x1e44, OK, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/flashchips.c Sat Oct 20 11:13:16 2012 (r1613) @@ -954,7 +954,7 @@ }, { .eraseblocks = { { 64 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -986,7 +986,7 @@ }, { .eraseblocks = { { 128 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -1018,7 +1018,7 @@ }, { .eraseblocks = { { 256 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -1050,7 +1050,7 @@ }, { .eraseblocks = { { 512 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -1082,7 +1082,7 @@ }, { .eraseblocks = { { 1024 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -1114,7 +1114,7 @@ }, { .eraseblocks = { { 2048 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, @@ -1153,7 +1153,7 @@ }, { .eraseblocks = { { 4096 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25l032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ @@ -1192,7 +1192,7 @@ }, { .eraseblocks = { { 4096 * 1024, 1 } }, .block_erase = spi_block_erase_c7, - } + } }, .printlock = spi_prettyprint_status_register_amic_a25lq032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ @@ -3413,11 +3413,11 @@ .name = "EN25F64", .bustype = BUS_SPI, .manufacture_id = EON_ID_NOPREFIX, - .model_id = EON_EN25F32, + .model_id = EON_EN25F64, .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4680,7 +4680,7 @@ .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7053,7 +7053,7 @@ .total_size = 64, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/flashrom.c Sat Oct 20 11:13:16 2012 (r1613) @@ -1086,7 +1086,8 @@ return 1; } if (image_stat.st_size != size) { - msg_gerr("Error: Image size doesn't match\n"); + msg_gerr("Error: Image size (%ld B) doesn't match the flash chip's size (%ld B)!\n", + image_stat.st_size, size); fclose(image); return 1; } Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/ft2232_spi.c Sat Oct 20 11:13:16 2012 (r1613) @@ -271,11 +271,11 @@ channel_count = -1; break; } - } - if (channel_count < 0 || strlen(arg) != 1) { - msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); - free(arg); - return -2; + if (channel_count < 0 || strlen(arg) != 1) { + msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); + free(arg); + return -2; + } } free(arg); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/ichspi.c Sat Oct 20 11:13:16 2012 (r1613) @@ -1675,11 +1675,9 @@ if (tmp2 & HSFS_FDV) desc_valid = 1; if (!(tmp2 & HSFS_FDOPSS) && desc_valid) - msg_pinfo("The Flash Descriptor Security Override " - "Strap-Pin is set. Restrictions implied\n" - "by the FRAP and FREG registers are NOT in " - "effect. Please note that Protected\n" - "Range (PR) restrictions still apply.\n"); + msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" + "the Master Section of the flash descriptor are NOT in effect. Please note\n" + "that Protected Range (PR) restrictions still apply.\n"); ich_init_opcodes(); if (desc_valid) { @@ -1720,15 +1718,13 @@ "yet.\n"); if (!ich_spi_force) programmer_may_write = 0; - msg_pinfo("Writes have been disabled. You can enforce " - "write support with the\nich_spi_force " - "programmer option, but it will most likely " - "harm your hardware!\nIf you force flashrom " - "you will get no support if something " - "breaks.\n"); + msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n" + "support with the ich_spi_force programmer option, but you will most likely\n" + "harm your hardware! If you force flashrom you will get no support if\n" + "something breaks. On a few mainboards it is possible to enable write\n" + "access by setting a jumper (see its documentation or the board itself).\n"); if (ich_spi_force) - msg_pinfo("Continuing with write support " - "because the user forced us to!\n"); + msg_pinfo("Continuing with write support because the user forced us to!\n"); } tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/nicrealtek.c Sat Oct 20 11:13:16 2012 (r1613) @@ -60,6 +60,14 @@ int nicrealtek_init(void) { + if (rget_io_perms()) + return 1; + + io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); + + if (register_shutdown(nicrealtek_shutdown, NULL)) + return 1; + /* Beware, this ignores the vendor ID! */ switch (pcidev_dev->device_id) { case 0x8139: /* RTL8139 */ @@ -74,14 +82,6 @@ break; } - if (rget_io_perms()) - return 1; - - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - - if (register_shutdown(nicrealtek_shutdown, NULL)) - return 1; - register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); return 0; Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/print.c Sat Oct 20 11:13:16 2012 (r1613) @@ -795,6 +795,7 @@ B("Foxconn", "6150K8MD-8EKRSH", OK, "http://www.foxconnchannel.com/ProductDetail.aspx?T=Motherboard&U=en-us00001…", NULL), B("Foxconn", "A6VMX", OK, "http://www.foxconnchannel.com/ProductDetail.aspx?T=Motherboard&U=en-us00003…", NULL), B("Foxconn", "P4M800P7MA-RS2", OK, "http://www.foxconnchannel.com/ProductDetail.aspx?T=Motherboard&U=en-us00001…", NULL), + B("Foxconn", "P55MX", OK, "http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us00004…", "Needs the MFG jumper to be set correctly before flashing to enable the Flash Descriptor Override Strap."), B("Freetech", "P6F91i", OK, "http://web.archive.org/web/20010417035034/http://www.freetech.com/prod/P6F9…", NULL), B("Foxconn", "Q45M", BAD, "http://www.foxconnchannel.com/ProductDetail.aspx?T=Motherboard&U=en-us00005…", "Probing works (Hardware sequencing, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Fujitsu-Siemens", "ESPRIMO P5915", OK, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/professionalpc/ESPRI…", "Mainboard model is D2312-A2."), Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Thu Oct 4 16:41:20 2012 (r1612) +++ trunk/serprog.c Sat Oct 20 11:13:16 2012 (r1613) @@ -877,8 +877,7 @@ unsigned char buf[4]; msg_pspew("%s usecs=%d\n", __func__, usecs); if (!sp_check_commandavail(S_CMD_O_DELAY)) { - msg_pdbg("Note: serprog_delay used, but the programmer doesn't " - "support delay\n"); + msg_pdbg2("serprog_delay used, but programmer doesn't support delays natively - emulating\n"); internal_delay(usecs); return; }

1 0

[PATCH] Rework extract_programmer_param to remove exit call
by Niklas Söderlund 19 Oct '12

19 Oct '12

- Utilise the reentrant strtok_r function to reduce complexity in extract_programmer_param. - Remove exit call in extract_programmer_param and introduce return code to indicate pass/fail. This pushes error handling to the caller. - Update all callers to do proper error handling. - Push checking of parameter key=value format checking to extract_programmer_param. Not all callers checked for this and this greatly reduces complexity at the caller. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- buspirate_spi.c | 16 +++----- chipset_enable.c | 14 +++---- dediprog.c | 5 +-- dummyflasher.c | 32 ++++++++-------- flash.h | 1 - flashrom.c | 110 ++++++++++++++++++++++++++----------------------------- ft2232_spi.c | 29 ++++++++------- ichspi.c | 56 ++++++++++++---------------- internal.c | 70 ++++++++++++++--------------------- it87spi.c | 5 +-- linux_spi.c | 9 ++--- ogp_spi.c | 8 ++-- pcidev.c | 6 +-- pony_spi.c | 31 +++++++--------- programmer.h | 3 +- rayer_spi.c | 12 +++--- serprog.c | 41 ++++++++------------- 17 files changed, 194 insertions(+), 254 deletions(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index 054b4ff..af37628 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -208,28 +208,22 @@ int buspirate_spi_init(void) int ret = 0; int i; - dev = extract_programmer_param("dev"); - if (dev && !strlen(dev)) { - free(dev); - dev = NULL; - } - if (!dev) { + if (extract_programmer_param("dev", &dev)) { msg_perr("No serial device given. Use flashrom -p buspirate_spi:dev=/dev/ttyUSB0\n"); return 1; } - speed = extract_programmer_param("spispeed"); - if (speed) { + if (!extract_programmer_param("spispeed", &speed)) { for (i = 0; spispeeds[i].name; i++) - if (!strncasecmp(spispeeds[i].name, speed, - strlen(spispeeds[i].name))) { + if (!strncasecmp(spispeeds[i].name, speed, strlen(spispeeds[i].name))) { spispeed = spispeeds[i].speed; break; } if (!spispeeds[i].name) msg_perr("Invalid SPI speed, using default.\n"); + + free(speed); } - free(speed); /* Default buffer size is 19: 16 bytes data, 3 bytes control. */ #define DEFAULT_BUFSIZE (16 + 3) diff --git a/chipset_enable.c b/chipset_enable.c index 0873b4e..bddf1c7 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -350,8 +350,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; - idsel = extract_programmer_param("fwh_idsel"); - if (idsel && strlen(idsel)) { + if (!extract_programmer_param("fwh_idsel", &idsel)) { uint64_t fwh_idsel_old, fwh_idsel; errno = 0; /* Base 16, nothing else makes sense. */ @@ -359,12 +358,14 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) if (errno) { msg_perr("Error: fwh_idsel= specified, but value could " "not be converted.\n"); - goto idsel_garbage_out; + free(idsel); + return ERROR_FATAL; } if (fwh_idsel & 0xffff000000000000ULL) { msg_perr("Error: fwh_idsel= specified, but value had " "unused bits set.\n"); - goto idsel_garbage_out; + free(idsel); + return ERROR_FATAL; } fwh_idsel_old = pci_read_long(dev, 0xd0); fwh_idsel_old <<= 16; @@ -375,13 +376,8 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff); rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ - } else if (idsel) { - msg_perr("Error: fwh_idsel= specified, but no value given.\n"); -idsel_garbage_out: free(idsel); - return ERROR_FATAL; } - free(idsel); /* Ignore all legacy ranges below 1 MB. * We currently only support flashing the chip which responds to diff --git a/dediprog.c b/dediprog.c index a81cf83..0986853 100644 --- a/dediprog.c +++ b/dediprog.c @@ -783,8 +783,7 @@ int dediprog_init(void) msg_pspew("%s\n", __func__); - voltage = extract_programmer_param("voltage"); - if (voltage) { + if (!extract_programmer_param("voltage", &voltage)) { millivolt = parse_voltage(voltage); free(voltage); if (millivolt < 0) @@ -821,7 +820,7 @@ int dediprog_init(void) return 1; } dediprog_endpoint = 2; - + if (register_shutdown(dediprog_shutdown, NULL)) return 1; diff --git a/dummyflasher.c b/dummyflasher.c index 655b678..580166e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -174,10 +174,14 @@ int dummy_init(void) msg_pspew("%s\n", __func__); - bustext = extract_programmer_param("bus"); - msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default"); - if (!bustext) + + if (!extract_programmer_param("bus", &bustext)) + msg_pdbg("Requested buses are: %s\n", bustext); + else { + msg_pdbg("Requested buses are: default\n"); bustext = strdup("parallel+lpc+fwh+spi"); + } + /* Convert the parameters to lowercase. */ tolower_string(bustext); @@ -202,8 +206,7 @@ int dummy_init(void) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); - tmp = extract_programmer_param("spi_write_256_chunksize"); - if (tmp) { + if (!extract_programmer_param("spi_write_256_chunksize", &tmp)) { spi_write_256_chunksize = atoi(tmp); free(tmp); if (spi_write_256_chunksize < 1) { @@ -212,8 +215,7 @@ int dummy_init(void) } } - tmp = extract_programmer_param("spi_blacklist"); - if (tmp) { + if (!extract_programmer_param("spi_blacklist", &tmp)) { i = strlen(tmp); if (!strncmp(tmp, "0x", 2)) { i -= 2; @@ -245,11 +247,10 @@ int dummy_init(void) for (i = 0; i < spi_blacklist_size; i++) msg_pdbg("%02x ", spi_blacklist[i]); msg_pdbg(", size %i\n", spi_blacklist_size); + free(tmp); } - free(tmp); - tmp = extract_programmer_param("spi_ignorelist"); - if (tmp) { + if (!extract_programmer_param("spi_ignorelist", &tmp)) { i = strlen(tmp); if (!strncmp(tmp, "0x", 2)) { i -= 2; @@ -281,12 +282,11 @@ int dummy_init(void) for (i = 0; i < spi_ignorelist_size; i++) msg_pdbg("%02x ", spi_ignorelist[i]); msg_pdbg(", size %i\n", spi_ignorelist_size); + free(tmp); } - free(tmp); #if EMULATE_CHIP - tmp = extract_programmer_param("emulate"); - if (!tmp) { + if (extract_programmer_param("emulate", &tmp)) { msg_pdbg("Not emulating any flash chip.\n"); /* Nothing else to do. */ goto dummy_init_out; @@ -358,8 +358,7 @@ int dummy_init(void) } #ifdef EMULATE_SPI_CHIP - status = extract_programmer_param("spi_status"); - if (status) { + if (!extract_programmer_param("spi_status", &status)) { char *endptr; errno = 0; emu_status = strtoul(status, &endptr, 0); @@ -377,8 +376,7 @@ int dummy_init(void) msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); memset(flashchip_contents, 0xff, emu_chip_size); - emu_persistent_image = extract_programmer_param("image"); - if (!emu_persistent_image) { + if (extract_programmer_param("image", &emu_persistent_image)) { /* Nothing else to do. */ goto dummy_init_out; } diff --git a/flash.h b/flash.h index 0bb6c2b..4bb2800 100644 --- a/flash.h +++ b/flash.h @@ -230,7 +230,6 @@ int read_flash_to_file(struct flashctx *flash, const char *filename); int min(int a, int b); int max(int a, int b); void tolower_string(char *str); -char *extract_param(char **haystack, const char *needle, const char *delim); int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); diff --git a/flashrom.c b/flashrom.c index a887e3b..6c3f93e 100644 --- a/flashrom.c +++ b/flashrom.c @@ -465,71 +465,65 @@ char *strcat_realloc(char *dest, const char *src) return dest; } -/* This is a somewhat hacked function similar in some ways to strtok(). - * It will look for needle with a subsequent '=' in haystack, return a copy of - * needle and remove everything from the first occurrence of needle to the next - * delimiter from haystack. - */ -char *extract_param(char **haystack, const char *needle, const char *delim) +static int extract_param(char *haystack, const char const *needle, char **value) { - char *param_pos, *opt_pos, *rest; - char *opt = NULL; - int optlen; - int needlelen; - - needlelen = strlen(needle); - if (!needlelen) { - msg_gerr("%s: empty needle! Please report a bug at " - "flashrom(a)flashrom.org\n", __func__); - return NULL; - } - /* No programmer parameters given. */ - if (*haystack == NULL) - return NULL; - param_pos = strstr(*haystack, needle); - do { - if (!param_pos) - return NULL; - /* Needle followed by '='? */ - if (param_pos[needlelen] == '=') { - - /* Beginning of the string? */ - if (param_pos == *haystack) - break; - /* After a delimiter? */ - if (strchr(delim, *(param_pos - 1))) - break; - } - /* Continue searching. */ - param_pos++; - param_pos = strstr(param_pos, needle); - } while (1); - - if (param_pos) { - /* Get the string after needle and '='. */ - opt_pos = param_pos + needlelen + 1; - optlen = strcspn(opt_pos, delim); - /* Return an empty string if the parameter was empty. */ - opt = malloc(optlen + 1); - if (!opt) { - msg_gerr("Out of memory!\n"); - exit(1); + char *pair, *pairptr; + char *keyptr, *tmp; + + pair = strtok_r(haystack, ",", &pairptr); + while (pair) { + tmp = strtok_r(pair, "=", &keyptr); + if (!strcmp(tmp, needle)) { + tmp = strtok_r(NULL, "=", &keyptr); + + if (!tmp) { + msg_perr("Missing argument for %s.\n", needle); + return 1; + } + + *value = strdup(tmp); + + if (!*value) { + msg_gerr("Out of memory!\n"); + return 1; + } + + return 0; } - strncpy(opt, opt_pos, optlen); - opt[optlen] = '\0'; - rest = opt_pos + optlen; - /* Skip all delimiters after the current parameter. */ - rest += strspn(rest, delim); - memmove(param_pos, rest, strlen(rest) + 1); - /* We could shrink haystack, but the effort is not worth it. */ + pair = strtok_r(NULL, ",", &pairptr); } - return opt; + return 1; } -char *extract_programmer_param(const char *param_name) +int extract_programmer_param(const char const *param_name, char **value) { - return extract_param(&programmer_param, param_name, ","); + char *scratch; + int ret; + + *value = NULL; + + if (!strlen(param_name)) { + msg_gerr("%s: no param name! Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } + + /* No programmer parameters given. */ + if (programmer_param == NULL) + return 1; + + /* Alloc scratch string */ + scratch = strdup(programmer_param); + if (!scratch) { + msg_gerr("Out of memory!\n"); + return 1; + } + + ret = extract_param(scratch, param_name, value); + + free(scratch); + + return ret; } /* Returns the number of well-defined erasers for a chip. */ diff --git a/ft2232_spi.c b/ft2232_spi.c index 31a6c5c..49efa69 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -184,8 +184,7 @@ int ft2232_spi_init(void) char *arg; double mpsse_clk; - arg = extract_programmer_param("type"); - if (arg) { + if (!extract_programmer_param("type", &arg)) { if (!strcasecmp(arg, "2232H")) { ft2232_type = FTDI_FT2232H_PID; channel_count = 2; @@ -243,11 +242,10 @@ int ft2232_spi_init(void) free(arg); return -1; } + free(arg); } - free(arg); - arg = extract_programmer_param("port"); - if (arg) { + if (!extract_programmer_param("port", &arg)) { switch (toupper((unsigned char)*arg)) { case 'A': ft2232_interface = INTERFACE_A; @@ -279,21 +277,20 @@ int ft2232_spi_init(void) } free(arg); - arg = extract_programmer_param("divisor"); - if (arg && strlen(arg)) { + if (!extract_programmer_param("divisor", &arg)) { unsigned int temp = 0; char *endptr; temp = strtoul(arg, &endptr, 10); if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" - "Valid are even values between 2 and 131072.\n", arg); + "Valid are even values between 2 and 131072.\n", arg); free(arg); return -2; } else { divisor = (uint32_t)temp; } + free(arg); } - free(arg); msg_pdbg("Using device type %s %s ", get_ft2232_vendorname(ft2232_vid, ft2232_type), @@ -312,12 +309,16 @@ int ft2232_spi_init(void) msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); } - arg = extract_programmer_param("serial"); - f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); - free(arg); + if (!extract_programmer_param("serial", &arg)) { + f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); + free(arg); - if (f < 0 && f != -5) { - msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); + if (f < 0 && f != -5) { + msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); + return -4; + } + } else { + msg_perr("No serial paramater specified.\n"); return -4; } diff --git a/ichspi.c b/ichspi.c index 8dd1893..61f63b3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1627,43 +1627,33 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, break; case CHIPSET_ICH8: default: /* Future version might behave the same */ - arg = extract_programmer_param("ich_spi_mode"); - if (arg && !strcmp(arg, "hwseq")) { - ich_spi_mode = ich_hwseq; - msg_pspew("user selected hwseq\n"); - } else if (arg && !strcmp(arg, "swseq")) { - ich_spi_mode = ich_swseq; - msg_pspew("user selected swseq\n"); - } else if (arg && !strcmp(arg, "auto")) { - msg_pspew("user selected auto\n"); - ich_spi_mode = ich_auto; - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for ich_spi_mode.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for ich_spi_mode: %s\n", - arg); + if (!extract_programmer_param("ich_spi_mode", &arg)) { + if (!strcmp(arg, "hwseq")) + ich_spi_mode = ich_hwseq; + else if (!strcmp(arg, "swseq")) + ich_spi_mode = ich_swseq; + else if (!strcmp(arg, "auto")) + ich_spi_mode = ich_auto; + else { + msg_perr("Unknown argument for ich_spi_mode: %s\n", arg); + free(arg); + return ERROR_FATAL; + } + msg_pspew("user selected %s\n", arg); free(arg); - return ERROR_FATAL; } - free(arg); - - arg = extract_programmer_param("ich_spi_force"); - if (arg && !strcmp(arg, "yes")) { - ich_spi_force = 1; - msg_pspew("ich_spi_force enabled.\n"); - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for ich_spi_force.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for ich_spi_force: \"%s\" " - "(not \"yes\").\n", arg); + + if (!extract_programmer_param("ich_spi_force", &arg)) { + if (!strcmp(arg, "yes")) { + ich_spi_force = 1; + msg_pspew("ich_spi_force enabled.\n"); + } else { + msg_perr("Unknown argument for ich_spi_force: \"%s\" (not \"yes\").\n", arg); + free(arg); + return ERROR_FATAL; + } free(arg); - return ERROR_FATAL; } - free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); diff --git a/internal.c b/internal.c index eda4d59..80bb794 100644 --- a/internal.c +++ b/internal.c @@ -176,62 +176,48 @@ int internal_init(void) const char *cb_model = NULL; char *arg; - arg = extract_programmer_param("boardenable"); - if (arg && !strcmp(arg,"force")) { - force_boardenable = 1; - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for boardenable.\n"); - free(arg); - return 1; - } else if (arg) { - msg_perr("Unknown argument for boardenable: %s\n", arg); + if (!extract_programmer_param("boardenable", &arg)) { + if (!strcmp(arg,"force")) { + force_boardenable = 1; + } else { + msg_perr("Unknown argument for boardenable: %s\n", arg); + free(arg); + return 1; + } free(arg); - return 1; } - free(arg); - arg = extract_programmer_param("boardmismatch"); - if (arg && !strcmp(arg,"force")) { - force_boardmismatch = 1; - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for boardmismatch.\n"); - free(arg); - return 1; - } else if (arg) { - msg_perr("Unknown argument for boardmismatch: %s\n", arg); + if (!extract_programmer_param("boardmismatch", &arg)) { + if (!strcmp(arg,"force")) { + force_boardmismatch = 1; + } else { + msg_perr("Unknown argument for boardmismatch: %s\n", arg); + free(arg); + return 1; + } free(arg); - return 1; } - free(arg); - - arg = extract_programmer_param("laptop"); - if (arg && !strcmp(arg, "force_I_want_a_brick")) - force_laptop = 1; - else if (arg && !strcmp(arg, "this_is_not_a_laptop")) - not_a_laptop = 1; - else if (arg && !strlen(arg)) { - msg_perr("Missing argument for laptop.\n"); - free(arg); - return 1; - } else if (arg) { - msg_perr("Unknown argument for laptop: %s\n", arg); + + if (!extract_programmer_param("laptop", &arg)) { + if (!strcmp(arg, "force_I_want_a_brick")) + force_laptop = 1; + else if (!strcmp(arg, "this_is_not_a_laptop")) + not_a_laptop = 1; + else { + msg_perr("Unknown argument for laptop: %s\n", arg); + free(arg); + return 1; + } free(arg); - return 1; } - free(arg); - arg = extract_programmer_param("mainboard"); - if (arg && strlen(arg)) { + if (!extract_programmer_param("mainboard", &arg)) { if (board_parse_parameter(arg, &board_vendor, &board_model)) { free(arg); return 1; } - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for mainboard.\n"); free(arg); - return 1; } - free(arg); if (rget_io_perms()) return 1; diff --git a/it87spi.c b/it87spi.c index a35ddc0..a85d37b 100644 --- a/it87spi.c +++ b/it87spi.c @@ -166,8 +166,7 @@ static uint16_t it87spi_probe(uint16_t port) flashport |= sio_read(port, 0x65); msg_pdbg("Serial flash port 0x%04x\n", flashport); /* Non-default port requested? */ - portpos = extract_programmer_param("it87spiport"); - if (portpos) { + if (!extract_programmer_param("it87spiport", &portpos)) { char *endptr = NULL; unsigned long forced_flashport; forced_flashport = strtoul(portpos, &endptr, 0); @@ -192,8 +191,8 @@ static uint16_t it87spi_probe(uint16_t port) sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); } + free(portpos); } - free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; if (internal_buses_supported & BUS_SPI) diff --git a/linux_spi.c b/linux_spi.c index 2f46463..2221ba0 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -66,15 +66,12 @@ int linux_spi_init(void) const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; - dev = extract_programmer_param("dev"); - if (!dev || !strlen(dev)) { - msg_perr("No SPI device given. Use flashrom -p " - "linux_spi:dev=/dev/spidevX.Y\n"); + if (extract_programmer_param("dev", &dev)) { + msg_perr("No SPI device given. Use flashrom -p linux_spi:dev=/dev/spidevX.Y\n"); return 1; } - p = extract_programmer_param("speed"); - if (p && strlen(p)) { + if (!extract_programmer_param("speed", &p)) { speed = (uint32_t)strtoul(p, &endp, 10) * 1024; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); diff --git a/ogp_spi.c b/ogp_spi.c index 25550b5..9b596bf 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -109,13 +109,13 @@ int ogp_spi_init(void) { char *type; - type = extract_programmer_param("rom"); - - if (!type) { + if (extract_programmer_param("rom", &type)) { msg_perr("Please use flashrom -p ogp_spi:rom=... to specify " "which flashchip you want to access.\n"); return 1; - } else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) { + } + + if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) { ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL; ogp_reg_siso = OGA1_XP10_BPROM_SI; ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR; diff --git a/pcidev.c b/pcidev.c index f2cbbac..37319c9 100644 --- a/pcidev.c +++ b/pcidev.c @@ -170,14 +170,14 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) pci_filter_init(pacc, &filter); /* Filter by bb:dd.f (if supplied by the user). */ - pcidev_bdf = extract_programmer_param("pci"); - if (pcidev_bdf != NULL) { + if (!extract_programmer_param("pci", &pcidev_bdf)) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { msg_perr("Error: %s\n", msg); + free(pcidev_bdf); return 0; } + free(pcidev_bdf); } - free(pcidev_bdf); for (dev = pacc->devices; dev; dev = dev->next) { if (pci_filter_match(&filter, dev)) { diff --git a/pony_spi.c b/pony_spi.c index 7875200..7b9e72e 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -113,16 +113,15 @@ int pony_spi_init(void) int have_prog = 0; /* The parameter is in format "dev=/dev/device,type=serbang" */ - arg = extract_programmer_param("dev"); - if (arg && strlen(arg)) { + if (!extract_programmer_param("dev", &arg)) { sp_fd = sp_openserport(arg, 9600); if (sp_fd < 0) { free(arg); return 1; } have_device++; + free(arg); } - free(arg); if (!have_device) { msg_perr("Error: No valid device specified.\n" @@ -130,22 +129,20 @@ int pony_spi_init(void) return 1; } - arg = extract_programmer_param("type"); - if (arg && !strcasecmp(arg, "serbang")) { - type = TYPE_SERBANG; - } else if (arg && !strcasecmp(arg, "si_prog")) { - type = TYPE_SI_PROG; - } else if (arg && !strcasecmp( arg, "ajawe")) { - type = TYPE_AJAWE; - } else if (arg && !strlen(arg)) { - msg_perr("Error: Missing argument for programmer type.\n"); - free(arg); - } else if (arg){ - msg_perr("Error: Invalid programmer type specified.\n"); + if (!extract_programmer_param("type", &arg)) { + if (!strcasecmp(arg, "serbang")) { + type = TYPE_SERBANG; + } else if (!strcasecmp(arg, "si_prog")) { + type = TYPE_SI_PROG; + } else if (!strcasecmp(arg, "ajawe")) { + type = TYPE_AJAWE; + } else { + msg_perr("Error: Invalid programmer type specified.\n"); + free(arg); + return 1; + } free(arg); - return 1; } - free(arg); /* * Configure the serial port pins, depending on the used programmer. diff --git a/programmer.h b/programmer.h index dedec67..93c3f93 100644 --- a/programmer.h +++ b/programmer.h @@ -475,7 +475,8 @@ extern int programmer_may_write; extern unsigned long flashbase; void check_chip_supported(const struct flashchip *chip); int check_max_decode(enum chipbustype buses, uint32_t size); -char *extract_programmer_param(const char *param_name); +int extract_programmer_param(const char const *param_name, char **value); + /* spi.c */ enum spi_controller { diff --git a/rayer_spi.c b/rayer_spi.c index b312610..4fbf55a 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -103,8 +103,7 @@ int rayer_spi_init(void) enum rayer_type rayer_type = TYPE_RAYER; /* Non-default port requested? */ - arg = extract_programmer_param("iobase"); - if (arg) { + if (!extract_programmer_param("iobase", &arg)) { char *endptr = NULL; unsigned long tmp; tmp = strtoul(arg, &endptr, 0); @@ -127,17 +126,16 @@ int rayer_spi_init(void) msg_pinfo("Non-default I/O base requested. This will " "not change the hardware settings.\n"); } + free(arg); } else { /* Pick a default value for the I/O base. */ lpt_iobase = 0x378; } - free(arg); - + msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n", lpt_iobase); - arg = extract_programmer_param("type"); - if (arg) { + if (!extract_programmer_param("type", &arg)) { if (!strcasecmp(arg, "rayer")) { rayer_type = TYPE_RAYER; } else if (!strcasecmp(arg, "xilinx")) { @@ -147,8 +145,8 @@ int rayer_spi_init(void) free(arg); return 1; } + free(arg); } - free(arg); switch (rayer_type) { case TYPE_RAYER: msg_pdbg("Using RayeR SPIPGM pinout.\n"); diff --git a/serprog.c b/serprog.c index b179ea4..2ccc0ed 100644 --- a/serprog.c +++ b/serprog.c @@ -379,8 +379,7 @@ int serprog_init(void) int have_device = 0; /* the parameter is either of format "dev=/dev/device:baud" or "ip=ip:port" */ - device = extract_programmer_param("dev"); - if (device && strlen(device)) { + if (!extract_programmer_param("dev", &device)) { baudport = strstr(device, ":"); if (baudport) { /* Split device from baudrate. */ @@ -401,23 +400,20 @@ int serprog_init(void) } have_device++; } - } - if (device && !strlen(device)) { - msg_perr("Error: No device specified.\n" - "Use flashrom -p serprog:dev=/dev/device:baud\n"); - free(device); - return 1; - } - free(device); - device = extract_programmer_param("ip"); - if (have_device && device) { - msg_perr("Error: Both host and device specified.\n" - "Please use either dev= or ip= but not both.\n"); free(device); - return 1; } - if (device && strlen(device)) { + + + if (!extract_programmer_param("ip", &device)) { + + if (have_device) { + msg_perr("Error: Both host and device specified.\n" + "Please use either dev= or ip= but not both.\n"); + free(device); + return 1; + } + baudport = strstr(device, ":"); if (baudport) { /* Split host from port. */ @@ -438,14 +434,9 @@ int serprog_init(void) } have_device++; } - } - if (device && !strlen(device)) { - msg_perr("Error: No host specified.\n" - "Use flashrom -p serprog:ip=ipaddr:port\n"); + free(device); - return 1; } - free(device); if (!have_device) { msg_perr("Error: Neither host nor device specified.\n" @@ -535,8 +526,7 @@ int serprog_init(void) spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } - spispeed = extract_programmer_param("spispeed"); - if (spispeed && strlen(spispeed)) { + if (!extract_programmer_param("spispeed", &spispeed)) { uint32_t f_spi_req, f_spi; uint8_t buf[4]; char *f_spi_suffix; @@ -578,8 +568,9 @@ int serprog_init(void) "It was actually set to %u Hz\n", f_spi_req, f_spi); } else msg_pdbg(MSGHEADER "Setting SPI clock rate to %u Hz failed!\n", f_spi_req); + + free(spispeed); } - free(spispeed); bt = serprog_buses_supported; if (sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL)) return 1; -- 1.7.12.3

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Re: [flashrom] NEED help for programing the EEPROM on intel NIC 9400PT
by Idwer Vollering 16 Oct '12

16 Oct '12

2012/10/16 zz z <ennory(a)gmail.com>: > Hello flashrom's developers: > > I want to save my ethernet adapter. > > I have an Intel 9400PT nic, the controller is 82572EI which was on your > supported list, but the PCI ID is not match, mine is 8086-107D, and your > list show 8086-10B9.And these two NIC is totally identical in hardware, just > different eeprom contents. > > My problem is I used "eeupdate" clear the PCI Vendor ID to 0000 by my > mistake. Now the PCI device id is 0000-107D. > > As the result BIOS & OS can't recognise it at all, even eeupdate itself ! > But some software (like AIDA64 ) can recognise it as a unknown device which > pci vendor id is 0000. > So I google that flashrom can help me ,(I have the original eep file.) I > download it and run it in DOS. I used command "flashrom -w 9400pt.eep -p > -nicintel_spi", then flashrom told me: >> >> Calibrating delay loop... OK. >> No EEPROM/flash device found. >> Note: flashrom can never write if the flash chip isn't found >> automatically. > > > So I need help how to using flashrom to program the eeprom on NIC. And can > flashrom use SMBUS address to flash?(I know the SMBUS address of this NIC.) http://blog.vodkamelone.de/archives/146-Unbricking-an-Intel-Pro1000-e1000-n… > > > Thanks a lot. > yours sincerely > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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NEED help for programing the EEPROM on intel NIC 9400PT
by zz z 16 Oct '12

16 Oct '12

Hello flashrom's developers: I want to save my ethernet adapter. I have an Intel 9400PT nic, the controller is 82572EI which was on your supported list, but the PCI ID is not match, mine is 8086-107D, and your list show 8086-10B9.And these two NIC is totally identical in hardware, just different eeprom contents. My problem is I used "eeupdate" clear the PCI Vendor ID to 0000 by my mistake. Now the PCI device id is 0000-107D. As the result BIOS & OS can't recognise it at all, even eeupdate itself ! But some software (like AIDA64 ) can recognise it as a unknown device which pci vendor id is 0000. So I google that flashrom can help me ,(I have the original eep file.) I download it and run it in DOS. I used command "flashrom -w 9400pt.eep -p -nicintel_spi", then flashrom told me: * > > Calibrating delay loop... OK. > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found automatically. * So I need help how to using flashrom to program the eeprom on NIC. And can flashrom use SMBUS address to flash?(I know the SMBUS address of this NIC.) Thanks a lot. yours sincerely

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Re: [flashrom] [PATCH 0/5] check_trans and probe_spi_rdid_edi
by Carl-Daniel Hailfinger 16 Oct '12

16 Oct '12

Am 03.10.2012 06:13 schrieb Stefan Tauner: > This patch set enables us to figure out if transactions will succeed > without executing them, which allows for a refactoring of > probe_spi_rdid_generic() which in consequence makes it possible to add > probe_spi_rdid_edi(). I think this is a good idea. Review below and in each individual patch. > The infrastructure code as a whole, but especially the ichspi code > is heavily modified. Please be aware of that if you test it on > mainboards. > > Stefan Tauner (5): > Refactor ichspi and prepare it for check_trans(). > Prepare wbsio_spi.c for check_trans(). > Introduce check_trans(). > Generify probe_spi_rdid_generic() and add probe_spi_rdid_edi(). > Let the dummy programmer emulate SPI payload limitations. > > This is the output of the dummy programmer to show the new behavior: > > flashrom v0.9.6.1-r1611 on Linux 3.2.0-31-generic (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian > Command line (3 args): ./flashrom -p dummy:bus=SPI,spi_prog=wbsio,emulate=M25P10.RES -V > Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 10 us, 100 myus = 127 us, 1000 myus = 1023 us, 10000 myus = 10024 us, 4 myus = 10 us, OK. > Initializing dummy programmer > Requested buses are: SPI > Enabling support for SPI flash. > Emulating ST M25P10.RES SPI flash chip (RES, page write) > Using SPI payload limitations of the wbsio programmer. > Filling fake flash chip with 0xff, size 131072 > The following protocols are supported: SPI. > Probing for AMIC A25L05PT, 64 kB: 3 byte RDID not supported on this SPI controller. This should have been "4 byte RDID..." > Probing for AMIC A25L05PU, 64 kB: 3 byte RDID not supported on this SPI controller. > [...] > Probing for Spansion S25FL064A, 8192 kB: 3 byte RDID not supported on this SPI controller. > Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x10, id2 0x10 > Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x10, id2 0x10 > Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xff, id2 0xff > Probing for SST SST25VF016B, 2048 kB: 3 byte RDID not supported on this SPI controller. > Probing for SST SST25VF032B, 4096 kB: 3 byte RDID not supported on this SPI controller. > Probing for SST SST25VF064C, 8192 kB: 3 byte RDID not supported on this SPI controller. > Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xff, id2 0xff > Probing for SST SST25VF040B, 512 kB: 3 byte RDID not supported on this SPI controller. > Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff > Probing for SST SST25VF080B, 1024 kB: 3 byte RDID not supported on this SPI controller. > [...] > Probing for ST M25P05-A, 64 kB: 3 byte RDID not supported on this SPI controller. > Probing for ST M25P05, 64 kB: probe_spi_res1: id 0x10 > Chip status register is 00 > Found ST flash chip "M25P05" (64 kB, SPI) on dummy. > Probing for ST M25P10-A, 128 kB: 3 byte RDID not supported on this SPI controller. > Probing for ST M25P10, 128 kB: probe_spi_res1: id 0x10 > Chip status register is 00 > Found ST flash chip "M25P10" (128 kB, SPI) on dummy. > Probing for ST M25P20, 256 kB: 3 byte RDID not supported on this SPI controller. > Probing for ST M25P40, 512 kB: 3 byte RDID not supported on this SPI controller. > Probing for ST M25P40-old, 512 kB: probe_spi_res1: id 0x10 > Probing for ST M25P80, 1024 kB: 3 byte RDID not supported on this SPI controller. > [...] > Probing for Winbond W25X64, 8192 kB: 3 byte RDID not supported on this SPI controller. > Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. > Probing for AMIC unknown AMIC SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. > [...] > Probing for Generic unknown SPI chip (RDID), 0 kB: 3 byte RDID not supported on this SPI controller. > Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff > Multiple flash chips were detected: "M25P05", "M25P10" > Please specify which chip to use with the -c <chipname> option. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 2/5] Prepare wbsio_spi.c for check_trans().
by Carl-Daniel Hailfinger 15 Oct '12

15 Oct '12

Am 03.10.2012 06:13 schrieb Stefan Tauner: > Introduce determine_mode() which contains the extracted bits of the init > function that do sanity checks but without altering the hardware state. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> I see that you took great care to avoid the pitfalls in converting that code. Good! Side note: That hardware is just awful from a capability/interface perspective. If I had a way to drive it by bitbanging, I'd do that instantly. However, the two of the four essential SPI lines (MOSI and MISO) are not usable as GPIO, so that way of working around hardware limitations is not going to work. > --- > wbsio_spi.c | 136 +++++++++++++++++++++++++++++++++-------------------------- > 1 file changed, 77 insertions(+), 59 deletions(-) > > diff --git a/wbsio_spi.c b/wbsio_spi.c > index 7d4bb2a..778b983 100644 > --- a/wbsio_spi.c > +++ b/wbsio_spi.c > @@ -61,6 +61,53 @@ done: > return flashport; > } > > +/* W83627DHG has 11 command modes: > + * 1=1 command only > + * 2=1 command+1 data write > + * 3=1 command+2 data read > + * 4=1 command+3 address > + * 5=1 command+3 address+1 data write > + * 6=1 command+3 address+4 data write > + * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read > + * 8=1 command+3 address+1 data read > + * 9=1 command+3 address+2 data read > + * a=1 command+3 address+3 data read > + * b=1 command+3 address+4 data read > + * > + * mode[7:4] holds the command mode > + * mode[3:0] holds SPI address bits [19:16] > + * > + * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\ > + * Would one more byte of RAM in the chip (to get all 24 bits) really make > + * such a big difference? > + */ > +static uint8_t determine_mode(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, > + const unsigned char *writearr) > +{ > + if (1 == writecnt && 0 == readcnt) { > + return 0x10; > + } else if (2 == writecnt && 0 == readcnt) { > + return 0x20; > + } else if (1 == writecnt && 2 == readcnt) { > + return 0x30; > + } else if (4 == writecnt && 0 == readcnt) { > + return 0x40 | (writearr[1] & 0x0f); Would it be possible to return only 0x40 here, and add the low nibble of writearr[1] inside wbsio_send_command? That low nibble is not part of the mode, it just happens to be stored in the same hw register for some modes. Same for other cases. > + } else if (5 == writecnt && 0 == readcnt) { > + return 0x50 | (writearr[1] & 0x0f); > + } else if (8 == writecnt && 0 == readcnt) { > + return 0x60 | (writearr[1] & 0x0f); > + } else if (5 == writecnt && 4 == readcnt) { > + /* XXX: TODO not supported by flashrom infrastructure! > + * This mode, 7, discards the fifth byte in writecnt, > + * but since we can not express that in flashrom, fail > + * the operation for now. > + */; > + } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { > + return ((7 + readcnt) << 4) | (writearr[1] & 0x0f); > + } > + return 0; > +} > + > static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, > unsigned int readcnt, > const unsigned char *writearr, > @@ -95,52 +142,37 @@ int wbsio_check_for_spi(void) > return 0; > } > > -/* W83627DHG has 11 command modes: > - * 1=1 command only > - * 2=1 command+1 data write > - * 3=1 command+2 data read > - * 4=1 command+3 address > - * 5=1 command+3 address+1 data write > - * 6=1 command+3 address+4 data write > - * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read > - * 8=1 command+3 address+1 data read > - * 9=1 command+3 address+2 data read > - * a=1 command+3 address+3 data read > - * b=1 command+3 address+4 data read > - * > - * mode[7:4] holds the command mode > - * mode[3:0] holds SPI address bits [19:16] > - * > - * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\ > - * Would one more byte of RAM in the chip (to get all 24 bits) really make > - * such a big difference? > - */ > static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, > unsigned int readcnt, > const unsigned char *writearr, > unsigned char *readarr) > { > int i; > - uint8_t mode = 0; > + uint8_t mode = determine_mode(flash, writecnt, readcnt, writearr); > > - msg_pspew("%s:", __func__); > + if (!mode) { > + msg_perr("%s: unsupported command type wr=%d rd=%d\n", > + __func__, writecnt, readcnt); > + /* Command type refers to the number of bytes read/written. */ > + return SPI_INVALID_LENGTH; > + } > > - if (1 == writecnt && 0 == readcnt) { > - mode = 0x10; > - } else if (2 == writecnt && 0 == readcnt) { > + msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); > + switch (mode & 0xF0) { That masking would become unnecessary. > + case 0x10: break; > + case 0x20: > OUTB(writearr[1], wbsio_spibase + 4); > msg_pspew(" data=0x%02x", writearr[1]); > - mode = 0x20; > - } else if (1 == writecnt && 2 == readcnt) { > - mode = 0x30; > - } else if (4 == writecnt && 0 == readcnt) { > + break; > + case 0x30: break; > + case 0x40: > msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); > for (i = 2; i < writecnt; i++) { > OUTB(writearr[i], wbsio_spibase + i); > msg_pspew("%02x", writearr[i]); > } > - mode = 0x40 | (writearr[1] & 0x0f); And here you could use mode |= (writearr[1] & 0x0f); Same for other cases where mode >= 0x40. > - } else if (5 == writecnt && 0 == readcnt) { > + break; > + case 0x50: > msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); > for (i = 2; i < 4; i++) { > OUTB(writearr[i], wbsio_spibase + i); > @@ -148,8 +180,8 @@ static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, > } > OUTB(writearr[i], wbsio_spibase + i); > msg_pspew(" data=0x%02x", writearr[i]); > - mode = 0x50 | (writearr[1] & 0x0f); > - } else if (8 == writecnt && 0 == readcnt) { > + break; > + case 0x60: > msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); > for (i = 2; i < 4; i++) { > OUTB(writearr[i], wbsio_spibase + i); > @@ -160,44 +192,30 @@ static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, > OUTB(writearr[i], wbsio_spibase + i); > msg_pspew("%02x", writearr[i]); > } > - mode = 0x60 | (writearr[1] & 0x0f); > - } else if (5 == writecnt && 4 == readcnt) { > - /* XXX: TODO not supported by flashrom infrastructure! > - * This mode, 7, discards the fifth byte in writecnt, > - * but since we can not express that in flashrom, fail > - * the operation for now. > - */ > - ; > - } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { > + break; > + case 0x70: /* unimplemented */ > + break; > + default: > msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); > for (i = 2; i < writecnt; i++) { > OUTB(writearr[i], wbsio_spibase + i); > msg_pspew("%02x", writearr[i]); > } > - mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); > - } > - msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); > - > - if (!mode) { > - msg_perr("%s: unsupported command type wr=%d rd=%d\n", > - __func__, writecnt, readcnt); > - /* Command type refers to the number of bytes read/written. */ > - return SPI_INVALID_LENGTH; > + break; > } > > OUTB(writearr[0], wbsio_spibase); > OUTB(mode, wbsio_spibase + 1); > programmer_delay(10); Side note: I have absolutely no idea why this programmer_delay() is here. It seems to be pointless... unless the hardware is even more broken than I thought. No need to change it, I just wanted to point it out. > > - if (!readcnt) > - return 0; > - > - msg_pspew("%s: returning data =", __func__); > - for (i = 0; i < readcnt; i++) { > - readarr[i] = INB(wbsio_spibase + 4 + i); > - msg_pspew(" 0x%02x", readarr[i]); > + if (readcnt > 0) { > + msg_pspew("%s: returning data =", __func__); > + for (i = 0; i < readcnt; i++) { > + readarr[i] = INB(wbsio_spibase + 4 + i); > + msg_pspew(" 0x%02x", readarr[i]); > + } > + msg_pspew("\n"); > } > - msg_pspew("\n"); > return 0; > } > I don't see the point of this last hunk. Except for additional indentation and an elimination of an early return, the code stays the same. IMHO the early return is more readable, but I guess code readability is in the eye of the beholder. I don't care that much either way, it's your choice. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 5/5] Let the dummy programmer emulate SPI payload limitations.
by Carl-Daniel Hailfinger 15 Oct '12

15 Oct '12

Am 03.10.2012 06:13 schrieb Stefan Tauner: > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -119,7 +119,7 @@ static uint32_t dummy_chip_readl(const struct flashctx *flash, > static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, > const chipaddr addr, size_t len); > > -static const struct spi_programmer spi_programmer_dummyflasher = { > +static struct spi_programmer spi_programmer_dummyflasher = { > .type = SPI_CONTROLLER_DUMMY, > .max_data_read = MAX_DATA_READ_UNLIMITED, > .max_data_write = MAX_DATA_UNSPECIFIED, > @@ -373,6 +373,19 @@ int dummy_init(void) > msg_pdbg("Initial status register is set to 0x%02x.\n", > emu_status); > } > + tmp = extract_programmer_param("spi_prog"); > + if (tmp) { > + if (!strcmp(tmp, "wbsio")) { > + spi_programmer_dummyflasher.check_trans = wbsio_spi_check_trans; This will cause compile failures if CONFIG_INTERNAL=no A similar #ifdef guard is needed for the programmer.h chunk unless we decide that it's ok to have prototypes for unavailable functions. > + msg_pdbg("Using SPI payload limitations of the %s programmer.\n", tmp); > + } else { > + msg_perr("Error: emulation of a programmer requested, " > + "but the programmer could not be parsed \"%s\".\n", tmp); > + free(tmp); > + return 1; > + } > + } > + free(tmp); > #endif > > msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 4/5] Generify probe_spi_rdid_generic() and add probe_spi_rdid_edi().
by Antonio Ospite 15 Oct '12

15 Oct '12

On Wed, 3 Oct 2012 06:13:04 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Previously the "generic" function was working/used for exactly two > cases, namely for manufacturer IDs with 0 or 1 continuation bytes. > For this behavior it was overly complicated. > > The new implementation handles up to 3 continuation bytes > automatically and allows for up to 4 model bytes which is directly > used to add support for an EDI probing function. The probe_spi_rdid4() > function is removed because it is no longer needed. > > The new probe_spi_rdid_generic() tries to figure out the maximum > allowed read size by using the recently added check_trans() function > to reduce the request size if necessary. While this does not make > detection to succeed in all theoretical situations, it improves the > code and will hopefully work in all realworld situations. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flashchips.c | 24 +++++++-------- > flashchips.h | 2 +- > spi25.c | 97 ++++++++++++++++++++++++++++++---------------------------- > 3 files changed, 63 insertions(+), 60 deletions(-) > A fixup like this is needed for probe_spi_rdid_edi() to be usable: diff --git a/chipdrivers.h b/chipdrivers.h index 1ef4959..b754076 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,7 +34,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int /* spi25.c */ int probe_spi_rdid(struct flashctx *flash); -int probe_spi_rdid4(struct flashctx *flash); +int probe_spi_rdid_edi(struct flashctx *flash); int probe_spi_rems(struct flashctx *flash); int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); -- Antonio Ospite http://ao2.it A: Because it messes up the order in which people normally read text. See http://en.wikipedia.org/wiki/Posting_style Q: Why is top-posting such a bad thing?

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[RFC, PATCH] Add read support for the Spansion S25FL129P flash chip
by Antonio Ospite 15 Oct '12

15 Oct '12

http://www.spansion.com/Support/Datasheets/S25FL129P_00.pdf http://www.spansion.com/Support/Application%20Notes/S25FL129P_Prog_Guide_AN… Signed-off-by: Antonio Ospite <ospite(a)studenti.unina.it> --- Hi, I was able to read the content of the flash chip in the subject with the patch below but I am not sure if the patch is correct and ready for submission, could someone please check with the datasheet? I know very little about flash chips. Moreover from the Datasheet (Table 9.2, page 34) I see that this chip comes in two variants, one with 64K sectors and one with 256KB sectors, and some "Extended Device Identification" is used to identify the right variant, I don't know if flashrom supports reading such information. I see that somewhere else that is supported: http://old.nabble.com/-PATCH--m25p80:-Add-Spansion-S25FL129P-serial-flashes… I didn't feel like testing erase/write either as the connection to the chip was/is quite unreliable, I just needed to get a rootfs off from it once (it's some embedded router). If anyone can suggest some really cheap place where to get test clips or probes in Italy (or even better feels like donating some), I might risk testing erase/write after we solve the issue about the chip variant. BTW the output after the patch: $ sudo ./flashrom -p ft2232_spi:type=tumpa,port=B -r flash.bin flashrom v0.9.6.1-r1599 on Linux 3.6.0-rc5-ao2 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Spansion flash chip "S25FL129P" (16384 kB, SPI) on ft2232_spi. Reading flash... done. Thanks, Antonio Ospite http://ao2.it flashchips.c | 28 ++++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 29 insertions(+) diff --git a/flashchips.c b/flashchips.c index a6c2004..ced6ad0 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6288,6 +6288,34 @@ const struct flashchip flashchips[] = { }, { + .vendor = "Spansion", + .name = "S25FL129P", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL129P, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { .vendor = "SST", .name = "SST25LF040A", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 8e51d35..d13773d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -480,6 +480,7 @@ #define SPANSION_S25FL016A 0x0214 #define SPANSION_S25FL032A 0x0215 #define SPANSION_S25FL064A 0x0216 +#define SPANSION_S25FL129P 0x2018 /* * SST25 chips are SPI, first byte of device ID is memory type, second -- 1.7.10.4

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Re: [flashrom] add Numonyx/Micron N25Q128
by Stefan Tauner 15 Oct '12

15 Oct '12

On Sat, 9 Jun 2012 14:51:15 +0200 frederic.temporelli(a)bull.net wrote: > Hello > > > Numonyx/Micron N25Q128 is used on new X9 motherboards from Supermicro (X9DRT, ...) > > Specs are availbale on Micron WWW site: > http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/S… > > Following patch add this chip to flashrom. Probe is OK. > Due to Manageability Engine, some work is required before being able to test READ/ERASE/WRITE... > > ================================================================================= > Signed-off-by: Frederic Temporelli <frederic.temporelli(a)bull.net> > > diff -urN flashrom-0.9.5.2-r1540/flashchips.c flashrom-0.9.5.2-r1540-n25q128/flashchips.c > --- flashrom-0.9.5.2-r1540/flashchips.c 2012-05-20 23:32:32.000000000 +0000 > +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.c 2012-06-09 14:41:07.064141076 +0000 > @@ -5453,6 +5453,37 @@ > }, > > { > + .vendor = "Numonyx", > + .name = "N25Q128", > + .bustype = BUS_SPI, > + .manufacture_id = ST_ID, > + .model_id = ST_N25Q128, > + .total_size = 16384, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_OK_PROBE, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {4 * 1024, 4096 } }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 256} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { {16 * 1024 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .unlock = spi_disable_blockprotect, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + }, > + > + > + { > .vendor = "PMC", > .name = "Pm25LV010", > .bustype = BUS_SPI, > diff -urN flashrom-0.9.5.2-r1540/flashchips.h flashrom-0.9.5.2-r1540-n25q128/flashchips.h > --- flashrom-0.9.5.2-r1540/flashchips.h 2012-05-14 01:51:46.000000000 +0000 > +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.h 2012-06-08 20:46:47.225385676 +0000 > @@ -587,6 +587,7 @@ > #define ST_M29W040B 0xE3 > #define ST_M29W512B 0x27 > #define ST_N25Q064 0xBA17 > +#define ST_N25Q128 0xBA18 /* also Numonyx N25Q128 */ > > #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ > #define MVC_V29C51000T 0x00 > ================================================================================= hello and thanks for your patch! this chip is a bit complicated and we cant merge the patch as it is. they have used the same plane RDID for multiple variants of the chip. some attributes are not important for flashrom and can be ignored, but some are very important, namely the boot sector layout. quote from p.52: > The N25Q128 is available in the following architecture versions: > Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with 16 > subsectors), > Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 subsectors) > Uniform version, 64 KB uniform sectors without any boot sectors and subsectors. the good news is that this differences can be detected by an extended RDID command in its 5th byte (1 manufacturer, 2 device, 1 length of the following extended data, the first EDID byte we want), see table 15. of this 5th byte we need to look at the first two bits to determine the architecture, see table 16. our current infrastructure (probe_spi_rdid_generic) cant handle that, but should... so we will plan a change, but please dont expect it to happen too soon. the bad news is that i am not even sure if the subsector erase commands work as flashrom expects. flashrom wants to use the same erase opcode for the hole address space, even for non-uniform layouts. this usually works fine, but afaics it is not specified in the datasheet what happens if one uses the subsector erase opcode on a non-subsector *on devices that actually have subsectors* (the emphasis stems from the fact that it *is* defined, that the subsector erase command is ignore by the uniform model: "Any Subsector Erase (SSE) instruction in devices with uniform architecture (meaning no boot sectors with subsectors) is rejected without having any effects on the device." (p. 98). other interesting bits of this chips: - bit#5 of the status register "is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array" - a flag status register that gives more info than the "legacy spi status register" - a non-volatile configuration register to configure dummy clock cycles, output driver strength and other stuff, and a volatile register that overrides the nvm settings the first two points can be somewhat ignored by us, the generic "write 0 to the status register" is good enough to unlock the device. regarding the ME: are you aware of my layout patches, that enable read, erase and verify on user-definable address ranges? see the patches from 2011-12-25 at http://patchwork.coreboot.org/project/flashrom/list/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Cache SPI RDID response
by Stefan Tauner 12 Oct '12

12 Oct '12

On Thu, 11 Oct 2012 19:16:40 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Wed, Oct 3, 2012 at 3:59 PM, Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > Not for merge... yet. > > It works for dummy, nothing else was tested. > > Limitations/bugs mentioned in the patch. > > > > Interesting approach. However, I think 3-byte vs. 4-byte RDID commands and > caching REMS might make patching spi_send_command rather messy. > > I made a patch that takes a different route by changing > probe_spi_{rdid,rdid4,rems} functions instead. My patch can be viewed via > Gerrit on Chromium.org @ > https://gerrit.chromium.org/gerrit/#/c/35376/2 (doesn't > apply cleanly against upsteam currently). > Much better, but still wrong :) We work around a stupid probing loop instead fixing the root cause (verbose prints will still be way too verbose with this patch). If there are good reasons to do it this way, then i have no problem with it, but if we just hack this into the SPI code because it is easier to implement and come to a consensus, then i'll make the latter hard :P Fixing the probing loop has been on my todo list for a long time and i will work on it as soon as the other architectural changes are merged (status register stuff, check_trans etc). We should postpone the discussion until then IMHO. I suggest that chromium uses David's method till then and someone reviews my other patches soon ;) OTOH it would not hurt to integrate this into upstream with one exception: it would introdcue even more conflicts between open patches: David: some of this heavily conflicts with my "Generify probe_spi_rdid_generic() and add probe_spi_rdid_edi()." and other patches from that set. Maybe it would be better if you leave out the compare_id() introduction to get less conflicts later. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Cache SPI RDID response
by Carl-Daniel Hailfinger 12 Oct '12

12 Oct '12

Not for merge... yet. It works for dummy, nothing else was tested. Limitations/bugs mentioned in the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_cache_rdid/spi.c =================================================================== --- flashrom-spi_cache_rdid/spi.c (Revision 1611) +++ flashrom-spi_cache_rdid/spi.c (Arbeitskopie) @@ -24,18 +24,46 @@ #include <strings.h> #include <string.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +/* FIXME: We want a per-command cache, not just a RDID cache. + * FIXME: We should cache this for spi_send_multicommand programmers as well. + */ +struct rdidcache { + int available; + unsigned char *readarr; +} rdidcache = {0}; + int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - return flash->pgm->spi.command(flash, writecnt, readcnt, writearr, + int ret; + unsigned char *tmp; + + if ((writearr[0] == JEDEC_RDID) && (rdidcache.available >= readcnt)) { + memcpy(readarr, rdidcache.readarr, readcnt); + return 0; + } + ret = flash->pgm->spi.command(flash, writecnt, readcnt, writearr, readarr); + if (!ret && (writearr[0] == JEDEC_RDID) && (rdidcache.available < readcnt)) { + tmp = realloc(rdidcache.readarr, readcnt); + if (!tmp) { + /* Oh well. Don't cache stuff, then. No problem. */ + msg_perr("Doom due to OOM! Brace for impact!\n"); + return ret; + } + rdidcache.readarr = tmp; + rdidcache.available = readcnt; + memcpy(rdidcache.readarr, readarr, readcnt); + } + return ret; } int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) -- http://www.hailfinger.org/

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Re: [flashrom] undetected Intel X79 (8086:1d41) flash chip
by Stefan Tauner 12 Oct '12

12 Oct '12

On Wed, 10 Oct 2012 13:26:09 +0300 Alexey Dobriyan <adobriyan(a)gmail.com> wrote: > > The problem is the locked ME region as quoted above. We are working on > > unlocking it, but intel does not provide us any documentation so please > > do not expect a solution soon. > > > > Can you please tell us which Supermicro board that is so that i can add > > it to our list of unsupported boards in the meantime? > > I can't, it's a custom(?) board with DMI info et al stripped and replaced. OK > Why this ME region is important? It doesn't overlap with BIOS region. > > Alexey, who know approximately nothing about BIOS internals The ME region contains the firmware for an embedded controller (EC) in the chipset. It is used for fan control and a number of other things and also has access to basically everything the CPU has access to. The interaction between the BIOS with this EC is not documented and it is theoretically possible that updating the BIOS alone without updating the ME firmware before would brick the PC. Flashrom plays safe and disables writes if it detects that we can not write to the ME region. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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undetected Intel X79 (8086:1d41) flash chip
by Alexey Dobriyan 10 Oct '12

10 Oct '12

This comes from Sandy Bridge mobo. Is it supported in trunk? I can experiment with the system a bit if necessary. 00:1f.0 ISA bridge [0601]: Intel Corporation Patsburg LPC Controller [8086:1d41] (rev 06) Subsystem: Super Micro Computer Inc Device [15d9:0669] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0c <?> 00: 86 80 41 1d 07 00 10 02 06 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 69 06 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 04 00 00 80 00 00 00 01 05 00 00 10 00 00 00 50: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 8b 8a 85 8b d0 00 00 00 80 80 8a 87 ff 00 00 00 70: 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 78 f0 80: 10 00 0f 3f 01 0a 0c 00 a1 0c 0c 00 41 16 1c 00 90: 00 00 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 a0: 18 0a 20 00 08 18 06 00 00 47 00 00 00 03 00 c0 b0: 00 00 00 00 00 00 00 00 00 0c 4c 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 c0 ff 00 00 0a 00 00 00 e0: 09 00 0c 10 00 00 00 00 91 02 64 0c 00 00 00 00 f0: 01 c0 d1 fe 00 00 00 00 87 0f 06 08 00 00 00 00 flashrom v0.9.6.1-r1564 on Linux 2.6.39-alta-22 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.0.0, GCC 4.4.3, little endian Command line (3 args): ./flashrom -VV -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 301M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1010 us, 10000 myus = 10041 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: not found dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel X79" with PCI ID 8086:1d41. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x000f0000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. 0x58: 0x0fff0800 FREG1: BIOS region (0x00800000-0x00ffffff) is read-write. 0x5C: 0x07ff0020 FREG2: WARNING: Management Engine region (0x00020000-0x007fffff) is locked. 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x001f0010 FREG4: Platform Data region (0x00010000-0x0001ffff) is read-write. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x03040003 FLMAP1 0x12100206 FLMAP2 0x00210020 --- Details --- NR (Number of Regions): 4 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 0 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x24900025 FLILL 0x00000000 --- Details --- Component 1 density: 16 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz No forbidden opcodes. === Region Section === FLREG0 0x000f0000 FLREG1 0x0fff0800 FLREG2 0x07ff0020 FLREG3 0x00000fff FLREG4 0x001f0010 --- Details --- Region 0 (Descr.) 0x00000000 - 0x0000ffff Region 1 (BIOS ) 0x00800000 - 0x00ffffff Region 2 (ME ) 0x00020000 - 0x007fffff Region 3 (GbE ) is unused. Region 4 (Platf.) 0x00010000 - 0x0001ffff === Master Section === FLMSTR1 0x1a1b0000 FLMSTR2 0x04050000 FLMSTR3 0x08090118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw rw ME r rw GbE r rw SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0xff, id2 0xff Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0xff, id2 0xff Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Unknown SFDP-capable chip, 0 kB: program_opcodes: preop=5006 optype=462b opmenu=055a0302c79f0190 on-the-fly OPCODE (0x5A) re-programmed, op-pos=2 SFDP revision = 1.0 SFDP number of parameter headers is 1 (NPH = 0). SFDP parameter table header 0/0: ID 0x00, version 1.0 Length 36 B, Parameter Table Pointer 0x000030 Parsing JEDEC flash parameter table... 3-Byte only addressing. Status register is non-volatile and the standard does not allow vendors to tell us whether EWSR/WREN is needed for status register writes - assuming EWSR. Write chunk size is at least 64 B. Flash chip size is 16384 kB. Block eraser 0: 4096 x 4096 B with opcode 0x20 Tried to add a duplicate block eraser: 4096 x 4096 B with opcode 0x20. Block eraser 1: 256 x 65536 B with opcode 0xd8 done. === SFDP has autodetected a flash chip which is not natively supported by flashrom yet. All standard operations (read, verify, erase and write) should work, but to support all possible features we need to add them manually. You can help us by mailing us the output of the following command to flashrom(a)flashrom.org: 'flashrom -VV [plus the -p/--programmer parameter (if needed)]' Thanks for your help! === Found Unknown flash chip "SFDP-capable chip" (16384 kB, SPI) at physical address 0x0. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba18 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Unknown flash chip "SFDP-capable chip" (16384 kB, SPI). No operations were specified. Restoring MMIO space at 0x7fb022bed8a0 Restoring MMIO space at 0x7fb022bed89c Restoring MMIO space at 0x7fb022bed898 Restoring MMIO space at 0x7fb022bed896 Restoring MMIO space at 0x7fb022bed894 Restoring PCI config space for 00:1f:0 reg 0xdc

2 2

[PATCH] serprog: add opcode to control the programmer's output drivers.
by Stefan Tauner 10 Oct '12

10 Oct '12

Also, move the macro list to its own file. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Implemented and tested with my atmegaXXu2 flasher, works great with my coreboot target. Does anybody have an idea for a better macro name? Maybe just S_CMD_S_DRIVERS? Documentation/serprog-protocol.txt | 33 +++++++--------------------- serprog.c | 42 +++++++++++++++--------------------- serprog.h | 25 +++++++++++++++++++++ 3 files changed, 50 insertions(+), 50 deletions(-) create mode 100644 serprog.h diff --git a/Documentation/serprog-protocol.txt b/Documentation/serprog-protocol.txt index d8733cc..58f4417 100644 --- a/Documentation/serprog-protocol.txt +++ b/Documentation/serprog-protocol.txt @@ -34,6 +34,7 @@ COMMAND Description Parameters Return Value 0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK + slen bytes of data 0x14 Set SPI clock frequency in Hz 32-bit requested frequency ACK + 32-bit set frequency / NAK +0x15 Toggle flash chip pin drivers 8-bit (0 disable, else enable) ACK / NAK 0x?? unimplemented command - invalid. @@ -82,6 +83,12 @@ Additional information of the above commands: lower than the one requested. If there is no lower frequency available the lowest possible should be used. The value chosen is sent back in the reply with an ACK. + 0x15 (S_CMD_S_PIN_STATE): + Sets the state of the pin drivers connected to the flash chip. Disabling them allows other + devices (e.g. a mainboard's chipset) to access the chip. This way the serprog controller can + remain attached to the flash chip even when the board is running. The user is responsible to + NOT connect VCC and other permanently externally driven signals to the programmer as needed. + If the value is 0, then the drivers should be disabled, otherwise they should be enabled. About mandatory commands: The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, but one can't really do anything with these commands. @@ -92,28 +99,4 @@ Additional information of the above commands: In addition, support for these commands is recommended: S_CMD_Q_PGMNAME, S_CMD_Q_BUSTYPE, S_CMD_Q_CHIPSIZE (if parallel). - -This define listing should help C coders - (it's here to be the single source for copying - will be a .h someday i think) -#define S_ACK 0x06 -#define S_NAK 0x15 -#define S_CMD_NOP 0x00 /* No operation */ -#define S_CMD_Q_IFACE 0x01 /* Query interface version */ -#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ -#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ -#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ -#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ -#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ -#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ -#define S_CMD_R_BYTE 0x09 /* Read a single byte */ -#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ -#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ -#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ -#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ -#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ -#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ -#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ -#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ -#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ -#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ -#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ +See also serprog.h. diff --git a/serprog.c b/serprog.c index b179ea4..0f31696 100644 --- a/serprog.c +++ b/serprog.c @@ -38,6 +38,7 @@ #include "flash.h" #include "programmer.h" #include "chipdrivers.h" +#include "serprog.h" #define MSGHEADER "serprog: " @@ -48,30 +49,6 @@ */ static int serprog_shutdown(void *data); -#define S_ACK 0x06 -#define S_NAK 0x15 -#define S_CMD_NOP 0x00 /* No operation */ -#define S_CMD_Q_IFACE 0x01 /* Query interface version */ -#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ -#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ -#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ -#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ -#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ -#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum length */ -#define S_CMD_R_BYTE 0x09 /* Read a single byte */ -#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ -#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ -#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ -#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ -#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ -#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ -#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ -#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ -#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ -#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ -#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ - static uint16_t sp_device_serbuf_size = 16; static uint16_t sp_device_opbuf_size = 300; /* Bitmap of supported commands */ @@ -687,6 +664,15 @@ int serprog_init(void) sp_device_opbuf_size); } + if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { + uint8_t en = 1; + if (sp_docommand(S_CMD_S_PIN_STATE, 1, &en, 0, NULL) != 0) { + msg_perr("Error: could not enable output buffers\n"); + return 1; + } else + msg_pdbg(MSGHEADER "Output drivers enabled\n"); + } else + msg_pdbg(MSGHEADER "Warning: Programmer does not support toggling its output drivers\n"); sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; @@ -759,9 +745,15 @@ static void sp_execute_opbuf(void) static int serprog_shutdown(void *data) { - msg_pspew("%s\n", __func__); if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) sp_execute_opbuf(); + if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { + uint8_t dis = 0; + if (sp_docommand(S_CMD_S_PIN_STATE, 1, &dis, 0, NULL) == 0) + msg_pdbg(MSGHEADER "Output drivers disabled\n"); + else + msg_perr(MSGHEADER "%s: Warning: could not disable output buffers\n", __func__); + } /* FIXME: fix sockets on windows(?), especially closing */ serialport_shutdown(&sp_fd); if (sp_max_write_n) diff --git a/serprog.h b/serprog.h new file mode 100644 index 0000000..b54aaea --- /dev/null +++ b/serprog.h @@ -0,0 +1,25 @@ +/* According to Serial Flasher Protocol Specification - version 1 */ +#define S_ACK 0x06 +#define S_NAK 0x15 +#define S_CMD_NOP 0x00 /* No operation */ +#define S_CMD_Q_IFACE 0x01 /* Query interface version */ +#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ +#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ +#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ +#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ +#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ +#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ +#define S_CMD_R_BYTE 0x09 /* Read a single byte */ +#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ +#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ +#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ +#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ +#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ +#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ +#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ +#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ +#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ +#define S_CMD_S_SPI_FREQ 0x14 /* Set SPI clock frequency */ +#define S_CMD_S_PIN_STATE 0x15 /* Enable/disable output drivers */ -- Kind regards, Stefan Tauner

1 0

[PATCH] Add support for Atmel AT26DF041.
by Stefan Tauner 07 Oct '12

07 Oct '12

Wicked chip: No WRSR, no write enable command, auto-erasing page write (but even without that page writes are recommended to write the whole page i.e. operate on a completely erased page), mad requirements on block refreshments if only partly written. Found on my Intel D946GZIS and tested with my serprog in situ. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 2 ++ flashchips.c | 14 +++++++--- spi.h | 10 ++++++++ spi25.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 4 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 1ef4959..f110807 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -41,7 +41,9 @@ int probe_spi_res2(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); diff --git a/flashchips.c b/flashchips.c index 4e09ab1..103aa7b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1795,18 +1795,24 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 256, /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { + .eraseblocks = { {256, 2048} }, + .block_erase = spi_block_erase_81, + }, { + .eraseblocks = { {2 * 1024, 256} }, + .block_erase = spi_block_erase_50, + }, { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, } - }, - .write = NULL /* Incompatible Page write */, - .read = spi_chip_read, + }, /* Supports also an incompatible page write (of exactly 256 B) and an auto-erasing write. */ + .write = spi_chip_write_1, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, /* 3.0-3.6V for higher speed, 2.7-3.6V normal */ }, diff --git a/spi.h b/spi.h index ce2ede8..1733fd3 100644 --- a/spi.h +++ b/spi.h @@ -76,11 +76,21 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 +/* Block Erase 0x50 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_50 0x50 +#define JEDEC_BE_50_OUTSIZE 0x04 +#define JEDEC_BE_50_INSIZE 0x00 + /* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 +/* Block Erase 0x81 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_81 0x81 +#define JEDEC_BE_81_OUTSIZE 0x04 +#define JEDEC_BE_81_INSIZE 0x00 + /* Block Erase 0xd8 is supported by EON/Macronix chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 diff --git a/spi25.c b/spi25.c index a65f548..10c5a4a 100644 --- a/spi25.c +++ b/spi25.c @@ -741,6 +741,86 @@ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, return 0; } +int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_50_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_50, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 10 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_81_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_81, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 8 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { -- Kind regards, Stefan Tauner

1 0

Re: [flashrom] W836xx: Supermicro X8DTL
by Stefan Tauner 04 Oct '12

04 Oct '12

On Thu, 4 Oct 2012 11:32:06 -0700 Jobe Bittman <jobe(a)opencandy.com> wrote: > root@vm2-prod.sea:~# flashrom -p internal -V > flashrom v0.9.6.1-r1596 on Linux 3.4.11-1.fc16.x86_64 (x86_64) > […] Hello and thanks for your report. Since the Winbond chip is apparently not involved in accessing the flash and we have numerous reports of similar Supermicro boards, i presume that it will just work. If you test it out please report any success or failure too, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

W836xx: Supermicro X8DTL
by Jobe Bittman 04 Oct '12

04 Oct '12

root@vm2-prod.sea:~# flashrom -p internal -V flashrom v0.9.6.1-r1596 on Linux 3.4.11-1.fc16.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.3 20120306 (Red Hat 4.6.3-2), little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 1062M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 9994 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X8DTL" DMI string system-version: "1234567890" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X8DTL" DMI string baseboard-version: "1234567890" DMI string chassis-type: "Main Server Chassis" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 1a. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=0, FLOCKDN=0 Programming OPCODES... done 0x08: 0x00000000 (FADDR) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000. Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x03, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L3205" (4096 kB, SPI). No operations were specified. Restoring MMIO space at 0x7f18338c18a0 Restoring MMIO space at 0x7f18338c189c Restoring MMIO space at 0x7f18338c1898 Restoring MMIO space at 0x7f18338c1896 Restoring MMIO space at 0x7f18338c1894 Restoring PCI config space for 00:1f:0 reg 0xdc

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Re: [flashrom] Numonyx N25Q064 (second try)
by Stefan Tauner 04 Oct '12

04 Oct '12

On Wed, 3 Oct 2012 20:40:44 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Thu, Jul 26, 2012 at 8:48 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > did you really test the 1.8V version too? > > > > Nope. We can set that to UNTESTED if you prefer, though I don't think > there's much reason to suspect it will fail when the 3V version works. Nope, but i don't trust any vendor too much. We have burned often enough (SFDP compatibility for example... ;) > On Thu, Jul 26, 2012 at 8:48 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > > > > .probe = probe_spi_rdid, > > > .probe_timing = TIMING_ZERO, > > > @@ -5450,9 +5454,44 @@ > > > .unlock = spi_disable_blockprotect, > > > .write = spi_chip_write_256, > > > .read = spi_chip_read, > > > + .voltage = {1700, 2000}, > > > }, > > > > > > { > > > + .vendor = "Numonyx", > > > + /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ > > > + .name = "N25Q064..3E", > > > + .bustype = BUS_SPI, > > > + .manufacture_id = ST_ID, > > > + .model_id = ST_N25Q064__3E, > > > + .total_size = 8192, > > > + .page_size = 256, > > > + /* supports SFDP */ > > > > Does it work as expected (testable by removing the chip definition)? > > > > Obviously not or I wouldn't have bothered to make a patch for it :-) In case you ever get the chance to test this again, i would really like to see the SFDP debug output. The SFDP implementation is still not tested very much, so there still might be bugs, even if faulty chips are more likely imo. Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> and committed in r1612, thanks! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1612 - trunk
by repository service 04 Oct '12

04 Oct '12

Author: stefanct Date: Thu Oct 4 16:41:20 2012 New Revision: 1612 URL: http://flashrom.org/trac/flashrom/changeset/1612 Log: Differentiate Numonyx N25Q064 1.8V and 3.0V versions. This patch differentiates between the N25Q064 1.8V version and 3.0V version which have different JEDEC IDs. It extends the chip name to include more characters of the part number. The first two of those characters indicate the process technology (65nm) and feature set (hold pin etc.), neither of which matter for flashrom at the moment. The third and fourth characters specify voltage and block/sector size and uniformity, which are important and hence included. To abstract the irrelevant portions of the part number leading up to the characters we care about, dots are used. This helps prevent unwanted changes in chip name that can break fragile scripts and confuse people. More about this schema here: http://www.flashrom.org/pipermail/flashrom/2012-July/009595.html Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Oct 2 00:45:08 2012 (r1611) +++ trunk/flashchips.c Thu Oct 4 16:41:20 2012 (r1612) @@ -5587,12 +5587,48 @@ { .vendor = "Numonyx", - .name = "N25Q064", + .name = "N25Q064..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q064, + .model_id = ST_N25Q064__1E, .total_size = 8192, .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Numonyx", + .name = "N25Q064..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q064__3E, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5612,6 +5648,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Oct 2 00:45:08 2012 (r1611) +++ trunk/flashchips.h Thu Oct 4 16:41:20 2012 (r1612) @@ -591,7 +591,8 @@ #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 -#define ST_N25Q064 0xBA17 +#define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, 64KB/4KB blocks/sectors */ +#define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, 64KB/4KB blocks/sectors */ #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ #define MVC_V29C51000T 0x00

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Re: [flashrom] Numonyx N25Q064 (second try)
by Stefan Tauner 04 Oct '12

04 Oct '12

On Wed, 25 Jul 2012 16:08:58 -0700 David Hendricks <dhendrix(a)google.com> wrote: > This patch differentiates between the N25Q064 1.8V version and 3.0V version > which have different JEDEC IDs. > > It extends the chip name to include the first few characters in the part > number. The first two of those characters indicate the process technology > (65nm) and feature set, neither of which matter for Flashrom. The third and > fourth characters specify voltage and block/sector size and uniformity, > which are important. > > To abstract the irrelevant portions of the part number leading up to the > characters we care about, dots are used. This helps prevent unwanted > changes in chip name that can break fragile scripts and confuse people. > More about this schema here: > http://www.flashrom.org/pipermail/flashrom/2012-July/009595.html > > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 1553) > +++ flashchips.c (working copy) > @@ -5425,12 +5425,16 @@ > > { > .vendor = "Numonyx", > - .name = "N25Q064", > + /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ > + .name = "N25Q064..1E", > .bustype = BUS_SPI, > .manufacture_id = ST_ID, > - .model_id = ST_N25Q064, > + .model_id = ST_N25Q064__1E, > .total_size = 8192, > .page_size = 256, > + /* supports SFDP */ > + /* OTP: 64B total; read 0x4B, write 0x42 */ > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > .tested = TEST_OK_PREW, did you really test the 1.8V version too? > .probe = probe_spi_rdid, > .probe_timing = TIMING_ZERO, > @@ -5450,9 +5454,44 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {1700, 2000}, > }, > > { > + .vendor = "Numonyx", > + /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ > + .name = "N25Q064..3E", > + .bustype = BUS_SPI, > + .manufacture_id = ST_ID, > + .model_id = ST_N25Q064__3E, > + .total_size = 8192, > + .page_size = 256, > + /* supports SFDP */ Does it work as expected (testable by removing the chip definition)? There are a number of other N25Q* chips available apparently. Do you plan to add them too (NB: http://patchwork.coreboot.org/patch/3652/)? Anyone else? Steven, our datasheet muncher maybe? :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] WRDI before RDID for AAI chips.
by Stefan Tauner 04 Oct '12

04 Oct '12

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- This is not for merge but just a reminder to not forget about this: AAI uses a stateful process for writes that will only reset on reception of WRDI or reset. In this state the chip will not react to other opcodes than AAI write and WRDI. Now when a chip gets interrupted while in this state, flashrom is not able to detect and use the chip, because it won't reply to the probes. TODO: either add WRDI to the generic RDID command after checking that this is safe, or add the probe_spi_rdid_wrdi command instead of probe_spi_rdid to all AAI-capable chips. Thanks to Denis 'GNUtoo' Carikli for reporting the problem. chipdrivers.h | 1 + flashchips.c | 2 +- spi25.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/chipdrivers.h b/chipdrivers.h index 1ef4959..a01e5e7 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int /* spi25.c */ int probe_spi_rdid(struct flashctx *flash); +int probe_spi_rdid_wrdi(struct flashctx *flash); int probe_spi_rdid4(struct flashctx *flash); int probe_spi_rems(struct flashctx *flash); int probe_spi_res1(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index e290e2f..00df2ac 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6390,7 +6390,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, + .probe = probe_spi_rdid_wrdi, .probe_timing = TIMING_ZERO, .block_erasers = { diff --git a/spi25.c b/spi25.c index a65f548..38179b6 100644 --- a/spi25.c +++ b/spi25.c @@ -173,6 +173,12 @@ int probe_spi_rdid(struct flashctx *flash) return probe_spi_rdid_generic(flash, 3); } +int probe_spi_rdid_wrdi(struct flashctx *flash) +{ + spi_write_disable(flash); + return probe_spi_rdid_generic(flash, 3); +} + int probe_spi_rdid4(struct flashctx *flash) { /* Some SPI controllers do not support commands with writecnt=1 and -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] ichspi: reprogram_opcode_on_the_fly return code fix.
by Stefan Tauner 03 Oct '12

03 Oct '12

On Wed, 12 Sep 2012 16:29:44 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > by carldani, found in our paste service history > --- > ichspi.c | 20 +++++++++++++------- > 1 file changed, 13 insertions(+), 7 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index ce9c553..fbc6ea7 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -409,13 +409,19 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un > else // we have an invalid case > return SPI_INVALID_LENGTH; > } > - int oppos = 2; // use original JEDEC_BE_D8 offset > - curopcodes->opcode[oppos].opcode = opcode; > - curopcodes->opcode[oppos].spi_type = spi_type; > - program_opcodes(curopcodes, 0); > - oppos = find_opcode(curopcodes, opcode); > - msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); > - return oppos; > + if (spi_type <= 3) { > + int oppos = 2; // use original JEDEC_BE_D8 offset > + curopcodes->opcode[oppos].opcode = opcode; > + curopcodes->opcode[oppos].spi_type = spi_type; > + program_opcodes(curopcodes, 0); > + oppos = find_opcode(curopcodes, opcode); > + msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); > + return oppos; > + } > + /* This case only happens if the writecnt/readcnt combination is > + * impossible to achieve on ICH SPI. > + */ > + return SPI_INVALID_LENGTH; > } > > static int find_opcode(OPCODES *op, uint8_t opcode) I think this patch is made obsolete by my latest check_trans patch set. I'll mark it superseded in patchwork. http://patchwork.coreboot.org/patch/3746/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH 5/5] Let the dummy programmer emulate SPI payload limitations.
by Stefan Tauner 03 Oct '12

03 Oct '12

As long as a programmer's check_trans code does not rely on the previous invocation of its init function one can trivially set that programmer's check_trans function instead of the dummy's default one. This allows for even better testing of the SPI infrastructure code under near realworld conditions. FIXME: add other programmers FIXME: add manpage doc Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- dummyflasher.c | 15 ++++++++++++++- programmer.h | 2 ++ wbsio_spi.c | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/dummyflasher.c b/dummyflasher.c index 4e08386..1d63b7a 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -119,7 +119,7 @@ static uint32_t dummy_chip_readl(const struct flashctx *flash, static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_programmer spi_programmer_dummyflasher = { +static struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -373,6 +373,19 @@ int dummy_init(void) msg_pdbg("Initial status register is set to 0x%02x.\n", emu_status); } + tmp = extract_programmer_param("spi_prog"); + if (tmp) { + if (!strcmp(tmp, "wbsio")) { + spi_programmer_dummyflasher.check_trans = wbsio_spi_check_trans; + msg_pdbg("Using SPI payload limitations of the %s programmer.\n", tmp); + } else { + msg_perr("Error: emulation of a programmer requested, " + "but the programmer could not be parsed \"%s\".\n", tmp); + free(tmp); + return 1; + } + } + free(tmp); #endif msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); diff --git a/programmer.h b/programmer.h index bcd9547..c2373e6 100644 --- a/programmer.h +++ b/programmer.h @@ -585,6 +585,8 @@ int mcp6x_spi_init(int want_spi); int sb600_probe_spi(struct pci_dev *dev); /* wbsio_spi.c */ +int wbsio_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr); int wbsio_check_for_spi(void); #endif diff --git a/wbsio_spi.c b/wbsio_spi.c index ec14c28..6164ae7 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -108,7 +108,7 @@ static uint8_t determine_mode(struct flashctx *flash, unsigned int writecnt, uns return 0; } -static int wbsio_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr) { if (determine_mode(flash, writecnt, readcnt, writearr) == 0) -- Kind regards, Stefan Tauner

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[PATCH 4/5] Generify probe_spi_rdid_generic() and add probe_spi_rdid_edi().
by Stefan Tauner 03 Oct '12

03 Oct '12

Previously the "generic" function was working/used for exactly two cases, namely for manufacturer IDs with 0 or 1 continuation bytes. For this behavior it was overly complicated. The new implementation handles up to 3 continuation bytes automatically and allows for up to 4 model bytes which is directly used to add support for an EDI probing function. The probe_spi_rdid4() function is removed because it is no longer needed. The new probe_spi_rdid_generic() tries to figure out the maximum allowed read size by using the recently added check_trans() function to reduce the request size if necessary. While this does not make detection to succeed in all theoretical situations, it improves the code and will hopefully work in all realworld situations. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 24 +++++++-------- flashchips.h | 2 +- spi25.c | 97 ++++++++++++++++++++++++++++++---------------------------- 3 files changed, 63 insertions(+), 60 deletions(-) diff --git a/flashchips.c b/flashchips.c index e290e2f..a69d899 100644 --- a/flashchips.c +++ b/flashchips.c @@ -547,7 +547,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -581,7 +581,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -615,7 +615,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -650,7 +650,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -685,7 +685,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -720,7 +720,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -760,7 +760,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PR, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -795,7 +795,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PR, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -830,7 +830,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PRE, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -865,7 +865,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -903,7 +903,7 @@ const struct flashchip flashchips[] = { .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PR, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -9752,7 +9752,7 @@ const struct flashchip flashchips[] = { .total_size = 0, .page_size = 256, .tested = TEST_BAD_PREW, - .probe = probe_spi_rdid4, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .write = NULL, .read = NULL, diff --git a/flashchips.h b/flashchips.h index 8e51d35..d353b9e 100644 --- a/flashchips.h +++ b/flashchips.h @@ -91,7 +91,7 @@ #define AMD_AM29LV800BT 0xDA /* Same as Am29LV800DT */ #define AMIC_ID 0x7F37 /* AMIC */ -#define AMIC_ID_NOPREFIX 0x37 /* AMIC */ +#define AMIC_ID_NOPREFIX 0x37 /* not AMIC, but used nevertheless in some AMIC chips */ #define AMIC_A25L05PT 0x2020 #define AMIC_A25L05PU 0x2010 #define AMIC_A25L10PT 0x2021 diff --git a/spi25.c b/spi25.c index a65f548..6310cf0 100644 --- a/spi25.c +++ b/spi25.c @@ -35,10 +35,13 @@ static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) int ret; int i; + ret = flash->pgm->spi.check_trans(flash, sizeof(cmd), bytes, cmd); + if (ret) + return ret; ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; - msg_cspew("RDID returned"); + msg_cspew("RDID returned %d bytes:", bytes); for (i = 0; i < bytes; i++) msg_cspew(" 0x%02x", readarr[i]); msg_cspew(". "); @@ -115,37 +118,54 @@ int spi_write_disable(struct flashctx *flash) return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } -static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) +/* The model_bytes parameter indicates the number of bytes of the model ID that have to match. + * The current implementation does work for manufacturer IDs with up to 3 continuation bytes and up to 4 bytes + * for the model identifier. */ +static int probe_spi_rdid_generic(struct flashctx *flash, int model_bytes) { + int i, j; const struct flashchip *chip = flash->chip; - unsigned char readarr[4]; - uint32_t id1; - uint32_t id2; - - if (spi_rdid(flash, readarr, bytes)) { - return 0; - } - - if (!oddparity(readarr[0])) - msg_cdbg("RDID byte 0 parity violation. "); - - /* Check if this is a continuation vendor ID. - * FIXME: Handle continuation device IDs. - */ - if (readarr[0] == 0x7f) { - if (!oddparity(readarr[1])) - msg_cdbg("RDID byte 1 parity violation. "); - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; - if (bytes > 3) { - id2 <<= 8; - id2 |= readarr[3]; + uint32_t id1 = 0; + uint32_t id2 = 0; + + /* As of 2012-09 (JEP106AJ) there exist 8 banks, so we need at most 8 bytes to identify a manufacturer: + * 7x continuation indicators (0x7F) + one ID byte. The problem is that a number of programmers do not + * support arbitrary transaction lenghts. This implementation does not support more than 3 continuation + * bytes because we use 32 bits for the ID and currently do not need more than banks 1-2 anyway. */ + const int MAX_RD = 4 + model_bytes; + uint8_t readarr[MAX_RD]; + i = MAX_RD; + do { + int ret = spi_rdid(flash, readarr, i); + if (ret == 0) + break; + if (ret != SPI_INVALID_LENGTH) + return ret; + /* We need at least 1 vendor + n chip bytes, less does not make sense */ + if (i <= 1 + model_bytes) { + msg_cinfo("%d byte RDID not supported on this SPI controller.\n", i); + return ret; + } + } while (i-- > 0); + + i = 0; + while (i < MAX_RD) { + uint8_t tmp = readarr[i]; + i++; + id1 = (id1 << 8) | tmp; + if (tmp != 0x7f) { + if (!oddparity(tmp)) { + msg_cdbg("Manufacturer ID parity violation at RDID byte %i. ID so far: 0x%x.\n", + i - 1, id1); + return 0; + } + break; } - } else { - id1 = readarr[0]; - id2 = (readarr[1] << 8) | readarr[2]; } + for (j = 0; j < model_bytes; j++) + id2 = (id2 << 8) | readarr[i + j]; + msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); if (id1 == chip->manufacture_id && id2 == chip->model_id) { @@ -170,29 +190,12 @@ static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) int probe_spi_rdid(struct flashctx *flash) { - return probe_spi_rdid_generic(flash, 3); + return probe_spi_rdid_generic(flash, 2); } -int probe_spi_rdid4(struct flashctx *flash) +int probe_spi_rdid_edi(struct flashctx *flash) { - /* Some SPI controllers do not support commands with writecnt=1 and - * readcnt=4. - */ - switch (flash->pgm->spi.type) { -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_IT87XX: - case SPI_CONTROLLER_WBSIO: - msg_cinfo("4 byte RDID not supported on this SPI controller\n"); - return 0; - break; -#endif -#endif - default: - return probe_spi_rdid_generic(flash, 4); - } - - return 0; + return probe_spi_rdid_generic(flash, 4); } int probe_spi_rems(struct flashctx *flash) -- Kind regards, Stefan Tauner

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[PATCH 3/5] Introduce check_trans().
by Stefan Tauner 03 Oct '12

03 Oct '12

Adds the infrastructure parts that allow for sanity checks of transactions without executing them. This includes new fields in struct spi_programmer and default implementations as well as concrete implementations for existing programmer where it makes sense. Some additional cleanups are done as a bonus where i took the opportunity, namely in sb600 and serprog. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- bitbang_spi.c | 1 + buspirate_spi.c | 14 +++++++++++++- dediprog.c | 24 ++++++++++++++++-------- dummyflasher.c | 1 + ft2232_spi.c | 14 +++++++++++++- ichspi.c | 9 +++++++++ it85spi.c | 1 + it87spi.c | 31 +++++++++++++++++++++++-------- linux_spi.c | 31 +++++++++++++++++++++++-------- programmer.h | 9 +++++++++ sb600spi.c | 51 ++++++++++++++++++++++++++++----------------------- serprog.c | 32 +++++++++++++++++++++----------- spi.c | 9 +++++++-- wbsio_spi.c | 10 ++++++++++ 14 files changed, 175 insertions(+), 62 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index 11d2de1..4b9f83a 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -67,6 +67,7 @@ static const struct spi_programmer spi_programmer_bitbang = { .type = SPI_CONTROLLER_BITBANG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .check_trans = default_spi_check_trans, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, .read = default_spi_read, diff --git a/buspirate_spi.c b/buspirate_spi.c index 054b4ff..340091c 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -129,6 +129,14 @@ static int buspirate_wait_for_string(unsigned char *buf, char *key) return ret; } +static int buspirate_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) + return SPI_INVALID_LENGTH; + return 0; +} + static int buspirate_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -136,6 +144,7 @@ static const struct spi_programmer spi_programmer_buspirate = { .type = SPI_CONTROLLER_BUSPIRATE, .max_data_read = 12, .max_data_write = 12, + .check_trans = buspirate_spi_check_trans, .command = buspirate_spi_send_command, .multicommand = default_spi_send_multicommand, .read = default_spi_read, @@ -421,8 +430,11 @@ static int buspirate_spi_send_command(struct flashctx *flash, unsigned int i = 0; int ret = 0; - if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) + if (buspirate_spi_check_trans(flash, writecnt, readcnt, writearr) != 0) { + msg_pspew("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); return SPI_INVALID_LENGTH; + } /* 3 bytes extra for CS#, len, CS#. */ if (buspirate_commbuf_grow(writecnt + readcnt + 3)) diff --git a/dediprog.c b/dediprog.c index a81cf83..643b324 100644 --- a/dediprog.c +++ b/dediprog.c @@ -439,6 +439,18 @@ static int dediprog_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned return dediprog_spi_write(flash, buf, start, len, DEDI_SPI_CMD_AAIWRITE); } +static int dediprog_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + /* Paranoid, but I don't want to be blamed if anything explodes. */ + if (writecnt > 16) + return 1; + /* 16 byte reads should work. */ + if (readcnt > 16) + return -1; + return 0; +} + static int dediprog_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, @@ -448,14 +460,9 @@ static int dediprog_spi_send_command(struct flashctx *flash, int ret; msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); - /* Paranoid, but I don't want to be blamed if anything explodes. */ - if (writecnt > 16) { - msg_perr("Untested writecnt=%i, aborting.\n", writecnt); - return 1; - } - /* 16 byte reads should work. */ - if (readcnt > 16) { - msg_perr("Untested readcnt=%i, aborting.\n", readcnt); + if (dediprog_spi_check_trans(flash, writecnt, readcnt, writearr) != 0) { + msg_perr("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); return 1; } @@ -740,6 +747,7 @@ static const struct spi_programmer spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, + .check_trans = dediprog_spi_check_trans, .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, diff --git a/dummyflasher.c b/dummyflasher.c index 655b678..4e08386 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -123,6 +123,7 @@ static const struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, + .check_trans = default_spi_check_trans, /* FIXME */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, .read = default_spi_read, diff --git a/ft2232_spi.c b/ft2232_spi.c index 31a6c5c..d139886 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -139,6 +139,14 @@ static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, return 0; } +static int ft2232_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + return 0; +} + static int ft2232_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -148,6 +156,7 @@ static const struct spi_programmer spi_programmer_ft2232 = { .type = SPI_CONTROLLER_FT2232, .max_data_read = 64 * 1024, .max_data_write = 256, + .check_trans = ft2232_spi_check_trans, .command = ft2232_spi_send_command, .multicommand = default_spi_send_multicommand, .read = default_spi_read, @@ -407,8 +416,11 @@ static int ft2232_spi_send_command(struct flashctx *flash, int bufsize; static int oldbufsize = 0; - if (writecnt > 65536 || readcnt > 65536) + if (ft2232_spi_check_trans(flash, writecnt, readcnt, writearr) != 0) { + msg_pspew("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); return SPI_INVALID_LENGTH; + } /* buf is not used for the response from the chip. */ bufsize = max(writecnt + 9, 260 + 9); diff --git a/ichspi.c b/ichspi.c index e60913c..0ce9dc2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1082,6 +1082,12 @@ static int prepare_opcode(struct flashctx *flash, unsigned int writecnt, unsigne return 0; } +static int ich_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + return prepare_opcode(flash, writecnt, readcnt, writearr, true, NULL); +} + static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -1563,6 +1569,7 @@ static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, .max_data_write = 64, + .check_trans = ich_spi_check_trans, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, .read = default_spi_read, @@ -1574,6 +1581,7 @@ static const struct spi_programmer spi_programmer_ich9 = { .type = SPI_CONTROLLER_ICH9, .max_data_read = 64, .max_data_write = 64, + .check_trans = ich_spi_check_trans, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, .read = default_spi_read, @@ -1881,6 +1889,7 @@ static const struct spi_programmer spi_programmer_via = { .type = SPI_CONTROLLER_VIA, .max_data_read = 16, .max_data_write = 16, + .check_trans = ich_spi_check_trans, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, .read = default_spi_read, diff --git a/it85spi.c b/it85spi.c index 0b074eb..67c7185 100644 --- a/it85spi.c +++ b/it85spi.c @@ -280,6 +280,7 @@ static const struct spi_programmer spi_programmer_it85xx = { .type = SPI_CONTROLLER_IT85XX, .max_data_read = 64, .max_data_write = 64, + .check_trans = default_spi_check_trans, .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, .read = default_spi_read, diff --git a/it87spi.c b/it87spi.c index a35ddc0..f7b2a9e 100644 --- a/it87spi.c +++ b/it87spi.c @@ -104,6 +104,8 @@ void probe_superio_ite(void) return; } +static int it8716f_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr); static int it8716f_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -117,6 +119,7 @@ static const struct spi_programmer spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, + .check_trans = it8716f_spi_check_trans, .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand, .read = it8716f_spi_chip_read, @@ -242,6 +245,18 @@ int init_superio_ite(void) return ret; } +static int it8716f_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + if (readcnt > 3) { + return -1; + } + if (writecnt != 1 && writecnt != 2 && writecnt != 4 && writecnt != 5) { + return 1; + } + return 0; +} + /* * The IT8716F only supports commands with length 1,2,4,5 bytes including * command byte and can not read more than 3 bytes from the device. @@ -259,14 +274,16 @@ static int it8716f_spi_send_command(struct flashctx *flash, uint8_t busy, writeenc; int i; + if (it8716f_spi_check_trans(flash, writecnt, readcnt, writearr) != 0) { + msg_pspew("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); + return SPI_INVALID_LENGTH; + } + do { busy = INB(it8716f_flashport) & 0x80; } while (busy); - if (readcnt > 3) { - msg_pinfo("%s called with unsupported readcnt %i.\n", - __func__, readcnt); - return SPI_INVALID_LENGTH; - } + switch (writecnt) { case 1: OUTB(writearr[0], it8716f_flashport + 1); @@ -292,9 +309,7 @@ static int it8716f_spi_send_command(struct flashctx *flash, OUTB(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; - default: - msg_pinfo("%s called with unsupported writecnt %i.\n", - __func__, writecnt); + default: /* Should never happen due to the checks in it8716f_spi_check_trans() */ return SPI_INVALID_LENGTH; } /* diff --git a/linux_spi.c b/linux_spi.c index 2f46463..2301b84 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -37,6 +37,8 @@ static int fd = -1; static int linux_spi_shutdown(void *data); +static int linux_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr); static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *txbuf, @@ -50,6 +52,7 @@ static const struct spi_programmer spi_programmer_linux = { .type = SPI_CONTROLLER_LINUX, .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ + .check_trans = linux_spi_check_trans, .command = linux_spi_send_command, .multicommand = default_spi_send_multicommand, .read = linux_spi_read, @@ -129,29 +132,41 @@ static int linux_spi_shutdown(void *data) return 0; } +static int linux_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + /* The implementation currently does not support requests that + don't start with sending a command. */ + if (writecnt == 0) + return SPI_INVALID_LENGTH; + return 0; +} + static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, - const unsigned char *txbuf, - unsigned char *rxbuf) + const unsigned char *writearr, + unsigned char *readarr) { int iocontrol_code; struct spi_ioc_transfer msg[2] = { { - .tx_buf = (uint64_t)(ptrdiff_t)txbuf, + .tx_buf = (uint64_t)(ptrdiff_t)writearr, .len = writecnt, }, { - .rx_buf = (uint64_t)(ptrdiff_t)rxbuf, + .rx_buf = (uint64_t)(ptrdiff_t)readarr, .len = readcnt, }, }; + int ret = linux_spi_check_trans(flash, writecnt, readcnt, writearr); + if (ret != 0) + msg_perr("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); + return ret; + if (fd == -1) return -1; - /* The implementation currently does not support requests that - don't start with sending a command. */ - if (writecnt == 0) - return SPI_INVALID_LENGTH; /* Just submit the first (write) request in case there is nothing to read. Otherwise submit both requests. */ diff --git a/programmer.h b/programmer.h index dedec67..bcd9547 100644 --- a/programmer.h +++ b/programmer.h @@ -529,9 +529,18 @@ struct spi_programmer { int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write_256)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write_aai)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); + /* Returns 0 if the supplied data can be sent by this programmer. Possible error codes include: + * SPI_INVALID_LENGTH if readcnt, writecnt or their combination is not allowed + * negative values if readcnt is too big + * positive values if writecnt is too big */ + int (*check_trans)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr); + int (*check_transs)(struct flashctx *flash, struct spi_command *cmds); const void *data; }; +int default_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr); int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..9acf476 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -89,33 +89,37 @@ static void execute_command(void) ; } +static int sb600_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + /* We expect 1 opcode byte plus up to 8 data bytes (in any direction): + * the opcode has its own register, the data bytes are sent via an 8 byte FIFO. */ + if ((writecnt == 0) || (writecnt - 1 + readcnt > 8)) { + return SPI_INVALID_LENGTH; + } + return 0; +} + + static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; - /* First byte is cmd which can not being sent through FIFO. */ - unsigned char cmd = *writearr++; + unsigned char cmd = *writearr; unsigned int readoffby1; unsigned char readwrite; - writecnt--; - - msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", - __func__, cmd, writecnt, readcnt); - - if (readcnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, " - "it is limited to 8 bytes\n", __func__, readcnt); + if (sb600_spi_check_trans(flash, writecnt, readcnt, writearr) != 0) { + msg_perr("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); return SPI_INVALID_LENGTH; } - if (writecnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not send %d bytes, " - "it is limited to 8 bytes\n", __func__, writecnt); - return SPI_INVALID_LENGTH; - } + /* First byte is cmd which can not be sent through FIFO. */ + writecnt--; + writearr++; /* This is a workaround for a bug in SB600 and SB700. If we only send * an opcode and no additional data/address, the SPI controller will @@ -123,7 +127,7 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, * the chip response is discarded and will not end up in the FIFO. * It is unclear if the CS# line is set high too early as well. */ - readoffby1 = (writecnt) ? 0 : 1; + readoffby1 = (writecnt == 0) ? 1 : 0; readwrite = (readcnt + readoffby1) << 4 | (writecnt); mmio_writeb(readwrite, sb600_spibar + 1); mmio_writeb(cmd, sb600_spibar + 0); @@ -196,13 +200,14 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, static const struct spi_programmer spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, - .max_data_read = 8, - .max_data_write = 5, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, + .max_data_read = 8, + .max_data_write = 5, + .check_trans = sb600_spi_check_trans, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, }; int sb600_probe_spi(struct pci_dev *dev) diff --git a/serprog.c b/serprog.c index b179ea4..4b0dc19 100644 --- a/serprog.c +++ b/serprog.c @@ -234,31 +234,31 @@ err_out: return 1; } -static int sp_check_commandavail(uint8_t command) +static int sp_check_commandavail(uint8_t cmd) { int byteoffs, bitoffs; - byteoffs = command / 8; - bitoffs = command % 8; + byteoffs = cmd / 8; + bitoffs = cmd % 8; return (sp_cmdmap[byteoffs] & (1 << bitoffs)) ? 1 : 0; } static int sp_automatic_cmdcheck(uint8_t cmd) { - if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { - msg_pdbg("Warning: Automatic command availability check failed " - "for cmd 0x%x - won't execute cmd\n", cmd); + if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) return 1; - } return 0; } -static int sp_docommand(uint8_t command, uint32_t parmlen, +static int sp_docommand(uint8_t cmd, uint32_t parmlen, uint8_t *params, uint32_t retlen, void *retparms) { unsigned char c; - if (sp_automatic_cmdcheck(command)) + if (sp_automatic_cmdcheck(cmd)) { + msg_pdbg("Warning: Automatic command availability check failed " + "for cmd 0x%x - won't execute cmd\n", cmd); return 1; - if (write(sp_fd, &command, 1) != 1) { + } + if (write(sp_fd, &cmd, 1) != 1) { msg_perr("Error: cannot write op code: %s\n", strerror(errno)); return 1; } @@ -316,8 +316,11 @@ static void sp_flush_stream(void) static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms) { uint8_t *sp; - if (sp_automatic_cmdcheck(cmd)) + if (sp_automatic_cmdcheck(cmd)) { + msg_pdbg("Warning: Automatic command availability check failed " + "for cmd 0x%x - won't execute cmd\n", cmd); return 1; + } sp = malloc(1 + parmlen); if (!sp) sp_die("Error: cannot malloc command buffer"); sp[0] = cmd; @@ -332,6 +335,12 @@ static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms) return 0; } +static int serprog_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + return sp_automatic_cmdcheck(S_CMD_O_SPIOP); +} + static int serprog_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -342,6 +351,7 @@ static struct spi_programmer spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .check_trans = serprog_spi_check_trans, .command = serprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = serprog_spi_read, diff --git a/spi.c b/spi.c index 94a76a7..046d095 100644 --- a/spi.c +++ b/spi.c @@ -30,12 +30,17 @@ #include "programmer.h" #include "spi.h" +int default_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + return 0; +} + int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - return flash->pgm->spi.command(flash, writecnt, readcnt, writearr, - readarr); + return flash->pgm->spi.command(flash, writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) diff --git a/wbsio_spi.c b/wbsio_spi.c index 778b983..ec14c28 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -108,6 +108,15 @@ static uint8_t determine_mode(struct flashctx *flash, unsigned int writecnt, uns return 0; } +static int wbsio_spi_check_trans(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + if (determine_mode(flash, writecnt, readcnt, writearr) == 0) + return SPI_INVALID_LENGTH; + + return 0; +} + static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -119,6 +128,7 @@ static const struct spi_programmer spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, + .check_trans = wbsio_spi_check_trans, .command = wbsio_spi_send_command, .multicommand = default_spi_send_multicommand, .read = wbsio_spi_read, -- Kind regards, Stefan Tauner

1 0

[PATCH 2/5] Prepare wbsio_spi.c for check_trans().
by Stefan Tauner 03 Oct '12

03 Oct '12

Introduce determine_mode() which contains the extracted bits of the init function that do sanity checks but without altering the hardware state. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- wbsio_spi.c | 136 +++++++++++++++++++++++++++++++++-------------------------- 1 file changed, 77 insertions(+), 59 deletions(-) diff --git a/wbsio_spi.c b/wbsio_spi.c index 7d4bb2a..778b983 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -61,6 +61,53 @@ done: return flashport; } +/* W83627DHG has 11 command modes: + * 1=1 command only + * 2=1 command+1 data write + * 3=1 command+2 data read + * 4=1 command+3 address + * 5=1 command+3 address+1 data write + * 6=1 command+3 address+4 data write + * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read + * 8=1 command+3 address+1 data read + * 9=1 command+3 address+2 data read + * a=1 command+3 address+3 data read + * b=1 command+3 address+4 data read + * + * mode[7:4] holds the command mode + * mode[3:0] holds SPI address bits [19:16] + * + * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\ + * Would one more byte of RAM in the chip (to get all 24 bits) really make + * such a big difference? + */ +static uint8_t determine_mode(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr) +{ + if (1 == writecnt && 0 == readcnt) { + return 0x10; + } else if (2 == writecnt && 0 == readcnt) { + return 0x20; + } else if (1 == writecnt && 2 == readcnt) { + return 0x30; + } else if (4 == writecnt && 0 == readcnt) { + return 0x40 | (writearr[1] & 0x0f); + } else if (5 == writecnt && 0 == readcnt) { + return 0x50 | (writearr[1] & 0x0f); + } else if (8 == writecnt && 0 == readcnt) { + return 0x60 | (writearr[1] & 0x0f); + } else if (5 == writecnt && 4 == readcnt) { + /* XXX: TODO not supported by flashrom infrastructure! + * This mode, 7, discards the fifth byte in writecnt, + * but since we can not express that in flashrom, fail + * the operation for now. + */; + } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { + return ((7 + readcnt) << 4) | (writearr[1] & 0x0f); + } + return 0; +} + static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -95,52 +142,37 @@ int wbsio_check_for_spi(void) return 0; } -/* W83627DHG has 11 command modes: - * 1=1 command only - * 2=1 command+1 data write - * 3=1 command+2 data read - * 4=1 command+3 address - * 5=1 command+3 address+1 data write - * 6=1 command+3 address+4 data write - * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read - * 8=1 command+3 address+1 data read - * 9=1 command+3 address+2 data read - * a=1 command+3 address+3 data read - * b=1 command+3 address+4 data read - * - * mode[7:4] holds the command mode - * mode[3:0] holds SPI address bits [19:16] - * - * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\ - * Would one more byte of RAM in the chip (to get all 24 bits) really make - * such a big difference? - */ static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; - uint8_t mode = 0; + uint8_t mode = determine_mode(flash, writecnt, readcnt, writearr); - msg_pspew("%s:", __func__); + if (!mode) { + msg_perr("%s: unsupported command type wr=%d rd=%d\n", + __func__, writecnt, readcnt); + /* Command type refers to the number of bytes read/written. */ + return SPI_INVALID_LENGTH; + } - if (1 == writecnt && 0 == readcnt) { - mode = 0x10; - } else if (2 == writecnt && 0 == readcnt) { + msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); + switch (mode & 0xF0) { + case 0x10: break; + case 0x20: OUTB(writearr[1], wbsio_spibase + 4); msg_pspew(" data=0x%02x", writearr[1]); - mode = 0x20; - } else if (1 == writecnt && 2 == readcnt) { - mode = 0x30; - } else if (4 == writecnt && 0 == readcnt) { + break; + case 0x30: break; + case 0x40: msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { OUTB(writearr[i], wbsio_spibase + i); msg_pspew("%02x", writearr[i]); } - mode = 0x40 | (writearr[1] & 0x0f); - } else if (5 == writecnt && 0 == readcnt) { + break; + case 0x50: msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { OUTB(writearr[i], wbsio_spibase + i); @@ -148,8 +180,8 @@ static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, } OUTB(writearr[i], wbsio_spibase + i); msg_pspew(" data=0x%02x", writearr[i]); - mode = 0x50 | (writearr[1] & 0x0f); - } else if (8 == writecnt && 0 == readcnt) { + break; + case 0x60: msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { OUTB(writearr[i], wbsio_spibase + i); @@ -160,44 +192,30 @@ static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt, OUTB(writearr[i], wbsio_spibase + i); msg_pspew("%02x", writearr[i]); } - mode = 0x60 | (writearr[1] & 0x0f); - } else if (5 == writecnt && 4 == readcnt) { - /* XXX: TODO not supported by flashrom infrastructure! - * This mode, 7, discards the fifth byte in writecnt, - * but since we can not express that in flashrom, fail - * the operation for now. - */ - ; - } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { + break; + case 0x70: /* unimplemented */ + break; + default: msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { OUTB(writearr[i], wbsio_spibase + i); msg_pspew("%02x", writearr[i]); } - mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); - } - msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); - - if (!mode) { - msg_perr("%s: unsupported command type wr=%d rd=%d\n", - __func__, writecnt, readcnt); - /* Command type refers to the number of bytes read/written. */ - return SPI_INVALID_LENGTH; + break; } OUTB(writearr[0], wbsio_spibase); OUTB(mode, wbsio_spibase + 1); programmer_delay(10); - if (!readcnt) - return 0; - - msg_pspew("%s: returning data =", __func__); - for (i = 0; i < readcnt; i++) { - readarr[i] = INB(wbsio_spibase + 4 + i); - msg_pspew(" 0x%02x", readarr[i]); + if (readcnt > 0) { + msg_pspew("%s: returning data =", __func__); + for (i = 0; i < readcnt; i++) { + readarr[i] = INB(wbsio_spibase + 4 + i); + msg_pspew(" 0x%02x", readarr[i]); + } + msg_pspew("\n"); } - msg_pspew("\n"); return 0; } -- Kind regards, Stefan Tauner

1 0

[PATCH 1/5] Refactor ichspi and prepare it for check_trans().
by Stefan Tauner 03 Oct '12

03 Oct '12

- Introduce prepare_opcode() which does: * find the offset of an opcode or reprogram the OPMENU as necessary * check if the writecnt and readcnt are legit for the transaction type * ensure that the allowed BBAR is obeyed. - Merge lookup_spi_type() and parts of reprogram_opcode_on_the_fly() into determine_spitype(). - Verify the writes in program_opcodes() and use it in error handling. - Refactor ich_spi_send_multicommand() to utilize above changes. - General cleanup of variable and constant names, among others: * opcode_index -> oppos everywhere * shortening of SPI_OPCODE_TYPE_* Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flash.h | 1 + ichspi.c | 347 +++++++++++++++++++++++++++++++++++--------------------------- 2 files changed, 196 insertions(+), 152 deletions(-) diff --git a/flash.h b/flash.h index 4913536..3230849 100644 --- a/flash.h +++ b/flash.h @@ -24,6 +24,7 @@ #ifndef __FLASH_H__ #define __FLASH_H__ 1 +#include <stdbool.h> #include <stdint.h> #include <stddef.h> #ifdef _WIN32 diff --git a/ichspi.c b/ichspi.c index 8dd1893..e60913c 100644 --- a/ichspi.c +++ b/ichspi.c @@ -135,10 +135,10 @@ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) // ICH9R SPI commands -#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 -#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 -#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 -#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 +#define READING_OP_NO_ADDR 0 +#define WRITING_OP_NO_ADDR 1 +#define READING_OP_WITH_ADDR 2 +#define WRITING_OP_WITH_ADDR 3 // ICH7 registers #define ICH7_REG_SPIS 0x00 /* 16 Bits */ @@ -261,14 +261,14 @@ static OPCODES O_ST_M25P = { JEDEC_EWSR, }, { - {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte - {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data - {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector - {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature - {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register - {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID - {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase + {JEDEC_BYTE_PROGRAM, WRITING_OP_WITH_ADDR, 0}, // Write Byte + {JEDEC_READ, READING_OP_WITH_ADDR, 0}, // Read Data + {JEDEC_BE_D8, WRITING_OP_WITH_ADDR, 0}, // Erase Sector + {JEDEC_RDSR, READING_OP_NO_ADDR, 0}, // Read Device Status Reg + {JEDEC_REMS, READING_OP_WITH_ADDR, 0}, // Read Electronic Manufacturer Signature + {JEDEC_WRSR, WRITING_OP_NO_ADDR, 0}, // Write Status Register + {JEDEC_RDID, READING_OP_NO_ADDR, 0}, // Read JDEC ID + {JEDEC_CE_C7, WRITING_OP_NO_ADDR, 0}, // Bulk erase } }; @@ -277,17 +277,17 @@ static OPCODES O_ST_M25P = { * is needed which is currently not in the chipset OPCODE table */ static OPCODE POSSIBLE_OPCODES[] = { - {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte - {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data - {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector - {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature - {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register - {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID - {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase - {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase - {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase - {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment + {JEDEC_BYTE_PROGRAM, WRITING_OP_WITH_ADDR, 0}, // Write Byte + {JEDEC_READ, READING_OP_WITH_ADDR, 0}, // Read Data + {JEDEC_BE_D8, WRITING_OP_WITH_ADDR, 0}, // Erase Sector + {JEDEC_RDSR, READING_OP_NO_ADDR, 0}, // Read Device Status Reg + {JEDEC_REMS, READING_OP_WITH_ADDR, 0}, // Read Electronic Manufacturer Signature + {JEDEC_WRSR, WRITING_OP_NO_ADDR, 0}, // Write Status Register + {JEDEC_RDID, READING_OP_NO_ADDR, 0}, // Read JDEC ID + {JEDEC_CE_C7, WRITING_OP_NO_ADDR, 0}, // Bulk erase + {JEDEC_SE, WRITING_OP_WITH_ADDR, 0}, // Sector erase + {JEDEC_BE_52, WRITING_OP_WITH_ADDR, 0}, // Block erase + {JEDEC_AAI_WORD_PROGRAM, WRITING_OP_NO_ADDR, 0}, // Auto Address Increment }; static OPCODES O_EXISTING = {}; @@ -370,66 +370,61 @@ static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) pprint_reg(SSFC, SCF, reg_val, "\n"); } -static uint8_t lookup_spi_type(uint8_t opcode) +static uint8_t determine_spitype(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) { - int a; - - for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) { - if (POSSIBLE_OPCODES[a].opcode == opcode) - return POSSIBLE_OPCODES[a].spi_type; + int i; + for (i = 0; i < ARRAY_SIZE(POSSIBLE_OPCODES); i++) { + if (POSSIBLE_OPCODES[i].opcode == opcode) + return POSSIBLE_OPCODES[i].spi_type; } - return 0xFF; + /* Try to guess spi type from read/write sizes. + * The following valid writecnt/readcnt combinations exist: + * writecnt = 4, readcnt >= 0 + * writecnt = 1, readcnt >= 0 + * writecnt >= 4, readcnt = 0 + * writecnt >= 1, readcnt = 0 + * writecnt >= 1 is guaranteed for all commands. + */ + msg_pspew("Need to guess spitype from payload lengths.\n"); + if (readcnt == 0) + /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS + * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data + * bytes are actual the address, they go to the bus anyhow + */ + return WRITING_OP_NO_ADDR; + else if (writecnt == 1) // and readcnt is > 0 + return READING_OP_NO_ADDR; + else if (writecnt == 4) // and readcnt is > 0 + return READING_OP_WITH_ADDR; + else // we have an invalid case + return 0xFF; } -static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +static int reprogram_opcode_on_the_fly(uint8_t opcode, uint8_t spi_type, unsigned int writecnt, unsigned int readcnt) { - uint8_t spi_type; - - spi_type = lookup_spi_type(opcode); - if (spi_type > 3) { - /* Try to guess spi type from read/write sizes. - * The following valid writecnt/readcnt combinations exist: - * writecnt = 4, readcnt >= 0 - * writecnt = 1, readcnt >= 0 - * writecnt >= 4, readcnt = 0 - * writecnt >= 1, readcnt = 0 - * writecnt >= 1 is guaranteed for all commands. - */ - if (readcnt == 0) - /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS - * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data - * bytes are actual the address, they go to the bus anyhow - */ - spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - else if (writecnt == 1) // and readcnt is > 0 - spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - else if (writecnt == 4) // and readcnt is > 0 - spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - else // we have an invalid case - return SPI_INVALID_LENGTH; - } - int oppos = 2; // use original JEDEC_BE_D8 offset + int ret; + const int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0); - oppos = find_opcode(curopcodes, opcode); - msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); - return oppos; + ret = program_opcodes(curopcodes, 0); + if (ret == 0) + msg_pdbg2("OPCODE (0x%02X) re-programmed on-the-fly, op-pos=%d\n", opcode, oppos); + return ret; } static int find_opcode(OPCODES *op, uint8_t opcode) { - int a; + int i; if (op == NULL) { msg_perr("\n%s: null OPCODES pointer!\n", __func__); return -1; } - for (a = 0; a < 8; a++) { - if (op->opcode[a].opcode == opcode) - return a; + for (i = 0; i < 8; i++) { + if (op->opcode[i].opcode == opcode) + return i; } return -1; @@ -549,6 +544,14 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); + + if ((preop != mmio_readw(ich_spibar + ICH7_REG_PREOP)) || + (optype != mmio_readw(ich_spibar + ICH7_REG_OPTYPE)) || + (opmenu[0] != mmio_readl(ich_spibar + ICH7_REG_OPMENU)) || + (opmenu[1] != mmio_readl(ich_spibar + ICH7_REG_OPMENU + 4))) { + msg_perr("Programming opcodes failed.\n"); + return 1; + } break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -563,6 +566,13 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); + if ((preop != mmio_readw(ich_spibar + ICH9_REG_PREOP)) || + (optype != mmio_readw(ich_spibar + ICH9_REG_OPTYPE)) || + (opmenu[0] != mmio_readl(ich_spibar + ICH9_REG_OPMENU)) || + (opmenu[1] != mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4))) { + msg_perr("Programming opcodes failed.\n"); + return 1; + } break; } @@ -720,11 +730,11 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, uint32_t temp32; uint16_t temp16; uint64_t opmenu; - int opcode_index; + int oppos; /* Is it a write command? */ - if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) - || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { + if ((op.spi_type == WRITING_OP_NO_ADDR) + || (op.spi_type == WRITING_OP_WITH_ADDR)) { write_cmd = 1; } @@ -765,17 +775,17 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, opmenu = REGREAD32(ICH7_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; - for (opcode_index = 0; opcode_index < 8; opcode_index++) { + for (oppos = 0; oppos < 8; oppos++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } - if (opcode_index == 8) { + if (oppos == 8) { msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } - temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; + temp16 |= ((uint16_t) (oppos & 0x07)) << 4; timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ /* Handle Atomic. Atomic commands include three steps: @@ -837,11 +847,10 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int timeout; uint32_t temp32; uint64_t opmenu; - int opcode_index; + int oppos; /* Is it a write command? */ - if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) - || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { + if ((op.spi_type == WRITING_OP_NO_ADDR) || (op.spi_type == WRITING_OP_WITH_ADDR)) { write_cmd = 1; } @@ -887,17 +896,17 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, opmenu = REGREAD32(ICH9_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; - for (opcode_index = 0; opcode_index < 8; opcode_index++) { + for (oppos = 0; oppos < 8; oppos++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } - if (opcode_index == 8) { + if (oppos == 8) { msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } - temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); + temp32 |= ((uint32_t) (oppos & 0x07)) << (8 + 4); timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ /* Handle Atomic. Atomic commands include three steps: @@ -982,86 +991,114 @@ static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, } } -static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, - unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) +/* Check command and prepare the appropriate opcode. + * The selected OPCODE will be returned in opcodep if it can be determined. + * If the dryrun flag is set, try do determine opcode sanity and availability only, do not change hw state + * (i.e. do not touch OPMENU). In that case opcodep is unused. */ +static int prepare_opcode(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, bool dryrun, OPCODE **opcodep) { - int result; - int opcode_index = -1; - const unsigned char cmd = *writearr; - OPCODE *opcode; - uint32_t addr = 0; - uint8_t *data; - int count; + OPCODE *opcode = NULL; + OPCODE emu_op = {0}; + if (writecnt == 0) + return SPI_INVALID_LENGTH; - /* find cmd in opcodes-table */ - opcode_index = find_opcode(curopcodes, cmd); - if (opcode_index == -1) { - if (!ichspi_lock) - opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); - if (opcode_index == SPI_INVALID_LENGTH) { - msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); + /* ensure that the requested opcode is available */ + int oppos = find_opcode(curopcodes, writearr[0]); + if (oppos >= 0) { + opcode = &(curopcodes->opcode[oppos]); + } else { + uint8_t spi_type = determine_spitype(writearr[0], writecnt, readcnt); + if (spi_type == 0xFF) { + if (!dryrun) + msg_pdbg("Could not determine spitype for opcode 0x%02x.\n", writearr[0]); return SPI_INVALID_LENGTH; - } else if (opcode_index == -1) { - msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", - cmd); + } + if (ichspi_lock) { + if (!dryrun) + msg_pdbg("OPCODES locked down and do not contain 0x%02x, can not execute.\n", + writearr[0]); return SPI_INVALID_OPCODE; + } else { + /* In a dryrun we expect that reprogramming works successfully, but we need to create + * an OPCODE object for the tests below. */ + if (dryrun) { + emu_op.opcode = writearr[0]; + emu_op.spi_type = spi_type; + opcode = &emu_op; + } else { + if (reprogram_opcode_on_the_fly(writearr[0], spi_type, writecnt, readcnt) != 0) + return SPI_GENERIC_ERROR; + oppos = find_opcode(curopcodes, writearr[0]); + opcode = &(curopcodes->opcode[oppos]); + } } } - opcode = &(curopcodes->opcode[opcode_index]); - /* The following valid writecnt/readcnt combinations exist: * writecnt = 4, readcnt >= 0 * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 - * writecnt >= 1 is guaranteed for all commands. - */ - if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && - (writecnt != 4)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, - writecnt); + * writecnt >= 1 is guaranteed for all commands. */ + if ((opcode->spi_type == READING_OP_WITH_ADDR) && (writecnt != 4)) { + if (!dryrun) + msg_perr("%s: Reading command requires an opcode (0x%02x) and exactly 3 address bytes, " + "but writecnt=%i.\n", __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } - if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && - (writecnt != 1)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, - writecnt); + if ((opcode->spi_type == READING_OP_NO_ADDR) && (writecnt != 1)) { + if (!dryrun) + msg_perr("%s: Reading command requires an opcode (0x%02x) without address bytes, " + "but writecnt=%i.\n", __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } - if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && - (writecnt < 4)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, - writecnt); + if ((opcode->spi_type == WRITING_OP_WITH_ADDR) && (writecnt < 4)) { + if (!dryrun) + msg_perr("%s: Writing command requires at least an opcode (0x%02x) and exactly " + "3 address bytes, but writecnt=%i.\n", __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } - if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || - (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && - (readcnt)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, - readcnt); + if (((opcode->spi_type == WRITING_OP_WITH_ADDR) || (opcode->spi_type == WRITING_OP_NO_ADDR)) && + (readcnt > 0)) { + if (!dryrun) + msg_perr("%s: Writing command with opcode (0x%02x) can read not bytes, " + "but readcnt=%i.\n", __func__, writearr[0], readcnt); return SPI_INVALID_LENGTH; } - /* if opcode-type requires an address */ - if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || - opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { - addr = (writearr[1] << 16) | - (writearr[2] << 8) | (writearr[3] << 0); + /* If the opcode type requires an address we check if it is below the allowed base. */ + if (opcode->spi_type == READING_OP_WITH_ADDR || opcode->spi_type == WRITING_OP_WITH_ADDR) { + uint32_t addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); + msg_perr("%s: Address 0x%06x below allowed range 0x%06x-0xffffff\n", + __func__, addr, ichspi_bbar); return SPI_INVALID_ADDRESS; } } + if (opcodep != NULL) + *opcodep = opcode; + return 0; +} + +static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + OPCODE *opcode; + uint32_t addr; + uint8_t *data; + int count; + + int result = prepare_opcode(flash, writecnt, readcnt, writearr, false, &opcode); + if (result != 0) { + msg_pspew("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); + return result; + } + /* Translate read/write array/count. * The maximum data length is identical for the maximum read length and * for the maximum write length excluding opcode and address. Opcode and @@ -1069,10 +1106,10 @@ static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, * and are thus not counted towards data length. The only exception * applies if the opcode definition (un)intentionally classifies said * opcode incorrectly as non-address opcode or vice versa. */ - if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { + if (opcode->spi_type == WRITING_OP_NO_ADDR) { data = (uint8_t *) (writearr + 1); count = writecnt - 1; - } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { + } else if (opcode->spi_type == WRITING_OP_WITH_ADDR) { data = (uint8_t *) (writearr + 4); count = writecnt - 4; } else { @@ -1080,11 +1117,11 @@ static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, count = readcnt; } + addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); result = run_opcode(flash, *opcode, addr, count, data); if (result) { msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); - if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || - (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { + if ((opcode->spi_type == WRITING_OP_WITH_ADDR) || (opcode->spi_type == READING_OP_WITH_ADDR)) { msg_pdbg("at address 0x%06x ", addr); } msg_pdbg("(payload length was %d).\n", count); @@ -1092,8 +1129,7 @@ static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, /* Print out the data array if it contains data to write. * Errors are detected before the received data is read back into * the array so it won't make sense to print it then. */ - if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || - (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { + if ((opcode->spi_type == WRITING_OP_WITH_ADDR) || (opcode->spi_type == WRITING_OP_NO_ADDR)) { int i; msg_pspew("The data was:\n"); for (i = 0; i < count; i++){ @@ -1358,17 +1394,17 @@ static int ich_hwseq_write(struct flashctx *flash, uint8_t *buf, return 0; } -static int ich_spi_send_multicommand(struct flashctx *flash, - struct spi_command *cmds) +static int ich_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) { int ret = 0; int i; int oppos, preoppos; for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { - if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { + struct spi_command *cmd_nxt = cmds + 1; + if (cmd_nxt->writecnt || cmd_nxt->readcnt) { /* Next command is valid. */ preoppos = find_preop(curopcodes, cmds->writearr[0]); - oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + oppos = find_opcode(curopcodes, cmd_nxt->writearr[0]); if ((oppos == -1) && (preoppos != -1)) { /* Current command is listed as preopcode in * ICH struct OPCODES, but next command is not @@ -1376,13 +1412,10 @@ static int ich_spi_send_multicommand(struct flashctx *flash, * Check for command sanity, then * try to reprogram the ICH opcode list. */ - if (find_preop(curopcodes, - (cmds + 1)->writearr[0]) != -1) { - msg_perr("%s: Two subsequent " - "preopcodes 0x%02x and 0x%02x, " + if (find_preop(curopcodes, cmd_nxt->writearr[0]) != -1) { + msg_perr("%s: Two subsequent preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", - __func__, cmds->writearr[0], - (cmds + 1)->writearr[0]); + __func__, cmds->writearr[0], cmd_nxt->writearr[0]); continue; } /* If the chipset is locked down, we'll fail @@ -1390,7 +1423,19 @@ static int ich_spi_send_multicommand(struct flashctx *flash, * No need to bother with fixups. */ if (!ichspi_lock) { - oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + uint8_t spi_type = determine_spitype(cmd_nxt->writearr[0], + cmd_nxt->writecnt, + cmd_nxt->readcnt); + if (spi_type == 0xFF) { + msg_pdbg("Could not determine spitype for opcode 0x%02x.\n", + cmd_nxt->writearr[0]); + return SPI_INVALID_LENGTH; + } + ret = reprogram_opcode_on_the_fly(cmd_nxt->writearr[0], spi_type, + cmd_nxt->writecnt, cmd_nxt->readcnt); + if (ret == -1) + continue; + oppos = find_opcode(curopcodes, cmd_nxt->writearr[0]); if (oppos == -1) continue; curopcodes->opcode[oppos].atomic = preoppos + 1; @@ -1793,10 +1838,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } } - if (ich_spi_mode == ich_auto && ichspi_lock && - ich_missing_opcodes()) { - msg_pinfo("Enabling hardware sequencing because " - "some important opcode is locked.\n"); + if (ich_spi_mode == ich_auto && ichspi_lock && ich_missing_opcodes()) { + msg_pinfo("Enabling hardware sequencing because an important opcode is unavailable.\n"); ich_spi_mode = ich_hwseq; } -- Kind regards, Stefan Tauner

1 0

[PATCH 0/5] check_trans and probe_spi_rdid_edi
by Stefan Tauner 03 Oct '12

03 Oct '12

This patch set enables us to figure out if transactions will succeed without executing them, which allows for a refactoring of probe_spi_rdid_generic() which in consequence makes it possible to add probe_spi_rdid_edi(). The infrastructure code as a whole, but especially the ichspi code is heavily modified. Please be aware of that if you test it on mainboards. Antonio: please rebase your Spansion patch on this one and extend it to add actually two chips by using the full 32 bit model IDs (0x20184d00, 0x20184d01) and .probe = probe_spi_rdid_edi. Stefan Tauner (5): Refactor ichspi and prepare it for check_trans(). Prepare wbsio_spi.c for check_trans(). Introduce check_trans(). Generify probe_spi_rdid_generic() and add probe_spi_rdid_edi(). Let the dummy programmer emulate SPI payload limitations. bitbang_spi.c | 1 + buspirate_spi.c | 14 ++- dediprog.c | 24 ++-- dummyflasher.c | 16 ++- flash.h | 1 + flashchips.c | 24 ++-- flashchips.h | 2 +- ft2232_spi.c | 14 ++- ichspi.c | 356 +++++++++++++++++++++++++++++++------------------------ it85spi.c | 1 + it87spi.c | 31 +++-- linux_spi.c | 31 +++-- programmer.h | 11 ++ sb600spi.c | 51 ++++---- serprog.c | 32 +++-- spi.c | 9 +- spi25.c | 97 +++++++-------- wbsio_spi.c | 146 ++++++++++++++--------- 18 files changed, 527 insertions(+), 334 deletions(-) This is the output of the dummy programmer to show the new behavior: flashrom v0.9.6.1-r1611 on Linux 3.2.0-31-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian Command line (3 args): ./flashrom -p dummy:bus=SPI,spi_prog=wbsio,emulate=M25P10.RES -V Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 10 us, 100 myus = 127 us, 1000 myus = 1023 us, 10000 myus = 10024 us, 4 myus = 10 us, OK. Initializing dummy programmer Requested buses are: SPI Enabling support for SPI flash. Emulating ST M25P10.RES SPI flash chip (RES, page write) Using SPI payload limitations of the wbsio programmer. Filling fake flash chip with 0xff, size 131072 The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L05PU, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L10PT, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L10PU, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L20PT, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L20PU, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L40PT, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L40PU, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L80P, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L16PT, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L16PU, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L512, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L010, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L020, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L040, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L080, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L016, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25L032, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for AMIC A25LQ032, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF021, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF041A, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF081, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF081A, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF161, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF321, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF321A, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DF641(A), 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25DQ161, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25F512B, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25FS010, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT25FS040, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT26DF041, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT26DF081A, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT26DF161, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT26DF161A, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT26F004, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45CS1282, 16896 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB011D, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB021D, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB041D, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB081D, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB161D, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB321C, 4224 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB321D, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel AT45DB642D, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for EMST F25L008A, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B05, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B05T, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B10, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B10T, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B20T, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B40T, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B80T, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B16T, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B32T, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25B64T, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F05, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F10, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25F64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q80(A), 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q32(A/B), 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25Q128, 16384 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25QH16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon EN25QH32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25Q128, 16384 kB: 3 byte RDID not supported on this SPI controller. Probing for GigaDevice GD25LQ32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L512, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L1005, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L2005, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L4005, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L8005, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L1605, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L1635D, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L1635E, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L3205, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L3235D, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L6405, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix MX25L12805, 16384 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx M25PE10, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx M25PE20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx M25PE40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx M25PE80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx M25PE16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Numonyx N25Q064, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV010, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV016B, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV020, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV040, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV080B, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC Pm25LV512, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for Sanyo LF25FW203A, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Spansion S25FL004A, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Spansion S25FL008A, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Spansion S25FL016A, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Spansion S25FL032A, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Spansion S25FL064A, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x10, id2 0x10 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x10, id2 0x10 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF016B, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25VF032B, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25VF064C, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF040B, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF080B, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25WF512, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25WF010, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25WF020, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for SST SST25WF040, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P05-A, 64 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P05, 64 kB: probe_spi_res1: id 0x10 Chip status register is 00 Found ST flash chip "M25P05" (64 kB, SPI) on dummy. Probing for ST M25P10-A, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P10, 128 kB: probe_spi_res1: id 0x10 Chip status register is 00 Found ST flash chip "M25P10" (128 kB, SPI) on dummy. Probing for ST M25P20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P40-old, 512 kB: probe_spi_res1: id 0x10 Probing for ST M25P80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25P128, 16384 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25PX16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25PX32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for ST M25PX64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25Q80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25Q16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25Q32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25Q64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25Q128, 16384 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X10, 128 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X20, 256 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X40, 512 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X80, 1024 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X16, 2048 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X32, 4096 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond W25X64, 8192 kB: 3 byte RDID not supported on this SPI controller. Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Atmel unknown Atmel SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Eon unknown Eon SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Macronix unknown Macronix SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for PMC unknown PMC SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for SST unknown SST SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for ST unknown ST SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Sanyo unknown Sanyo SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Generic unknown SPI chip (RDID), 0 kB: 3 byte RDID not supported on this SPI controller. Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff Multiple flash chips were detected: "M25P05", "M25P10" Please specify which chip to use with the -c <chipname> option. -- Kind regards, Stefan Tauner

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Re: [flashrom] Foxconn P55mx\H55mx
by Stefan Tauner 02 Oct '12

02 Oct '12

On Tue, 2 Oct 2012 18:02:12 +0400 Владислав Быков <vladislavbyk1(a)gmail.com> wrote: > No problem :3 Thanks a lot! This proves that the register contents of the locking registers are indeed altered by the pin and that flashrom will automatically pick that information up and just works. I'll add a note to the entry of your board and will change the lock message accordingly. > Btw, maybe you have jabber or icq? :) It would be convenient) I am somewhat flattered, but i prefer public communication by mail. This way it gets archived and can help other people in the future. If you want to chat with me/us, you are welcomed to join our IRC channel (#flashrom) on freenode (chat.freenode.net). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] Foxconn P55mx\H55mx
by Idwer Vollering 02 Oct '12

02 Oct '12

2012/10/2 Владислав Быков <vladislavbyk1(a)gmail.com>: > No problem :3 > Default jumper position (enabled): >> >> >> sudo flashrom -p internal -VV >> [sudo] password for vladislavbyk: >> flashrom v0.9.6.1-r1564 on Linux 3.5.4-1-ARCH (i686) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> flashrom was built with libpci 3.1.10, GCC 4.7.1 20120721 (prerelease), >> little endian >> Command line (3 args): flashrom -p internal -VV >> Calibrating delay loop... OS timer resolution is 1 usecs, 1355M loops per >> second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 1126 us, 10000 myus = >> 9925 us, 4 myus = 4 us, OK. >> >> Initializing internal programmer >> No coreboot table found. >> DMI string system-manufacturer: "To Be Filled By O.E.M." >> DMI string system-product-name: "To Be Filled By O.E.M." >> DMI string system-version: "To Be Filled By O.E.M." >> DMI string baseboard-manufacturer: "Foxconn" >> DMI string baseboard-product-name: "H55MX-S Series" >> DMI string baseboard-version: "1.1" >> DMI string chassis-type: "Desktop" >> Found ITE Super I/O, ID 0x8720 on port 0x2e >> Found chipset "Intel H55" with PCI ID 8086:3b06. Enabling flash write... >> 0xfff80000/0xffb80000 FWH IDSEL: 0x0 >> 0xfff00000/0xffb00000 FWH IDSEL: 0x0 >> 0xffe80000/0xffa80000 FWH IDSEL: 0x1 >> 0xffe00000/0xffa00000 FWH IDSEL: 0x1 >> 0xffd80000/0xff980000 FWH IDSEL: 0x2 >> 0xffd00000/0xff900000 FWH IDSEL: 0x2 >> 0xffc80000/0xff880000 FWH IDSEL: 0x3 >> 0xffc00000/0xff800000 FWH IDSEL: 0x3 >> 0xff700000/0xff300000 FWH IDSEL: 0x4 >> 0xff600000/0xff200000 FWH IDSEL: 0x5 >> 0xff500000/0xff100000 FWH IDSEL: 0x6 >> 0xff400000/0xff000000 FWH IDSEL: 0x7 >> 0xfff80000/0xffb80000 FWH decode enabled >> 0xfff00000/0xffb00000 FWH decode enabled >> 0xffe80000/0xffa80000 FWH decode disabled >> 0xffe00000/0xffa00000 FWH decode disabled >> 0xffd80000/0xff980000 FWH decode disabled >> 0xffd00000/0xff900000 FWH decode disabled >> 0xffc80000/0xff880000 FWH decode disabled >> 0xffc00000/0xff800000 FWH decode disabled >> 0xff700000/0xff300000 FWH decode disabled >> 0xff600000/0xff200000 FWH decode disabled >> 0xff500000/0xff100000 FWH decode disabled >> 0xff400000/0xff000000 FWH decode disabled >> Maximum FWH chip size: 0x100000 bytes >> BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 >> Root Complex Register Block address = 0xfed1c000 >> GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 >> (SPI) >> Top Swap : not enabled >> SPIBAR = 0xfed1c000 + 0x3800 >> 0x04: 0x6008 (HSFS) >> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, >> FLOCKDN=0 >> Programming OPCODES... >> program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 >> done >> OP Type Pre-OP >> op[0]: 0x02, write w/ addr, none >> op[1]: 0x03, read w/ addr, none >> op[2]: 0xd8, write w/ addr, none >> op[3]: 0x05, read w/o addr, none >> op[4]: 0x90, read w/ addr, none >> op[5]: 0x01, write w/o addr, none >> op[6]: 0x9f, read w/o addr, none >> op[7]: 0xc7, write w/o addr, none >> Pre-OP 0: 0x06, Pre-OP 1: 0x50 >> >> 0x06: 0x0000 (HSFC) >> HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 >> 0x08: 0x00000000 (FADDR) >> 0x50: 0x00000a0b (FRAP) >> BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b >> 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region >> (0x00000000-0x00000fff) is read-only. >> >> 0x58: 0x07ff0700 FREG1: BIOS region (0x00700000-0x007fffff) is read-write. >> 0x5C: 0x06ff0001 FREG2: WARNING: Management Engine region >> (0x00001000-0x006fffff) is locked. >> 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. >> 0x64: 0x00001fff FREG4: Platform Data region is unused. >> 0x74: 0x00000000 (PR0 is unused) >> 0x78: 0x00000000 (PR1 is unused) >> 0x7C: 0x00000000 (PR2 is unused) >> 0x80: 0x00000000 (PR3 is unused) >> 0x84: 0x00000000 (PR4 is unused) >> Please send a verbose log to flashrom(a)flashrom.org if this board is not >> listed on >> http://flashrom.org/Supported_hardware#Supported_mainboards yet. >> Writes have been disabled. You can enforce write support with the >> ich_spi_force programmer option, but it will most likely harm your >> hardware! >> If you force flashrom you will get no support if something breaks. >> >> 0x90: 0x00 (SSFS) >> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 >> 0x91: 0xf84200 (SSFC) >> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 >> 0x94: 0x5006 (PREOP) >> 0x96: 0x463b (OPTYPE) >> 0x98: 0x05d80302 (OPMENU) >> 0x9C: 0xc79f0190 (OPMENU+4) >> 0xA0: 0x00000000 (BBAR) >> 0xC4: 0x00000000 (LVSCC) >> LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 >> 0xC8: 0x00002001 (UVSCC) >> UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20, VCL=0 >> 0xD0: 0x00000000 (FPB) >> >> Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. >> === Content Section === >> FLVALSIG 0x0ff0a55a >> FLMAP0 0x02040102 >> FLMAP1 0x10100206 >> FLMAP2 0x00000020 >> >> --- Details --- >> NR (Number of Regions): 3 >> FRBA (Flash Region Base Address): 0x040 >> NC (Number of Components): 2 >> FCBA (Flash Component Base Address): 0x020 >> ISL (ICH/PCH Strap Length): 16 >> FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 >> NM (Number of Masters): 3 >> FMBA (Flash Master Base Address): 0x060 >> MSL/PSL (MCH/PROC Strap Length): 0 >> FMSBA (Flash MCH/PROC Strap Base Address): 0x200 >> >> === Component Section === >> FLCOMP 0x0930001b >> FLILL 0x00000000 >> >> --- Details --- >> Component 1 density: 4 MB >> Component 2 density: 4 MB >> Read Clock Frequency: 20 MHz >> Read ID and Status Clock Freq.: 33 MHz >> Write and Erase Clock Freq.: 33 MHz >> Fast Read is supported. >> Fast Read Clock Frequency: 33 MHz >> No forbidden opcodes. >> >> === Region Section === >> FLREG0 0x00000000 >> FLREG1 0x07ff0700 >> FLREG2 0x06ff0001 >> FLREG3 0x00001fff >> >> --- Details --- >> Region 0 (Descr.) 0x00000000 - 0x00000fff >> Region 1 (BIOS ) 0x00700000 - 0x007fffff >> Region 2 (ME ) 0x00001000 - 0x006fffff >> Region 3 (GbE ) is unused. >> >> === Master Section === >> FLMSTR1 0x0a0b0000 >> FLMSTR2 0x0c0d0000 >> FLMSTR3 0x08080118 >> >> --- Details --- >> Descr. BIOS ME GbE Platf. >> BIOS r rw rw >> ME r rw rw >> GbE rw >> >> Enabling hardware sequencing due to multiple flash chips detected. >> SPI Read Configuration: prefetching enabled, caching enabled, OK. >> No IT87* serial flash segment enabled. >> The following protocols are supported: FWH, Programmer-specific. >> Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash >> chips with a combined density of 8192 kB. >> There is only one partition containing the whole address space (0x000000 - >> 0x7fffff). >> There are 2048 erase blocks with 4096 B each. >> Found Programmer flash chip "Opaque flash chip" (8192 kB, >> Programmer-specific) at physical address 0x0. >> Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 >> 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x02, id2 >> 0x00, id1 is normal flash content, id2 is normal flash content >> Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4e, id2 >> 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than >> supported size 1024 kB of chipset/board/programmer for FWH interface, >> probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than >> supported size 1024 kB of chipset/board/programmer for FWH interface, >> probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 >> 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4e, id2 >> 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 >> 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is >> normal flash content >> >> Found Programmer flash chip "Opaque flash chip" (8192 kB, >> Programmer-specific). >> No operations were specified. >> Restoring MMIO space at 0xb77908a0 >> Restoring MMIO space at 0xb779089c >> Restoring MMIO space at 0xb7790898 >> Restoring MMIO space at 0xb7790896 >> Restoring MMIO space at 0xb7790894 >> >> Restoring PCI config space for 00:1f:0 reg 0xdc >> >> > > > Disabled: >> >> ^[[A% >> >> sudo flashrom -p internal -VV >> [sudo] password for vladislavbyk: >> flashrom v0.9.6.1-r1564 on Linux 3.5.4-1-ARCH (i686) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> flashrom was built with libpci 3.1.10, GCC 4.7.1 20120721 (prerelease), >> little endian >> Command line (3 args): flashrom -p internal -VV >> Calibrating delay loop... OS timer resolution is 1 usecs, 1328M loops per >> second, 10 myus = 9 us, 100 myus = 96 us, 1000 myus = 1083 us, 10000 myus = >> 9907 us, 4 myus = 3 us, OK. >> >> Initializing internal programmer >> No coreboot table found. >> DMI string system-manufacturer: "To Be Filled By O.E.M." >> DMI string system-product-name: "To Be Filled By O.E.M." >> DMI string system-version: "To Be Filled By O.E.M." >> DMI string baseboard-manufacturer: "Foxconn" >> DMI string baseboard-product-name: "H55MX-S Series" >> DMI string baseboard-version: "1.1" >> DMI string chassis-type: "Desktop" >> Found ITE Super I/O, ID 0x8720 on port 0x2e >> Found chipset "Intel H55" with PCI ID 8086:3b06. Enabling flash write... >> 0xfff80000/0xffb80000 FWH IDSEL: 0x0 >> 0xfff00000/0xffb00000 FWH IDSEL: 0x0 >> 0xffe80000/0xffa80000 FWH IDSEL: 0x1 >> 0xffe00000/0xffa00000 FWH IDSEL: 0x1 >> 0xffd80000/0xff980000 FWH IDSEL: 0x2 >> 0xffd00000/0xff900000 FWH IDSEL: 0x2 >> 0xffc80000/0xff880000 FWH IDSEL: 0x3 >> 0xffc00000/0xff800000 FWH IDSEL: 0x3 >> 0xff700000/0xff300000 FWH IDSEL: 0x4 >> 0xff600000/0xff200000 FWH IDSEL: 0x5 >> 0xff500000/0xff100000 FWH IDSEL: 0x6 >> 0xff400000/0xff000000 FWH IDSEL: 0x7 >> 0xfff80000/0xffb80000 FWH decode enabled >> 0xfff00000/0xffb00000 FWH decode enabled >> 0xffe80000/0xffa80000 FWH decode disabled >> 0xffe00000/0xffa00000 FWH decode disabled >> 0xffd80000/0xff980000 FWH decode disabled >> 0xffd00000/0xff900000 FWH decode disabled >> 0xffc80000/0xff880000 FWH decode disabled >> 0xffc00000/0xff800000 FWH decode disabled >> 0xff700000/0xff300000 FWH decode disabled >> 0xff600000/0xff200000 FWH decode disabled >> 0xff500000/0xff100000 FWH decode disabled >> 0xff400000/0xff000000 FWH decode disabled >> Maximum FWH chip size: 0x100000 bytes >> BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 >> Root Complex Register Block address = 0xfed1c000 >> GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 >> (SPI) >> Top Swap : not enabled >> SPIBAR = 0xfed1c000 + 0x3800 >> 0x04: 0x4008 (HSFS) >> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, >> FLOCKDN=0 >> The Flash Descriptor Security Override Strap-Pin is set. Restrictions >> implied >> by the FRAP and FREG registers are NOT in effect. Please note that >> Protected >> Range (PR) restrictions still apply. >> Programming OPCODES... >> program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 >> done >> OP Type Pre-OP >> op[0]: 0x02, write w/ addr, none >> op[1]: 0x03, read w/ addr, none >> op[2]: 0xd8, write w/ addr, none >> op[3]: 0x05, read w/o addr, none >> op[4]: 0x90, read w/ addr, none >> op[5]: 0x01, write w/o addr, none >> op[6]: 0x9f, read w/o addr, none >> op[7]: 0xc7, write w/o addr, none >> Pre-OP 0: 0x06, Pre-OP 1: 0x50 >> >> 0x06: 0x0000 (HSFC) >> HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 >> 0x08: 0x00000000 (FADDR) >> 0x50: 0x0000ffff (FRAP) >> BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff >> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is >> read-write. >> 0x58: 0x07ff0700 FREG1: BIOS region (0x00700000-0x007fffff) is read-write. >> 0x5C: 0x06ff0001 FREG2: Management Engine region (0x00001000-0x006fffff) >> is read-write. >> 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. >> 0x64: 0x00001fff FREG4: Platform Data region is unused. >> 0x74: 0x00000000 (PR0 is unused) >> 0x78: 0x00000000 (PR1 is unused) >> 0x7C: 0x00000000 (PR2 is unused) >> 0x80: 0x00000000 (PR3 is unused) >> 0x84: 0x00000000 (PR4 is unused) >> >> 0x90: 0x00 (SSFS) >> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 >> 0x91: 0xf84200 (SSFC) >> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 >> 0x94: 0x5006 (PREOP) >> 0x96: 0x463b (OPTYPE) >> 0x98: 0x05d80302 (OPMENU) >> 0x9C: 0xc79f0190 (OPMENU+4) >> 0xA0: 0x00000000 (BBAR) >> 0xC4: 0x00000000 (LVSCC) >> LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 >> 0xC8: 0x00002001 (UVSCC) >> UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20, VCL=0 >> 0xD0: 0x00000000 (FPB) >> >> Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. >> === Content Section === >> FLVALSIG 0x0ff0a55a >> FLMAP0 0x02040102 >> FLMAP1 0x10100206 >> FLMAP2 0x00000020 >> >> --- Details --- >> NR (Number of Regions): 3 >> FRBA (Flash Region Base Address): 0x040 >> NC (Number of Components): 2 >> FCBA (Flash Component Base Address): 0x020 >> ISL (ICH/PCH Strap Length): 16 >> FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 >> NM (Number of Masters): 3 >> FMBA (Flash Master Base Address): 0x060 >> MSL/PSL (MCH/PROC Strap Length): 0 >> FMSBA (Flash MCH/PROC Strap Base Address): 0x200 >> >> === Component Section === >> FLCOMP 0x0930001b >> FLILL 0x00000000 >> >> --- Details --- >> Component 1 density: 4 MB >> Component 2 density: 4 MB >> Read Clock Frequency: 20 MHz >> Read ID and Status Clock Freq.: 33 MHz >> Write and Erase Clock Freq.: 33 MHz >> Fast Read is supported. >> Fast Read Clock Frequency: 33 MHz >> No forbidden opcodes. >> >> === Region Section === >> FLREG0 0x00000000 >> FLREG1 0x07ff0700 >> FLREG2 0x06ff0001 >> FLREG3 0x00001fff >> >> --- Details --- >> Region 0 (Descr.) 0x00000000 - 0x00000fff >> Region 1 (BIOS ) 0x00700000 - 0x007fffff >> Region 2 (ME ) 0x00001000 - 0x006fffff >> Region 3 (GbE ) is unused. >> >> === Master Section === >> FLMSTR1 0x0a0b0000 >> FLMSTR2 0x0c0d0000 >> FLMSTR3 0x08080118 >> >> --- Details --- >> Descr. BIOS ME GbE Platf. >> BIOS r rw rw >> ME r rw rw >> GbE rw >> >> Enabling hardware sequencing due to multiple flash chips detected. >> SPI Read Configuration: prefetching enabled, caching enabled, OK. >> No IT87* serial flash segment enabled. >> The following protocols are supported: FWH, Programmer-specific. >> Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash >> chips with a combined density of 8192 kB. >> There is only one partition containing the whole address space (0x000000 - >> 0x7fffff). >> There are 2048 erase blocks with 4096 B each. >> Found Programmer flash chip "Opaque flash chip" (8192 kB, >> Programmer-specific) at physical address 0x0. >> Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0x8c, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 >> 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x02, id2 >> 0x00, id1 is normal flash content, id2 is normal flash content >> Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4e, id2 >> 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, >> id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than >> supported size 1024 kB of chipset/board/programmer for FWH interface, >> probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than >> supported size 1024 kB of chipset/board/programmer for FWH interface, >> probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0x8c, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> >> Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4e, id2 0x56, id1 >> parity violation, id1 is normal flash content, id2 is normal flash content >> Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 >> 0x8c, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> >> Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 >> 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4e, id2 >> 0x56, id1 parity violation, id1 is normal flash content, id2 is normal flash >> content >> Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 >> 0x14, id2 0x8c, id1 parity violation, id1 is normal flash content, id2 is >> normal flash content >> >> Found Programmer flash chip "Opaque flash chip" (8192 kB, >> Programmer-specific). >> No operations were specified. >> Restoring MMIO space at 0xb77438a0 >> Restoring MMIO space at 0xb774389c >> Restoring MMIO space at 0xb7743898 >> Restoring MMIO space at 0xb7743896 >> Restoring MMIO space at 0xb7743894 >> >> Restoring PCI config space for 00:1f:0 reg 0xdc > > > Btw, maybe you have jabber or icq? :) It would be convenient) No, but you are welcome to join #flashrom on irc.freenode.net http://flashrom.org/IRC > 2012/10/2 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> >> >> On Tue, 2 Oct 2012 17:41:21 +0400 >> Владислав Быков <vladislavbyk1(a)gmail.com> wrote: >> >> > Yep, i toggle jumper, it's named MFG. It's should be disable (writed to >> > mainboard manual) until i start flash. >> >> Ok, thanks, can you please run "flashrom -p internal -VV" with the >> jumper in the previous/untoggled/default position and send us the >> output? I would like to know if/how the contents of the registers >> change by this exactly. This is not clearly documented publicly by >> Intel but might be helpful to us in the future. >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] Foxconn P55mx\H55mx
by Stefan Tauner 02 Oct '12

02 Oct '12

On Tue, 2 Oct 2012 17:41:21 +0400 Владислав Быков <vladislavbyk1(a)gmail.com> wrote: > Yep, i toggle jumper, it's named MFG. It's should be disable (writed to > mainboard manual) until i start flash. Ok, thanks, can you please run "flashrom -p internal -VV" with the jumper in the previous/untoggled/default position and send us the output? I would like to know if/how the contents of the registers change by this exactly. This is not clearly documented publicly by Intel but might be helpful to us in the future. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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