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[PATCH 09/12] Add support for Micron/Numonyx/ST M25PX80.
by Stefan Tauner 15 Jun '13

15 Jun '13

Also, refine status register prettyprinting and unlocking of all family members and add OTP details. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 50 ++++++++++++++++++++++++++++++++++++++++++-------- flashchips.h | 1 + 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/flashchips.c b/flashchips.c index ea67bc2..1071046 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9954,6 +9954,38 @@ const struct flashchip flashchips[] = { { .vendor = "ST", + .name = "M25PX80", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25PX80, + .total_size = 1024, + .page_size = 256, + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { { 4 * 1024, 256 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "ST", .name = "M25PX16", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -9978,8 +10010,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -9992,7 +10024,8 @@ const struct flashchip flashchips[] = { .model_id = ST_M25PX32, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PRE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -10009,8 +10042,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -10024,7 +10057,8 @@ const struct flashchip flashchips[] = { .model_id = ST_M25PX64, .total_size = 8192, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PRE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -10041,8 +10075,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ .write = spi_chip_write_256, .read = spi_chip_read, }, diff --git a/flashchips.h b/flashchips.h index 5cb84a9..e1b87c9 100644 --- a/flashchips.h +++ b/flashchips.h @@ -615,6 +615,7 @@ #define ST_M45PE40 0x4013 #define ST_M45PE80 0x4014 #define ST_M45PE16 0x4015 +#define ST_M25PX80 0x7114 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 #define ST_M25PX64 0x7117 -- Kind regards, Stefan Tauner

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[PATCH 08/12] Add support for AMIC A25LQ16 and A25LQ64.
by Stefan Tauner 15 Jun '13

15 Jun '13

Also, refine unlocking of A25L032, A25LQ32A and A25LQ032. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++---- flashchips.h | 4 ++- 2 files changed, 89 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 84d8fe9..ea67bc2 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1155,8 +1155,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_amic_a25l032, - .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ + .printlock = spi_prettyprint_status_register_amic_a25l032, /* bit5: T/B, bit6: prot size */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -1164,12 +1164,52 @@ const struct flashchip flashchips[] = { { .vendor = "AMIC", - .name = "A25LQ032", + .name = "A25LQ16", + .bustype = BUS_SPI, + .manufacture_id = AMIC_ID_NOPREFIX, + .model_id = AMIC_A25LQ16, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { { 4 * 1024, 512 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 64 * 1024, 32 } }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 32 } }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 2048 * 1024, 1 } }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 2048 * 1024, 1 } }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_amic_a25l032, /* bit5: T/B, bit6: prot size */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "AMIC", + .name = "A25LQ032/A25LQ32A", .bustype = BUS_SPI, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A25LQ032, .total_size = 4096, .page_size = 256, + /* A25LQ32A supports SFDP */ /* OTP: 64B total; read 0x4B, 0x48; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, @@ -1194,8 +1234,49 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_amic_a25l032, - .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ + .printlock = spi_prettyprint_status_register_amic_a25l032, /* bit5: T/B, bit6: prot size */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "AMIC", + .name = "A25LQ64", + .bustype = BUS_SPI, + .manufacture_id = AMIC_ID_NOPREFIX, + .model_id = AMIC_A25LQ032, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 2048 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 256 } }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 128 } }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 8192 * 1024, 1 } }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 8192 * 1024, 1 } }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enhance (sic!) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, diff --git a/flashchips.h b/flashchips.h index 2442c9e..5cb84a9 100644 --- a/flashchips.h +++ b/flashchips.h @@ -112,7 +112,9 @@ #define AMIC_A25L080 0x3014 #define AMIC_A25L016 0x3015 #define AMIC_A25L032 0x3016 -#define AMIC_A25LQ032 0x4016 +#define AMIC_A25LQ16 0x4015 +#define AMIC_A25LQ032 0x4016 /* Same as A25LQ32A, but the latter supports SFDP */ +#define AMIC_A25LQ64 0x4017 #define AMIC_A29002B 0x0d #define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 -- Kind regards, Stefan Tauner

1 0

[PATCH 07/12] Add support for more Eon EN25QH chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - EN25QH64 - EN25QH128 - EN25QH256 (defunct due to addressing) Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- flashchips.h | 3 ++ 2 files changed, 123 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 2cd4274..84d8fe9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3856,7 +3856,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -3876,8 +3877,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -3893,7 +3894,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -3913,8 +3915,120 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH64", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH64, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH128", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH128, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH256", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH256, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + /* EN4B: 0xB7, EX4B: 0xE9 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_BAD_REW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, diff --git a/flashchips.h b/flashchips.h index 5fac8dc..2442c9e 100644 --- a/flashchips.h +++ b/flashchips.h @@ -257,6 +257,9 @@ #define EON_EN25Q128 0x3018 #define EON_EN25QH16 0x7015 #define EON_EN25QH32 0x7016 +#define EON_EN25QH64 0x7017 +#define EON_EN25QH128 0x7018 +#define EON_EN25QH256 0x7019 #define EON_EN25S10 0x3811 #define EON_EN25S20 0x3812 #define EON_EN25S40 0x3813 -- Kind regards, Stefan Tauner

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[PATCH 06/12] Add support for Eon EN25S series.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - EN25S10 - EN25S20 - EN25S40 - EN25S80 - EN25S16 - EN25S32 - EN25S64 Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + flashchips.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 7 ++ spi25_statusreg.c | 14 +++ 4 files changed, 273 insertions(+) diff --git a/chipdrivers.h b/chipdrivers.h index 4bb356a..fce3ed4 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -90,6 +90,7 @@ int spi_disable_blockprotect_at25f512a(struct flashctx *flash); int spi_disable_blockprotect_at25f512b(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); +int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash); int spi_prettyprint_status_register_s33(struct flashctx *flash); int spi_disable_blockprotect_s33(struct flashctx *flash); int spi_prettyprint_status_register_sst25(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 6bd92a6..2cd4274 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3922,6 +3922,257 @@ const struct flashchip flashchips[] = { { .vendor = "Eon", + .name = "EN25S10", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S10, + .total_size = 128, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S20", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S20, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S40", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S40, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S80", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S80, + .total_size = 1024, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S16", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S16, + .total_size = 2048, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S32", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S32, + .total_size = 4096, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4096 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4096 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S64", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S64, + .total_size = 8192, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8192 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8192 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", .name = "EN29F010", .bustype = BUS_PARALLEL, .manufacture_id = EON_ID, diff --git a/flashchips.h b/flashchips.h index 6e0646e..5fac8dc 100644 --- a/flashchips.h +++ b/flashchips.h @@ -257,6 +257,13 @@ #define EON_EN25Q128 0x3018 #define EON_EN25QH16 0x7015 #define EON_EN25QH32 0x7016 +#define EON_EN25S10 0x3811 +#define EON_EN25S20 0x3812 +#define EON_EN25S40 0x3813 +#define EON_EN25S80 0x3814 +#define EON_EN25S16 0x3815 +#define EON_EN25S32 0x3816 +#define EON_EN25S64 0x3817 #define EON_EN29F512 0x7F21 #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 946e790..33dd780 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -570,6 +570,20 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0); } +/* === Eon === */ + +int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_srwd(status); + msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis"); + spi_prettyprint_status_register_bp(status, 3); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === Intel === */ /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ -- Kind regards, Stefan Tauner

1 0

[PATCH 05/12] Add support for Numonyx M45PE series.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - M45PE10 - M45PE20 - M45PE40 - M45PE80 - M45PE16 Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 5 +++ 2 files changed, 140 insertions(+) diff --git a/flashchips.c b/flashchips.c index 9b9979a..6bd92a6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6504,6 +6504,141 @@ const struct flashchip flashchips[] = { { .vendor = "Numonyx", + .name = "M45PE10", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE10, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 512} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE20", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE20, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE40", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 2048} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE80", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 4096} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE16", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 8192} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 768ba80..6e0646e 100644 --- a/flashchips.h +++ b/flashchips.h @@ -598,6 +598,11 @@ #define ST_M25P32 0x2016 #define ST_M25P64 0x2017 #define ST_M25P128 0x2018 +#define ST_M45PE10 0x4011 +#define ST_M45PE20 0x4012 +#define ST_M45PE40 0x4013 +#define ST_M45PE80 0x4014 +#define ST_M45PE16 0x4015 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 #define ST_M25PX64 0x7117 -- Kind regards, Stefan Tauner

1 0

[PATCH 04/12] Add support for some GigaDevice GD25* chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

- GigaDevice GD25T80 - GigaDevice GD25Q10 - GigaDevice GD25Q512 Also, improve some others. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 189 +++++++++++++++++++++++++++++++++++++++++++++------------- flashchips.h | 12 +++- 2 files changed, 159 insertions(+), 42 deletions(-) diff --git a/flashchips.c b/flashchips.c index fdf9ec5..9b9979a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -4173,7 +4173,118 @@ const struct flashchip flashchips[] = { { .vendor = "GigaDevice", - .name = "GD25Q20", + .name = "GD25LQ32", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ32, + .total_size = 4096, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q512", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q512, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q10", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q10, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q20(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q20, @@ -4202,16 +4313,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q40", + .name = "GD25Q40(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q40, @@ -4240,10 +4351,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4279,16 +4390,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q16", + .name = "GD25Q16(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q16, @@ -4318,10 +4429,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4357,10 +4468,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4396,10 +4507,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4435,53 +4546,51 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25LQ32", + .name = "GD25T80", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, - .model_id = GIGADEVICE_GD25LQ32, - .total_size = 4096, + .model_id = GIGADEVICE_GD25T80, + .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + /* OTP: 256B total; enter 0x3A */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, + .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = - { + .block_erasers = { { - .eraseblocks = { {4 * 1024, 1024} }, + .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {32 * 1024, 128} }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_52, }, { - .eraseblocks = { {64 * 1024, 64} }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp4, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, - .voltage = {1700, 1950}, + .voltage = {2700, 3600}, }, - + { .vendor = "Hyundai", .name = "HY29F002T", diff --git a/flashchips.h b/flashchips.h index 944aa4b..768ba80 100644 --- a/flashchips.h +++ b/flashchips.h @@ -307,14 +307,22 @@ #define FUJITSU_MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define GIGADEVICE_ID 0xC8 /* GigaDevice */ -#define GIGADEVICE_GD25Q20 0x4012 -#define GIGADEVICE_GD25Q40 0x4013 +#define GIGADEVICE_GD25T80 0x3114 +#define GIGADEVICE_GD25Q512 0x4010 +#define GIGADEVICE_GD25Q10 0x4011 +#define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25QB */ +#define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25QB */ #define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B only? */ +#define GIGADEVICE_GD25LQ40 0x6013 +#define GIGADEVICE_GD25LQ80 0x6014 +#define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 +#define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ +#define GIGADEVICE_GD25LQ128 0x6018 #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ -- Kind regards, Stefan Tauner

1 0

[PATCH 03/12] Add support for all Sanyo LE25FW chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - Sanyo LE25FW403A - Sanyo LE25FW418A - Sanyo LE25FW806 - Sanyo LE25FW808 Also, fix wrong description of Sanyo LE25FW203A. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- flashchips.h | 5 +++ 2 files changed, 141 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 4490491..fdf9ec5 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7235,11 +7235,11 @@ const struct flashchip flashchips[] = { { .vendor = "Sanyo", - .name = "LF25FW203A", + .name = "LE25FW203A", .bustype = BUS_SPI, .manufacture_id = SANYO_ID, .model_id = SANYO_LE25FW203A, - .total_size = 2048, + .total_size = 256, .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -7247,17 +7247,147 @@ const struct flashchip flashchips[] = { .block_erasers = { { - .eraseblocks = { {64 * 1024, 32} }, + .eraseblocks = { {256, 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, + .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW403A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW403A, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 2 * 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW418A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW418A, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* some quad-read supported ("HD_READ mode") */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW806", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW806, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW808", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW808, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {8 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* some quad-read supported ("HD_READ mode") */ + .voltage = {2700, 3600}, }, { diff --git a/flashchips.h b/flashchips.h index 41903d2..944aa4b 100644 --- a/flashchips.h +++ b/flashchips.h @@ -482,6 +482,11 @@ */ #define SANYO_ID 0x62 #define SANYO_LE25FW203A 0x1600 +#define SANYO_LE25FW403A 0x1100 +#define SANYO_LE25FW406 0x07 /* RES2 */ +#define SANYO_LE25FW418A 0x10 /* RES2 and some weird 1 byte RDID variant */ +#define SANYO_LE25FW806 0x26 /* RES2 and some weird 1 byte RDID variant */ +#define SANYO_LE25FW808 0x20 /* RES2 and some weird 1 byte RDID variant */ #define SHARP_ID 0xB0 /* Sharp */ #define SHARP_LH28F008BJ__PT 0xEC -- Kind regards, Stefan Tauner

1 0

[PATCH 02/12] Introduce spi_block_erase_db().
by Stefan Tauner 15 Jun '13

15 Jun '13

Used for page erase on some chips (e.g. Numonyx M45PE and Sanyo LF25FW series). Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + spi.h | 5 +++++ spi25.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/chipdrivers.h b/chipdrivers.h index c64de79..4bb356a 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -51,6 +51,7 @@ int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_byte_program(struct flashctx *flash, unsigned int addr, uint8_t databyte); diff --git a/spi.h b/spi.h index 297125e..9e38e74 100644 --- a/spi.h +++ b/spi.h @@ -106,6 +106,11 @@ #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 +/* Page Erase 0xDB */ +#define JEDEC_PE 0xDB +#define JEDEC_PE_OUTSIZE 0x04 +#define JEDEC_PE_INSIZE 0x00 + /* Read Status Register */ #define JEDEC_RDSR 0x05 #define JEDEC_RDSR_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 4f1452e..26da13d 100644 --- a/spi25.c +++ b/spi25.c @@ -565,6 +565,47 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, return 0; } +/* Page erase (usually 256B blocks) */ +int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_PE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_PE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + } }; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + + /* Wait until the Write-In-Progress bit is cleared. + * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -745,6 +786,8 @@ erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) return &spi_block_erase_d7; case 0xd8: return &spi_block_erase_d8; + case 0xdb: + return &spi_block_erase_db; default: msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " "this at flashrom(a)flashrom.org\n", __func__, opcode); -- Kind regards, Stefan Tauner

1 0

[PATCH 01/12] Introduce additional SPI status register helpers.
by Stefan Tauner 15 Jun '13

15 Jun '13

- spi_prettyprint_status_register_default_welwip(): It just prettyprints the plain hex value and the welwip bits. - spi_prettyprint_status_register_default_bp4(): Prints the hex value, welwip, bp0-5 and srwd bits. - spi_disable_blockprotect_bp2_srwd(), - spi_disable_blockprotect_bp3_srwd() and spi_disable_blockprotect_bp4_srwd(): Three new common block unprotection functions for the frequent cases where there is a status register lock bit at bit #7 and some block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 +++++- flashchips.c | 6 ++++-- spi25_statusreg.c | 49 +++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 52 insertions(+), 9 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index dd20631..c64de79 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -63,10 +63,15 @@ int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); int spi_prettyprint_status_register_plain(struct flashctx *flash); +int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); int spi_prettyprint_status_register_default_bp1(struct flashctx *flash); int spi_prettyprint_status_register_default_bp2(struct flashctx *flash); int spi_prettyprint_status_register_default_bp3(struct flashctx *flash); +int spi_prettyprint_status_register_default_bp4(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); +int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash); +int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash); +int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash); int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); @@ -82,7 +87,6 @@ int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); int spi_disable_blockprotect_at25f(struct flashctx *flash); int spi_disable_blockprotect_at25f512a(struct flashctx *flash); int spi_disable_blockprotect_at25f512b(struct flashctx *flash); -int spi_disable_blockprotect_at25f4096(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_s33(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 6ec3749..4490491 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1849,7 +1849,8 @@ const struct flashchip flashchips[] = { } }, .printlock = spi_prettyprint_status_register_at25f4096, - .unlock = spi_disable_blockprotect_at25f4096, + /* "Bits 5-6 are 0s when device is not in an internal write cycle." Better leave them alone: */ + .unlock = spi_disable_blockprotect_bp2_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -4473,7 +4474,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 53952fe..946e790 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -177,6 +177,27 @@ int spi_disable_blockprotect(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0); } +/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and + * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly + * non-0). */ +int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); +} + +/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and + * protected/locked by bit #7. */ +int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0); +} + +/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and + * protected/locked by bit #7. */ +int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0); +} static void spi_prettyprint_status_register_hex(uint8_t status) { @@ -242,6 +263,16 @@ int spi_prettyprint_status_register_plain(struct flashctx *flash) return 0; } +/* Print the plain hex value and the welwip bits only. */ +int spi_prettyprint_status_register_default_welwip(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* Works for many chips of the * AMIC A25L series * and MX MX25L512 @@ -293,6 +324,17 @@ int spi_prettyprint_status_register_default_bp3(struct flashctx *flash) return 0; } +int spi_prettyprint_status_register_default_bp4(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_srwd(status); + spi_prettyprint_status_register_bp(status, 4); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === Amic === * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using * spi_prettyprint_status_register_default_bp1 or @@ -518,11 +560,6 @@ int spi_disable_blockprotect_at25f512b(struct flashctx *flash) return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25f4096(struct flashctx *flash) -{ - return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); -} - int spi_disable_blockprotect_at25fs010(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0); @@ -538,7 +575,7 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ int spi_disable_blockprotect_s33(struct flashctx *flash) { - return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); + return spi_disable_blockprotect_bp2_srwd(flash); } int spi_prettyprint_status_register_s33(struct flashctx *flash) -- Kind regards, Stefan Tauner

1 0

[PATCH 00/12] Flashchip galore
by Stefan Tauner 15 Jun '13

15 Jun '13

So... I took a closer look at the existing monster patch and found quite some mistakes which Steven did not catch (e.g. non-working probing methods), which is quite normal for such big patches. It is easy to overlook small bits in such a huge diff, hence my advice to never do it this way again (please). While reviewing and splitting the patch I also noticed that only most basic chip support was added with many of the small details missing (status register printing and proper unlocking, comments regarding OTP, SFDP, different I/O modes etc.). This is the result of my rework. I'd be happy to see someone looking through it and/or asking questions regarding anything that I have changed. I'll this set shortly before the release of 0.9.7 (which will be released tomorrow or next week). Thanks to everybody involved so far! Stefan Tauner (12): Introduce additional SPI status register helpers. Introduce spi_block_erase_db(). Add support for all Sanyo LE25FW chips. Add support for some GigaDevice GD25* chips. Add support for Numonyx M45PE series. Add support for Eon EN25S series. Add support for more Eon EN25QH chips. Add support for AMIC A25LQ16 and A25LQ64. Add support for Micron/Numonyx/ST M25PX80. Add support for Spansion S25FL2 chips. Add support for Spansion S25FL...S chips. Add support for remaining Numonyx (Micron) N25Q chips. chipdrivers.h | 15 +- flashchips.c | 3212 +++++++++++++++++++++++++++++++++++++---------------- flashchips.h | 61 +- spi.h | 10 + spi25.c | 88 ++ spi25_statusreg.c | 93 +- 6 files changed, 2505 insertions(+), 974 deletions(-) -- Kind regards, Stefan Tauner

1 0

Re: [flashrom] USB 3 PCI Card support (request to add device)
by Philipp Post 13 Jun '13

13 Jun '13

I have added some flashrom and linux logs which might be helpfull: The USB 3 PCI card has the following system properties: DRIVER=xhci_hcd PCI_CLASS=C0330 PCI_ID=1033:0194 PCI_SUBSYS_ID=1033:0194 PCI_SLOT_NAME=0000:03:00.0 MODALIAS=pci:v00001033d00000194sv00001033sd00000194bc0Csc03i30 There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 02:0a.0) and a PCI soundcard installed. Tried to read the flash rom out of the 82541PI Intel NIC without problems. /sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to "rom" which the USB 3 and the soundcard do not. I am not sure if that means that the rom is not accessible at all or if Ubuntu just does not know how. Thanks in advance, brgds Philipp -----Ursprüngliche Nachricht----- Von: Philipp Post [mailto:Post.Philipp@googlemail.com] Gesendet: Donnerstag, 24. Januar 2013 19:23 An: 'flashrom(a)flashrom.org' Betreff: USB 3 PCI Card support (request to add device) Good day, following configuration: - USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB chip and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in - IBM NetVista 8305 Desktop PC - built year 2003 The issue with the card is that it needs a flash rom update to work with Windows Vista and up, otherwise the device does not work at all in these OS ("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu 11.3 out of the box works fine. RENESAS has a rom update for the chip and a flash update tool which however does not work with PCI cards, but just chips soldered to mainboards. At least this seems to me the reason why it does not work. Chip is recognized but the RENESAS tool says "Can not load / access firmware". The tool has the option to change the device / vendor id as well via .ini file. The card used is the only PCI USB 3 card on the market and basically works very well when it works - with max PCI speed of course, which means approx. double speed of USB 2. The card exists in hardware version 1 (RENESAS chip uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to hardware version 1. The name of the manufacturer behind the card is unknown to me, but it could be an ADDONICS product. I do not have a technical drawing of the card and I fear I can not obtain one but I do have the card itself. My question: would it be possible to incorporate this card into flashrom? Would be great if someone could do it as I do not have the necessary skills to do it myself. In case you need further information, please let me know. Thanks in advance, brgds Philipp Links and further reading: -------------------------- Card Information from different sellers (same card): http://www.addonics.com/products/ad2u3pci.php http://eu.startech.com/Cards-Adapters/USB-3.0/Cards/2-Port-PCI-SuperSpeed-US B-3-Card-Adapter~PCIUSB3S2 http://www.lindy.de/premium-usb-3-karte-2-port-pci/51082.html ATMEL rom specification (contains info how to write rom images): www.atmel.com/Images/doc3689.pdf Renesas USB chip information: http://www.renesas.eu/products/soc/usb_assp/product/upd720200a/index.jsp RENESAS rom update 4.0.2.0 with Windows updater (32 + 64 Bit) and drivers: http://www.station-drivers.com/page/renesas.htm We need: "Firmware Version 4.0.2.0 pour uPD720200a" RENESAS MS DOS flash update tool (which did not do the job): http://www.computerbase.de/forum/attachment.php?attachmentid=283282&d=133832 3319 IBM NetVista 8305 Hardware Maintenance Manual: http://download.lenovo.com/ibmdl/pub/pc/pccbbs/netvista_pdf/24p2969.pdf Hardware Ids: Renesas Electronics USB 3.0 Host Controller: PCI\VEN_1033&DEV_0194&SUBSYS_01941033&REV_04\5&25043F3&0&0048F0 Renesas Electronics USB 3.0 Root Hub NUSB3\ROOT_HUB30\6&2D374EF3&2

2 6

X79 Motherboard untested - reassurance? ;)
by Rupert Bailey 11 Jun '13

11 Jun '13

Hello team, Keen to find out if using flashbios is a good idea for my chipset Chipset: Intel X79 Motherboard: FX79 System: SX79R5 Shuttle Part of the reason why I think I need to do a bios update is because my 12.04 Ubuntu system is providing this error message on startup: [ 3.858429] EDAC sbridge: ECC is disabled. Aborting [ 3.858471] EDAC sbridge: Couldn't find mci handler And several forum posts were indicating that updates might fix this.

1 0

Re: [flashrom] [PATCH] Add W25Q....W series.
by Stefan Tauner 09 Jun '13

09 Jun '13

On Fri, 22 Feb 2013 17:07:00 +0100 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - Use ".V" (and "_V" in macros) for 3.3V Winbond 25Q chips. > Rename the existing chips and add a .voltage entry where it was missing. > - Use ".W" (and "_W" in macros) for 1.8V Winbond 25Q chips. > - Add a feature flag for QPI-enabled chips: FEATURE_QPI. > - Add W25Q20.W, W25Q40.W, W25Q80.W, W25Q16.W, W25Q32.W, W25Q64.W. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > […] > diff --git a/print.c b/print.c > […] > - B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), > + B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), > […] Self-acked and committed in r1677, but without the changes in print.c. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1677 - trunk
by repository service 09 Jun '13

09 Jun '13

Author: stefanct Date: Sun Jun 9 16:00:46 2013 New Revision: 1677 URL: http://flashrom.org/trac/flashrom/changeset/1677 Log: Add W25Q...W series. - Use ".V" (and "_V" in macros) for 3.3V Winbond 25Q chips. Rename the existing chips and add a .voltage entry where it was missing. - Use ".W" (and "_W" in macros) for 1.8V Winbond 25Q chips. - Add W25Q20.W, W25Q40.W, W25Q80.W, W25Q16.W, W25Q32.W, W25Q64.W. Based on chromiumos' 469707f0d9b7d81b6c6bb2cace13f09db70f4382 http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=com… Signed-off-by: Yung-Chieh Lo <yjlou%chromium.org(a)gtempaccount.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Jun 1 02:30:31 2013 (r1676) +++ trunk/flashchips.c Sun Jun 9 16:00:46 2013 (r1677) @@ -10007,13 +10007,14 @@ { .vendor = "Winbond", - .name = "W25Q80", + .name = "W25Q80.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q80, + .model_id = WINBOND_NEX_W25Q80_V, .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -10046,13 +10047,14 @@ { .vendor = "Winbond", - .name = "W25Q16", + .name = "W25Q16.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q16, + .model_id = WINBOND_NEX_W25Q16_V, .total_size = 2048, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -10085,13 +10087,14 @@ { .vendor = "Winbond", - .name = "W25Q32", + .name = "W25Q32.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q32, + .model_id = WINBOND_NEX_W25Q32_V, .total_size = 4096, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -10124,13 +10127,14 @@ { .vendor = "Winbond", - .name = "W25Q64", + .name = "W25Q64.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q64, + .model_id = WINBOND_NEX_W25Q64_V, .total_size = 8192, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -10158,17 +10162,19 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { .vendor = "Winbond", - .name = "W25Q128", + .name = "W25Q128.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q128, + .model_id = WINBOND_NEX_W25Q128_V, .total_size = 16384, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, @@ -10196,6 +10202,244 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W25Q20.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q20_W, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q40.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q40_W, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q80.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q80_W, + .total_size = 1024, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q16.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q16_W, + .total_size = 2048, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q32.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_W, + .total_size = 4096, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q64.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q64_W, + .total_size = 8192, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ }, { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat Jun 1 02:30:31 2013 (r1676) +++ trunk/flashchips.h Sun Jun 9 16:00:46 2013 (r1677) @@ -655,12 +655,20 @@ #define WINBOND_NEX_W25X16 0x3015 #define WINBOND_NEX_W25X32 0x3016 #define WINBOND_NEX_W25X64 0x3017 -#define WINBOND_NEX_W25Q40 0x4013 -#define WINBOND_NEX_W25Q80 0x4014 -#define WINBOND_NEX_W25Q16 0x4015 -#define WINBOND_NEX_W25Q32 0x4016 -#define WINBOND_NEX_W25Q64 0x4017 -#define WINBOND_NEX_W25Q128 0x4018 +#define WINBOND_NEX_W25Q40_V 0x4013 /* W25Q40BV; W25Q40BL (2.3-3.6V) */ +#define WINBOND_NEX_W25Q80_V 0x4014 /* W25Q80BV */ +#define WINBOND_NEX_W25Q16_V 0x4015 /* W25Q16CV; W25Q16DV */ +#define WINBOND_NEX_W25Q32_V 0x4016 /* W25Q32BV; W25Q32FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV */ +#define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ +#define WINBOND_NEX_W25Q40_W 0x5013 /* W25Q40BW */ +#define WINBOND_NEX_W25Q80_W 0x5014 /* W25Q80BW */ +#define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ +#define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ +#define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ +#define WINBOND_NEX_W25Q128_W 0x6018 /* (No W version known) W25Q128FV in QPI mode */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49

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Correupted Bios
by Mike Kallan 09 Jun '13

09 Jun '13

Dear Sir/Madam Let me brief you what happened... I bought a refurbished HP Desktop 4 months ago, and I set up the system FIRST time yesterday. Everything worked find till I updated the bios to the latest. At the end of the flashing, I got a message saying couldn't update the bios and I was forced to reboot the computer. Since that time, my computer doesn't work at all... I flush the bios from the mother board changing the pin and my computer started working except my keyboard and mouse doesn't work at all. So I have to shut down the computer manually by pressing power button on the desktop... If I restart the computer, I won't get anything on the monitor... I would be very grateful you will be able to help me in this situation. My computer details are as follows Model#: HP Pavilion P7-1141 (P7-1000) Prod#: QX351AAR#ABA Motherboard Name: AAHD3-HB Socket Type: FM1 Chipset: AMD Hudson-D3 FCH Form Factor: uATX: 24.3 cm (9.6 inches) x 24.3 cm (9.6 inches) Processor AMD Quad-Core A8-3800 Socket Type: FM1 Memory 8gb (Max. 16-GB) 4-Slots Hard Drive 1-TB 7200rpm Video AMD Radeon HD 6550D (Shared) Audio AMD Hudson-D3 Mother Board Spec & Clearing CMOS http://h10025.www1.hp.com/ewfrf/wc/document?cc=us&lc=en&dlc=en&docname=c029… http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us… Thanks in advance Mike

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Re: [flashrom] FAILED: <Elitegroup GF8200A>
by Stefan Tauner 08 Jun '13

08 Jun '13

On Fri, 7 Jun 2013 21:09:21 -0400 Knowledge <dark.knowledge.lnx(a)gmail.com> wrote: > thanks in advance, but came up with a misfortune, there was a power > outage in my area and did not have UPS, to start again the pc and did > not respond, I am on a black screen T_T..... > > there will be some way to load the bios by other means? appreciate any > information of hope :'( that's very unfortunate :/ before you try anything else, try to reset the cmos memory (with a jumper usually). maybe the update was successful "enough" and the black screen is just caused by non-default settings. if that does not help there are essentially two options: 1. using the recovery code if it is still intact 2. using an external programmer to rewrite the flash chip usually there is a small part of the bios with a very limited initialization of the mainboard that is able to read bios files from floppy disks and write them to the flash chip (known as bootblock). but there is no floppy connector on that board AFAICS... no idea how this stuff works nowadays. some boards have special means to update via USB sticks, but no idea how good that works in general. also, we don't know if that part of the flash is ok. the error happened in the part where the bootblock usually is... the other option is to use an external programmer which can be another mainboard which also has a dip8 socket for its flash chip. (see http://flashrom.org/Technology#DIP8:_Dual_In-line_Package.2C_8_pins) it is possible to boot with the original chip and then swap it with the wrongly written one and write it again. this does not work with all boards but many. another option is to use a separate device to access the flash chip. for example you could use an arduino or a buspirate or any other embedded hardware that can connect to a PC with some effort. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: <Elitegroup GF8200A>
by Knowledge 08 Jun '13

08 Jun '13

PD: I use my old pc pentium III for contact 2013/6/7, Knowledge <dark.knowledge.lnx(a)gmail.com>: > thanks in advance, but came up with a misfortune, there was a power > outage in my area and did not have UPS, to start again the pc and did > not respond, I am on a black screen T_T..... > > there will be some way to load the bios by other means? appreciate any > information of hope :'( > > sorry for my bad English, greetings from chile. > > > > 2013/6/7, Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: >> Hi, >> >> can you please retry to write your update with >> sudo flashrom -p internal -w 78NAA512.ROM -VVV -o retry.log >> and if that still fails please try to write the backup with >> sudo flashrom -p internal -w backup.rom -VVV -o backup_write.log >> and send us the files, thanks. >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > > > -- > -- > <a href="dark.knowledge.lnx(a)gmail.com"><img > src="http://img262.imageshack.us/img262/1382/mailex5.png" > border="0"</></a> > > <a href="http://ubuntucounter.geekosophical.net" title="The Ubuntu > Counter Project - user number # 15441"><img > src="http://ubuntucounter.geekosophical.net/img/ubuntu-user2.php?user=15441" > alt="The Ubuntu Counter Project - user number # 15441" /></a> > -- -- <a href="dark.knowledge.lnx(a)gmail.com"><img src="http://img262.imageshack.us/img262/1382/mailex5.png" border="0"</></a> <a href="http://ubuntucounter.geekosophical.net" title="The Ubuntu Counter Project - user number # 15441"><img src="http://ubuntucounter.geekosophical.net/img/ubuntu-user2.php?user=15441" alt="The Ubuntu Counter Project - user number # 15441" /></a>

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Re: [flashrom] FAILED: <Elitegroup GF8200A>
by Stefan Tauner 08 Jun '13

08 Jun '13

Hi, can you please retry to write your update with sudo flashrom -p internal -w 78NAA512.ROM -VVV -o retry.log and if that still fails please try to write the backup with sudo flashrom -p internal -w backup.rom -VVV -o backup_write.log and send us the files, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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FAILED: <Elitegroup GF8200A>
by Knowledge 07 Jun '13

07 Jun '13

detected NVIDIA MCP78S DMI string system-manufacturer: "ECS" DMI string system-product-name: "GeForce 8000 series" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "GeForce 8000 series" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP78S" with PCI ID 10de:075c. wasabi@wasabi-G:~/Descargas/bios$ sudo flashrom -p internal -r backup.rom flashrom v0.9.6.1-r1563 on Linux 3.9.3-pf (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP78S". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfbf80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Reading flash... done. wasabi@wasabi-G:~/Descargas/bios$ sudo flashrom -p internal -w 78NAA512.ROM flashrom v0.9.6.1-r1563 on Linux 3.9.3-pf (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP78S". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfbf80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFY FAILED at 0x000ff300! Expected=0x00, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0xff Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! product page http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=873&C… bios downloaded http://download.ecsusa.com/dlfileecs/bios/mb/p4/GF8200A/78NAA512.zip -- -- <a href="dark.knowledge.lnx(a)gmail.com"><img src="http://img262.imageshack.us/img262/1382/mailex5.png" border="0"</></a> <a href="http://ubuntucounter.geekosophical.net" title="The Ubuntu Counter Project - user number # 15441"><img src="http://ubuntucounter.geekosophical.net/img/ubuntu-user2.php?user=15441" alt="The Ubuntu Counter Project - user number # 15441" /></a>

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Re: [flashrom] Added chipsets
by Stefan Tauner 04 Jun '13

04 Jun '13

On Mon, 3 Jun 2013 22:38:01 -0400 Steven Zakulec <spzakulec(a)gmail.com> wrote: > So, I think Stefan is going to handle the review of the S25FL128S / 256S > Spansion chips since they're a bit unusual. I'll handle those and maybe some other nitpicks when you two are done, yes. > The E and the uniform sector comment. This is because there are certain > chips that once had (or still do) have hybrid sector setups- the top block > of the chip could have one value, and the bottom block another. There are 3 possible erase sector layouts in this chip family. 'E' has uniform sectors (meaning that every erase address range done by any one opcode is equal in size) and then there are two other variants that split the top or bottom block into a number of subdivisions. As explained on IRC these were invented and useful earlier in computer history for bootblocks. But since flash chips got bigger and usually include quite fine-grained erase opcodes today, I don't think many of those variants of this family are in the wild, but that might be overly naive and optimistic. :) > Flashrom can only handle uniform sectors right now. That is incorrect. Flashrom *does* support them (e.g. Am29F002(N)BT). The problem is that with the current probing methods supported flashrom can not distinguish between those variants of the Micron chips. See Numonxy datasheet of the N25Q128 with "subsectors" (Rev 7, May 2011), section 9.1.1 Read Identification (RDID) explains how to identify the (non-)uniform layouts (respectively) with the bits in the first EDID byte (the second one seems to be not specified btw). The problem is: currently flashrom does only read the first 3 bytes (which is everything there was before they (Atmel has the patent afaik (yes this seems to be really patentable in countries with ridiculous patent rules)) to extend RDID like that). This will be solved by my in my GSoC project this summer. Until then I think it is ok to add them and expect them to be uniform. If there are really non-uniform variants out there the will be erase errors, but using another erase operation (which is done automatically) will work fine. But it is certainly a good idea to document that, hence the comments in flashchips.h. > +#define ST_N25Q256A13 0xBA19 /* N25Q256, 3.0V */ > should be: > +#define ST_N25Q256__3 0xBA19 /* N25Q256, 3.0V */ > > +#define ST_N25Q256A11 0xBB19 /* N25Q256, 1.8V */ > should be: > +#define ST_N25Q256__1 0xBB19 /* N25Q256, 1.8V */ > > +#define ST_N25Q512A13 0xBA20 /* N25Q512, 3.0V */ > should be: > +#define ST_N25Q512__3 0xBA20 /* N25Q512, 3.0V */ > > +#define ST_N25Q512A11 0xBB20 /* N25Q512, 1.8V */ > should be: > +#define ST_N25Q512__1 0xBB20 /* N25Q512, 1.8V */ > > +#define ST_N25Q00AA13 0xBA21 /* N25Q00A, 3.0V */ > should be: > +#define ST_N25Q00A__3 0xBA21 /* N25Q00A, 3.0V */ and please mention non-uniformness if you spot it in one of those datasheets (I have not checked that, but I guess Steven did so already). I will handle any further iterations of this patch set (so please be sure to mail it to the mailing list, Nikolay). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Added chipsets
by Steven Zakulec 04 Jun '13

04 Jun '13

So, I think Stefan is going to handle the review of the S25FL128S / 256S Spansion chips since they're a bit unusual. I'm going to cover the flashchips.h part of the patch, and some issues with chip names/IDs that came up in review of the flashchips.h part. In general, chip names should contain only important characters- unimportant characters should be marked with a . or an _ depending on the field in flashchips.c and with an _ for names in flashchips.h. See http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html for the reasoning here, and N25Q064..1E for an example. The Spansion chips you've added seem to have an extra letter at the end that's not important, so I would remove it. >From flashchips.h: #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ #define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ Here's examples of chips with names that have been shortened due to unimportant characters. The underscore ( _ ) is used to replace the unimportant characters. There's also another item there that's important: #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ The E and the uniform sector comment. This is because there are certain chips that once had (or still do) have hybrid sector setups- the top block of the chip could have one value, and the bottom block another. Flashrom can only handle uniform sectors right now. The N25Q128A13 is a great example of this: the Numonyx datasheet from Feb 2011 mentions it has uniform sectors, but the May 2011 sheet says it has top or bottom sectors +#define ST_N25Q128A13 0xBA18 /* N25Q128, 3.0V */ should be: +#define ST_N25Q128__3E 0xBA18 /* N25Q128, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128A11 0xBB18 /* N25Q128, 1.8V */ should be: +#define ST_N25Q128__1E 0xBB18 /* N25Q128, 1.8V, (uniform sectors expected) */ +#define ST_N25Q256A13 0xBA19 /* N25Q256, 3.0V */ should be: +#define ST_N25Q256__3 0xBA19 /* N25Q256, 3.0V */ +#define ST_N25Q256A11 0xBB19 /* N25Q256, 1.8V */ should be: +#define ST_N25Q256__1 0xBB19 /* N25Q256, 1.8V */ +#define ST_N25Q512A13 0xBA20 /* N25Q512, 3.0V */ should be: +#define ST_N25Q512__3 0xBA20 /* N25Q512, 3.0V */ +#define ST_N25Q512A11 0xBB20 /* N25Q512, 1.8V */ should be: +#define ST_N25Q512__1 0xBB20 /* N25Q512, 1.8V */ +#define ST_N25Q00AA13 0xBA21 /* N25Q00A, 3.0V */ should be: +#define ST_N25Q00A__3 0xBA21 /* N25Q00A, 3.0V */ Please adjust the .name and .model_id fields in flashchips.c so the names are properly shortened as done above: .name uses periods in place of characters .model_id uses underscores ( _ ) in place of characters Please see N25Q064..3E for an example of this in flashchips.c I realize this may be a lot to take in, so ask questions, and if I can't answer it, hopefully someone else on the list can.

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mac address problem with nvidia MCP55V-Pro
by Jon Morby 02 Jun '13

02 Jun '13

hi … I don't suppose anyone has any experience updating or fixing MAC addresses on Nvidea nVIDIA MCP55V-Pro (Supermicro H8DMT+) ? Following an experimental reflash everything went well, except afterwards we noticed the mac address had been reset link/ether 66:77:44:22:33:12 brd ff:ff:ff:ff:ff:ff -- Jon Morby FidoNet - the internet made simple! 10 - 16 Tiller Road, London, E14 8PX tel: 0845 004 3050 / fax: 0845 004 3051

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Re: [flashrom] Added chipsets
by Stefan Tauner 02 Jun '13

02 Jun '13

On Fri, May 17, 2013 at 1:12 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > Hi Steven > > "Please add page programming eraseblocks" > what did you mean? > > I think this patch is big and i will write a function page erase blocks > (DB hex) after committing patch. Hi Nikolay, I would very much prefer if you could add that function before we commit the M45 series. Feel free to split the existing patch on chip families... I will probably do that anyway before committing it. Another general nitpick: if it is not too much of a hassle please do not spread the TODO comment for the .printlock field over 3 lines; "/* TODO: improve */" is used everywhere else and your editor probably expanded that automatically. Thanks for your continued effort (and thanks to Steven for his reviews too). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] z68extreme4 mainboard
by Stefan Tauner 01 Jun '13

01 Jun '13

On Thu, 16 May 2013 15:21:23 +1000 David MacKinnon <blaedd(a)gmail.com> wrote: > 0x54: 0x000f0000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. > 0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write. > 0x5C: 0x03ff0010 FREG2: WARNING: Management Engine region (0x00010000-0x003fffff) is locked. > 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. > 0x64: 0x00001fff FREG4: Platform Data region is unused. Hello David, thanks for your report! The problem is the locked ME region as quoted above. For more details please see http://flashrom.org/ME I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Asrock Fatal1ty Z77 Performance > unsupported - logs attached
by "Jürgen Dorn" 01 Jun '13

01 Jun '13

regards, Jürgen

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[PATCH 2/2] Introduce serialport_config().
by Stefan Tauner 01 Jun '13

01 Jun '13

This allows to easily reconfigure a serial port as needed in the Bus Pirate speedup. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- programmer.h | 1 + serial.c | 105 +++++++++++++++++++++++++++++++++------------------------- 2 files changed, 60 insertions(+), 46 deletions(-) diff --git a/programmer.h b/programmer.h index 2ea7b48..6361eb8 100644 --- a/programmer.h +++ b/programmer.h @@ -656,6 +656,7 @@ typedef int fdtype; void sp_flush_incoming(void); fdtype sp_openserport(char *dev, unsigned int baud); +int serialport_config(fdtype fd, unsigned int baud); void __attribute__((noreturn)) sp_die(char *msg); extern fdtype sp_fd; /* expose serialport_shutdown as it's currently used by buspirate */ diff --git a/serial.c b/serial.c index 5f74fd1..0504aaa 100644 --- a/serial.c +++ b/serial.c @@ -160,35 +160,18 @@ static void msg_perr_strerror(const char *msg) #endif } -fdtype sp_openserport(char *dev, unsigned int baud) +int serialport_config(fdtype fd, unsigned int baud) { -#ifdef _WIN32 - HANDLE fd; - char *dev2 = dev; - if ((strlen(dev) > 3) && - (tolower((unsigned char)dev[0]) == 'c') && - (tolower((unsigned char)dev[1]) == 'o') && - (tolower((unsigned char)dev[2]) == 'm')) { - dev2 = malloc(strlen(dev) + 5); - if (!dev2) { - msg_perr_strerror("Out of memory: "); - return SER_INV_FD; - } - strcpy(dev2, "\\\\.\\"); - strcpy(dev2 + 4, dev); - } - fd = CreateFile(dev2, GENERIC_READ | GENERIC_WRITE, 0, NULL, - OPEN_EXISTING, 0, NULL); - if (dev2 != dev) - free(dev2); - if (fd == INVALID_HANDLE_VALUE) { - msg_perr_strerror("Cannot open serial port: "); - return SER_INV_FD; + if (fd == SER_INV_FD) { + msg_perr("%s: File descriptor is invalid.\n", __func__); + return 1; } + +#ifdef _WIN32 DCB dcb; if (!GetCommState(fd, &dcb)) { msg_perr_strerror("Could not fetch original serial port configuration: "); - goto out_close; + return 1; } const struct baudentry *entry = round_baud(baud); dcb.BaudRate = entry->flag; @@ -197,35 +180,25 @@ fdtype sp_openserport(char *dev, unsigned int baud) dcb.StopBits = ONESTOPBIT; if (!SetCommState(fd, &dcb)) { msg_perr_strerror("Could not change serial port configuration: "); - goto out_close; + return 1; } if (!GetCommState(fd, &dcb)) { msg_perr_strerror("Could not fetch new serial port configuration: "); - goto out_close; + return 1; } msg_pdbg("Baud rate is %ld.\n", dcb.BaudRate); - return fd; -out_close: - CloseHandle(sp_fd); - return SER_INV_FD; #else struct termios wanted, observed; - int fd; - fd = open(dev, O_RDWR | O_NOCTTY | O_NDELAY); - if (fd < 0) { - msg_perr_strerror("Cannot open serial port: "); - return SER_INV_FD; - } fcntl(fd, F_SETFL, 0); if (tcgetattr(fd, &observed) != 0) { msg_perr_strerror("Could not fetch original serial port configuration: "); - goto out_close; + return 1; } wanted = observed; const struct baudentry *entry = round_baud(baud); if (cfsetispeed(&wanted, entry->flag) != 0 || cfsetospeed(&wanted, entry->flag) != 0) { msg_perr_strerror("Could not set serial baud rate: "); - goto out_close; + return 1; } wanted.c_cflag &= ~(PARENB | CSTOPB | CSIZE | CRTSCTS); wanted.c_cflag |= (CS8 | CLOCAL | CREAD); @@ -234,11 +207,11 @@ out_close: wanted.c_oflag &= ~OPOST; if (tcsetattr(fd, TCSANOW, &wanted) != 0) { msg_perr_strerror("Could not change serial port configuration: "); - goto out_close; + return 1; } if (tcgetattr(fd, &observed) != 0) { msg_perr_strerror("Could not fetch new serial port configuration: "); - goto out_close; + return 1; } if (observed.c_cflag != wanted.c_cflag || observed.c_lflag != wanted.c_lflag || @@ -246,14 +219,54 @@ out_close: observed.c_oflag != wanted.c_oflag || cfgetispeed(&observed) != cfgetispeed(&wanted)) { msg_perr("%s: Some requested options did not stick.\n", __func__); - goto out_close; + return 1; } - msg_pdbg("Baud rate is %d.\n", entry->baud); - return fd; + msg_pdbg("Baud rate is %d now.\n", entry->baud); +#endif + return 0; +} -out_close: - close(sp_fd); - return SER_INV_FD; +fdtype sp_openserport(char *dev, unsigned int baud) +{ + fdtype fd; +#ifdef _WIN32 + char *dev2 = dev; + if ((strlen(dev) > 3) && + (tolower((unsigned char)dev[0]) == 'c') && + (tolower((unsigned char)dev[1]) == 'o') && + (tolower((unsigned char)dev[2]) == 'm')) { + dev2 = malloc(strlen(dev) + 5); + if (!dev2) { + msg_perr_strerror("Out of memory: "); + return SER_INV_FD; + } + strcpy(dev2, "\\\\.\\"); + strcpy(dev2 + 4, dev); + } + fd = CreateFile(dev2, GENERIC_READ | GENERIC_WRITE, 0, NULL, + OPEN_EXISTING, 0, NULL); + if (dev2 != dev) + free(dev2); + if (fd == INVALID_HANDLE_VALUE) { + msg_perr_strerror("Cannot open serial port: "); + return SER_INV_FD; + } + if (serialport_config(fd, baud) != 0) { + CloseHandle(fd); + return SER_INV_FD; + } + return fd; +#else + fd = open(dev, O_RDWR | O_NOCTTY | O_NDELAY); + if (fd < 0) { + msg_perr_strerror("Cannot open serial port: "); + return SER_INV_FD; + } + if (serialport_config(fd, baud) != 0) { + close(fd); + return SER_INV_FD; + } + return fd; #endif } -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Combine serialport_write and serialport_read into serialport_rw.
by Carl-Daniel Hailfinger 01 Jun '13

01 Jun '13

Am 01.04.2013 03:14 schrieb Stefan Tauner: > Because they share almost all code, combine them into serialport_rw > and export the old functions as wrappers. This makes reads "empty reads"- > aware and programmers able to detect such problems even on "blocking" > reads. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > diff --git a/serial.c b/serial.c > index 49484f5..6679b7c 100644 > --- a/serial.c > +++ b/serial.c > @@ -28,6 +28,7 @@ > #include <sys/stat.h> > #include <errno.h> > #include <inttypes.h> > +#include <stdbool.h> > #ifdef _WIN32 > #include <conio.h> > #else > @@ -328,68 +329,61 @@ int serialport_shutdown(void *data) > return 0; > } > > -int serialport_write(unsigned char *buf, unsigned int writecnt) > +/* Writes (if \c outdir is true) or reads \c todo bytes from/into \c buf. > + * Tries up to 10 times with a timeout of \c ms ms between each try. */ > +static int serialport_rw(unsigned char *buf, unsigned int todo, bool outdir, unsigned int ms) > { > + const char * const op = outdir ? "write" : "read"; > #ifdef _WIN32 > - DWORD tmp = 0; > + DWORD cur = 0; > #else > - ssize_t tmp = 0; > + ssize_t cur = 0; > #endif > - unsigned int empty_writes = 250; /* results in a ca. 125ms timeout */ > + unsigned int empty_tries = 10; > > - while (writecnt > 0) { > + while (todo > 0) { > #ifdef _WIN32 > - WriteFile(sp_fd, buf, writecnt, &tmp, NULL); > + if (outdir) > + WriteFile(sp_fd, buf, todo, &cur, NULL); > + else > + ReadFile(sp_fd, buf, todo, &cur, NULL); > #else > - tmp = write(sp_fd, buf, writecnt); > + if (outdir) > + cur = write(sp_fd, buf, todo); > + else > + cur = read(sp_fd, buf, todo); > #endif > - if (tmp == -1) { > - msg_perr("Serial port write error!\n"); > + if (cur == -1) { > + msg_perr("Serial port %s error!\n", op); > return 1; The logic of error handling is non-portable (AFAICS the number of read/written bytes for the error case is 0 on Windows and -1 on POSIX). That said, it was non-portable before, so this patch doesn't change it for the worse. > } > - if (!tmp) { > - msg_pdbg2("Empty write\n"); > - empty_writes--; > - programmer_delay(500); > - if (empty_writes == 0) { > + if (cur == 0) { > + msg_pdbg2("Empty %s.\n", op); > + empty_tries--; > + programmer_delay(ms * 1000); > + if (empty_tries == 0) { > msg_perr("Serial port is unresponsive!\n"); That message is actually wrong for the read case. If the serial device (e.g. Bus Pirate) disappears, you'll get 0-byte reads forever, at least on Linux. AFAICS blocking reads shall either return an error or at least 1 byte. That rule seems to be valid on Linux and Windows. Errors can be transient, though (see EINTR and other fun stuff). Suggested alternative wording: "Serial port is unresponsive or disappeared" > return 1; > } > } > - writecnt -= tmp; > - buf += tmp; > + todo -= cur; > + buf += cur; > } > > return 0; > } > > -int serialport_read(unsigned char *buf, unsigned int readcnt) > +int serialport_write(unsigned char *buf, unsigned int writecnt) > { > -#ifdef _WIN32 > - DWORD tmp = 0; > -#else > - ssize_t tmp = 0; > -#endif > - > - while (readcnt > 0) { > -#ifdef _WIN32 > - ReadFile(sp_fd, buf, readcnt, &tmp, NULL); > -#else > - tmp = read(sp_fd, buf, readcnt); > -#endif > - if (tmp == -1) { > - msg_perr("Serial port read error!\n"); > - return 1; > - } > - if (!tmp) > - msg_pdbg2("Empty read\n"); > - readcnt -= tmp; > - buf += tmp; > - } > + return serialport_rw(buf, writecnt, true, 1); > +} > > - return 0; > +int serialport_read(unsigned char *buf, unsigned int readcnt) > +{ > + return serialport_rw(buf, readcnt, false, 10); > } > > + > /* Tries up to timeout ms to read readcnt characters and places them into the array starting at c. Returns > * 0 on success, positive values on temporary errors (e.g. timeouts) and negative ones on permanent errors. > * If really_read is not NULL, this function sets its contents to the number of bytes read successfully. */ Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1676 - branches/stuge
by repository service 01 Jun '13

01 Jun '13

Author: stefanct Date: Sat Jun 1 02:30:31 2013 New Revision: 1676 URL: http://flashrom.org/trac/flashrom/changeset/1676 Log: Remove Peter's obsolete branch. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Deleted: branches/stuge/

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[commit] r1675 - trunk
by repository service 01 Jun '13

01 Jun '13

Author: stefanct Date: Sat Jun 1 02:06:12 2013 New Revision: 1675 URL: http://flashrom.org/trac/flashrom/changeset/1675 Log: Change warning regarding protected ICH regions. There is no good reason to collect further log files of locked Intel- based boards. Forward affected users directly to an explanation in the wiki instead. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 23 23:47:46 2013 (r1674) +++ trunk/ichspi.c Sat Jun 1 02:06:12 2013 (r1675) @@ -1700,6 +1700,10 @@ /* Handle FREGx and FRAP registers */ for (i = 0; i < 5; i++) ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); + if (ich_spi_rw_restricted) + msg_pwarn("Not all flash regions are freely accessible by flashrom. This is " + "most likely\ndue to an active ME. Please see http://flashrom.org/ME " + "for details.\n"); } /* Handle PR registers */ @@ -1711,11 +1715,6 @@ } if (ich_spi_rw_restricted) { - msg_pinfo("Please send a verbose log to " - "flashrom(a)flashrom.org if this board is not " - "listed on\n" - "http://flashrom.org/Supported_hardware#Supported_mainboards " - "yet.\n"); if (!ich_spi_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n"

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Script for collecting flashrom compatibility with motherboards
by Alexey Vazhnov 31 May '13

31 May '13

Hi! Perhaps we can check many hardware for compatibility with Linux. Condition: test must be fast, so no manual intervention. So now I prepare some PXE images for collect hardware information. How do I collect maximum information about motherboards chips compatible with flashrom? Currently I see only one variant — write motherboard name with «flashrom -r /dev/null» stdout. -- Yours respectfully, Alexey Vazhnov Jabber: vazhnov(a)jabber.ru

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Re: [flashrom] Read test - Dell Dimension C521
by Stefan Tauner 31 May '13

31 May '13

On Wed, 15 May 2013 10:39:44 +0200 Gil <agile81(a)gmail.com> wrote: > seems fine > > flashrom v0.9.6.1-r1563 on Linux generic (i686) > flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian > Command line (5 args): flashrom -VVV -p internal -o fl1 > Calibrating delay loop... OS timer resolution is 2 usecs, 948M loops > per second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 997 us, > 10000 myus = 10369 us, 8 myus = 9 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Dell Inc" > DMI string system-product-name: "Dimension C521" > DMI string system-version: " " > DMI string baseboard-manufacturer: "Dell Inc" > DMI string baseboard-product-name: " " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found chipset "NVIDIA MCP51" with PCI ID 10de:0260. Enabling flash write... > OK. > ... > The following protocols are supported: Non-SPI. > ... > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e > Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical > address 0xfff80000. > ... > Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). > No operations were specified. > Restoring PCI config space for 00:0a:0 reg 0x6d > > Saved BIOS ROM ok Hi Gil and thanks for your report. We are not really interested in (successful) read tests for boards (because they don't tell anything about writes and we do not keep track of that separately). Also, please do not prune logs even if you think you do us a favor and that there is lots of useless stuff in it. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Winbond W25X20 on Tumpa programmer works
by J. Domburg 31 May '13

31 May '13

As subject. Verbose read and write output of flashrom is attached. Cheers, Jeroen

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Asus P8P67 LE works, successfully wrote and verified
by artemis3 30 May '13

30 May '13

Hello, I checked your wiki matrix, and I'm not sure i quite understand where it says "NO (42)" what exactly means. I have this motherboard, which is a B2. there is a B3 next to it in your hardware table with a green "OK" (P8P67 PRO). I went ahead and tried flashing anyway and it worked!, It could write and verify back an old bios (1104) downloaded from Asus page. This board was nearly bricked by the writing of a B3 bios which made all sort of trouble to it, after several attempts (wouldn't post) i managed to boot linux and went with flashrom. Note 42 has this written: "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked." But this is wrong, flashrom identified chip MX25L3205 like the other 2 previous models. I have no idea what this ME and ICH business is to deserve a red NO, but it worked with mine. Asus page happily mentions "Pre-B3 revision motherboard users can also download and use the new B3 revision BIOS, drivers and utilities." http://event.asus.com/2011/mb/Identify_B3_Motherboards/ That is absolutely wrong!, Pre B3 users can't use any B3 BIOS image!. In my case, the bios got all sensor values wrong, and it wanted to shutdown as it thought the processor was over/under temp, voltage etc, i managed to turn off all power setting things i could to be able to post, and the bios would often freeze requiring moving the clear jumper before even wanting to turn the power on again many times. I also learned something about Asus: while their BIOS EZ Flash tool happily allows upgrading to this dangerous B3 bios in a B2 board, it won't let you flash back to the older working version, genius move... I used flashrom 0.9.5.2+r1517-1 from the Ubuntu repository. flashrom v0.9.5.2-r1517 on Linux 3.5.0-28-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel P67". Enabling flash write... OK. Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000.

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Re: [flashrom] New board for list
by Stefan Tauner 30 May '13

30 May '13

On Sat, 18 May 2013 15:48:56 -0400 Aurelius R <maxrowsell(a)gmail.com> wrote: > The board from the HP Pavilion a6200n which has the NVIDIA nForce 430 > Chipset works great -- I tested it multiple times reading, writing and > erasing the BIOS chip, no flaws, no errors at all. I'm also going to try > and write the VESA chip (nVidia MCP61-80) which seems to be a separate > chip, because that is the chip that seems to be causing all the trouble on > this board. > > Anyway, just thought you'd like to add that info to your list. I can also > provide the dump from flashrom -V that the program says to email to you, as > support isn't quite complete for my board/chip if you want. Hello Alexander, yes please send a verbose log (probing for the chip is good enough for now, no need to read/write). Can you confirm that this is the board in question? http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01077676&tmp_task=prod… You seem to be under the impression that the graphics core uses a separate flash chip for its firmware. This is probably not the case. Instead it shares it with the "BIOS" chip that flashrom accesses. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Fwd: Re: Added chipsets
by Steven Zakulec 28 May '13

28 May '13

---------- Forwarded message ---------- From: "Николай Николаев" <evrinoma(a)gmail.com> Date: May 28, 2013 1:28 AM Subject: Re: [flashrom] Added chipsets To: "Steven Zakulec" <spzakulec(a)gmail.com> Cc: Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev

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Please help
by Aaron Brown 28 May '13

28 May '13

Hi . I installed flashrom 9.6.1 but cant find any button that says "write flashrom" please tell me, how exactly I can write the bios ? ------------------------------------------------------------------------------ with big honor. Aaron

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Re: [flashrom] Added chipsets
by Николай Николаев 28 May '13

28 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/28 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Re: [flashrom] Added chipsets
by Николай Николаев 28 May '13

28 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/27 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi steven, 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > Before I get started on the review, just a general comment or two. > If you plan to contribute in the future (which I certainly hope you will), > please break submissions down into blocks of 5-10 chips. This makes it so > much easier for me, and any other reviewers, to quickly check the patch and > provide feedback in a timely manner. > Sorry, this is my first patch. My next patch i wrote with you wish. ( http://patchwork.coreboot.org/patch/3896/) 8) > In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, > 16), should only have > + .feature_bits = FEATURE_WRSR_WREN, > set when the command is there. It appears I may have been unclear there, > because instead of removing just the WREN flag, you removed the whole line > (the chips do have a Write Status Register- WRSR). > > Continuing the review from Numonyx M45PE16. > Sorry i don't know which flag must be used. You right these chips have a only WREN instruction, and i think if these chips doesn't have a feature that i exclude feature_bits. Maybe we will be able to specify the details. > Numonyx M25PX80- > + .voltage = {2700, 3600}, > The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B > 3/2013) > > + .tested = TEST_OK_PREW, > Unless I'm reading it wrong, it looks like you're adding this chip as a > fully tested one- would you mind supplying some logs showing that it > successfully does these operations? (write logs shouldn't contain all :S > (for skipped blocks) next to the addresses). > You right this is my typos, and i fixed them. > Numonyx N25Q00AA13- > I'll admit I don't really know how this chip works, but it seems there > should be a 3rd eraseblock from the description of the memory organization > (datasheet is Rev E, 2/12): > > Memory Configuration and Block Diagram > The memory is a stacked device comprised of four 256Mb chips. Each chip is > internally > partitioned into two 128Mb segments. Each page of memory can be > individually pro- > grammed. Bits are programmed from one through zero. The device is > subsector, sector, > or single 256Mb chip erasable, but not page-erasable. Bits are erased from > zero through > one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 > sectors (64KB > each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); > and 64 OTP > bytes are located outside the main memory array. > > You've got: > + .eraseblocks = { {4 * 1024, 32768 } }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 2048 } }, > + .block_erase = spi_block_erase_d8, > > There's a die erase opcode, which I am unfamiliar with- maybe it handles > erasing a single 256Mb chip at a time? > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. But chip N25Q00AA13 has a other op-code to initiate die erase command C4 (hex) > Sanyo LF25FW203A / LE25FW203A- > Thanks so much for getting to the bottom of this chip, and figuring out > which chip it actually is. > > .probe = probe_spi_rdid, > Maybe I'm reading the patch wrong, but you appear to be missing the > .probe_timing line for this chip. > You reading patch wrong. The probe_timing line for this chip is present below in source code. > LE25FW418A, LE25FW808 and LE25FW806 - > For the LE25FW806A you included the small sector erase, but left it out > for the rest of the chips- any particular reason for this? > Because only LE25FW806A has a small sector erase op-code instruction, other chips didn't have it. > > I'll cover from Spansion S25FL128S to the end tomorrow. > Excellent how to delete all versions of the patch and leave only comments in one thread? I send a new version patch -- With best regards Nikolay Nikolaev С Уважением Николаев Николай -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Failing to write flash to Abit AN-M2HD motherboard
by Jon Wickström 27 May '13

27 May '13

Hi, Here is some more info regarding my last email. Writing the new flash image failed. Before that I read the old and verified it with flashrom. //Jonte --8<--- $ sudo flashrom -v bios_old_2013-05-26.bin flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Verifying flash... VERIFIED. jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/ ABITFAE.BAT AWDFLASH.EXE M628A_20.BIN M628A_20.TXT RUNME.BAT jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/M628A_20.BIN flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0007ffff: 0x5f21f ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. -- jonte(a)xn--wickstrm-t4a.fi

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Flashrom advised to email!
by Eamon M 27 May '13

27 May '13

Hi, Flashrom advised to email. Flashing 2048k bios rom file to a Lanner FW-8750 motherboard gave the following error as attached. Any help would be gratefully received. Regards, Eamon

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 12:02 PM, Steven Zakulec <spzakulec(a)gmail.com>wrote: > > > > On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > >> Hi steven, >> >> 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> >>> >>> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, >>> 80, 16), should only have >>> + .feature_bits = FEATURE_WRSR_WREN, >>> set when the command is there. It appears I may have been unclear >>> there, because instead of removing just the WREN flag, you removed the >>> whole line (the chips do have a Write Status Register- WRSR). >>> >> >>> Continuing the review from Numonyx M45PE16. >>> >> Sorry i don't know which flag must be used. You right these chips have a >> only WREN instruction, and i think if these chips doesn't have a feature >> that i exclude feature_bits. Maybe we will be able to specify the details. >> > Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > + .feature_bits = FEATURE_WRSR > > I've been informed by others that your original idea of dropping the FEATURE line is actually correct, so you should do that instead of what I proposed.

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > Hi steven, > > 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > >> Before I get started on the review, just a general comment or two. >> If you plan to contribute in the future (which I certainly hope you >> will), please break submissions down into blocks of 5-10 chips. This makes >> it so much easier for me, and any other reviewers, to quickly check the >> patch and provide feedback in a timely manner. >> > Sorry, this is my first patch. My next patch i wrote with you wish. ( > http://patchwork.coreboot.org/patch/3896/) 8) > > > >> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, >> 16), should only have >> + .feature_bits = FEATURE_WRSR_WREN, >> set when the command is there. It appears I may have been unclear there, >> because instead of removing just the WREN flag, you removed the whole line >> (the chips do have a Write Status Register- WRSR). >> > >> Continuing the review from Numonyx M45PE16. >> > Sorry i don't know which flag must be used. You right these chips have a > only WREN instruction, and i think if these chips doesn't have a feature > that i exclude feature_bits. Maybe we will be able to specify the details. > Other people can provide more details on the general case, but in this instance, with only a WREN instruction, the FEATURE line should be: + .feature_bits = FEATURE_WRSR > > >> Numonyx M25PX80- >> + .voltage = {2700, 3600}, >> The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B >> 3/2013) >> >> + .tested = TEST_OK_PREW, >> Unless I'm reading it wrong, it looks like you're adding this chip as a >> fully tested one- would you mind supplying some logs showing that it >> successfully does these operations? (write logs shouldn't contain all :S >> (for skipped blocks) next to the addresses). >> > You right this is my typos, and i fixed them. > > >> Numonyx N25Q00AA13- >> I'll admit I don't really know how this chip works, but it seems there >> should be a 3rd eraseblock from the description of the memory organization >> (datasheet is Rev E, 2/12): >> >> Memory Configuration and Block Diagram >> The memory is a stacked device comprised of four 256Mb chips. Each chip >> is internally >> partitioned into two 128Mb segments. Each page of memory can be >> individually pro- >> grammed. Bits are programmed from one through zero. The device is >> subsector, sector, >> or single 256Mb chip erasable, but not page-erasable. Bits are erased >> from zero through >> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >> sectors (64KB >> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >> and 64 OTP >> bytes are located outside the main memory array. >> >> You've got: >> + .eraseblocks = { {4 * 1024, 32768 } }, >> + .block_erase = spi_block_erase_20, >> + }, { >> + .eraseblocks = { {64 * 1024, 2048 } }, >> + .block_erase = spi_block_erase_d8, >> >> There's a die erase opcode, which I am unfamiliar with- maybe it handles >> erasing a single 256Mb chip at a time? >> > > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three > instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. > But chip N25Q00AA13 has a other op-code to initiate die erase command > C4 (hex) > > So, how do you do a single-chip erase for this chip? > > >> Sanyo LF25FW203A / LE25FW203A- >> Thanks so much for getting to the bottom of this chip, and figuring out >> which chip it actually is. >> >> .probe = probe_spi_rdid, >> Maybe I'm reading the patch wrong, but you appear to be missing the >> .probe_timing line for this chip. >> > You reading patch wrong. The probe_timing line for this chip is present > below in source code. > Okay- thanks for checking. > > >> LE25FW418A, LE25FW808 and LE25FW806 - >> For the LE25FW806A you included the small sector erase, but left it out >> for the rest of the chips- any particular reason for this? >> > Because only LE25FW806A has a small sector erase op-code instruction, > other chips didn't have it. > > What data sheets do you have for those chips? The ones below list the small sector erase op-code as D7. LE25FW418A: 61709 SY 20090428-S00004 No.A1432 LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 >> >> I'll cover from Spansion S25FL128S to the end tomorrow. >> > Excellent > > > how to delete all versions of the patch and leave only comments in one > thread? > Don't change what you're doing for this patch. > > I send a new version patch > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай >

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

Before I get started on the review, just a general comment or two. If you plan to contribute in the future (which I certainly hope you will), please break submissions down into blocks of 5-10 chips. This makes it so much easier for me, and any other reviewers, to quickly check the patch and provide feedback in a timely manner. In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, 16), should only have + .feature_bits = FEATURE_WRSR_WREN, set when the command is there. It appears I may have been unclear there, because instead of removing just the WREN flag, you removed the whole line (the chips do have a Write Status Register- WRSR). Continuing the review from Numonyx M45PE16. Numonyx M25PX80- + .voltage = {2700, 3600}, The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B 3/2013) + .tested = TEST_OK_PREW, Unless I'm reading it wrong, it looks like you're adding this chip as a fully tested one- would you mind supplying some logs showing that it successfully does these operations? (write logs shouldn't contain all :S (for skipped blocks) next to the addresses). Numonyx N25Q00AA13- I'll admit I don't really know how this chip works, but it seems there should be a 3rd eraseblock from the description of the memory organization (datasheet is Rev E, 2/12): Memory Configuration and Block Diagram The memory is a stacked device comprised of four 256Mb chips. Each chip is internally partitioned into two 128Mb segments. Each page of memory can be individually pro- grammed. Bits are programmed from one through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 sectors (64KB each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); and 64 OTP bytes are located outside the main memory array. You've got: + .eraseblocks = { {4 * 1024, 32768 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048 } }, + .block_erase = spi_block_erase_d8, There's a die erase opcode, which I am unfamiliar with- maybe it handles erasing a single 256Mb chip at a time? Sanyo LF25FW203A / LE25FW203A- Thanks so much for getting to the bottom of this chip, and figuring out which chip it actually is. .probe = probe_spi_rdid, Maybe I'm reading the patch wrong, but you appear to be missing the .probe_timing line for this chip. LE25FW418A, LE25FW808 and LE25FW806 - For the LE25FW806A you included the small sector erase, but left it out for the rest of the chips- any particular reason for this? I'll cover from Spansion S25FL128S to the end tomorrow. On Tue, May 21, 2013 at 4:29 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > A new version patch > > Was checked: > -functions block erase for all chips > -feature bits for all chips > -model_id for all chips > -manufacture_id for all chips > -voltage for all chips > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Abit AN-M2HD
by Jon Wickström 26 May '13

26 May '13

Hi, I mailed you earlier today regarding my Abit AN-M2HD main board. I think there are different revisions of this board, I don't know which I have. I was asked on irc to provide the following: flashrom -p internal -V http://paste.flashrom.org/view.php?id=1646 lcpci -nnvvvxxx http://paste.flashrom.org/view.php?id=1647 superiotool -deV http://paste.flashrom.org/view.php?id=1648 flashrom -p internal -r readout.rom http://paste.flashrom.org/view.php?id=1649 I assume it will be some time before somebody has time to look at this, so I will try forcing the flash with abits own flash utility. Supposedly this is a bug in the BIOS. With best regards, //Jonte -- jonte(a)xn--wickstrm-t4a.fi

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Board Abit AN-M2HD
by Jon Wickström 26 May '13

26 May '13

Hi, I find it a bit interesting the board specifies MCP68, but the chipset found is MCP67. I tried to flash the board from a dos boot image (via grub), but got the error that the flash is write protected. It seems forcing the write worked for somebody: http://www.technologicalwanderings.co.uk/node/70 I have not tried that. //Jonte --8<--- $ sudo flashrom -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 696M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 9958 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Unknow" DMI string system-product-name: "Unknow" DMI string system-version: "Unknow" DMI string baseboard-manufacturer: "nVIDIA" DMI string baseboard-product-name: "AN-M2HD(MCP68)" DMI string baseboard-version: "1.x " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP67" with PCI ID 10de:0548. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0542 at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x4c, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

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flashrom verbose log
by Andrew Butterworth 25 May '13

25 May '13

1 0

Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)
by Rudolf Marek 24 May '13

24 May '13

Hi all, I was asked by Idwer to look into this. Since the patch was code reviewed already I have just some comments: 1) does it work if IMC is disabled? If not, we should first detect if IMC firmware is active. 2) it writes to reserved bits 7:1 This should be easy fix 3) is there a way to release it back after writes are done? Alternative way would be to send "go to IDLE/ram command to firmware. Thanks Rudolf

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[commit] r1674 - trunk
by repository service 23 May '13

23 May '13

Author: stefanct Date: Thu May 23 23:47:46 2013 New Revision: 1674 URL: http://flashrom.org/trac/flashrom/changeset/1674 Log: dediprog: fix SPI clock setting. Avoid setting SPI speed on firmware versions < 5.0.0 and note this limitation in the man page. Use the correct offset of the "12M" element in the spispeeds array to match our manpage and the default of Dediprog's dpcmd. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/dediprog.c trunk/flashrom.8 Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Fri May 3 23:58:28 2013 (r1673) +++ trunk/dediprog.c Thu May 23 23:47:46 2013 (r1674) @@ -184,12 +184,15 @@ */ static int dediprog_set_spi_speed(unsigned int spispeed_idx) { - int ret; + if (dediprog_firmwareversion < FIRMWARE_VERSION(5, 0, 0)) { + msg_pwarn("Skipping to set SPI speed because firmware is too old.\n"); + return 0; + } - msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); + msg_pdbg("SPI speed is %s Hz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, - NULL, 0x0, DEFAULT_TIMEOUT); + int ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; @@ -789,7 +792,7 @@ { struct usb_device *dev; char *voltage, *device, *spispeed, *target_str; - int spispeed_idx = 2; + int spispeed_idx = 1; int millivolt = 3500; long usedevice = 0; long target = 1; @@ -806,7 +809,7 @@ } } if (!spispeeds[i].name) { - msg_perr("Error: Invalid 'spispeed' value.\n"); + msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed); free(spispeed); return 1; } Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Fri May 3 23:58:28 2013 (r1673) +++ trunk/flashrom.8 Thu May 23 23:47:46 2013 (r1674) @@ -683,7 +683,8 @@ .sp An optional .B spispeed -parameter specifies the frequency of the SPI bus. Syntax is +parameter specifies the frequency of the SPI bus. The firmware on the device needs to be 5.0.0 or newer. +Syntax is .sp .B " flashrom \-p dediprog:spispeed=frequency" .sp

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M2N-MX SE Plus: flashrom -V
by Jonathan Wakely 23 May '13

23 May '13

flashrom v0.9.6.1-r1639 on Linux 3.9.2-200.fc18.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, GCC 4.7.2 20121109 (Red Hat 4.7.2-8), little endian Command line (1 args): flashrom -V Using default programmer "internal". Calibrating delay loop... OS timer resolution is 1 usecs, 861M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 9970 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M2N-MX SE Plus" DMI string baseboard-version: "Rev x.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Super I/O ID 0x8712 is not on the list of flash capable controllers. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 Found Macronix flash chip "MX25L8005" (1024 kB, SPI). No operations were specified.

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Re: [flashrom] Added chipsets
by Steven Zakulec 23 May '13

23 May '13

Thanks for the update. I will take a look at it soon. On May 21, 2013 4:31 AM, "Николай Николаев" <evrinoma(a)gmail.com> wrote: > A new version patch > > Was checked: > -functions block erase for all chips > -feature bits for all chips > -model_id for all chips > -manufacture_id for all chips > -voltage for all chips > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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