- flashrom - mail.coreboot.org

NVIDIA MCP73
by Koen Rousseau 22 Mar '14

22 Mar '14

Reading, writing an verifying the BIOS on my old Acer Aspire M5640 PC's motherboard worked like a charm. Many thanks!

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SuperMicro H8QME2 motherboards work great with Flashrom
by Greg Tippitt 21 Mar '14

21 Mar '14

On the hardware section of the wiki the SuperMicro H8QME2 was not mentioned, but several others from SM were supported. I needed to upgrade the BIOS on my motherboard before I could upgrade from dual core to hex core Opteron CPUs. It worked dead simple. I tried to do the -z option to send in, but it said that option wasn't compiled for. Thanks for a great program Greg Tippitt

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W836xx: Foxconn nT435/nT535: flashrom -V
by Matt Keys 20 Mar '14

20 Mar '14

Hello, I was looking into coreboot compatibility with my nettop and noticed within the flashrom output (full log attached) : " Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. " You'll find the requested output of flashrom -V below. Regards, Matt ------ root@nettop:~# flashrom -V flashrom v0.9.6.1-r1563 on Linux 3.11.0-18-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (1 args): flashrom -V Please select a programmer with the --programmer parameter. Valid choices are: internal, dummy, nic3com, nicrealtek, gfxnvidia, drkaiser, satasii, ft2232_spi, serprog, buspirate_spi, rayer_spi, pony_spi, nicintel, nicintel_spi, ogp_spi, satamv root@nettop:~#

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Re: [flashrom] Intel S5000PAL: Flash Not Found
by Sean Everson 19 Mar '14

19 Mar '14

All, I have a number of Intel S5000PAL motherboards that I would like to use FLASHROM to manage if at all possible. According to the Intel Docs at: http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000pal_… The motherboard has the 6321ESB chipset which is listed as supported on the flashrom.org wiki page. When I try to use FLASHROM to read the flash I get an error message that the flash is not found. Can someone provide me with some guidance on what additional information or steps I can take to investigate this further? I have pasted the flashrom -V output here: http://pastebin.com/Rr24eXa5 Thanks for your help! --Sean On Wed, Mar 19, 2014 at 12:18 PM, Sean Everson <sean.everson(a)gmail.com> wrote: > All, > > > I have a number of Intel S5000PAL motherboards that I would like to use > FLASHROM to manage if at all possible. According to the Intel Docs at: > > > http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000pal_… > > > The box contains the 6321ESB chipset which is listed as supported on the > flashrom.org wiki page. > > > When I try to use FLASHROM to read the flash I get an error message that the > flash is not found. Can someone provide me with some guidance on what > additional information or steps I can take to investigate this further? > > > I am including the output from flashrom -V below. > > > Thanks for your help! > > > --Sean > > > > # ./flashrom -V -p internal -r /tmp/bios.bin > > flashrom v0.9.7-r1764 on Linux 2.6.32.24 (x86_64) > > flashrom is free software, get the source code at http://www.flashrom.org > > > flashrom was built with libpci 3.2.1, GCC 4.7.1, little endian > > Command line (5 args): ./flashrom -V -p internal -r /tmp/bios.bin > > Calibrating delay loop... OS timer resolution is 1 usecs, 2824M loops per > second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = > 10025 us, 4 myus = 4 us, OK. > > Initializing internal programmer > > No coreboot table found. > > Using Internal DMI decoder. > > DMI string chassis-type: "Rack Mount Chassis" > > DMI string system-manufacturer: "Intel" > > DMI string system-product-name: "T5000PAL" > > DMI string system-version: "Not Specified" > > DMI string baseboard-manufacturer: "Intel" > > DMI string baseboard-product-name: "T5000PAL0 " > > DMI string baseboard-version: "FRU Ver 0.05" > > W836xx enter config mode worked or we were already in config mode. W836xx > leave config mode had no effect. > > Active config mode, unknown reg 0x20 ID: f2. > > Please send the output of "flashrom -V" to > > flashrom(a)flashrom.org with W836xx: your board name: flashrom -V > > as the subject to help us finish support for your Super I/O. Thanks. > > Found chipset "Intel 631xESB/632xESB/3100" with PCI ID 8086:2670. Enabling > flash write... > > 0xfff80000/0xffb80000 FWH IDSEL: 0x0 > > 0xfff00000/0xffb00000 FWH IDSEL: 0x0 > > 0xffe80000/0xffa80000 FWH IDSEL: 0x0 > > 0xffe00000/0xffa00000 FWH IDSEL: 0x0 > > 0xffd80000/0xff980000 FWH IDSEL: 0x0 > > 0xffd00000/0xff900000 FWH IDSEL: 0x0 > > 0xffc80000/0xff880000 FWH IDSEL: 0x0 > > 0xffc00000/0xff800000 FWH IDSEL: 0x0 > > 0xff700000/0xff300000 FWH IDSEL: 0x4 > > 0xff600000/0xff200000 FWH IDSEL: 0x5 > > 0xff500000/0xff100000 FWH IDSEL: 0x6 > > 0xff400000/0xff000000 FWH IDSEL: 0x7 > > 0xfff80000/0xffb80000 FWH decode enabled > > 0xfff00000/0xffb00000 FWH decode enabled > > 0xffe80000/0xffa80000 FWH decode enabled > > 0xffe00000/0xffa00000 FWH decode enabled > > 0xffd80000/0xff980000 FWH decode enabled > > 0xffd00000/0xff900000 FWH decode enabled > > 0xffc80000/0xff880000 FWH decode enabled > > 0xffc00000/0xff800000 FWH decode enabled > > 0xff700000/0xff300000 FWH decode disabled > > 0xff600000/0xff200000 FWH decode disabled > > 0xff500000/0xff100000 FWH decode disabled > > 0xff400000/0xff000000 FWH decode disabled > > Maximum FWH chip size: 0x400000 bytesSPI Read Configuration: prefetching > disabled, caching enabled, > > BIOS_CNTL = 0x03: BIOS Lock Enable: enabled, BIOS Write Enable: enabled > > Warning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed. > > New value is 0x03. > > OK. > > The following protocols are supported: FWH. > > Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 > is normal flash content, id2 is normal flash content > > Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is > normal flash content, id2 is normal flash content > > Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, > id1 is normal flash content, id2 is normal flash content > > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, > id1 is normal flash content, id2 is normal flash content > > Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 > 0xd0, id1 is normal flash content, id2 is normal flash content > > Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 > 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > > Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9b, id2 > 0x0c, id1 is normal flash content, id2 is normal flash content > > Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 > is normal flash content, id2 is normal flash content > > Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xc9, id2 > 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > > Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is > normal flash content, id2 is normal flash content > > Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is > normal flash content, id2 is normal flash content > > Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is > normal flash content, id2 is normal flash content > > Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is > normal flash content, id2 is normal flash content > > Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 > parity violation, id1 is normal flash content, id2 is normal flash content > > Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9b, id2 > 0x0c, id1 is normal flash content, id2 is normal flash content > > Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9b, id2 > 0x0c, id1 is normal flash content, id2 is normal flash content > > Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9b, id2 > 0x0c, id1 is normal flash content, id2 is normal flash content > > Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 > 0xd0, id1 is normal flash content, id2 is normal flash content > > Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xc9, id2 > 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash > content > > Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 > 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash content > > No EEPROM/flash device found. > > Note: flashrom can never write if the flash chip isn't found automatically. > > Restoring PCI config space for 00:1f:0 reg 0xdc > >

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Re: [flashrom] GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"
by David Hendricks 19 Mar '14

19 Mar '14

On Wed, Mar 19, 2014 at 5:58 AM, Allen Yan <lexkde(a)gmail.com> wrote: > Hi, David, > I was reading flashrom code base following the internal programmer > way. I also read mail > "http://www.flashrom.org/pipermail/flashrom/2013-March/010704.html" > and checked the Ibex peak datasheet about ME firmware. Here are some > questions: > about "Locking and unlocking of access protections of flash chips" > 1 which mechanism locks the flash?a software way or a hardware way > by the programmer. As in the Atmel AT25DL161, the protection ways are > "hardware protection, using WP pin", "Sector lockdown with permanent > freeze option", "individual sector protection with global > protect/unprotect feature". > All of the above :-) You will need to determine: - Which write-protection scheme is in place? Is it intended to prevent erroneous software from writing to the flash, or is it intended to prevent any re-writing of the flash? - Can it be disabled / worked around so that content can be updated? - How to restore the settings when you are finished. > 2 Does this problem concerns the ME firmware issue. > Yes. > 3 How to do the test? Is the test at specific mainboard and flash chip > enough? > IIRC Flashrom already tests for motherboards which are known to require a workaround, for example if a GPIO must be inverted in order to de-assert /WP. board_enable.c has many of these tests. It also knows about block protect bits in SPI ROMs. I think the main issue with modern systems (Intel in particular) is the management engine. > 4 How to value the work at last as stefan mentioned in the suggestion? > > > Actually, a little frustrating after I saw stefanct's mail. > It's very valuable :-) I put some effort into this functionality for ChromeOS, since handling write-protection is a requirement for Chromebooks. Here are some examples: Skip regions locked via flash descriptor for Intel platforms: https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/1ed1d35… writeprotect.c, which contains block protect mapping for several flash chips: https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/master/… Unfortunately we never reached a consensus regarding how to port this code to upstream. It would be nice if somebody like you can help to re-factor this code so that it can be accepted upstream. > On 3/18/14, Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > > On Mon, 17 Mar 2014 09:56:43 +0800 > > 严进一 <lexkde(a)gmail.com> wrote: > > > >> Hi, > >> I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of > >> Micro-system and Information Technology, Chinese Academy of Sciences. I > >> used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd > >> for about two years (2007.7~2009.2). My major now is optoelectronics. > But > >> I have a lot of fun while programming, in my heart the working > experience > >> of being a BIOS engineer is still very exciting. > >> I think GsoC is a nice platform for me to participate the open source > >> community. When I search the GsoC projects and organizations, the > coreboot > >> and flashrom projects are definitely the right choices for me. I have a > >> spare ASUS P5KPL PC at my hand, but the chipset is not in the support > list > >> of coreboot project. So I consider the flashrom project is the better > >> choice. I also have a home-made flash programmer based on uspasp. > >> I'd like to choose “Locking and unlocking of access protections of flash > >> chips” for GSoC 2014. > >> Now I'm not very familiar with the program structure of flashrom, so I > >> expect your guidence and hope to contribute for flashrom and coreboot > even > >> if my application is not accpeted. > >> Thanks! Look forward to your kind advice! > > > > Hello Jinyi, > > > > thanks for your interest in flashrom. I have been the most active > > flashrom developer in the last years and would probably be responsible > > to integrate your work and answer questions if you get stuck. I agree > > that the coreboot-related projects are probably the best choice for you > > (there are not many low-level projects participating sadly... that's > > how I ended up here too ;). I also have to admit that the P5KPL is > > probably not very helpful AFAICT. But I don't think that this is a show > > stopper regarding coreboot (or seabios) projects and that your skills > > and insights obtained at ASUS regarding x86 might be more useful in a > > non-flashrom project. Also, the project you chose requires to > > understand two code bases ("ours" and that maintained by google/ > > chromiumos ppl) and interact with two communities and persuade at least > > one of them that your solution is sound and profitable. On the other > > hand, I am biased because I will apply for a flashrom GSoC project > > myself probably. ;) > > The code bases have a very similar core so that should not be a big > > issue at all. Producing something that will be praised by everyone on > > the other hand is really hard. The vanilla flashrom community is > > traditionally very (very) picky regarding changes, especially user > > interface changes. This is also the reason why there is a chromiumos > > fork of flashrom... > > > > I have talked to David (dhendrix) and he is willing to mentor you this > > year. If you want to pursue this project (and the patch you sent seems > > to indicate that ;) I suggest you talk to him directly about details > > of the assignment (here or on IRC). > > > > Adding new flash chips as you have done is a very good first step to > > get to know flashrom a bit better. The fun begins with the awkward > > models though :) > > I suggest you test flashrom on any hardware available to you (including > > network cards for example)... there is always room for improvement and > > learning a foreign code base is always easier when on has a specific > > goal to reach. > > -- > > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > > _______________________________________________ > > flashrom mailing list > > flashrom(a)flashrom.org > > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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FAILED: PCENGINES APU
by markus 19 Mar '14

19 Mar '14

C:\>flashrom -p internal:laptop=this_is_not_a_laptop -c MX25L1605A/MX25L1606E -w APUBIO.ROM flashrom v0.9.6.1-r1705 on FreeDOS 7 (i786) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. pcilib: Bus 00 seen twice (firmware bug). Ignored. coreboot table found at 0x7e17cc00. Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". ======================================================================== WARNING! You may be running flashrom on an unsupported laptop. We could not detect this for sure because your vendor has not setup the SMBIOS tables correctly. You can enforce execution by adding '-p internal:laptop=this_is_not_a_laptop' to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Macronix flash chip "MX25L1605A/MX25L1606E" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x00000000! Expected=0x4c, Found=0xcc, failed byte count from 0x00000000-0x001fffff: 0xe2a0 Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! -- Best regards, Markus Better Privacy with PGP encrypted Mail: http://activezone.de/pgp/ Fingerprint: 58C5 8BAF 6FCE B24F 1881 B5B8 F2A8 E1D0 484B 0054 Threema ID: 7ZRET2JY „Wer die Freiheit aufgibt um Sicherheit zu gewinnen, der wird am Ende beides verlieren.“ -- Benjamin Franklin

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[commit] r1769 - trunk
by repository service 19 Mar '14

19 Mar '14

Author: stefanct Date: Wed Mar 19 18:17:06 2014 New Revision: 1769 URL: http://flashrom.org/trac/flashrom/changeset/1769 Log: linux_spi: Stop messing up the units of SPI speed. 'speed' is stored in Hz, so rename the variable to 'speed_hz' to clarify any potential confusion. Also, when printing the speed after setting it with an ioctl, convert it to kHz to match the units given in the message. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Wed Mar 19 18:17:00 2014 (r1768) +++ trunk/linux_spi.c Wed Mar 19 18:17:06 2014 (r1769) @@ -60,7 +60,7 @@ int linux_spi_init(void) { char *p, *endp, *dev; - uint32_t speed = 0; + uint32_t speed_hz = 0; /* FIXME: make the following configurable by CLI options. */ /* SPI mode 0 (beware this also includes: MSB first, CS active low and others */ const uint8_t mode = SPI_MODE_0; @@ -68,7 +68,7 @@ p = extract_programmer_param("spispeed"); if (p && strlen(p)) { - speed = (uint32_t)strtoul(p, &endp, 10) * 1000; + speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); free(p); @@ -98,14 +98,14 @@ return 1; /* We rely on the shutdown function for cleanup from here on. */ - if (speed > 0) { - if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) { + if (speed_hz > 0) { + if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed_hz) == -1) { msg_perr("%s: failed to set speed to %d Hz: %s\n", - __func__, speed, strerror(errno)); + __func__, speed_hz, strerror(errno)); return 1; } - msg_pdbg("Using %d kHz clock\n", speed); + msg_pdbg("Using %d kHz clock\n", speed_hz/1000); } if (ioctl(fd, SPI_IOC_WR_MODE, &mode) == -1) {

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[commit] r1768 - trunk
by repository service 19 Mar '14

19 Mar '14

Author: stefanct Date: Wed Mar 19 18:17:00 2014 New Revision: 1768 URL: http://flashrom.org/trac/flashrom/changeset/1768 Log: linux_spi: Fix conversion from kHz to Hz. A kilohertz is exactly 1000 hertz, not 1024 hertz. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Mon Mar 17 23:07:29 2014 (r1767) +++ trunk/linux_spi.c Wed Mar 19 18:17:00 2014 (r1768) @@ -68,7 +68,7 @@ p = extract_programmer_param("spispeed"); if (p && strlen(p)) { - speed = (uint32_t)strtoul(p, &endp, 10) * 1024; + speed = (uint32_t)strtoul(p, &endp, 10) * 1000; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); free(p);

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Intel S5000PAL: Flash Not Found
by Sean Everson 19 Mar '14

19 Mar '14

*All,I have a number of Intel S5000PAL motherboards that I would like to use FLASHROM to manage if at all possible. According to the Intel Docs at:http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000p… <http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000pal_…>The box contains the 6321ESB chipset which is listed as supported on the flashrom.org <http://flashrom.org> wiki page.When I try to use FLASHROM to read the flash I get an error message that the flash is not found. Can someone provide me with some guidance on what additional information or steps I can take to investigate this further?I am including the output from flashrom -V below.Thanks for your help!--Sean# ./flashrom -V -p internal -r /tmp/bios.binflashrom v0.9.7-r1764 on Linux 2.6.32.24 (x86_64)flashrom is free software, get the source code at http://www.flashrom.org <http://www.flashrom.org>flashrom was built with libpci 3.2.1, GCC 4.7.1, little endianCommand line (5 args): ./flashrom -V -p internal -r /tmp/bios.binCalibrating delay loop... OS timer resolution is 1 usecs, 2824M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10025 us, 4 myus = 4 us, OK.Initializing internal programmerNo coreboot table found.Using Internal DMI decoder.DMI string chassis-type: "Rack Mount Chassis"DMI string system-manufacturer: "Intel"DMI string system-product-name: "T5000PAL"DMI string system-version: "Not Specified"DMI string baseboard-manufacturer: "Intel"DMI string baseboard-product-name: "T5000PAL0 "DMI string baseboard-version: "FRU Ver 0.05"W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect.Active config mode, unknown reg 0x20 ID: f2.Please send the output of "flashrom -V" to flashrom(a)flashrom.org <flashrom(a)flashrom.org> with W836xx: your board name: flashrom -Vas the subject to help us finish support for your Super I/O. Thanks.Found chipset "Intel 631xESB/632xESB/3100" with PCI ID 8086:2670. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x00xfff00000/0xffb00000 FWH IDSEL: 0x00xffe80000/0xffa80000 FWH IDSEL: 0x00xffe00000/0xffa00000 FWH IDSEL: 0x00xffd80000/0xff980000 FWH IDSEL: 0x00xffd00000/0xff900000 FWH IDSEL: 0x00xffc80000/0xff880000 FWH IDSEL: 0x00xffc00000/0xff800000 FWH IDSEL: 0x00xff700000/0xff300000 FWH IDSEL: 0x40xff600000/0xff200000 FWH IDSEL: 0x50xff500000/0xff100000 FWH IDSEL: 0x60xff400000/0xff000000 FWH IDSEL: 0x70xfff80000/0xffb80000 FWH decode enabled0xfff00000/0xffb00000 FWH decode enabled0xffe80000/0xffa80000 FWH decode enabled0xffe00000/0xffa00000 FWH decode enabled0xffd80000/0xff980000 FWH decode enabled0xffd00000/0xff900000 FWH decode enabled0xffc80000/0xff880000 FWH decode enabled0xffc00000/0xff800000 FWH decode enabled0xff700000/0xff300000 FWH decode disabled0xff600000/0xff200000 FWH decode disabled0xff500000/0xff100000 FWH decode disabled0xff400000/0xff000000 FWH decode disabledMaximum FWH chip size: 0x400000 bytesSPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x03: BIOS Lock Enable: enabled, BIOS Write Enable: enabledWarning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed.New value is 0x03.OK.The following protocols are supported: FWH.Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW040, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentNo EEPROM/flash device found.Note: flashrom can never write if the flash chip isn't found automatically.Restoring PCI config space for 00:1f:0 reg 0xdc*

1 0

GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"
by 严进一 19 Mar '14

19 Mar '14

Hi, I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. I used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is optoelectronics. But I have a lot of fun while programming, in my heart the working experience of being a BIOS engineer is still very exciting. I think GsoC is a nice platform for me to participate the open source community. When I search the GsoC projects and organizations, the coreboot and flashrom projects are definitely the right choices for me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in the support list of coreboot project. So I consider the flashrom project is the better choice. I also have a home-made flash programmer based on uspasp. I'd like to choose “Locking and unlocking of access protections of flash chips” for GSoC 2014. Now I'm not very familiar with the program structure of flashrom, so I expect your guidence and hope to contribute for flashrom and coreboot even if my application is not accpeted. Thanks! Look forward to your kind advice! Regards, Jinyi Yan

3 2

Micron N25Q512, or at least its lower quarter
by David Madl 19 Mar '14

19 Mar '14

Hi, I have a new prototype development board here, with an 512 MBit Flash chip, Micron N25Q512 (precise type is N25Q512A11G40). I managed to create a config [1] that reads fine, but fails to write [2]. I understand that flashrom cannot access chips larger than 16 MBytes, but the chip should still be able to work in 3-byte addressing mode for the lower 16 MBytes. This is what I have created in flashchips.c (copy & pasted, then adapted from the part N25Q128, assuming with a bit of good faith and some datasheet comparison that they should behave alike). Has anyone ever successfully written to a small part of a 4-byte flash chip? Thanks, David ========================= [1] new stuff for flashchips.c { .vendor = "Micron/Numonyx/ST", .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q512__3E, /* .total_size = 65536,*/ .total_size = 16384, .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { /*.eraseblocks = { {4 * 1024, 16384 } },*/ .eraseblocks = { {4 * 1024, 4096 } }, .block_erase = spi_block_erase_20, }, { /*.eraseblocks = { {64 * 1024, 1024} },*/ .eraseblocks = { {64 * 1024, 256} }, .block_erase = spi_block_erase_d8, }, { /*.eraseblocks = { {65536 * 1024, 1} },*/ .eraseblocks = { {16384 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, ========================= [2] output from flashrom trying to write, and failing: # /root/flashrom -p ft2232_spi:type=232H,divisor=8 -c 'N25Q512..3E' -V -w flash.rom flashrom v0.9.7-r1711 on Linux 3.13.6-1-ARCH (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2 20140206 (prerelease), little endian Command line (7 args): /root/flashrom -p ft2232_spi:type=232H,divisor=8 -c N25Q512..3E -V -w flash.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1588M loops per second, 10 myus = 9 us, 100 myus = 117 us, 1000 myus = 1005 us, 10000 myus = 10324 us, 4 myus = 4 us, OK. Initializing ft2232_spi programmer Using device type FTDI FT232H channel A. Disable divide-by-5 front stage Set clock divisor MPSSE clock: 60.000000 MHz, divisor: 8, SPI clock: 7.500000 MHz No loopback of TDI/DO TDO/DI Set data bits The following protocols are supported: SPI. Probing for Micron/Numonyx/ST N25Q512..3E, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba20 Found Micron/Numonyx/ST flash chip "N25Q512..3E" (16384 kB, SPI) on ft2232_spi. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Top/Bottom (TB) is top Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W, 0x001000-0x001fff:E FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00001000-0x00001fff: 0x1000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:E FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0x10000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0xffffff:E FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00ffffff: 0x1000000 ERASE FAILED! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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Re: [flashrom] CHIPSET: ALIX 2d13
by Stefan Tauner 18 Mar '14

18 Mar '14

On Tue, 18 Mar 2014 21:44:10 +0100 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2014-03-18 18:49 GMT+01:00 Timo Buhrmester <timo(a)math.uni-bonn.de>: > > > flashrom on debian wheezy told me to mail you. > > The board in question is this one: http://pcengines.ch/alix2d13.htm > > > > > Found chipset "AMD CS5536". Enabling flash write... OK. > > > WARNING: unexpected second chipset match: "AMD CS5536" > > > ignoring, please report lspci and board URL to flashrom(a)flashrom.org > > > with 'CHIPSET: your board name' in the subject line. > > > Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address > > 0xfff00000. > > > Reading flash... done. > > > > # lspci -vvvxxx > > 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] > > Host Bridge (rev 33) > > Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] > > Host Bridge > > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- > > ParErr- Stepping- SERR- FastB2B- DisINTx- > > Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > > <TAbort- <MAbort- >SERR- <PERR- INTx- > > Latency: 248, Cache Line Size: 32 bytes > > Region 0: I/O ports at ac1c [size=4] > > 00: 22 10 80 20 05 00 20 02 33 00 00 06 08 f8 80 00 > > > ^^^^^^ ^^^^^^ > The above numbers read as 0x1022, 0x2080 > > Only one line should match, see > https://github.com/stefanct/flashrom/blob/master/chipset_enable.c#L1375 > Which version of flashrom are you using? THAT device is only matched ONCE, but 00:0f.0 is 0x1022, 0x2090: 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) […] 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

CHIPSET: ALIX 2d13
by Timo Buhrmester 18 Mar '14

18 Mar '14

flashrom on debian wheezy told me to mail you. The board in question is this one: http://pcengines.ch/alix2d13.htm > Found chipset "AMD CS5536". Enabling flash write... OK. > WARNING: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom(a)flashrom.org > with 'CHIPSET: your board name' in the subject line. > Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. > Reading flash... done. # lspci -vvvxxx 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 248, Cache Line Size: 32 bytes Region 0: I/O ports at ac1c [size=4] 00: 22 10 80 20 05 00 20 02 33 00 00 06 08 f8 80 00 10: 1d ac 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block Subsystem: Advanced Micro Devices [AMD] Geode LX AES Security Block Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at efff4000 (32-bit, non-prefetchable) [size=16K] Kernel driver in use: Geode LX AES 00: 22 10 82 20 06 00 a0 02 00 00 10 10 08 00 00 00 10: 00 40 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 82 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 09 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at 1000 [size=256] Region 1: Memory at e0000000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 10 00 00 00 00 00 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 1400 [size=256] Region 1: Memory at e0040000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 14 00 00 00 00 04 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 15 Region 0: I/O ports at 1800 [size=256] Region 1: Memory at e0080000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 18 00 00 00 00 08 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0f 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: I/O ports at 6000 [size=8] Region 1: I/O ports at 6100 [size=256] Region 2: I/O ports at 6200 [size=64] Region 3: I/O ports at <unassigned> Region 4: I/O ports at 9d00 [size=128] Region 5: I/O ports at 9c00 [size=64] Kernel driver in use: cs5535-mfd 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 10: 01 60 00 00 01 61 00 00 01 62 00 00 01 00 00 00 20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) (prog-if 80 [Master]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 248, Cache Line Size: 32 bytes Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at ff00 [size=16] Kernel driver in use: pata_amd 00: 22 10 9a 20 05 00 a0 02 01 80 01 01 08 f8 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ff 00 00 00 00 00 00 00 00 00 00 22 10 9a 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 02 f0 00 00 00 00 00 00 00 00 99 20 2a 00 00 20 50: 00 00 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.4 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 12 Region 0: Memory at efffe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: 22 10 94 20 06 00 30 02 02 10 03 0c 08 00 00 00 10: 00 e0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 04 00 00 40: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.5 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 12 Region 0: Memory at efffd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: 22 10 95 20 06 00 30 02 02 20 03 0c 08 00 00 00 10: 00 d0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 04 00 00 40: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ------------>8------------------------------------------------- Kind Regards, Timo Buhrmester

2 1

Re: [flashrom] [PATCH] Add support for 82574L to nicintel_spi.c
by Bill Paul 17 Mar '14

17 Mar '14

Of all the gin joints in all the towns in all the world, Idwer Vollering had to walk into mine at 02:09:35 on Friday 14 March 2014 and say: > 2014-03-13 22:59 GMT+01:00 Bill Paul <wpaul(a)windriver.com>: > > I recently found a need to re-flash the option ROM on an Intel 82574L > > gigabit > > ethernet card. These are a bit more common these days than the 82571 and > > 82572 > > and relatively cheap. It turns out this works with flashrom, but it > > doesn't detect the PCI ID for the device out of the box. Below is a > > patch add it to nicintel_spi.c. Note that there are probably other > > devices in the PRO/1000 family that would work too. > > > > Here's an example run with the latest code from svn: > > > > [...] > > flashrom v0.9.7-unknown on FreeBSD 10.0-RELEASE (amd64) > > flashrom is free software, get the source code at http://www.flashrom.org > > > > Calibrating delay loop... OK. > > Found Winbond flash chip "W25X40" (512 kB, SPI) on nicintel_spi. > > Reading old flash chip contents... done. > > Erasing and writing flash chip... Erase/write done. > > Verifying flash... VERIFIED. > > [...] > > > > FreeBSD detects the device as follows: > > > > em1@pci0:2:0:0: class=0x020000 card=0xa01f8086 chip=0x10d38086 rev=0x00 > > hdr=0x00 > > > > vendor = 'Intel Corporation' > > device = '82574L Gigabit Network Connection' > > class = network > > subclass = ethernet > > > > I also added links to the Intel PCIe ethernet controllers programming > > manual > > and the 82574 datasheet. > > > > Incidentally, thanks to everyone involved for their work in this project. > > It > > helped me out of a bit of a jam. > > > > -Bill > > > > Signed-off-by: Bill Paul <wpaul(a)windriver.com> > > This patch is Acked-by: Idwer Vollering <vidwer(a)gmail.com> > when you adjust the PDF URL in a follow-up patch, see below. Updated patch is below. -Bill Signed-off-by: Bill Paul <wpaul(a)windriver.com> Index: nicintel_spi.c =================================================================== --- nicintel_spi.c (revision 1766) +++ nicintel_spi.c (working copy) @@ -17,14 +17,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* - * Datasheet: + * Datasheets: * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx - * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf + * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x- family-gbe-controllers-software-dev-manual.html + * + * PCIe GbE Controllers Open Source Software Developer's Manual + * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe- controllers-open-source-manual.html + * + * Intel 82574 Gigabit Ethernet Controller Family Datasheet + * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe- controller-datasheet.html */ #include <stdlib.h> #include <unistd.h> #include "flash.h" @@ -70,10 +76,11 @@ const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, {0}, }; static void nicintel_request_spibus(void) -- ============================================================================= -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, wpaul(a)windriver.com | Master of Unix-Fu - Wind River Systems ============================================================================= "I put a dollar in a change machine. Nothing changed." - George Carlin =============================================================================

2 1

[commit] r1767 - trunk
by repository service 17 Mar '14

17 Mar '14

Author: stefanct Date: Mon Mar 17 23:07:29 2014 New Revision: 1767 URL: http://flashrom.org/trac/flashrom/changeset/1767 Log: Add support for Intel 82574L to nicintel_spi.c. Signed-off-by: Bill Paul <wpaul(a)windriver.com> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/nicintel_spi.c Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Fri Mar 14 09:10:02 2014 (r1766) +++ trunk/nicintel_spi.c Mon Mar 17 23:07:29 2014 (r1767) @@ -19,10 +19,16 @@ */ /* - * Datasheet: + * Datasheets: * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx - * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf + * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-famil… + * + * PCIe GbE Controllers Open Source Software Developer's Manual + * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-contro… + * + * Intel 82574 Gigabit Ethernet Controller Family Datasheet + * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-cont… */ #include <stdlib.h> @@ -72,6 +78,7 @@ {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, {0}, };

1 0

Re: [flashrom] Erase failed
by Leonardo Pedretti 17 Mar '14

17 Mar '14

Nevermind! I risked downloading and compiling the last build, selected the internal programmer and worked like a charm! Thank you very much!! Best regards! ---------------------------------------------------------------------------------- Leonardo Pedretti Código Dínamo +54 11 50935333 / +54 11 15 35745251 http://www.codigodinamo.com 2014-03-17 15:29 GMT-03:00 Leonardo Pedretti <lpedretti(a)codigodinamo.com>: > Hey! sorry to bother you, i really try to help myself out, but in this > case i lack any knowledge of the details of bios memory management. > I have tried to flash the bios on my k8n Neo4 Platinum pcb v 1.0, the > write started giving errors, output follows... > > flashrom v0.9.2-r1141 on Linux 2.6.32-5-686 (i686), built with libpci > 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "NVIDIA CK804", enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Disabling flash write protection for board "MSI K8N Neo4-F"... OK. > Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address > 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Erasing flash chip... SUCCESS. > Programming page: address: 0x00040000 writing sector at 0xb744d000 failed! > > writing sector at 0xb744d400 failed! > writing sector at 0xb744d800 failed! > writing sector at 0xb744dc00 failed! > address: 0x00041000 writing sector at 0xb744e000 failed! > > writing sector at 0xb744e400 failed! > writing sector at 0xb744e800 failed! > writing sector at 0xb744ec00 failed! > address: 0x00042000 writing sector at 0xb744f000 failed! > > writing sector at 0xb744f400 failed! > writing sector at 0xb744f800 failed! > writing sector at 0xb744fc00 failed! > address: 0x00043000 writing sector at 0xb7450000 failed! > > writing sector at 0xb7450400 failed! > writing sector at 0xb7450800 failed! > writing sector at 0xb7450c00 failed! > address: 0x00044000 writing sector at 0xb7451000 failed! > > writing sector at 0xb7451400 failed! > writing sector at 0xb7451800 failed! > writing sector at 0xb7451c00 failed! > address: 0x00045000 writing sector at 0xb7452000 failed! > > writing sector at 0xb7452400 failed! > writing sector at 0xb7452800 failed! > writing sector at 0xb7452c00 failed! > address: 0x00046000 writing sector at 0xb7453000 failed! > > writing sector at 0xb7453400 failed! > writing sector at 0xb7453800 failed! > writing sector at 0xb7453c00 failed! > address: 0x00047000 writing sector at 0xb7454000 failed! > > writing sector at 0xb7454400 failed! > writing sector at 0xb7454800 failed! > writing sector at 0xb7454c00 failed! > address: 0x00048000 writing sector at 0xb7455000 failed! > > writing sector at 0xb7455400 failed! > writing sector at 0xb7455800 failed! > writing sector at 0xb7455c00 failed! > address: 0x00049000 writing sector at 0xb7456000 failed! > > writing sector at 0xb7456400 failed! > writing sector at 0xb7456800 failed! > writing sector at 0xb7456c00 failed! > address: 0x0004a000 writing sector at 0xb7457000 failed! > > writing sector at 0xb7457400 failed! > writing sector at 0xb7457800 failed! > writing sector at 0xb7457c00 failed! > address: 0x0004b000 writing sector at 0xb7458000 failed! > > writing sector at 0xb7458400 failed! > writing sector at 0xb7458800 failed! > writing sector at 0xb7458c00 failed! > address: 0x0004c000 writing sector at 0xb7459000 failed! > > writing sector at 0xb7459400 failed! > writing sector at 0xb7459800 failed! > writing sector at 0xb7459c00 failed! > address: 0x0004d000 writing sector at 0xb745a000 failed! > > writing sector at 0xb745a400 failed! > writing sector at 0xb745a800 failed! > writing sector at 0xb745ac00 failed! > address: 0x0004e000 writing sector at 0xb745b000 failed! > > writing sector at 0xb745b400 failed! > writing sector at 0xb745b800 failed! > writing sector at 0xb745bc00 failed! > address: 0x0004f000 writing sector at 0xb745c000 failed! > > writing sector at 0xb745c400 failed! > writing sector at 0xb745c800 failed! > writing sector at 0xb745cc00 failed! > address: 0x00050000 writing sector at 0xb745d000 failed! > > writing sector at 0xb745d400 failed! > writing sector at 0xb745d800 failed! > writing sector at 0xb745dc00 failed! > address: 0x00051000 writing sector at 0xb745e000 failed! > > writing sector at 0xb745e400 failed! > writing sector at 0xb745e800 failed! > writing sector at 0xb745ec00 failed! > address: 0x00052000 writing sector at 0xb745f000 failed! > > writing sector at 0xb745f400 failed! > writing sector at 0xb745f800 failed! > writing sector at 0xb745fc00 failed! > address: 0x00053000 writing sector at 0xb7460000 failed! > > writing sector at 0xb7460400 failed! > writing sector at 0xb7460800 failed! > writing sector at 0xb7460c00 failed! > address: 0x00054000 writing sector at 0xb7461000 failed! > > writing sector at 0xb7461400 failed! > writing sector at 0xb7461800 failed! > writing sector at 0xb7461c00 failed! > address: 0x00055000 writing sector at 0xb7462000 failed! > > writing sector at 0xb7462400 failed! > writing sector at 0xb7462800 failed! > writing sector at 0xb7462c00 failed! > address: 0x00056000 writing sector at 0xb7463000 failed! > > writing sector at 0xb7463400 failed! > writing sector at 0xb7463800 failed! > writing sector at 0xb7463c00 failed! > address: 0x00057000 writing sector at 0xb7464000 failed! > > writing sector at 0xb7464400 failed! > writing sector at 0xb7464800 failed! > writing sector at 0xb7464c00 failed! > address: 0x00058000 writing sector at 0xb7465000 failed! > > writing sector at 0xb7465400 failed! > writing sector at 0xb7465800 failed! > writing sector at 0xb7465c00 failed! > address: 0x00059000 writing sector at 0xb7466000 failed! > > writing sector at 0xb7466400 failed! > writing sector at 0xb7466800 failed! > writing sector at 0xb7466c00 failed! > address: 0x0005a000 writing sector at 0xb7467000 failed! > > writing sector at 0xb7467400 failed! > writing sector at 0xb7467800 failed! > writing sector at 0xb7467c00 failed! > address: 0x0005b000 writing sector at 0xb7468000 failed! > > writing sector at 0xb7468400 failed! > writing sector at 0xb7468800 failed! > writing sector at 0xb7468c00 failed! > address: 0x0005c000 writing sector at 0xb7469000 failed! > > writing sector at 0xb7469400 failed! > writing sector at 0xb7469800 failed! > writing sector at 0xb7469c00 failed! > address: 0x0005d000 writing sector at 0xb746a000 failed! > > writing sector at 0xb746a400 failed! > writing sector at 0xb746a800 failed! > writing sector at 0xb746ac00 failed! > address: 0x0005e000 writing sector at 0xb746b000 failed! > > writing sector at 0xb746b400 failed! > writing sector at 0xb746b800 failed! > writing sector at 0xb746bc00 failed! > address: 0x0005f000 writing sector at 0xb746c000 failed! > > writing sector at 0xb746c400 failed! > writing sector at 0xb746c800 failed! > writing sector at 0xb746cc00 failed! > DONE!ss: 0x0007f000 > COMPLETE. > Verifying flash... VERIFY FAILED at 0x00005555! Expected=0xff, Read=0xaa, > failed byte count from 0x00000000-0x0007ffff: 0x1fd7c > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org! > > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > > Thanx for any guidance! > > Best regards! > > > ---------------------------------------------------------------------------------- > Leonardo Pedretti > Código Dínamo > +54 11 50935333 / +54 11 15 35745251 > http://www.codigodinamo.com > >

1 0

Erase failed
by Leonardo Pedretti 17 Mar '14

17 Mar '14

Hey! sorry to bother you, i really try to help myself out, but in this case i lack any knowledge of the details of bios memory management. I have tried to flash the bios on my k8n Neo4 Platinum pcb v 1.0, the write started giving errors, output follows... flashrom v0.9.2-r1141 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "MSI K8N Neo4-F"... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: address: 0x00040000 writing sector at 0xb744d000 failed! writing sector at 0xb744d400 failed! writing sector at 0xb744d800 failed! writing sector at 0xb744dc00 failed! address: 0x00041000 writing sector at 0xb744e000 failed! writing sector at 0xb744e400 failed! writing sector at 0xb744e800 failed! writing sector at 0xb744ec00 failed! address: 0x00042000 writing sector at 0xb744f000 failed! writing sector at 0xb744f400 failed! writing sector at 0xb744f800 failed! writing sector at 0xb744fc00 failed! address: 0x00043000 writing sector at 0xb7450000 failed! writing sector at 0xb7450400 failed! writing sector at 0xb7450800 failed! writing sector at 0xb7450c00 failed! address: 0x00044000 writing sector at 0xb7451000 failed! writing sector at 0xb7451400 failed! writing sector at 0xb7451800 failed! writing sector at 0xb7451c00 failed! address: 0x00045000 writing sector at 0xb7452000 failed! writing sector at 0xb7452400 failed! writing sector at 0xb7452800 failed! writing sector at 0xb7452c00 failed! address: 0x00046000 writing sector at 0xb7453000 failed! writing sector at 0xb7453400 failed! writing sector at 0xb7453800 failed! writing sector at 0xb7453c00 failed! address: 0x00047000 writing sector at 0xb7454000 failed! writing sector at 0xb7454400 failed! writing sector at 0xb7454800 failed! writing sector at 0xb7454c00 failed! address: 0x00048000 writing sector at 0xb7455000 failed! writing sector at 0xb7455400 failed! writing sector at 0xb7455800 failed! writing sector at 0xb7455c00 failed! address: 0x00049000 writing sector at 0xb7456000 failed! writing sector at 0xb7456400 failed! writing sector at 0xb7456800 failed! writing sector at 0xb7456c00 failed! address: 0x0004a000 writing sector at 0xb7457000 failed! writing sector at 0xb7457400 failed! writing sector at 0xb7457800 failed! writing sector at 0xb7457c00 failed! address: 0x0004b000 writing sector at 0xb7458000 failed! writing sector at 0xb7458400 failed! writing sector at 0xb7458800 failed! writing sector at 0xb7458c00 failed! address: 0x0004c000 writing sector at 0xb7459000 failed! writing sector at 0xb7459400 failed! writing sector at 0xb7459800 failed! writing sector at 0xb7459c00 failed! address: 0x0004d000 writing sector at 0xb745a000 failed! writing sector at 0xb745a400 failed! writing sector at 0xb745a800 failed! writing sector at 0xb745ac00 failed! address: 0x0004e000 writing sector at 0xb745b000 failed! writing sector at 0xb745b400 failed! writing sector at 0xb745b800 failed! writing sector at 0xb745bc00 failed! address: 0x0004f000 writing sector at 0xb745c000 failed! writing sector at 0xb745c400 failed! writing sector at 0xb745c800 failed! writing sector at 0xb745cc00 failed! address: 0x00050000 writing sector at 0xb745d000 failed! writing sector at 0xb745d400 failed! writing sector at 0xb745d800 failed! writing sector at 0xb745dc00 failed! address: 0x00051000 writing sector at 0xb745e000 failed! writing sector at 0xb745e400 failed! writing sector at 0xb745e800 failed! writing sector at 0xb745ec00 failed! address: 0x00052000 writing sector at 0xb745f000 failed! writing sector at 0xb745f400 failed! writing sector at 0xb745f800 failed! writing sector at 0xb745fc00 failed! address: 0x00053000 writing sector at 0xb7460000 failed! writing sector at 0xb7460400 failed! writing sector at 0xb7460800 failed! writing sector at 0xb7460c00 failed! address: 0x00054000 writing sector at 0xb7461000 failed! writing sector at 0xb7461400 failed! writing sector at 0xb7461800 failed! writing sector at 0xb7461c00 failed! address: 0x00055000 writing sector at 0xb7462000 failed! writing sector at 0xb7462400 failed! writing sector at 0xb7462800 failed! writing sector at 0xb7462c00 failed! address: 0x00056000 writing sector at 0xb7463000 failed! writing sector at 0xb7463400 failed! writing sector at 0xb7463800 failed! writing sector at 0xb7463c00 failed! address: 0x00057000 writing sector at 0xb7464000 failed! writing sector at 0xb7464400 failed! writing sector at 0xb7464800 failed! writing sector at 0xb7464c00 failed! address: 0x00058000 writing sector at 0xb7465000 failed! writing sector at 0xb7465400 failed! writing sector at 0xb7465800 failed! writing sector at 0xb7465c00 failed! address: 0x00059000 writing sector at 0xb7466000 failed! writing sector at 0xb7466400 failed! writing sector at 0xb7466800 failed! writing sector at 0xb7466c00 failed! address: 0x0005a000 writing sector at 0xb7467000 failed! writing sector at 0xb7467400 failed! writing sector at 0xb7467800 failed! writing sector at 0xb7467c00 failed! address: 0x0005b000 writing sector at 0xb7468000 failed! writing sector at 0xb7468400 failed! writing sector at 0xb7468800 failed! writing sector at 0xb7468c00 failed! address: 0x0005c000 writing sector at 0xb7469000 failed! writing sector at 0xb7469400 failed! writing sector at 0xb7469800 failed! writing sector at 0xb7469c00 failed! address: 0x0005d000 writing sector at 0xb746a000 failed! writing sector at 0xb746a400 failed! writing sector at 0xb746a800 failed! writing sector at 0xb746ac00 failed! address: 0x0005e000 writing sector at 0xb746b000 failed! writing sector at 0xb746b400 failed! writing sector at 0xb746b800 failed! writing sector at 0xb746bc00 failed! address: 0x0005f000 writing sector at 0xb746c000 failed! writing sector at 0xb746c400 failed! writing sector at 0xb746c800 failed! writing sector at 0xb746cc00 failed! DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFY FAILED at 0x00005555! Expected=0xff, Read=0xaa, failed byte count from 0x00000000-0x0007ffff: 0x1fd7c Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Thanx for any guidance! Best regards! ---------------------------------------------------------------------------------- Leonardo Pedretti Código Dínamo +54 11 50935333 / +54 11 15 35745251 http://www.codigodinamo.com

1 0

Sorry for two identical mail from Jinyi Yan
by Allen Yan 17 Mar '14

17 Mar '14

Hi, I'm sorry for that I send two identical mail with subject <[flashrom] GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"> using two different mailbox. >From now on, I would only use "lexkde(a)gmail.com" as the mailbox. Thanks! Jinyi Yan

1 0

[Patch] Add support for Atmel AT25DL161
by Allen Yan 17 Mar '14

17 Mar '14

This patch adds support for Atmel AT25DL161, 2Mbytes SPI flash which look like the low voltage version of Atmel AT25DQ161. It has no pre test for now. Index: flashchips.c =================================================================== --- flashchips.c (Revision 1766) +++ flashchips.c (Arbeitskopie) @@ -1671,77 +1671,114 @@ { .vendor = "Atmel", .name = "AT25DF641(A)", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT25DF641, .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 256} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 128} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {8 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {8 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_at25df_sec, .unlock = spi_disable_blockprotect_at2x_global_unprotect_sec, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, }, - + { + .vendor = "Atmel", + .name = "AT25DL161", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25DL161, + .total_size = 2048, + .page_size = 256, + /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_at25df_sec, + .unlock = spi_disable_blockprotect_at2x_global_unprotect_sec, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, { .vendor = "Atmel", .name = "AT25DQ161", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT25DQ161, .total_size = 2048, .page_size = 256, /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 512} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 64} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {2 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {2 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_at25df_sec, .unlock = spi_disable_blockprotect_at2x_global_unprotect_sec, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, },

1 0

GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"
by yanjinyi＠mail.sim.ac.cn 17 Mar '14

17 Mar '14

Hi, I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. I used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is optoelectronics. But I have a lot of fun while programming, in my heart the working experience of being a BIOS engineer is still very exciting. I think GsoC is a nice platform for me to participate the open source community. When I search the GsoC projects and organizations, the coreboot and flashrom projects are definitely the right choices for me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in the support list of coreboot project. So I consider the flashrom project is the better choice. I also have a home-made flash programmer based on uspasp. I'd like to choose “Locking and unlocking of access protections of flash chips” for GSoC 2014. Now I'm not very familiar with the program structure of flashrom, so I expect your guidence and hope to contribute for flashrom and coreboot even if my application is not accpeted. Thanks! Look forward to your kind advice! Regards, Jinyi Yan

1 0

Z87 flash not supported flashrom 0.9.6.1+r1563-1
by Rob Whyte 16 Mar '14

16 Mar '14

Hi, as the topic reflects flashrom 0.9.6.1+r1563-1 was unable to flash my Gigabyte Z87m-d3h. Much thanks goes to Carldani on IRC for helping me get my board back to a bootable state. It would be great if the upcoming LTS of Ubuntu, Trusty 14.04 can be upgraded since these boards are common and should be supported out of the box. A great IRC community and my thanks go out to you all for the work that goes in to maintaining and updating Flashrom. For me, being blind and using text to speech I use this tool, I also recommend Flashrom to vinuxproject.org users that are also blind and want an accessible method to flash their chips. Thank you Kind regards Rob Whyte http://www.launchpad.net/~fudge

1 0

ASUS A7V8X-MX board support
by François Revol 14 Mar '14

14 Mar '14

(note I'm not subscribed to the list) This patch adds support for the ASUS A7V8X-MX motherboard. Before, despite being mentionned as supported on http://flashrom.org/Supported_hardware , flashrom failed to detect the flash chip: http://paste.flashrom.org/view.php?id=2041 After, the flash chip is detected: http://paste.flashrom.org/view.php?id=2044 It seems the trick is the same as for the MX-SE variant, which is already in. I didn't try flashing as the only other chip I have doesn't seem to be detected, probably because of incompatible pinout due to it being LPC/FWH instead of parallel. François.

2 3

[PATCH] Add support for 82574L to nicintel_spi.c
by Bill Paul 14 Mar '14

14 Mar '14

I recently found a need to re-flash the option ROM on an Intel 82574L gigabit ethernet card. These are a bit more common these days than the 82571 and 82572 and relatively cheap. It turns out this works with flashrom, but it doesn't detect the PCI ID for the device out of the box. Below is a patch add it to nicintel_spi.c. Note that there are probably other devices in the PRO/1000 family that would work too. Here's an example run with the latest code from svn: [...] flashrom v0.9.7-unknown on FreeBSD 10.0-RELEASE (amd64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25X40" (512 kB, SPI) on nicintel_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. [...] FreeBSD detects the device as follows: em1@pci0:2:0:0: class=0x020000 card=0xa01f8086 chip=0x10d38086 rev=0x00 hdr=0x00 vendor = 'Intel Corporation' device = '82574L Gigabit Network Connection' class = network subclass = ethernet I also added links to the Intel PCIe ethernet controllers programming manual and the 82574 datasheet. Incidentally, thanks to everyone involved for their work in this project. It helped me out of a bit of a jam. -Bill Signed-off-by: Bill Paul <wpaul(a)windriver.com> Index: nicintel_spi.c =================================================================== --- nicintel_spi.c (revision 1765) +++ nicintel_spi.c (working copy) @@ -17,14 +17,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* - * Datasheet: + * Datasheets: * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf + * + * PCIe GbE Controllers Open Source Software Developer's Manual + * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe- controllers-open-source-manual.html + * + * Intel 82574 Gigabit Ethernet Controller Family Datasheet + * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe- controller-datasheet.html */ #include <stdlib.h> #include <unistd.h> #include "flash.h" @@ -70,10 +76,11 @@ const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, {0}, }; static void nicintel_request_spibus(void) -- ============================================================================= -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, wpaul(a)windriver.com | Master of Unix-Fu - Wind River Systems ============================================================================= "I put a dollar in a change machine. Nothing changed." - George Carlin =============================================================================

2 1

[commit] r1766 - trunk
by repository service 14 Mar '14

14 Mar '14

Author: stefanct Date: Fri Mar 14 09:10:02 2014 New Revision: 1766 URL: http://flashrom.org/trac/flashrom/changeset/1766 Log: Add board enable for ASUS A7V8X-MX. Use the same trick as for the MX-SE variant. Despite being mentioned as supported on http://flashrom.org/Supported_hardware flashrom fails to detect the flash chip without this. Signed-off-by: François Revol <revol(a)free.fr> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Mar 5 01:16:16 2014 (r1765) +++ trunk/board_enable.c Fri Mar 14 09:10:02 2014 (r1766) @@ -2333,6 +2333,7 @@ {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise}, + {0x1106, 0x3177, 0x1043, 0x80F9, 0x1106, 0x3205, 0x1043, 0x80F9, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},

1 0

[PATCH] Add support for Intel 82574L ethernet card
by Bill Paul 13 Mar '14

13 Mar '14

I recently found a need to re-flash the option ROM on an Intel 82574L gigabit ethernet card. These are a bit more common these days than the 82571 and 82572 and relatively cheap. It turns out this works with flashrom, but it doesn't detect the PCI ID for the device out of the box. Attached is a patch add it to nicintel_spi.c. Note that there are probably other devices in the PRO/1000 family that would work too. Here's an example run with the latest code from svn: [...] flashrom v0.9.7-unknown on FreeBSD 10.0-RELEASE (amd64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25X40" (512 kB, SPI) on nicintel_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. [...] FreeBSD detects the device as follows: em1@pci0:2:0:0: class=0x020000 card=0xa01f8086 chip=0x10d38086 rev=0x00 hdr=0x00 vendor = 'Intel Corporation' device = '82574L Gigabit Network Connection' class = network subclass = ethernet I also added links to the Intel PCIe ethernet controllers programming manual and the 82574 datasheet. Incidentally, thanks to everyone involved for their work in this project. It helped me out of a bit of a jam. -Bill -- ============================================================================= -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, wpaul(a)windriver.com | Master of Unix-Fu - Wind River Systems ============================================================================= "I put a dollar in a change machine. Nothing changed." - George Carlin =============================================================================

1 0

[PATCH] Refactor spi_read_status_register usage
by Carl-Daniel Hailfinger 08 Mar '14

08 Mar '14

spi_read_status_register() is used in open-coded loops everywhere just to check if SPI_SR_WIP bit cleared. The logic is missing a timeout detection, and we can save quite a lot of code by introducing a function which waits until SPI_SR_WIP is cleared or a timeout is reached. Untested. May explode. Unfinished. More functions need to be converted to the new style. Will change behaviour if the chip is too slow or hangs. Should prevent flashrom from hanging without any visible output. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_rdsr_refactor/spi25.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25.c (Arbeitskopie) @@ -328,14 +328,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_60); + return result; } int spi_chip_erase_62(struct flashctx *flash) @@ -365,14 +360,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 2-5 s, so wait in 100 ms steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_62); + return result; } int spi_chip_erase_c7(struct flashctx *flash) @@ -401,14 +391,9 @@ msg_cerr("%s failed during command execution\n", __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_C7); + return result; } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, @@ -444,13 +429,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_52); + return result; } /* Block size is usually @@ -491,13 +472,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D8); + return result; } /* Block size is usually @@ -536,13 +513,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D7); + return result; } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ @@ -579,13 +552,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_SE); + return result; } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -619,13 +588,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_50); + return result; } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -659,13 +624,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 8 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_81); + return result; } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, Index: flashrom-spi_rdsr_refactor/spi25_statusreg.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25_statusreg.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25_statusreg.c (Arbeitskopie) @@ -43,7 +43,6 @@ static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) { int result; - int i = 0; /* * WRSR requires either EWSR or WREN depending on chip type. * The code below relies on the fact hat EWSR and WREN have the same @@ -78,17 +77,10 @@ /* WRSR performs a self-timed erase before the changes take effect. * This may take 50-85 ms in most cases, and some chips apparently * allow running RDSR only once. Therefore pick an initial delay of - * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. + * 100 ms, then wait until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register(flash) & SPI_SR_WIP) { - if (++i > 490) { - msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; - } - programmer_delay(10 * 1000); - } - return 0; + return spi_wait_status_register_ready(flash, 4900 * 1000, JEDEC_WRSR); } int spi_write_status_register(struct flashctx *flash, int status) @@ -108,6 +100,28 @@ return ret; } +/* timeout is specified in usecs. */ +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode) +{ + /* At least 1 usec between iterations. */ + int single_delay = (timeout / 100) ? : 1; + int elapsed = 0; + int halftime = 0; + + while (spi_read_status_register(flash) & SPI_SR_WIP) { + elapsed += single_delay; + if ((elapsed > timeout / 2) && !halftime) { + msg_cdbg("Debug: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout/2); + } + if (elapsed >= timeout) { + msg_cerr("Error: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout); + return TIMEOUT_ERROR; + } + programmer_delay(single_delay); + } + return 0; +} + uint8_t spi_read_status_register(struct flashctx *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; Index: flashrom-spi_rdsr_refactor/chipdrivers.h =================================================================== --- flashrom-spi_rdsr_refactor/chipdrivers.h (Revision 1653) +++ flashrom-spi_rdsr_refactor/chipdrivers.h (Arbeitskopie) @@ -60,6 +60,7 @@ /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode); int spi_write_status_register(struct flashctx *flash, int status); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_bp1(struct flashctx *flash); -- http://www.hailfinger.org/

1 1

Flashrom work with motherboard ASUS M3N-H/HDMI
by Franc SERRES 05 Mar '14

05 Mar '14

Hi I'm correctly flashing my motherboard ASUS M3N-H/HDMI for upgrading to a new official ASUS BIOS under Kubuntu 13.10. I join a tar.gz file with all results of manipulations how it's ask by this software. Thank's for your great Jobs guy Sincerely Franc SERRES -- Que l'Open source soit avec toi. Utilise l'Open source Luc... A non-text attachment has been stripped: FlashBIOS_ASUS_M3N-H⁄HDMI.tar.gz It is available at http://paste.flashrom.org/view.php?id=2039

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Re: [flashrom] [Ubuntu] Dediprog SF100 support with Winbond W25Q64FW
by Kurt Qiao 05 Mar '14

05 Mar '14

Hi Carl, i found dediprog_spi_send_command in dediprog.c, after below action: ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, (char *)readarr, readcnt, DEFAULT_TIMEOUT); readarr will become 0x534631 ("SF1"), even i didn't put a ROM on my SF100. i have no idea about this usb device request, the meaning of wValue 0xbb8 to dediprog device hope this info help for debug, thanks. BR, Kurt 2014-03-05 8:35 GMT+08:00 Kurt Qiao <kurtqqh(a)gmail.com>: > resent loop flashrom.org > > Hi Carl, > > Thanks for reply. > 1. i update SF100 fm to v5.5.0, need to support windows8 > 2. here's my libusb dpkg info > ii libusb-0.1-4 2:0.1.12-20 userspace USB programming library > ii libusb-1.0-0 2:1.0.9~rc3-2u userspace USB programming library > ii libusb-dev 2:0.1.12-20 userspace USB programming library > developmen > > BR, > Kurt > > > 2014-03-05 8:33 GMT+08:00 Kurt Qiao <kurtqqh(a)gmail.com>: > > Hi Carl, >> >> Thanks for reply. >> 1. i update SF100 fm to v5.5.0, need to support windows8 >> 2. here's my libusb dpkg info >> ii libusb-0.1-4 2:0.1.12-20 userspace USB programming library >> ii libusb-1.0-0 2:1.0.9~rc3-2u userspace USB programming library >> ii libusb-dev 2:0.1.12-20 userspace USB programming library >> developmen >> >> BR, >> Kurt >> >> >> 2014-03-05 8:14 GMT+08:00 Carl-Daniel Hailfinger < >> c-d.hailfinger.devel.2006(a)gmx.net>: >> >> Hi Kurt, >>> >>> Am 24.02.2014 09:29 schrieb Kurt Qiao: >>> > hope anyone can help me out, i try to implement flashrom to support >>> > dediprog SF100 on my Ubuntu. config as below: >>> > OS: Ubuntu12.04 X64 >>> > Dediprog: SF100, fm ver: 5.5.0 >>> >>> We only have tested flashrom support with SF100 firmware versions from >>> 2.0 to 5.2. It should work with firmware version 5.5, but we have not >>> tested it. >>> >>> >>> > SPI ROM: winbond W25Q64FW, id 0xef 6017 >>> > >>> > plugging my SF100, and use below cmd >>> > flashrom -p dediprog -V >>> > i can see the program detect my sf100 but fail to detect the SPI >>> ROM. log >>> > as attached file. >>> > ---log---- >>> > Probing for Winbond W25Q64.V, 8192 kB: RDID byte 0 parity violation. >>> > probe_spi_rdid_generic: id1 0x53, id2 0x4631 >>> > ----log--- >>> > >>> > as the log shows, seems flashrom read SPI ROM id is 0x53, 0x4631, >>> but >>> > actually my SPI ROM on board is winbond with id 0xef, 0x6017(i confirm >>> this >>> > with windows dediprog). >>> > so i have no idea why flashrom detect wrong id, and the flashchips.h >>> > already have WINBOND_NEX_W25Q64_W 0x6017 support. >>> >>> 0x53 0x46 0x31 is the string "SF1". This string is returned by the SF100 >>> if we query the firmware version. >>> I think we have a bug in the dediprog firmware or in the dediprog driver >>> or in libusb. Which version of libusb are you using? >>> >>> Regards, >>> Carl-Daniel >>> >>> -- >>> http://www.hailfinger.org/ >>> >>> >> >

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Re: [flashrom] [Ubuntu] Dediprog SF100 support with Winbond W25Q64FW
by Kurt Qiao 05 Mar '14

05 Mar '14

resent loop flashrom.org Hi Carl, Thanks for reply. 1. i update SF100 fm to v5.5.0, need to support windows8 2. here's my libusb dpkg info ii libusb-0.1-4 2:0.1.12-20 userspace USB programming library ii libusb-1.0-0 2:1.0.9~rc3-2u userspace USB programming library ii libusb-dev 2:0.1.12-20 userspace USB programming library developmen BR, Kurt 2014-03-05 8:33 GMT+08:00 Kurt Qiao <kurtqqh(a)gmail.com>: > Hi Carl, > > Thanks for reply. > 1. i update SF100 fm to v5.5.0, need to support windows8 > 2. here's my libusb dpkg info > ii libusb-0.1-4 2:0.1.12-20 userspace USB programming library > ii libusb-1.0-0 2:1.0.9~rc3-2u userspace USB programming library > ii libusb-dev 2:0.1.12-20 userspace USB programming library > developmen > > BR, > Kurt > > > 2014-03-05 8:14 GMT+08:00 Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2006(a)gmx.net>: > > Hi Kurt, >> >> Am 24.02.2014 09:29 schrieb Kurt Qiao: >> > hope anyone can help me out, i try to implement flashrom to support >> > dediprog SF100 on my Ubuntu. config as below: >> > OS: Ubuntu12.04 X64 >> > Dediprog: SF100, fm ver: 5.5.0 >> >> We only have tested flashrom support with SF100 firmware versions from >> 2.0 to 5.2. It should work with firmware version 5.5, but we have not >> tested it. >> >> >> > SPI ROM: winbond W25Q64FW, id 0xef 6017 >> > >> > plugging my SF100, and use below cmd >> > flashrom -p dediprog -V >> > i can see the program detect my sf100 but fail to detect the SPI ROM. >> log >> > as attached file. >> > ---log---- >> > Probing for Winbond W25Q64.V, 8192 kB: RDID byte 0 parity violation. >> > probe_spi_rdid_generic: id1 0x53, id2 0x4631 >> > ----log--- >> > >> > as the log shows, seems flashrom read SPI ROM id is 0x53, 0x4631, but >> > actually my SPI ROM on board is winbond with id 0xef, 0x6017(i confirm >> this >> > with windows dediprog). >> > so i have no idea why flashrom detect wrong id, and the flashchips.h >> > already have WINBOND_NEX_W25Q64_W 0x6017 support. >> >> 0x53 0x46 0x31 is the string "SF1". This string is returned by the SF100 >> if we query the firmware version. >> I think we have a bug in the dediprog firmware or in the dediprog driver >> or in libusb. Which version of libusb are you using? >> >> Regards, >> Carl-Daniel >> >> -- >> http://www.hailfinger.org/ >> >> >

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[PATCH] clean up physmap, fix unaligned mapping problems
by Carl-Daniel Hailfinger 05 Mar '14

05 Mar '14

Convert all physmaps in the internal DMI code to use aligned readonly maps. Convert all physmaps in the cbtable code to use unaligned readonly maps. Make physunmap() a generic architecture-independent wrapper. Add physunmap_unaligned() to complement physmap*_unaligned(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-physmap_ro_rw_aligned_unaligned_cleanup/dmi.c =================================================================== --- flashrom-physmap_ro_rw_aligned_unaligned_cleanup/dmi.c (Revision 1764) +++ flashrom-physmap_ro_rw_aligned_unaligned_cleanup/dmi.c (Arbeitskopie) @@ -153,7 +153,7 @@ { int i = 0, j = 0; - uint8_t *dmi_table_mem = physmap_round("DMI Table", base, len); + uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); if (dmi_table_mem == NULL) { msg_perr("Unable to access DMI Table\n"); return; Index: flashrom-physmap_ro_rw_aligned_unaligned_cleanup/cbtable.c =================================================================== --- flashrom-physmap_ro_rw_aligned_unaligned_cleanup/cbtable.c (Revision 1764) +++ flashrom-physmap_ro_rw_aligned_unaligned_cleanup/cbtable.c (Arbeitskopie) @@ -261,7 +261,7 @@ #else start = 0x0; #endif - table_area = physmap_ro("low megabyte", start, BYTES_TO_MAP - start); + table_area = physmap_ro_unaligned("low megabyte", start, BYTES_TO_MAP - start); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot low tables.\n"); return -1; @@ -276,8 +276,9 @@ if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; start &= ~(getpagesize() - 1); - physunmap(table_area, BYTES_TO_MAP); - table_area = physmap_ro("high tables", start, BYTES_TO_MAP); + physunmap_unaligned(table_area, BYTES_TO_MAP); + // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case + table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot high tables.\n"); return -1; Index: flashrom-physmap_ro_rw_aligned_unaligned_cleanup/physmap.c =================================================================== --- flashrom-physmap_ro_rw_aligned_unaligned_cleanup/physmap.c (Revision 1764) +++ flashrom-physmap_ro_rw_aligned_unaligned_cleanup/physmap.c (Arbeitskopie) @@ -27,6 +27,7 @@ #include <string.h> #include <errno.h> #include "flash.h" +#include "programmer.h" #include "hwaccess.h" #if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__) @@ -89,7 +90,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { __dpmi_meminfo mi; @@ -118,7 +119,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { } #elif defined(__MACH__) && defined(__APPLE__) @@ -139,7 +140,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); } @@ -192,13 +193,8 @@ return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { - if (len == 0) { - msg_pspew("Not unmapping zero size at %p\n", virt_addr); - return; - } - munmap(virt_addr, len); } #endif @@ -242,7 +238,7 @@ return 1; } struct undo_physmap_data *d = data; - physunmap(d->virt_addr, d->len); + physunmap_unaligned(d->virt_addr, d->len); free(data); return 0; } @@ -292,7 +288,7 @@ struct undo_physmap_data *d = malloc(sizeof(struct undo_physmap_data)); if (d == NULL) { msg_perr("%s: Out of memory!\n", __func__); - physunmap(virt_addr, len); + physunmap_unaligned(virt_addr, len); return ERROR_PTR; } @@ -300,7 +296,7 @@ d->len = len; if (register_shutdown(undo_physmap, d) != 0) { msg_perr("%s: Could not register shutdown function!\n", __func__); - physunmap(virt_addr, len); + physunmap_unaligned(virt_addr, len); return ERROR_PTR; } } @@ -308,9 +304,41 @@ return virt_addr + offset; } +void physunmap_unaligned(void *virt_addr, size_t len) +{ + /* No need to check for zero size, such mappings would have yielded ERROR_PTR. */ + if (virt_addr == ERROR_PTR) { + msg_perr("Trying to unmap a nonexisting mapping!\n" + "Please report a bug at flashrom(a)flashrom.org\n"); + return; + } + + sys_physunmap_unaligned(virt_addr, len); +} + +void physunmap(void *virt_addr, size_t len) +{ + uintptr_t tmp; + + /* No need to check for zero size, such mappings would have yielded ERROR_PTR. */ + if (virt_addr == ERROR_PTR) { + msg_perr("Trying to unmap a nonexisting mapping!\n" + "Please report a bug at flashrom(a)flashrom.org\n"); + return; + } + tmp = (uintptr_t)virt_addr; + /* We assume that the virtual address of a page-aligned physical address is page-aligned as well. By + * extension, rounding a virtual unaligned address as returned by physmap should yield the same offset + * between rounded and original virtual address as between rounded and original physical address. + */ + round_to_page_boundaries(&tmp, &len); + virt_addr = (void *)tmp; + physunmap_unaligned(virt_addr, len); +} + void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_EXACT); + return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); } void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) @@ -318,12 +346,12 @@ return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); } -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); + return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_ROUND); } -void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } Index: flashrom-physmap_ro_rw_aligned_unaligned_cleanup/programmer.h =================================================================== --- flashrom-physmap_ro_rw_aligned_unaligned_cleanup/programmer.h (Revision 1764) +++ flashrom-physmap_ro_rw_aligned_unaligned_cleanup/programmer.h (Arbeitskopie) @@ -277,9 +277,10 @@ /* physmap.c */ void *physmap(const char *descr, uintptr_t phys_addr, size_t len); void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len); void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); +void physunmap_unaligned(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); -- http://www.hailfinger.org/

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[commit] r1765 - trunk
by repository service 05 Mar '14

05 Mar '14

Author: hailfinger Date: Wed Mar 5 01:16:16 2014 New Revision: 1765 URL: http://flashrom.org/trac/flashrom/changeset/1765 Log: Clean up physmap, fix unaligned mapping problems Convert all physmaps in dmi.c to use aligned readonly maps. Convert all physmaps in cbtable.c to use unaligned readonly maps. Make physunmap() a generic architecture-independent wrapper. Add physunmap_unaligned() to complement physmap*_unaligned(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cbtable.c trunk/dmi.c trunk/physmap.c trunk/programmer.h Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Thu Nov 21 16:59:52 2013 (r1764) +++ trunk/cbtable.c Wed Mar 5 01:16:16 2014 (r1765) @@ -261,7 +261,7 @@ #else start = 0x0; #endif - table_area = physmap_ro("low megabyte", start, BYTES_TO_MAP - start); + table_area = physmap_ro_unaligned("low megabyte", start, BYTES_TO_MAP - start); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot low tables.\n"); return -1; @@ -276,8 +276,9 @@ if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; start &= ~(getpagesize() - 1); - physunmap(table_area, BYTES_TO_MAP); - table_area = physmap_ro("high tables", start, BYTES_TO_MAP); + physunmap_unaligned(table_area, BYTES_TO_MAP); + // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case + table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); if (ERROR_PTR == table_area) { msg_perr("Failed getting access to coreboot high tables.\n"); return -1; Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Thu Nov 21 16:59:52 2013 (r1764) +++ trunk/dmi.c Wed Mar 5 01:16:16 2014 (r1765) @@ -153,7 +153,7 @@ { int i = 0, j = 0; - uint8_t *dmi_table_mem = physmap_round("DMI Table", base, len); + uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); if (dmi_table_mem == NULL) { msg_perr("Unable to access DMI Table\n"); return; Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Nov 21 16:59:52 2013 (r1764) +++ trunk/physmap.c Wed Mar 5 01:16:16 2014 (r1765) @@ -27,6 +27,7 @@ #include <string.h> #include <errno.h> #include "flash.h" +#include "programmer.h" #include "hwaccess.h" #if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__) @@ -89,7 +90,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { __dpmi_meminfo mi; @@ -118,7 +119,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { } #elif defined(__MACH__) && defined(__APPLE__) @@ -139,7 +140,7 @@ #define sys_physmap_rw_uncached sys_physmap #define sys_physmap_ro_cached sys_physmap -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); } @@ -192,13 +193,8 @@ return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } -void physunmap(void *virt_addr, size_t len) +void sys_physunmap_unaligned(void *virt_addr, size_t len) { - if (len == 0) { - msg_pspew("Not unmapping zero size at %p\n", virt_addr); - return; - } - munmap(virt_addr, len); } #endif @@ -242,7 +238,7 @@ return 1; } struct undo_physmap_data *d = data; - physunmap(d->virt_addr, d->len); + physunmap_unaligned(d->virt_addr, d->len); free(data); return 0; } @@ -292,7 +288,7 @@ struct undo_physmap_data *d = malloc(sizeof(struct undo_physmap_data)); if (d == NULL) { msg_perr("%s: Out of memory!\n", __func__); - physunmap(virt_addr, len); + physunmap_unaligned(virt_addr, len); return ERROR_PTR; } @@ -300,7 +296,7 @@ d->len = len; if (register_shutdown(undo_physmap, d) != 0) { msg_perr("%s: Could not register shutdown function!\n", __func__); - physunmap(virt_addr, len); + physunmap_unaligned(virt_addr, len); return ERROR_PTR; } } @@ -308,9 +304,41 @@ return virt_addr + offset; } +void physunmap_unaligned(void *virt_addr, size_t len) +{ + /* No need to check for zero size, such mappings would have yielded ERROR_PTR. */ + if (virt_addr == ERROR_PTR) { + msg_perr("Trying to unmap a nonexisting mapping!\n" + "Please report a bug at flashrom(a)flashrom.org\n"); + return; + } + + sys_physunmap_unaligned(virt_addr, len); +} + +void physunmap(void *virt_addr, size_t len) +{ + uintptr_t tmp; + + /* No need to check for zero size, such mappings would have yielded ERROR_PTR. */ + if (virt_addr == ERROR_PTR) { + msg_perr("Trying to unmap a nonexisting mapping!\n" + "Please report a bug at flashrom(a)flashrom.org\n"); + return; + } + tmp = (uintptr_t)virt_addr; + /* We assume that the virtual address of a page-aligned physical address is page-aligned as well. By + * extension, rounding a virtual unaligned address as returned by physmap should yield the same offset + * between rounded and original virtual address as between rounded and original physical address. + */ + round_to_page_boundaries(&tmp, &len); + virt_addr = (void *)tmp; + physunmap_unaligned(virt_addr, len); +} + void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_EXACT); + return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); } void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) @@ -318,12 +346,12 @@ return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); } -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); + return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_ROUND); } -void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Thu Nov 21 16:59:52 2013 (r1764) +++ trunk/programmer.h Wed Mar 5 01:16:16 2014 (r1765) @@ -277,9 +277,10 @@ /* physmap.c */ void *physmap(const char *descr, uintptr_t phys_addr, size_t len); void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len); void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); +void physunmap_unaligned(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void);

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Re: [flashrom] [Ubuntu] Dediprog SF100 support with Winbond W25Q64FW
by Carl-Daniel Hailfinger 05 Mar '14

05 Mar '14

Hi Kurt, Am 24.02.2014 09:29 schrieb Kurt Qiao: > hope anyone can help me out, i try to implement flashrom to support > dediprog SF100 on my Ubuntu. config as below: > OS: Ubuntu12.04 X64 > Dediprog: SF100, fm ver: 5.5.0 We only have tested flashrom support with SF100 firmware versions from 2.0 to 5.2. It should work with firmware version 5.5, but we have not tested it. > SPI ROM: winbond W25Q64FW, id 0xef 6017 > > plugging my SF100, and use below cmd > flashrom -p dediprog -V > i can see the program detect my sf100 but fail to detect the SPI ROM. log > as attached file. > ---log---- > Probing for Winbond W25Q64.V, 8192 kB: RDID byte 0 parity violation. > probe_spi_rdid_generic: id1 0x53, id2 0x4631 > ----log--- > > as the log shows, seems flashrom read SPI ROM id is 0x53, 0x4631, but > actually my SPI ROM on board is winbond with id 0xef, 0x6017(i confirm this > with windows dediprog). > so i have no idea why flashrom detect wrong id, and the flashchips.h > already have WINBOND_NEX_W25Q64_W 0x6017 support. 0x53 0x46 0x31 is the string "SF1". This string is returned by the SF100 if we query the firmware version. I think we have a bug in the dediprog firmware or in the dediprog driver or in libusb. Which version of libusb are you using? Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

HM87 test report
by Vasiliy Vylegzhanin 04 Mar '14

04 Mar '14

read and write look ok

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[PATCH] internal programmer: handle failed chip mapping
by Carl-Daniel Hailfinger 04 Mar '14

04 Mar '14

Mapping a chip with the internal programmer on x86 will fail if the chip is larger than 16 MByte due to traditional x86 architecture constraints. No LPC/FWH chips of sizes bigger than 4 MByte are known, and Parallel chips are limited to older x86 chipsets and way smaller sizes because of address line shortage. We do see quite large SPI chips (even >16 MByte) and flashrom shouldn't fail probing or accessing them. Given that we have no chance to map those chips into the address space completely, make sure they are handled properly with indirect accesses Caveat: The code is proof-of-concept quality and litters the codebase with exit(1). We need to discuss what do do in that case. Testing should be done on a x86 machine which has SPI flash, and with r1702 reverted to have the 32 MByte chips again in flashchips.c (ignore the incorrect r1701 changelog which speaks of 32 MByte chip removal, that only happens in r1702). If flashrom successfully finishes probing without an abort in between, the patch does what it should. Or not. Read on. Without this patch and a reverted r1702, flashrom may successfully finish probing anyway due to the earlier physmap cleanups by Niklas Söderlund (r1744 and r1745). That's just the result from missing error checks, though. Applying this patch against a r1701 checkout (all files being r1701) should result in a fixed probe vs. a failing probe for plain r1701. A backported version of the patch against r1701 can be found at http://paste.flashrom.org/view.php?id=2027 Thanks for reading. Regards, Carl-Daniel Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-internal_no_chip_mapping_larger_16mbyte/flash.h =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/flash.h (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/flash.h (Arbeitskopie) @@ -186,6 +186,7 @@ struct flashctx { struct flashchip *chip; + bool virtual_memory_is_usable; chipaddr virtual_memory; /* Some flash devices have an additional register space. */ chipaddr virtual_registers; Index: flashrom-internal_no_chip_mapping_larger_16mbyte/it87spi.c =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/it87spi.c (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/it87spi.c (Arbeitskopie) @@ -385,7 +385,7 @@ * the mainboard does not use IT87 SPI translation. This should be done * via a programmer parameter for the internal programmer. */ - if ((flash->chip->total_size * 1024 > 512 * 1024)) { + if (!flash->virtual_memory_is_usable || (flash->chip->total_size * 1024 > 512 * 1024)) { spi_read_chunked(flash, buf, start, len, 3); } else { mmio_readn((void *)(flash->virtual_memory + start), buf, len); Index: flashrom-internal_no_chip_mapping_larger_16mbyte/internal.c =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/internal.c (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/internal.c (Arbeitskopie) @@ -365,45 +365,69 @@ } #endif +void *internal_map(const char *descr, uintptr_t phys_addr, size_t len) +{ + return physmap(descr, phys_addr, len); +} + +void internal_unmap(void *virt_addr, size_t len) +{ + physunmap(virt_addr, len); +} + static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); mmio_writeb(val, (void *) addr); } static void internal_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); mmio_writew(val, (void *) addr); } static void internal_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); mmio_writel(val, (void *) addr); } static uint8_t internal_chip_readb(const struct flashctx *flash, const chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); return mmio_readb((void *) addr); } static uint16_t internal_chip_readw(const struct flashctx *flash, const chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); return mmio_readw((void *) addr); } static uint32_t internal_chip_readl(const struct flashctx *flash, const chipaddr addr) { + if (!flash->virtual_memory_is_usable) + exit(1); return mmio_readl((void *) addr); } static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len) { + if (!flash->virtual_memory_is_usable) + exit(1); mmio_readn((void *)addr, buf, len); return; } Index: flashrom-internal_no_chip_mapping_larger_16mbyte/wbsio_spi.c =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/wbsio_spi.c (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/wbsio_spi.c (Arbeitskopie) @@ -20,6 +20,7 @@ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -204,6 +205,8 @@ static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { + if (!flash->virtual_memory_is_usable) + exit(1); mmio_readn((void *)(flash->virtual_memory + start), buf, len); return 0; } Index: flashrom-internal_no_chip_mapping_larger_16mbyte/flashrom.c =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/flashrom.c (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/flashrom.c (Arbeitskopie) @@ -68,8 +68,8 @@ .type = OTHER, .devs.note = NULL, .init = internal_init, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, + .map_flash_region = internal_map, + .unmap_flash_region = internal_unmap, .delay = internal_delay, }, #endif @@ -1086,6 +1086,10 @@ base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + if (flash->virtual_memory == (chipaddr)ERROR_PTR) + flash->virtual_memory_is_usable = false; + else + flash->virtual_memory_is_usable = true; /* We handle a forced match like a real match, we just avoid probing. Note that probe_flash() * is only called with force=1 after normal probing failed. Index: flashrom-internal_no_chip_mapping_larger_16mbyte/programmer.h =================================================================== --- flashrom-internal_no_chip_mapping_larger_16mbyte/programmer.h (Revision 1764) +++ flashrom-internal_no_chip_mapping_larger_16mbyte/programmer.h (Arbeitskopie) @@ -325,6 +325,8 @@ int register_superio(struct superio s); extern enum chipbustype internal_buses_supported; int internal_init(void); +void *internal_map(const char *descr, uintptr_t phys_addr, size_t len); +void internal_unmap(void *virt_addr, size_t len); #endif /* hwaccess.c */ -- http://www.hailfinger.org/

1 0

flashrom -V
by Volker Twer 01 Mar '14

01 Mar '14

Hey, I'm thinking about upgrading my BIOS and found "flashrom" in DEBIAN-repositories. Running a "read" on the builtin BIOS I saw the request for sending you some information - so here you are. Does "guesswork" mean, it might be unsafe to use this software on this board/bios? Thanks for your work! Greetings, Volker This ist the requested output flashrom v0.9.6.1-r1563 on Linux 3.13-3.slh.2-aptosid-686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (3 args): flashrom -V -p internal Calibrating delay loop... OS timer resolution is 2 usecs, 1238M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 9989 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "NF-M2SV" DMI string baseboard-product-name: "www.abit.com.tw " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Super I/O ID 0x8726 is not on the list of flash capable controllers. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x40, id2 0x07, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040C" (512 kB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040C" (512 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

2 1

Re: [flashrom] Tested AT25DF161
by Stefan Tauner 01 Mar '14

01 Mar '14

On Sun, 2 Mar 2014 00:28:16 +0400 Alex K <lepik.stv(a)gmail.com> wrote: > Sorry, I do not quite understand your question, but I'll try to answer. > I forgot when recording chip, specify a log file entry. Because I have a > log file cleanup, and reading to compare the recorded information. > To clean the chip pin WP, I connect to the GND. For writing and reading > from the chip, pin WP connects to the VCC. > > […] > > I hope this information will help you. Yes, thank you. I'll mark the chip as fully tested. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Tested AT25DF161
by Stefan Tauner 01 Mar '14

01 Mar '14

On Sat, 1 Mar 2014 23:12:15 +0400 Alex K <lepik.stv(a)gmail.com> wrote: > Hello I tested for cleaning work, reading, writing, memory AT25DF161 using > Bus Pirate v4. > Used: > flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) > flashrom was built with GCC 4.7.2, little endian > Baud rate is 115200. > Detected Bus Pirate hardware v4 > Detected Bus Pirate firmware 6.2 ("v6.2-beta1") > Using SPI command set v2. > SPI speed is 8MHz > Raw bitbang mode version 1 > Raw SPI mode version 1 > The following protocols are supported: SPI. > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 > 0x4602 > Found Atmel flash chip "AT25DF161" (2048 kB, SPI) on buspirate_spi. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 0x0c. > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): all sectors are > protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > === > > Initially, there was a problem with the use of long cables (> 20 cm). > After verification of the firmware did not pass. > Replaced wires from Bus Pirate at length (10cm), all turned out. Many > thanks for the utility. I think that you can remove the status UNTESTED > with this chip. Thank you again. > I think it is reasonable to point out the page on the wiki that the length > of wire for the Bus Pirate is very desirable <= 10 cm, to avoid many > mistakes. This saves the trouble of starting recording, reading chips. > > Sorry for my bad english, I'm from Russia. Hello Alex, thanks for your report! I am wondering a bit about the status register bits. According to your log the software write protection is enabled (and the parsing of the raw value 0x0c seems to be correct, so this is not only a cosmetic problem). Did you change anything since you wrote to the chip? Regarding the cable lengths: The troubleshooting section of the bus pirate wiki page links to this: http://flashrom.org/ISP and the first problem mentioned there are too long cables ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Tested AT25DF161
by Alex K 01 Mar '14

01 Mar '14

Hello I tested for cleaning work, reading, writing, memory AT25DF161 using Bus Pirate v4. Used: flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) flashrom was built with GCC 4.7.2, little endian Baud rate is 115200. Detected Bus Pirate hardware v4 Detected Bus Pirate firmware 6.2 ("v6.2-beta1") Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4602 Found Atmel flash chip "AT25DF161" (2048 kB, SPI) on buspirate_spi. Ignoring security lockdown (if present) Ignoring status register byte 2 Chip status register is 0x0c. Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is asserted Chip status register: Software Protection Status (SWP): all sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set === Initially, there was a problem with the use of long cables (> 20 cm). After verification of the firmware did not pass. Replaced wires from Bus Pirate at length (10cm), all turned out. Many thanks for the utility. I think that you can remove the status UNTESTED with this chip. Thank you again. I think it is reasonable to point out the page on the wiki that the length of wire for the Bus Pirate is very desirable <= 10 cm, to avoid many mistakes. This saves the trouble of starting recording, reading chips. Sorry for my bad english, I'm from Russia. -- С уважением Алексей

1 0

FAILED: SST49LF004A/B
by Tim Sebastian 28 Feb '14

28 Feb '14

Hello, I'm trying to use flashrom to write a new bios to my device. It successfully writes the beginning of the bios and then fails with the error: 0x040000-0x040fff:W writing sector at 0xb7ea0000 failed! And again with the second erase function : Trying erase function 1... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:W writing sector at 0xb7ea0000 failed! leaving the bios in an unstable state. Further experimentation shows that writing the bios fails on both erasing and writing any sector after 0x040000, which is exactly halfway through the bios (2Mb out of 4Mb). Reading from those areas works without a problem. The lock status for every block is reported as 00, full access. Full log is below. I took a look at the source code for flashrom in order to see if I could easily fix the problem. I created a minimal flashrom-like clone that works with my chip: #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include <stdio.h> #include <sys/mman.h> #define D(bios, pos) *((volatile char*)bios + pos) void write_byte(void* bios, int pos, char value) { char tmp1, tmp2; int i = 0; int tries = 4; retry: D(bios, 0x5555) = 0xAA; D(bios, 0x2AAA) = 0x55; D(bios, 0x5555) = 0xA0; D(bios, pos) = value; tmp1 = D(bios, 0) & 0x40; while (i++ < 0xFFFFFFF) { tmp2 = D(bios, 0) & 0x40; if (tmp1 == tmp2) { break; } tmp1 = tmp2; } if (D(bios, pos) != value) { if (tries > 0) { tries--; goto retry; } printf("Error writing value\n"); } } void try_replace(void* bios, int pos) { printf("Pos = %x:\n", pos); printf("Old: %hhx\n", D(bios, pos)); write_byte(bios, pos, 0); printf("New: %hhx\n", D(bios, pos)); printf("\n"); } int main() { int fd = open("/dev/mem", O_RDWR); void *bios = mmap(NULL, 0x80000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0xfff80000); char old; try_replace(bios, 0); try_replace(bios, 0x20000); try_replace(bios, 0x3ff00); try_replace(bios, 0x40000); try_replace(bios, 0x50000); try_replace(bios, 0x60000); try_replace(bios, 0x70000); munmap(bios, 0x80000); close(fd); return 0; } And it outputs: Pos = 0: Old: 25 New: 0 Pos = 20000: Old: 81 New: 0 Pos = 3ff00: Old: ff New: 0 Pos = 40000: Old: ff Error writing value New: ff Pos = 50000: Old: ff Error writing value New: ff Pos = 60000: Old: ff Error writing value New: ff Pos = 70000: Old: ff Error writing value New: ff *Note that running this script will write garbage to your bios. Make sure to keep an original backup nearby.* As you can see, the problem is easily reproducible. What can cause writing to fail on where the high bit of the address is set (0x40000-0x7ffff)? Full log: =========================================== flashrom v0.9.7-r1711 on Linux 2.6.35.12 (i586) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, GCC 4.6.1, little endian Command line (5 args): ./flashrom --programmer internal -w my_bios -V Calibrating delay loop... OS timer resolution is 4 usecs, 78M loops per second, 10 myus = 12 us, 100 myus = 108 us, 1000 myus = 1030 us, 10000 myus = 10131 us, 16 myus = 21 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: not found dmidecode execution unsuccessful - continuing without DMI info Found Winbond Super I/O, id 0x52 WARNING: No chipset found. Flash detection will most likely fail. The following protocols are supported: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49(H)F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49F080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49F080T, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for ESMT F49B002UA, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0x0000, id2 0x0000 Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x25, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x25, id2 0x2d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x25, id2 0x2d Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0x25, id2 0x7b, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39L010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39L020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xd2, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Found SST flash chip "SST49LF004A/B" (512 kB, FWH). Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:EW, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:W, 0x03e000-0x03efff:W, 0x03f000-0x03ffff:W, 0x040000-0x040fff:W writing sector at 0xb7ea0000 failed! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:W writing sector at 0xb7ea0000 failed! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF!

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Getting Flashrom running on OS X v10.9.2 (Mavericks)
by Nicholas Ouimet 27 Feb '14

27 Feb '14

Hi Flashrom community, I'm trying to install Flashrom 0.9.7 on OS X v10.9.2 and I download the source, and then use terminal commands cd make AND I get an error Checking for libpci headers... .test.c:3:10: fatal error: 'pci/pci.h' file not found #include <pci/pci.h> So I read that I need to install PCUtils, and again, using the cd and then make, I get an error 192:~ ouimetnick$ cd /Users/ouimetnick/Desktop/flashrom/pciutils-3.1.9 192:pciutils-3.1.9 ouimetnick$ make /Applications/Xcode.app/Contents/Developer/usr/bin/make -C lib all make[1]: *** No rule to make target `/System/Library/Frameworks/ApplicationServices.framework/Headers/ApplicationServices.h', needed by `DirectHW.o'. Stop. make: *** [lib/libpci.a] Error 2 192:pciutils-3.1.9 ouimetnick$ How do I fix and install this? Also, DirectHW needs to be installed, and when attempting to install that (using the cd, and then make command), I get the following ** BUILD FAILED ** The following build commands failed: CompileC build/DirectHW.build/Release/KEXT.build/Objects-normal/i386/DirectHW.o DirectHW.cpp normal i386 c++ com.apple.compilers.llvm.clang.1_0.compiler (1 failure) make: *** [build] Error 65 192:DirectHW ouimetnick$ Could anyone offer some help? I want to get Flashrom running so I can use my Bus Pirate. Thanks, Nick ouimetnick(a)gmail.com

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Re: [flashrom] flashrom support for SST26VF064B
by Stefan Tauner 27 Feb '14

27 Feb '14

On Wed, 26 Feb 2014 14:57:32 -0800 Wei Hu <wei(a)aristanetworks.com> wrote: > Hi flashrom folks, > > I'm trying to add support for SST26VF064B after I got a patch from Elias. I > made some changes to it after reading the datasheet, but none of the block > erasing commands worked, and I don't know why... I don't see obvious problems either, but I did not read the datasheet. Two things I would check: - is there a write protection pin or register bits that might silently block any modification requests? - is the opcode sequence including wren? (this is probably done automatically by the ichspi driver, but i cant remember the details) And you could test if hardware sequencing (or SFDP) works as a workaround (but I doubt SFDP would behave differently for the lower block sizes and some of them are obviously wrong in the SFDP table anyway (or you have found a bug)). A full verbose log could shed some more light on it too, but I doubt it. If we get this to work we would probably like to commit this patch. For this either of you must sign it off according to http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom support for SST26VF064B
by Wei Hu 26 Feb '14

26 Feb '14

Hi flashrom folks, I'm trying to add support for SST26VF064B after I got a patch from Elias. I made some changes to it after reading the datasheet, but none of the block erasing commands worked, and I don't know why... Erasing and writing flash chip... *Trying erase function 0... 0x000000-0x000fff*:E program_opcodes: preop=5006 optype=463b opmenu=05200302c79f0190 on-the-fly *OPCODE (0x20)* re-programmed, op-pos=2 FAILED at 0x00000010! Expected=0xff, Found=0x5a, failed byte count from 0x00000000-0x00000fff: 0x83 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. *Trying erase function 1... 0x000000-0x00ffff*:E program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 on-the-fly *OPCODE (0xD8)* re-programmed, op-pos=2 FAILED at 0x00000010! Expected=0xff, Found=0x5a, failed byte count from 0x00000000-0x0000ffff: 0xdf16 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. *Trying erase function 2... 0x000000-0x7fffff*:EFAILED at 0x00000010! Expected=0xff, Found=0x5a, failed byte count from 0x00000000-0x007fffff: 0x702b2a ERASE FAILED! Looking for another erase function. No usable erase functions left. FAILED! It tried the commands for erasing 4KB, 64KB, 8MB, and all failed... This is basically what I had in the block_erasers[] array. Full diff is attached. Thanks for your help! { { .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {64 * 1024, 128} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {8 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, },

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W836xx: Lenovo 2325AEG: flashrom -V
by Stefan Midjich 26 Feb '14

26 Feb '14

flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 3185M loops per second, 10 myus = 10 us, 100 myus = 120 us, 1000 myus = 1021 us, 10000 myus = 10016 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "2325AEG" DMI string system-version: "ThinkPad X230" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "2325AEG" DMI string baseboard-version: "Win8 Pro DPK TPG" DMI string chassis-type: "Notebook" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. -- Hälsningar / Greetings http://Stefan.Midjich.name

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laptop bios
by Sheri Soltz 26 Feb '14

26 Feb '14

I am trying to use flashrom to make a bios backup file on my lenovo thinkpad x131e chromebook (intel celeron 1007u cpu). I have set developer-mode and have physically opened the laptop and set the write protect switch to the write enable position. I am using the command "sudo flashrom -p internal -r backup.bin -o backup.log" But when I check the md5sum for backup.bin it is different from each previous backup.bin. Shouldn't the md5sum of the backup stay the same, as long as the bios has not been changed? Here is the output from backup.log: flashrom v0.9.7-r1711 on Linux 3.8.11 (x86_64) flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian Command line (7 args): flashrom -p internal -r bku1.bin -o bku1.log -V Calibrating delay loop... OS timer resolution is 1 usecs, 1493M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1002 us, 10000 myus = 10007 us, 4 myus = 4 us, OK. Initializing internal programmer Found candidate at: 00000500-00000510 Found coreboot table at 0x00000500. Found candidate at: 00000000-000003d8 Found coreboot table at 0x00000000. coreboot table found at 0xacedd000. coreboot header(24) checksum: 7b8d table(984) checksum: eeda entries: 18 Vendor ID: GOOGLE, part ID: Stout DMI string system-manufacturer: "GOOGLE" DMI string system-product-name: "Stout" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "Desktop" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518, Rev 0x08 on port 0x2e. Found chipset "Intel HM77" with PCI ID 8086:1e57. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xc000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. The Flash Descriptor Override Strap-Pin is set. Restrictions implied by the Master Section of the flash descriptor are NOT in effect. Please note that Protected Range (PR) restrictions still apply. Reading OPCODES... done OP Type Pre-OP op[0]: 0x01, write w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x20, write w/ addr, none op[5]: 0x9f, read w/o addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0x0b, read w/ addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is read-write. 0x5C: 0x01ff0001 FREG2: Management Engine region (0x00001000-0x001fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94400 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=4, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0xb32d (OPTYPE) 0x98: 0x05030201 (OPMENU) 0x9C: 0x0bd89f20 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00000000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xC8: 0x00000000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x49300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0200 FLREG2 0x01ff0001 FLREG3 0x00001fff FLREG4 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00200000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x001fffff Region 3 (GbE ) is unused. Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw SPI Read Configuration: prefetching enabled, caching enabled, OK. Super I/O ID 0x8518 is not on the list of flash capable controllers. No board enable found matching coreboot IDs vendor="GOOGLE", model="Stout". The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512A, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F1024(A), 128 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F2048, 256 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F4096, 512 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605D/MX25L1608D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6406E/MX25L6436E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6445E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805(D), 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512(A), 64 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW418A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW806, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW808, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080(A), 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) at physical address 0xff800000. Chip status register is 0x80. Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x50, id2 0xb0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x5f, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x5f, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Reading flash... done. Restoring MMIO space at 0x7ff643ff18a0 Any help/advise/suggestions would be appreciated. My aim was to use flashrom (if possible) to flash some bios other than the chromebook bios. Thanks Sheri

2 3

Help me flash coreboot for extra cash?
by Jonathon Byrd 25 Feb '14

25 Feb '14

I have a Lenovo Yoga 2 Pro with i5 Intel Processor. I hate this UEFI microcrap. Would somebody mind helping me flash this existing BIOS with COREBOOT so that I can put linux on my laptop?   -j

1 0

[Ubuntu] Dediprog SF100 support with Winbond W25Q64FW
by Kurt Qiao 24 Feb '14

24 Feb '14

hello there, hope anyone can help me out, i try to implement flashrom to support dediprog SF100 on my Ubuntu. config as below: OS: Ubuntu12.04 X64 Dediprog: SF100, fm ver: 5.5.0 SPI ROM: winbond W25Q64FW, id 0xef 6017 i download flashrom v0.9.7 from http://flashrom.org/Downloads, i noticed v0.9.8 would enable dediprog by default but couldn't download now. unzip the download file and cd flashrom-0.9.7 and make with below cmd: make CONFIG_DEDIPROG=yes sudo make install plugging my SF100, and use below cmd flashrom -p dediprog -V i can see the program detect my sf100 but fail to detect the SPI ROM. log as attached file. ---log---- Probing for Winbond W25Q64.V, 8192 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x53, id2 0x4631 ----log--- as the log shows, seems flashrom read SPI ROM id is 0x53, 0x4631, but actually my SPI ROM on board is winbond with id 0xef, 0x6017(i confirm this with windows dediprog). so i have no idea why flashrom detect wrong id, and the flashchips.h already have WINBOND_NEX_W25Q64_W 0x6017 support. any help would be appreciate, thanks very much! BR, kurtqiao 2014.02.24

1 0

Failure using flashrom and BusPirate to flash Macronix MX25L3206E bios chip
by Matthew Kiss 22 Feb '14

22 Feb '14

Hello, I'm using flashrom via buspirate_spi to try and access the Macronix MX25L3206E bios chip on my Asus G73JW laptop. Here is the command line I'm using: flashrom.exe -p buspirate_spi:dev=com3,spispeed=1M Attached is more info on my laptop and the software I'm using, as well as the flashrom log. Regards, Matt

2 2

Hello
by Ilie Pasol 22 Feb '14

22 Feb '14

Hy guys,first thing i wanna thank you for your great software and second i waana ask you if you planning to include this chip Micron N25Q064A 13E40 in your hardware support in the future?Thanks !

3 3

[PATCH] Use read-only mappings for DMI tables everywhere.
by Stefan Tauner 20 Feb '14

20 Feb '14

R/W mappings cause explosions sometimes. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Simply rename (and refine) physmap_round to physmap_ro_round because dmi is the only user anyway. The patch was tested on real hardware that had problems without it. W/o patch: http://paste.flashrom.org/view.php?id=1983 With patch: http://paste.flashrom.org/view.php?id=1990 Without vetoes I will commit this soonish. dmi.c | 2 +- physmap.c | 4 ++-- programmer.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/dmi.c b/dmi.c index ef7ae2c..708e2b2 100644 --- a/dmi.c +++ b/dmi.c @@ -153,7 +153,7 @@ static void dmi_table(uint32_t base, uint16_t len, uint16_t num) { int i = 0, j = 0; - uint8_t *dmi_table_mem = physmap_round("DMI Table", base, len); + uint8_t *dmi_table_mem = physmap_ro_round("DMI Table", base, len); if (dmi_table_mem == NULL) { msg_perr("Unable to access DMI Table\n"); return; diff --git a/physmap.c b/physmap.c index 9638c78..ad7586e 100644 --- a/physmap.c +++ b/physmap.c @@ -318,9 +318,9 @@ void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); } -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len) +void *physmap_ro_round(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_ROUND); + return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_ROUND); } void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len) diff --git a/programmer.h b/programmer.h index 0c51f58..f08286a 100644 --- a/programmer.h +++ b/programmer.h @@ -277,7 +277,7 @@ int processor_flash_enable(void); /* physmap.c */ void *physmap(const char *descr, uintptr_t phys_addr, size_t len); void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_round(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro_round(const char *descr, uintptr_t phys_addr, size_t len); void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 -- Kind regards, Stefan Tauner

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Problems with Jetway Board and Winbond chip
by Hans-Martin Roßmann 17 Feb '14

17 Feb '14

Hey there… first of all: Thank you for that incredible flashrom tool. But sadly: I can not write my BIOS chip on my Jetway Board. I got a Jetway NC96FL Mainboard with a Winbond W25Q80BV BIOS Chip, Intel NM10 Chipset and running Ubuntu 10.10. Flashrom detects the chip and the chipset well, but can not disable block protection. So it is not possible to write. I also tried to flash the chip with the Serprog/Arduino-Flasher on an Arduino Uno and it works. (But I want to burn it with my Jetway Board.) Then I tried to write it in my Jetway Board with manual raising the /WP-Pin of the Winbond Chip to VCC and it works too. So is it something (GPIO) to raise the /WP-Pin in the chipset? Can somebody help me? I attached the logs from: $ flashrom -p internal -w flash.rom (write.log) $ flashrom -p internal -V (flash.log) $ lspci -nnvvxxx (lspci.log) $ superiotool -deV (superio.log) Thanks a lot, Hans-Martin

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