- flashrom - mail.coreboot.org

please, helpme. AMI BIOS SPI FLASH ROM 96 MB
by Alberto Perez 09 Nov '15

09 Nov '15

please, helpme. i want flashear mi notebook ( http://bangho.com.ar/wp-content/uploads/2015/04/Ultrabook-Bangho-ZERO-1430-…) but I do not know how to do it. I do not know what parameter to use in --programmer. my bios is AMI BIOS SPI Flash ROM de 96 M b Por favor, alguien puede ayudarme: Quiero hacer un volcado de la memoria rom de mi notebook pero no sé cómo hacerlo.

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Reporte LE25FU406B and LE25FU406B
by Jose Luis León 09 Nov '15

09 Nov '15

Hi all, I am doing send logs that applied on chips: SANYO LE25FU406B - http://chopapp.com/#7cvgvoav SANYO LE25FU406C - http://chopapp.com/#zw01179t too I attaching conversation of IRC channel. I am using chopapp because pastebin failed :s

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Asus F2A85-M PRO
by Denis 'GNUtoo' Carikli 08 Nov '15

08 Nov '15

Hi, here what I did: 0) The board has an external GPU in it that has an option rom, and the OS is GNU/Linux in BIOS mode. My CPU doesn't have a GPU. That is important, because in some other configuration, flashrom complained that something was accessing the flash. 1) flashrom -p internal -w build/coreboot.rom 2) poweroff (I've systemd, so that powers off the board cleanly) 3) boot and see some coreboot logs (the port is WIP) 4) take off the flash chip, dump it from another computer with an external programmer (openmoko in my case). 5) compare md5sum with build/coreboot.rom => fails, compare both images with vbindiff => some zones are different. Unlike with my Asrock E350M1 (I reported the issue on IRC for that one), this time I didn't bother looking at what the differences were. Denis.

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Re: [flashrom] SFDP has autodetected a flash chip which is not natively supported by flashrom yet
by Stefan Tauner 06 Nov '15

06 Nov '15

On Thu, 5 Nov 2015 03:38:14 +0800 Greg Tippit <greg(a)tippitt.net> wrote: > First off, thank you for your work on such a useful program. I have > used it more times that I can remember, and I have never had a single > problem flashing a motherboard BIOS using your program. If you > accepted PayPal donations, I would buy you all a beverage of your > choice. > > I have a new stick PC from China called the MeeGoPad T02, which uses > an Intel Atom SOC. > > They have a little English support at x86pad.com, where I found a > updated BIOS for this device. > > When I made of backup of the existing BIOS on the device, I got the > message about it not yet having native support. The read seemed to go > okay. I have attached a copy of the verbose output as you requested. > > Assuming all the normal warnings, is it safe to try flashing the new > BIOS using flashrom, or should I wait for you to work your "Native > Magic"? Hi, AFAICT it should work fine. However, full support was already added and is available since commit r1889. So you could also upgrade if you like. I'd appreciate a report afterwards in any case. ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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SFDP has autodetected a flash chip which is not natively supported by flashrom yet
by Greg Tippit 04 Nov '15

04 Nov '15

First off, thank you for your work on such a useful program. I have used it more times that I can remember, and I have never had a single problem flashing a motherboard BIOS using your program. If you accepted PayPal donations, I would buy you all a beverage of your choice. I have a new stick PC from China called the MeeGoPad T02, which uses an Intel Atom SOC. They have a little English support at x86pad.com, where I found a updated BIOS for this device. When I made of backup of the existing BIOS on the device, I got the message about it not yet having native support. The read seemed to go okay. I have attached a copy of the verbose output as you requested. Assuming all the normal warnings, is it safe to try flashing the new BIOS using flashrom, or should I wait for you to work your "Native Magic"? Thank you, Greg Tippitt

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Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger 03 Nov '15

03 Nov '15

Hi Mark, thanks for the log and the explanation. This was indeed helpful. May I suggest you take a look at the nvramtool utility from the coreboot project? It works fine even on normal BIOS (needs to be run as root, though). http://www.coreboot.org/Nvramtool I used nvramtool in the past to dump all 256 bytes of NVRAM. For a hexdump, try this: # nvramtool -x If this gets you the same result as SRCMOS.EXE, you could throw the DOS utility away. The interesting parameters are: -b OUTPUT_FILE: Dump CMOS memory contents to file. -B INPUT_FILE: Write file contents to CMOS memory. -x: Show hex dump of CMOS memory. -X DUMPFILE: Show hex dump of CMOS dumpfile. Regards, Carl-Daniel On 02.11.2015 11:06, Rowlinson Mark wrote: > Hi Carl-Daniel, > I've attached the logfile output as requested. > The SRCMOS .EXE utility that comes on the BIOS update image saves 256 bytes of data. The older versions has 128 bytes of data and the remainder was all 00x. The last version has data within the last 128 bytes and that makes all the difference. > Whether the utility only processed the first 128 bytes initially and was corrected to save/restore the extra 128 bytes I don't know but it certainly does the trick now. > It is a DOS based utility and I've been able to configure a FreeDOS image under GRUB so that it will boot it once to set the BIOS settings I need and then boot back to the Linux OS. > Getting the settings out was a bit of a chore as I had to hex dump them to the screen so I could take a picture (and then type them in) as the image can't be updated and has no access to any other devices. Running the utility from a USB device is no help either as the moment I disable USB in the BIOS I can't access the utility to write the settings to a file. > Best Regards, > Mark Rowlinson, Principal Engineer, Unix Support > MISGB Implementation Distributed > > Fujitsu > > > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: 29 October 2015 00:37 > To: Rowlinson Mark <Mark.Rowlinson(a)uk.fujitsu.com>; flashrom(a)flashrom.org > Subject: Re: [flashrom] Flash chip/chipset not found > > > Hi Mark, > > would it be possible for you to generate a log file using the additional parameter --output logfile.txt when doing a read of the flash chip, then send that log file to us? > > That would help us to finally merge support for the VT8251 chipset in your point-of-sale IBM/Toshiba AnyPlace Kiosk Model 48xx series. We have a strict rule that flashrom must be 100% reliable and thus we keep log files for any newly supported/tested chipset around for reference. Your log file would be used as reference for VT8251. > > That said, it would be very interesting to know where the settings are actually stored. Have you looked into the top 128 bytes of NVRAM? Maybe there is another flash chip? Is there any way to trace what the save/restore tool does (i.e. does it run on Linux)? > > Regards, > Carl-Daniel > > > > > > On 28.10.2015 23:25, Rowlinson Mark wrote: > >> Hi Carl-Daniel, >> >> That change does allow the chipset to be recognised and it will write out the ROM. It seems to be the BIOS code only (no settings) as it doesn't change if I change any settings within the BIOS. >> >> I've been directed to a save/restore utility that comes on the BIOS update image and it seems the last version actually accesses the data I'm interested in so I'm investigating this route at the moment. >> >> Best Regards, >> Mark Rowlinson >> -----Original Message----- >> >> From: Carl-Daniel Hailfinger >> [mailto:c-d.hailfinger.devel.2006@gmx.net] >> Sent: 24 October 2015 09:22 >> To: Rowlinson Mark <Mark.Rowlinson(a)uk.fujitsu.com<mailto:Mark.Rowlinson@uk.fujitsu.com>>; >> flashrom(a)flashrom.org<mailto:flashrom@flashrom.org> >> >> Subject: Re: [flashrom] Flash chip/chipset not found >> >> Hi Mark, >> >> this is a VIA VT8251 PCI to ISA Bridge you're using. >> >> I think Stefan Tauner (in CC) already was discussing something similar here: >> http://www.flashrom.org/pipermail/flashrom/2012-July/009552.html >> That email even has a patch attached. >> On 22.10.2015 22:24, Rowlinson Mark wrote: >>> Thanks for the swift response, I have attached output from the command requested. >>> >>> The device in question is an IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. The models we have are a mixture of 4838-310 and 4838-330 and support documentation refers to them as 4838-3xx. >> Heh, would be fun to add this to our tests. >> >> Regards, >> Carl-Daniel

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flashrom
by Денис 03 Nov '15

03 Nov '15

flashrom v0.9.2-r1141 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 969M loops per second, 10 myus = 10 us, 100 myus = 98 us, 1000 myus = 1059 us, 10000 myus = 11659 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M2N-MX SE" DMI string baseboard-version: "Rev x.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8712 Found chipset "NVIDIA MCP61", enabling flash write... chipset PCI ID is 10de:03e0, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x96, id2 0x5e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x96, id2 0x5e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x96, id2 0x5e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x96, id2 0x5e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. -- Денис Кораблев

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Winbond flash chip "W39V080FA" (1024 kB, FWH)
by Fabian Hoffmann 03 Nov '15

03 Nov '15

1 0

Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger 02 Nov '15

02 Nov '15

Hi Mark, would it be possible for you to generate a log file using the additional parameter --output logfile.txt when doing a read of the flash chip, then send that log file to us? That would help us to finally merge support for the VT8251 chipset in your point-of-sale IBM/Toshiba AnyPlace Kiosk Model 48xx series. We have a strict rule that flashrom must be 100% reliable and thus we keep log files for any newly supported/tested chipset around for reference. Your log file would be used as reference for VT8251. That said, it would be very interesting to know where the settings are actually stored. Have you looked into the top 128 bytes of NVRAM? Maybe there is another flash chip? Is there any way to trace what the save/restore tool does (i.e. does it run on Linux)? Regards, Carl-Daniel On 28.10.2015 23:25, Rowlinson Mark wrote: > Hi Carl-Daniel, > > That change does allow the chipset to be recognised and it will write out the ROM. It seems to be the BIOS code only (no settings) as it doesn't change if I change any settings within the BIOS. > > I've been directed to a save/restore utility that comes on the BIOS update image and it seems the last version actually accesses the data I'm interested in so I'm investigating this route at the moment. > > Best Regards, > Mark Rowlinson > > -----Original Message----- > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: 24 October 2015 09:22 > To: Rowlinson Mark <Mark.Rowlinson(a)uk.fujitsu.com>; flashrom(a)flashrom.org > Subject: Re: [flashrom] Flash chip/chipset not found > > Hi Mark, > > this is a VIA VT8251 PCI to ISA Bridge you're using. > > I think Stefan Tauner (in CC) already was discussing something similar here: > http://www.flashrom.org/pipermail/flashrom/2012-July/009552.html > That email even has a patch attached. > > > On 22.10.2015 22:24, Rowlinson Mark wrote: >> Thanks for the swift response, I have attached output from the command requested. >> >> The device in question is an IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. The models we have are a mixture of 4838-310 and 4838-330 and support documentation refers to them as 4838-3xx. > Heh, would be fun to add this to our tests. > > Regards, > Carl-Daniel >

2 1

SOIC8 test clip - cant write to BIOS SPI flash chip
by Robert Brown 01 Nov '15

01 Nov '15

Unfortunately I don't have any soldering tools or experience, so if you could give an advice about ISP programming (In-System-Programming/In-Situ-Programming) , it will be super helpful! I teardown a bricked laptop, removed AC power, laptop's power battery, and even a small CMOS battery, and now I am trying to write a working BIOS image to laptop's SPI flash chip using a SOIC8 test clip. But here is a problem: I could read a dump from this BIOS chip without problems, however it fails when I am trying to write - so the contents of BIOS flash chip are remaining unchanged. Luckily I found out this helpful wiki page - http://flashrom.org/ISP , which describes common problems with this ISP method of flashing, as well as gives 3 hints for solution! Sadly this page is currently down, so here is a screenshot: http://i.imgur.com/SJEYHR2.png 1. - tried to make shorter wires, less than 10cm as they recommend - it did not help 2. - soldering is out of possibility, cant do it, and also: wires are already short and they are good quality (pure copper) 3. - This hint looks more promising, but I need help in understanding this piece of information: "disconnect Vcc from the programmer and power it with its normal PSU" If I understand correctly, by Vcc they mean Vcc pin of the BIOS flash chip. But if I disconnect Vcc from the programmer, what is "normal PSU" which should power this Vcc pin? Should I connect to motherboard a laptop's power battery, or small CMOS battery, or AC adapter of laptop, so that this Vcc pin would be powered by them, or it is forbidden to do it while using SPI programmer in the same time? Or its better to try to power Vcc of flash chip from "USB to TTL" adapter - which has this 3V3 (3.3V) voltage pin? Yours faithfully, Robert Brown _______________________________________________________________ Get the Free email that has everyone talking at <a href=http://www.mail2world.com target=new>http://www.mail2world.com</a> Unlimited Email Storage POP3 Calendar SMS Translator Much More!

3 3

[PATCH] Use nanosleep() instead of usleep() where available.
by Stefan Tauner 01 Nov '15

01 Nov '15

usleep() has been obsolete for quite a while. The only target where it is currently used without alternative is DOS. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- While setting up uClibc on the buildbot in a rather limited configuration I noticed that the only thing that made it fail was the use of usleep(). usleep() has been made obsolete with POSIX.1-2001 and was removed in POSIX.1-2008 hence it would be great to get rid of it completely. However, DJGPP for DOS does not provide an alternative so we are stuck there. Still, we can migrate everything else (but Windows) to nanosleep with this patch. Verified against the buildbot. udelay.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/udelay.c b/udelay.c index c03bcc4..60a8604 100644 --- a/udelay.c +++ b/udelay.c @@ -22,6 +22,7 @@ #ifndef __LIBPAYLOAD__ #include <unistd.h> +#include <time.h> #include <sys/time.h> #include <stdlib.h> #include <limits.h> @@ -174,9 +175,11 @@ void internal_sleep(unsigned int usecs) { #if IS_WINDOWS Sleep((usecs + 999) / 1000); -#else +#elif defined(__DJGPP__) sleep(usecs / 1000000); usleep(usecs % 1000000); +#else + nanosleep(&(struct timespec){usecs / 1000000, (usecs * 1000) % 1000000000}, NULL); #endif } -- Kind regards, Stefan Tauner

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Re: [flashrom] trouble flashing EN25S64 on Lenovo N21 chromebook
by Stefan Tauner 01 Nov '15

01 Nov '15

On Sun, 4 Oct 2015 18:22:35 -0500 Kyle Stanevich <kstanevich(a)imsa.edu> wrote: > Hi, > > I am still having trouble flashing the EN25S64 chip on my Lenovo N21 > chromebook. I have connected a raspberry pi to the EN25S64 on the Lenovo > N21 motherboard chip via this clip ( > http://www.amazon.com/Qunqi-Soic8-Flash-Clips-Programmer/dp/B014IXR9RG). On > the raspberry pi (which is running raspbian) I run the command "sudo > ./flashrom -VVV -p linux_spi:dev=/dev/spidev0.0 -w ~/Downloads/bios.bin". I > have removed the write protect screw, but I don't think that matters > because I am connecting to the chip directly. > > I have tried to compile google's (chromiumos') version of flashrom, but I > could not get it to compile due to many errors. Therefore, I am using the > latest version of flashrom which compiles fine. > > It seams to me that the problem is there is something not working correctly > writing/erasing/reading to the chip. Erase functions 1 through 3 all fail > when using the command shown above. It hangs up on erase function 2 for a > very long time. I had to run it overnight until erase function 2 failed. I > have tried running the same command again, and it is currently still stuck > at "Trying erase function 2... 0x000000-0x7fffff:E". It has been stuck at > this line for 16 hours, with the raspberry pi at 100% cpu usage the entire > time. > > The line "This flash part has status UNTESTED for operations: PROBE READ > ERASE WRITE" indicates to me that this chip has not yet been tested. I > would like to help out with testing for this chip since I have one and have > the hardware required to flash it. What can I do to help out? Hi, usually even untested SPI flash chips work just fine. They are all pretty similar and we use the same source code for them apart from tiny bits like the actual ID. Thus I don't believe there is anything wrong with the code but your hardware setup. Take a look at http://flashrom.org/RaspberryPi especially the note under the pin table. I presume you did not connect all input pins of the flash chip... Also, see http://flashrom.org/ISP if that was not the issue. The long erases could also come from that, but other causes like kernel or flashrom bugs are theoretically possible as well (although unlikely IMO). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Add (implicit) support for musl libc.
by Stefan Tauner 31 Oct '15

31 Oct '15

This is mostly achieved by fixing or refining the inclusion of header files and replacing glibc-specific ifdefs with more generic ones. - <sys/io.h>: Contains iopl(2) and x86 I/O port access functions (inb, outb etc). Generally Linux-specific but also availble on debian/kFreeBSD. Provided by glibc as well as musl and uclibc. Include it if we are running Linux or if glibc is detected. - <sys/fcntl.h>: should be (and is) replaced by <fcntl.h> (without the "sys" prefix). - <linux/spi/spidev.h>: Does not include all necessary headers, namely _IOC_SIZEBITS that is used in the definition of SPI_MSGSIZE is not brought in via <linux/ioctl.h> but instead we relied so far on glibc's including it via <sys/ioctl.h>. Change that to explicitly including <linux/ioctl.h>. - <endian.h>: Would also be available in musl but there is no easy way to detect it so we do not try yet. The bug report and initial patches were Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- New version because the sys/io.h change was actually breaking Debian/kFreeBSD! Moved it down where all the IN[BWL]/OUT[BWL] definitions are. hwaccess.h | 14 ++++++++------ linux_spi.c | 5 +++-- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/hwaccess.h b/hwaccess.h index 3e46192..390f0e4 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -26,12 +26,6 @@ #include "platform.h" -#if IS_X86 -#if defined(__GLIBC__) -#include <sys/io.h> -#endif -#endif - #if NEED_PCI == 1 /* * libpci headers use the variable name "index" which triggers shadowing @@ -115,6 +109,7 @@ #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) /* Nonstandard libc-specific macros for determining endianness. */ +/* musl provides an endian.h as well... but it can not be detected from within C. */ #if defined(__GLIBC__) #include <endian.h> #if BYTE_ORDER == LITTLE_ENDIAN @@ -204,6 +199,13 @@ cpu_to_be(64) #if NEED_PCI == 1 #if IS_X86 +/* sys/io.h provides iopl(2) and x86 I/O port access functions (inb, outb etc). + * It is included in glibc (thus available also on debian/kFreeBSD) but also in other libcs that mimic glibc, + * e.g. musl and uclibc. */ +#if defined(__linux__) || defined(__GLIBC__) +#include <sys/io.h> +#endif + #define __FLASHROM_HAVE_OUTB__ 1 /* for iopl and outb under Solaris */ diff --git a/linux_spi.c b/linux_spi.c index 26725e1..19b4965 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -22,13 +22,14 @@ #include <stdio.h> #include <string.h> #include <stdlib.h> -#include <sys/fcntl.h> +#include <fcntl.h> #include <errno.h> #include <ctype.h> #include <unistd.h> +#include <sys/ioctl.h> #include <linux/types.h> #include <linux/spi/spidev.h> -#include <sys/ioctl.h> +#include <linux/ioctl.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -- Kind regards, Stefan Tauner

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[PATCH 1/2] Add missing header for musl compatibility
by Gwenhael Goavec-Merou 30 Oct '15

30 Oct '15

From: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> According to : http://autobuild.buildroot.net/results/3de/3de936d9be79e151e66af15193084d82… linux/ioctl.h header must be included in linux_spi.c to obtain missing _IOC_SIZEBITS. Patch based on : http://git.buildroot.net/buildroot/commit/package/c-periphery/0001-Add-miss… Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> --- linux_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux_spi.c b/linux_spi.c index 26725e1..8d72420 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -28,6 +28,7 @@ #include <unistd.h> #include <linux/types.h> #include <linux/spi/spidev.h> +#include <linux/ioctl.h> #include <sys/ioctl.h> #include "flash.h" #include "chipdrivers.h" -- 2.4.9

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Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger 28 Oct '15

28 Oct '15

Hi Mark, this is a VIA VT8251 PCI to ISA Bridge you're using. I think Stefan Tauner (in CC) already was discussing something similar here: http://www.flashrom.org/pipermail/flashrom/2012-July/009552.html That email even has a patch attached. On 22.10.2015 22:24, Rowlinson Mark wrote: > Thanks for the swift response, I have attached output from the command requested. > > The device in question is an IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. The models we have are a mixture of 4838-310 and 4838-330 and support documentation refers to them as 4838-3xx. Heh, would be fun to add this to our tests. Regards, Carl-Daniel

2 2

CHIPSET: alix 3d3
by John Vacek 27 Oct '15

27 Oct '15

Proceeding anyway because user forced us to. Found chipset "AMD CS5536". Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. No operations were specified. http://www.pcengines.ch/alix3d3.htm root@kali-alix:~# lspci -nn 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33) 00:01.1 VGA compatible controller [0300]: Advanced Micro Devices [AMD] Geode LX Video [1022:2081] 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082] 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0c.0 SATA controller [0106]: Silicon Image, Inc. SiI 3512 [SATALink/SATARaid] Serial ATA Controller [1095:3512] (rev 01) 00:0e.0 Network controller [0280]: Broadcom Corporation BCM4306 802.11a/b/g [14e4:4324] (rev 02) 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03) 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) 00:0f.3 Multimedia audio controller [0401]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] (rev 01) 00:0f.4 USB controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02) 00:0f.5 USB controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)

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Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger 22 Oct '15

22 Oct '15

Hi Mark, On 21.10.2015 16:18, Rowlinson Mark wrote: > I have a 32bit touch screen device running CentOS 5.2 which has some of its BIOS settings accessible in /dev/nvram and others elsewhere else (that's why I've been loooking at flashrom). > I have tried later distributions (CentOS 6.7 and the System Rescue CD) and they both report the following: > [root@server ~]# /var/tmp/flashrom-0.9.8/flashrom -p internal > flashrom v0.9.8-r1888 on Linux 2.6.32-573.el6.i686 (i686) > [...] > WARNING: No chipset found. Flash detection will most likely fail. > No EEPROM/flash device found. It seems we have to add some PCI IDs to our southbridge table. Do you have an exact name of the machine in question? > What information is needed to identify the chipset in use so support can be added for these devices? (as root) lspci -nnvvvxxx That should be sufficient for us to find out the southbridge and some of its settings. Regards, Carl-Daniel

2 1

[RFC PATCH] add support for N25Q256
by Cédric Le Goater 22 Oct '15

22 Oct '15

I needed to reflash a N25Q256 on a host system and hacked flashrom to make this work. For this, I used the 4-Bytes address support developed by Boris Baykov. This is why the patch is an RFC. The whole patchset is available under github here: https://github.com/legoater/flashrom I can help in getting this patchset merged but do the comments in : http://patchwork.coreboot.org/patch/4272/ need to be all addressed or can we rework a bit the patchset to merge the main changes separately : - 4-bytes addressing - W25Q256.V support - SFDP - Progress visualization - ... Tested under Linux with spidev. Signed-off-by: Cédric Le Goater <clg(a)fr.ibm.com> --- flashchips.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) Index: flashrom.git/flashchips.c =================================================================== --- flashrom.git.orig/flashchips.c +++ flashrom.git/flashchips.c @@ -9330,6 +9330,48 @@ const struct flashchip flashchips[] = { }, { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__3E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI + | FEATURE_4BA_SUPPORT, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192 } }, + .block_erase = spi_block_erase_20_4ba, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "MoselVitelic", .name = "V29C51000B", .bustype = BUS_PARALLEL,

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Flash chip/chipset not found
by Rowlinson Mark 21 Oct '15

21 Oct '15

Hi, I have a 32bit touch screen device running CentOS 5.2 which has some of its BIOS settings accessible in /dev/nvram and others elsewhere else (that's why I've been loooking at flashrom). I have tried later distributions (CentOS 6.7 and the System Rescue CD) and they both report the following: [root@server ~]# /var/tmp/flashrom-0.9.8/flashrom -p internal flashrom v0.9.8-r1888 on Linux 2.6.32-573.el6.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. WARNING: No chipset found. Flash detection will most likely fail. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. [root@server ~]# What information is needed to identify the chipset in use so support can be added for these devices? Best Regards, Mark Rowlinson Unless otherwise stated, this email has been sent from Fujitsu Services Limited, from Fujitsu (FTS) Limited, or from Fujitsu Telecommunications Europe Limited, together "Fujitsu". This email is only for the use of its intended recipient. Its contents are subject to a duty of confidence and may be privileged. Fujitsu does not guarantee that this email has not been intercepted and amended or that it is virus-free. Fujitsu Services Limited, registered in England No 96056, registered office 22 Baker Street, London W1U 3BW. Fujitsu (FTS) Limited, registered in England No 03808613, registered office 22 Baker Street, London W1U 3BW. PFU Imaging Solutions Europe Limited, registered in England No 1578652, registered office Hayes Park Central, Hayes End Road, Hayes, Middlesex, UB4 8FE. Fujitsu Telecommunications Europe Limited, registered in England No 2548187, registered office Solihull Parkway, Birmingham Business Park, Birmingham, B37 7YU.

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by David Hendricks 21 Oct '15

21 Oct '15

Cool, glad it worked! To make things slightly easier, you should also try keeping the CMOS battery and DIM (whatever that is) in. On Tue, Oct 20, 2015 at 4:51 PM, Arpita Biswas <arpita.biswas07(a)gmail.com> wrote: > Hi David, > > That did the trick !!! Thanks a bunch ! For anyone else interested, here > is the combination of things I did : > > SOIC config as (1) mentioned earlier + held down the power button for 30 > sec to reset it + removed CMOS battery + removed jumper on SPI header (that > cuts off the processor signal to SPI chip) + plugged in the power cable > (that way enough power was there throughout the board for dediprog to > detect) + removed the DIM (dunno if that made any difference, but did it > since a post mentioned it anyways!). > > Dediprog then detected it sweetly :) :) > > Cheers, > - Arpita > > On Tue, Oct 20, 2015 at 2:05 PM, David Hendricks <dhendrix(a)google.com> > wrote: > >> >> >> On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas < >> arpita.biswas07(a)gmail.com> wrote: >> >>> Hi all, >>> >>> I am trying to update BIOS with coreboot onto HP Envy H87 haswell >>> chipset (ipm87_mp) >>> <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am >>> using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). >>> However dediprog doesn't detect the chip when it's soldered on-board. On >>> removing the chip from board, I can detect/read/write onto it without any >>> issues. >>> >>> I've tried (and failed) with the following configurations : >>> (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP >>> (IO2) ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD >>> (IO3) ---> 3.3V, VCC ---> 3.3V with motherboard power ON. >>> >>> (2) Same config as above but I tried to isolate the chip by removing >>> CMOS battery + removing jumper on SPI header + powering OFF the motherboard. >>> >>> (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. >>> >>> (4) I tried using flashrom on the box too as internal programmer, but it >>> did not recognize the SPI chip. Error log says "Found Programmer flash chip >>> "Opaque flash chip" (8192 kB, Programmer-specific)." >>> >>> I've a feeling that something on the motherboard is interfering with the >>> SPI chip since an off-board chip is working fine. Does anybody have any >>> pointers on what could be going wrong ? >>> >> >> I suspect your motherboard does not isolate the SPI ROM's voltage supply >> and thus your Dediprog is effectively powering other components on the >> board. >> >> If you can find a way to hold the PCH and ME in reset while the board is >> powered on, that might work. Or, with the board off, you can try using an >> external power supply (the usual warnings about possibly frying your board >> apply). >> >> >> >>> >>> Thanks in advance, >>> - Arpita >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >> >> -- >> David Hendricks (dhendrix) >> Systems Software Engineer, Google Inc. >> > > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by Arpita Biswas 21 Oct '15

21 Oct '15

Hi David, That did the trick !!! Thanks a bunch ! For anyone else interested, here is the combination of things I did : SOIC config as (1) mentioned earlier + held down the power button for 30 sec to reset it + removed CMOS battery + removed jumper on SPI header (that cuts off the processor signal to SPI chip) + plugged in the power cable (that way enough power was there throughout the board for dediprog to detect) + removed the DIM (dunno if that made any difference, but did it since a post mentioned it anyways!). Dediprog then detected it sweetly :) :) Cheers, - Arpita On Tue, Oct 20, 2015 at 2:05 PM, David Hendricks <dhendrix(a)google.com> wrote: > > > On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas <arpita.biswas07(a)gmail.com > > wrote: > >> Hi all, >> >> I am trying to update BIOS with coreboot onto HP Envy H87 haswell >> chipset (ipm87_mp) >> <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am >> using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). >> However dediprog doesn't detect the chip when it's soldered on-board. On >> removing the chip from board, I can detect/read/write onto it without any >> issues. >> >> I've tried (and failed) with the following configurations : >> (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) >> ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> >> 3.3V, VCC ---> 3.3V with motherboard power ON. >> >> (2) Same config as above but I tried to isolate the chip by removing CMOS >> battery + removing jumper on SPI header + powering OFF the motherboard. >> >> (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. >> >> (4) I tried using flashrom on the box too as internal programmer, but it >> did not recognize the SPI chip. Error log says "Found Programmer flash chip >> "Opaque flash chip" (8192 kB, Programmer-specific)." >> >> I've a feeling that something on the motherboard is interfering with the >> SPI chip since an off-board chip is working fine. Does anybody have any >> pointers on what could be going wrong ? >> > > I suspect your motherboard does not isolate the SPI ROM's voltage supply > and thus your Dediprog is effectively powering other components on the > board. > > If you can find a way to hold the PCH and ME in reset while the board is > powered on, that might work. Or, with the board off, you can try using an > external power supply (the usual warnings about possibly frying your board > apply). > > > >> >> Thanks in advance, >> - Arpita >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. >

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by David Hendricks 20 Oct '15

20 Oct '15

On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas <arpita.biswas07(a)gmail.com> wrote: > Hi all, > > I am trying to update BIOS with coreboot onto HP Envy H87 haswell chipset > (ipm87_mp) > <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am > using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). > However dediprog doesn't detect the chip when it's soldered on-board. On > removing the chip from board, I can detect/read/write onto it without any > issues. > > I've tried (and failed) with the following configurations : > (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) > ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> > 3.3V, VCC ---> 3.3V with motherboard power ON. > > (2) Same config as above but I tried to isolate the chip by removing CMOS > battery + removing jumper on SPI header + powering OFF the motherboard. > > (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. > > (4) I tried using flashrom on the box too as internal programmer, but it > did not recognize the SPI chip. Error log says "Found Programmer flash chip > "Opaque flash chip" (8192 kB, Programmer-specific)." > > I've a feeling that something on the motherboard is interfering with the > SPI chip since an off-board chip is working fine. Does anybody have any > pointers on what could be going wrong ? > I suspect your motherboard does not isolate the SPI ROM's voltage supply and thus your Dediprog is effectively powering other components on the board. If you can find a way to hold the PCH and ME in reset while the board is powered on, that might work. Or, with the board off, you can try using an external power supply (the usual warnings about possibly frying your board apply). > > Thanks in advance, > - Arpita > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by Arpita Biswas 20 Oct '15

20 Oct '15

Hi all, I am trying to update BIOS with coreboot onto HP Envy H87 haswell chipset (ipm87_mp) <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). However dediprog doesn't detect the chip when it's soldered on-board. On removing the chip from board, I can detect/read/write onto it without any issues. I've tried (and failed) with the following configurations : (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> 3.3V, VCC ---> 3.3V with motherboard power ON. (2) Same config as above but I tried to isolate the chip by removing CMOS battery + removing jumper on SPI header + powering OFF the motherboard. (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. (4) I tried using flashrom on the box too as internal programmer, but it did not recognize the SPI chip. Error log says "Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific)." I've a feeling that something on the motherboard is interfering with the SPI chip since an off-board chip is working fine. Does anybody have any pointers on what could be going wrong ? Thanks in advance, - Arpita

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Re: [flashrom] SOIC8 test clip - cant write to BIOS SPI flash chip
by Robert Brown 17 Oct '15

17 Oct '15

Dear Nico, > > It might be easier to help if we knew your Laptop model. Also, please > provide a full log of the failing flashrom run with the -V switch, you > can specify a log file with -o. > Right now I'm away from that laptop and cant remember its model (or provide a flashrom log) However I remember the most important thing: the model of BIOS SPI flash chip is EON EN25QH32 which is supported by flashrom since version 0.9.6 . I got a latest datasheet at official EON website ( here it is - http://www.eonssi.com/upfile/p2013114174725.pdf ) > > Please further define "without problems". Did you try several reads and > compared the contents? > Yes I tried several reads and the contents of flash chip are always the same. Moreover, I was able to successfully write 00s and FFs for a few times, and right now the contents of SPI flash chip: 00's - first 1MB , FF's - last 3MB > > By guessing two possible issues come in mind: 1. Your programmer doesn't provide > enough power for erasure. 2. The write protection pin of your flash chip is asserted. > Because I was able to write at least some stuff, I believe that your 1st theory is true: maybe a part of current that should be going to flash chip for a successfull write, is powering a half of the surrounding circuit instead... > > I'd try with the AC adapter. In that case Vcc must _not_ be connected to > your programmer. GND, OTOH, has to stay connected. > > Not forbidden. It's sometimes even encouraged because there are boards > where the Vcc pin of the flash chip is directly connected to other > chips, which would draw down the power from the programmer. > Thank you very much for advice, Nico! As soon as I get back to equipment I am going to disconnect a Vcc pin from a programmer to avoid the overvoltage (just checked the datasheet above and Vcc is the 8th leg of that flash chip) Hopefully it will be powered good enough by the AC adapter ;-) Just not sure what to do with a CMOS battery, too afraid to connect it back together with AC adapter - if there would be overvoltage I am screwed... > >> >> Or its better to try to power Vcc of flash chip from "USB to TTL" >> adapter - which has this 3V3 (3.3V) voltage pin? >> > > It really depends on your machine. > EN25QH32 datasheet tells that this flash chip supports between 2.7V and 3.6V, 3.3V seems OK and I would probably try taking it to Vcc from "USB to TTL adapter" if the solution with a laptop's AC adapter will not work... AC adapter would also powering EC controller, so what if EC will setup a write protect? Best wishes, Robert Brown <-----Original Message-----> >From: Nico Huber [nico.h at gmx.de] >Subject: Re: [flashrom] SOIC8 test clip - cant write to BIOS SPI flash chip > > >On 17.10.2015 02:07, Robert Brown wrote: >> But here is a problem: I could read a dump from this BIOS chip without >> problems, however > > >> it fails when I am trying to write - so the contents of BIOS flash chip >> are remaining unchanged. >Log please. By guessing two possible issues come in mind: 1. Your pro- >grammer doesn't provide enough power for erasure. 2. The write protec- >tion pin of your flash chip is asserted. > >> Should I connect to motherboard a laptop's power battery, or small CMOS >> battery, or AC adapter of laptop, >I'd try with the AC adapter. In that case Vcc must _not_ be connected to >your programmer. GND, OTOH, has to stay connected. > >> so that this Vcc pin would be powered by them, or it is forbidden to do >> it while using SPI programmer in the same time? >Not forbidden. It's sometimes even encouraged because there are boards >where the Vcc pin of the flash chip is directly connected to other >chips, which would draw down the power from the programmer. > >> Or its better to try to power Vcc of flash chip from "USB to TTL" >> adapter - which has this 3V3 (3.3V) voltage pin? >It really depends on your machine. > >Nico >. > _______________________________________________________________ Get the Free email that has everyone talking at <a href=http://www.mail2world.com target=new>http://www.mail2world.com</a> Unlimited Email Storage POP3 Calendar SMS Translator Much More!

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SOIC8 test clip - cant write to BIOS SPI flash chip
by r_brown100r＠aim.com 17 Oct '15

17 Oct '15

Unfortunately I don't have any soldering tools or experience, so if you could give an advice about ISP programming (In-System-Programming/In-Situ-Programming) , it will be super helpful! I teardown a bricked laptop, removed AC power, laptop's power battery, and even a small CMOS battery, and now I am trying to write a working BIOS image to laptop's SPI flash chip using a SOIC8 test clip. But here is a problem: I could read a dump from this BIOS chip without problems, however it fails when I am trying to write - so the contents of BIOS flash chip are remaining unchanged. Luckily I found out this helpful wiki page - http://flashrom.org/ISP , which describes common problems with this ISP method of flashing, as well as gives 3 hints for solution! Sadly this page is currently down, so here is a screenshot: http://i.imgur.com/SJEYHR2.png 1. - tried to make shorter wires, less than 10cm as they recommend - it did not help 2. - soldering is out of possibility, cant do it, and also: wires are already short and they are good quality (pure copper) 3. - This hint looks more promising, but I need help in understanding this piece of information: "disconnect Vcc from the programmer and power it with its normal PSU" If I understand correctly, by Vcc they mean Vcc pin of the BIOS flash chip. But if I disconnect Vcc from the programmer, what is "normal PSU" which should power this Vcc pin? Should I connect to motherboard a laptop's power battery, or small CMOS battery, or AC adapter of laptop, so that this Vcc pin would be powered by them, or it is forbidden to do it while using SPI programmer in the same time? Or its better to try to power Vcc of flash chip from "USB to TTL" adapter - which has this 3V3 (3.3V) voltage pin? Yours faithfully, Robert Brown

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M25P10-A write success confirmed and verified
by Stefan Tauner 16 Oct '15

16 Oct '15

We got a mail by a reporter who does not want to get his email address published, therefore I will quote his email verbatim below. > Hello, > > I can confirm that I have just successfully flashed an ST 25P10VP flash > chip, in circuit, using a Raspberry Pi, its onboard SPI, a Pomona 5250 SOIC > clip and some female jumper wires. > > I updated the Raspberry Pi B+ with rpi-update to the latest firmware and > kernel, and compiled the code from svn://flashrom.org/flashrom/trunk on the > Raspberry device itself. I just used the -p and -w parameters to make this > work, no other magic. Flashrom reported write success and verified status > on the chip. > > According to Micron documentation, the markings 25P10VP correspond to a > M25P10-A, and flashrom recognizes this type indeed. Since the status for > writing this chip is still a question mark, I thought I should report a > success. > > I encountered zero errors during the use of flashrom, everything worked in > one go. Flashrom allowed me to recover a friend's WD HDD with a burnt-out > PCB. So a big thank you is in order! > > Thank you so much! > > P.S. Could you please keep my e-mail address private? > > Kind regards, > Martijn Schiedon I'll add the respective flag for the M25P10-A. Thanks Martijn for the report! Please include a verbose log file next time. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1897 - trunk
by repository service 16 Oct '15

16 Oct '15

Author: stefanct Date: Fri Oct 16 04:16:20 2015 New Revision: 1897 URL: http://flashrom.org/trac/flashrom/changeset/1897 Log: Add support for 128 bytes write granularity. Some chips such as the ENE KB9012 internal flash require a write granularity of 128 bytes. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Acked-by: Nico Huber <nico.h(a)gmx.de> Modified: trunk/flash.h trunk/flashrom.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 5 18:53:22 2015 (r1896) +++ trunk/flash.h Fri Oct 16 04:16:20 2015 (r1897) @@ -85,6 +85,7 @@ write_gran_1bit, /* Each bit can be cleared individually. */ write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause * its contents to be either undefined or to stay unchanged. */ + write_gran_128bytes, /* If less than 128 bytes are written, the unwritten bytes are undefined. */ write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 5 18:53:22 2015 (r1896) +++ trunk/flashrom.c Fri Oct 16 04:16:20 2015 (r1897) @@ -781,6 +781,9 @@ break; } break; + case write_gran_128bytes: + result = need_erase_gran_bytes(have, want, len, 128); + break; case write_gran_256bytes: result = need_erase_gran_bytes(have, want, len, 256); break; @@ -847,6 +850,9 @@ case write_gran_1byte_implicit_erase: stride = 1; break; + case write_gran_128bytes: + stride = 128; + break; case write_gran_256bytes: stride = 256; break;

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Re: [flashrom] Report: Intel DH67CF BLH6710H.86A.0160.2012.1204.1156 read
by Leonardo Villarreal Cortez 15 Oct '15

15 Oct '15

hello, i have an intel board series dh67, i need bios dump. can help me facilitating the file of dump ? thanks -- Atentamente, Leonardo Villarreal.

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flashrom output on HP 425 Notebook
by bleoal＠openmailbox.org 12 Oct '15

12 Oct '15

Hello: My name is Bruno, last few days ago I founded information about the coreboot project. My question is: Why flashrom says it doesn't support my motherboard if my chipset is supported on the coreboot project wiki. Northbridge: AMD Fam10h Support:OK Southbridge: AMD SB7x0/SB8x0/SB9x0 1002:439d Support:OK SuperI/O: SMSC® FDC37B72x Support:OK CPU: AMD Athlon II P340 Dual-Core Here is the output: Flashrom 0.9.5.2-r1517 : $ sudo flashrom -p internal -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-29-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 731M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10009 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP 425" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "1475" DMI string baseboard-version: "KBC Version 72.13" DMI string chassis-type: "Notebook" Laptop detected via DMI. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. lspci -nnvvxxx $ sudo lspci -nnvvxxx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=12 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: 1.6GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [40] HyperTransport: Retry Mode Capabilities: [9c] HyperTransport: #1a Capabilities: [f8] HyperTransport: #1c 00: 22 10 01 96 06 00 30 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 08 9c 00 c0 c1 00 00 00 0b 00 00 00 42 20 05 00 50: 3c 10 75 14 08 40 00 90 08 10 05 00 08 10 05 00 60: 00 00 00 00 8e 00 00 00 00 02 20 00 0f 80 86 81 70: 00 00 00 00 00 00 00 00 a5 00 01 11 00 00 00 20 80: 00 00 00 00 10 00 04 03 20 c8 00 00 13 26 00 10 90: 00 00 00 80 3d 01 00 00 47 00 00 00 08 f8 7c d0 a0: 26 00 66 00 00 00 00 83 00 00 00 00 79 01 c0 07 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 80 08 54 80 01 20 00 11 00 d0 00 00 00 d0: 60 09 75 1e 02 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 0d 02 00 00 64 40 05 00 f0: 00 00 00 00 01 00 00 00 08 00 00 e0 00 00 00 00 00:01.0 PCI bridge [0604]: Hewlett-Packard Company Device [103c:9602] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00005000-00005fff Memory behind bridge: 94200000-943fffff Prefetchable memory behind bridge: 0000000080000000-000000008fffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Kernel modules: shpchp 00: 3c 10 02 96 07 00 30 02 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 51 51 20 02 20: 20 94 30 94 01 80 f1 8f 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 3c 10 75 14 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 3c 10 75 14 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 0) [1022:9604] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00003000-00004fff Memory behind bridge: 93200000-941fffff Prefetchable memory behind bridge: 0000000090000000-00000000910fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4159 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 04 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 31 41 00 00 20: 20 93 10 94 01 90 01 91 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 01 43 00 11 78 00 00 24 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 59 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 3) [1022:9607] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=05, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: 92200000-931fffff Prefetchable memory behind bridge: 0000000091100000-00000000920fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #247, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #7, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4161 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 07 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 05 00 21 21 00 00 20: 20 92 10 93 11 91 01 92 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 f7 00 00 00 11 60 00 3c 00 70: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 4) [1022:9608] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Memory behind bridge: 92100000-921fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #9, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4169 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 08 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 20 20: 10 92 10 92 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 00 42 00 11 70 00 00 4c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 69 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (prog-if 01 [AHCI 1.0]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 6018 [size=8] Region 1: I/O ports at 6024 [size=4] Region 2: I/O ports at 6010 [size=8] Region 3: I/O ports at 6020 [size=4] Region 4: I/O ports at 6000 [size=16] Region 5: Memory at 9440b000 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] SATA HBA v1.0 InCfgSpace Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ahci 00: 02 10 91 43 07 00 30 02 00 01 06 01 10 40 00 00 10: 19 60 00 00 25 60 00 00 11 60 00 00 21 60 00 00 20: 01 60 00 00 00 b0 40 94 00 00 00 00 3c 10 75 14 30: 00 00 00 00 70 00 00 00 00 00 00 00 0a 01 00 00 40: 14 80 bc 00 01 00 20 00 00 00 80 00 00 00 00 00 50: 05 70 86 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 50 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 a4 10 00 0f 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 06 14 14 00 ab 01 08 00 f0 00 00 00 90: 27 60 74 c7 00 43 06 00 00 01 00 00 01 58 b1 02 a0: 0c 00 00 00 13 00 06 03 00 00 64 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 e0: 80 00 00 00 00 00 00 00 00 00 00 00 10 00 00 3f f0: 00 00 00 00 00 00 00 00 77 77 77 00 00 00 00 00 00:12.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 18 Region 0: Memory at 9440a000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 13 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 a0 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 00 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94409000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 90 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 18 Region 0: Memory at 94408000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 13 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 80 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 14 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94407000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 13 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 70 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 03 01 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller [1002:4385] (rev 42) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel modules: sp5100_tco, i2c-piix4 00: 02 10 85 43 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: Advanced Micro Devices [AMD] nee ATI SBx00 Azalia (Intel HDA) [1002:4383] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at 94400000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_hda_intel Kernel modules: snd-hda-intel 00: 02 10 83 43 06 00 10 04 40 00 03 04 08 40 00 00 10: 04 00 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 02 00 01 10 00 00 00 00 00 00 01 00 00 00 50: 01 00 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 9d 43 0f 00 20 02 40 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 41 ff 03 ff 07 ff 20 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 90 0e 00 fe 00 00 0f 00 b8 ff ff ff 70: 67 45 23 00 01 00 00 00 1c 00 00 00 05 0a 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 d6 fe a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 09 39 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge [1002:4384] (rev 40) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=07, subordinate=07, sec-latency=64 I/O behind bridge: 00001000-00001fff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 02 10 84 43 07 00 a0 02 40 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 07 07 40 10 10 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 26 00 3c ff 00 00 00 00 0c 0f 3d d1 00 00 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba 98 10 02 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.5 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin C routed to IRQ 18 Region 0: Memory at 94406000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 99 43 17 00 a0 02 00 10 03 0c 10 40 00 00 10: 00 60 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 80 01 03 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at 94405000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 50 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 0f 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94404000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 13 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 40 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 03 01 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b+ Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency: 1.6GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 01 00 e0 00 00 00 20 a8 2e 01 10 fe 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 a0 11 00 60 09 f5 83 13 00 00 00 90: d0 02 85 80 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 80 00 80 ff 8f 00 03 00 90 00 00 1f 94 00 90: 03 20 94 00 80 3f 94 00 03 40 94 00 00 ff df 00 a0: 03 00 e0 00 80 ff e0 00 03 00 e1 00 00 bf fe 00 b0: 03 c0 fe 00 80 fe ff 00 03 ff ff 00 00 ff ff 00 c0: 13 00 00 00 00 f0 ff 00 00 00 00 00 16 82 00 00 d0: 00 00 00 00 0a 30 f0 00 00 00 00 00 18 10 60 00 e0: 03 00 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel modules: amd64_edac_mod 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 04 00 00 0b 00 00 00 00 80: 00 00 00 00 04 00 00 00 00 00 00 ff 00 00 00 00 90: 00 00 01 08 00 41 08 00 0a 00 00 80 e7 88 71 0e a0: 00 02 00 00 00 00 00 00 00 00 01 00 00 00 00 00 b0: 29 62 51 8c 7f 00 00 00 1c 08 3e 04 40 01 e8 1f c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 78 3c 00 f0 01 30 03 01 f9 19 18 0e e7 11 18 20 e0: 44 c2 1d 0e 2f eb 30 00 14 2c 30 1e 00 90 87 c1 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff ff ff 3f 58 00 b0 4a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 05 00 60 1a 00 00 00 10 51 80 01 60 70: 51 11 32 60 01 01 98 00 14 0c 20 00 11 08 07 00 80: 81 f6 0b e6 e6 41 e6 01 08 00 00 00 00 60 58 02 90: 00 00 00 00 80 00 00 00 90 0f 88 70 00 00 00 00 a0: b9 0a 0d b0 ef 0f 88 2b 28 07 04 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 24 0f 81 c8 14 0b 39 03 43 52 27 70 e0: 00 00 00 00 30 06 40 01 61 5f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 63 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller [0300]: Advanced Micro Devices [AMD] nee ATI RS880M [Mobility Radeon HD 4200 Series] [1002:9712] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at 80000000 (32-bit, prefetchable) [size=256M] Region 1: I/O ports at 5000 [size=256] Region 2: Memory at 94300000 (32-bit, non-prefetchable) [size=64K] Region 5: Memory at 94200000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: fglrx_pci Kernel modules: fglrx, radeon 00: 02 10 12 97 07 00 10 00 00 00 00 03 10 00 80 00 10: 08 00 00 80 01 50 00 00 00 00 30 94 00 00 00 00 20: 00 00 00 00 00 00 20 94 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.1 Audio device [0403]: Advanced Micro Devices [AMD] nee ATI RS880 HDMI Audio [Radeon HD 4200 Series] [1002:970f] Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 19 Region 0: Memory at 94310000 (32-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: snd_hda_intel Kernel modules: snd-hda-intel 00: 02 10 0f 97 07 00 10 00 00 00 03 04 10 00 80 00 10: 00 00 31 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] (rev 02) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 43 Region 0: I/O ports at 3000 [size=256] Region 2: Memory at 90010000 (64-bit, prefetchable) [size=4K] Region 4: Memory at 90000000 (64-bit, prefetchable) [size=64K] Expansion ROM at 90020000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 4171 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [ac] MSI-X: Enable- Count=2 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP+ BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 01-00-00-00-ff-ff-00-00 Kernel driver in use: r8169 Kernel modules: r8169 00: ec 10 36 81 07 04 10 00 02 00 00 02 10 00 00 00 10: 01 30 00 00 00 00 00 00 0c 00 01 90 00 00 00 00 20: 0c 00 00 90 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 fe ff 40 00 00 00 00 00 00 00 07 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c 30 e0 fe 00 00 00 00 71 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 00 00 10 50 19 00 11 3c 07 00 80: 43 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 01 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06:00.0 Network controller [0280]: Broadcom Corporation BCM4313 802.11b/g/n Wireless LAN Controller [14e4:4727] (rev 01) Subsystem: Hewlett-Packard Company Device [103c:1483] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at 92100000 (64-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=2 PME- Capabilities: [58] Vendor Specific Information: Len=78 <?> Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [d0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us, L1 <64us ClockPM+ Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [13c v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 00-00-af-ff-ff-0d-cc-52 Capabilities: [16c v1] Power Budgeting <?> Kernel driver in use: wl Kernel modules: wl, bcma, brcmsmac 00: e4 14 27 47 06 00 10 00 01 00 80 02 10 00 00 00 10: 04 00 10 92 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 83 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 58 03 06 08 40 00 00 05 d0 80 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 09 48 78 00 11 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 10 00 18 00 00 00 00 80 00 00 00 03 00 00 00 90: 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 03 00 00 10 10 18 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 10 00 01 00 a0 8f 00 00 00 00 10 00 11 6c 17 00 e0: 42 00 11 30 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Superiotool output: $ sudo superiotool -deV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0400, id=0x014c Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC FDC37B72x (id=0x4c, rev=0x01) at 0x2e Register dump: idx 03 20 21 22 23 24 26 27 28 2b 2c 2d 2e 2f val 00 4c 01 00 00 04 2e 00 00 00 00 00 00 00 def 03 4c 00 00 00 04 MM MM 00 NA NA NA NA NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 00 00 00 00 00 00 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 00 00 00 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA 00 00 00 00 02 03 LDN 0x07 (Keyboard) idx 30 70 72 f0 val 01 01 0c 00 def 00 00 00 00 LDN 0x08 (Aux I/O) idx 30 b0 b1 b2 b3 b8 c0 c1 c2 c3 c4 c5 c6 c8 ca cb cc d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 ef f0 f1 f2 f3 f4 f6 f9 fa val 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 NA NA NA NA NA 00 01 NA NA NA 00 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 00 MM NA NA NA LDN 0x0a (ACPI) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 NA NA No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff

2 1

Re: [flashrom] Flashrom failed on Acer C720P, using Fedora 23
by Jonathan Alfonso 12 Oct '15

12 Oct '15

1 0

Flashrom failed on Acer C720P, using Fedora 23
by Jonathan Alfonso 12 Oct '15

12 Oct '15

Hi, I have this output... http://paste.flashrom.org/view.php?id=2803 I can't reboot right now, so I'm looking for a fix... I don't know what to do though. Help is definitely appreciated...

1 0

Re: [flashrom] trouble flashing EN25S64 on Lenovo N21 chromebook
by Kyle Stanevich 08 Oct '15

08 Oct '15

Hi, This is just a follow up email. I was wondering what the status is of support for the EN25S64 bios chip. I have tried to flash it many times and it always fails. See my message below for more details. I would like to help out with any testing for this chip, however if I don't hear back from you soon, I will probably be returning the laptop I have which contains the EN25S64 chip. Thanks, Kyle Stanevich On Oct 4, 2015 6:22 PM, "Kyle Stanevich" <kstanevich(a)imsa.edu> wrote: > Hi, > > I am still having trouble flashing the EN25S64 chip on my Lenovo N21 > chromebook. I have connected a raspberry pi to the EN25S64 on the Lenovo > N21 motherboard chip via this clip ( > http://www.amazon.com/Qunqi-Soic8-Flash-Clips-Programmer/dp/B014IXR9RG). > On the raspberry pi (which is running raspbian) I run the command "sudo > ./flashrom -VVV -p linux_spi:dev=/dev/spidev0.0 -w ~/Downloads/bios.bin". I > have removed the write protect screw, but I don't think that matters > because I am connecting to the chip directly. > > I have tried to compile google's (chromiumos') version of flashrom, but I > could not get it to compile due to many errors. Therefore, I am using the > latest version of flashrom which compiles fine. > > It seams to me that the problem is there is something not working > correctly writing/erasing/reading to the chip. Erase functions 1 through 3 > all fail when using the command shown above. It hangs up on erase function > 2 for a very long time. I had to run it overnight until erase function 2 > failed. I have tried running the same command again, and it is currently > still stuck at "Trying erase function 2... 0x000000-0x7fffff:E". It has > been stuck at this line for 16 hours, with the raspberry pi at 100% cpu > usage the entire time. > > The line "This flash part has status UNTESTED for operations: PROBE READ > ERASE WRITE" indicates to me that this chip has not yet been tested. I > would like to help out with testing for this chip since I have one and have > the hardware required to flash it. What can I do to help out? > > Thanks, > Kyle Stanevich > > > > On Sat, Oct 3, 2015 at 3:56 PM, Stefan Tauner < > stefan.tauner(a)alumni.tuwien.ac.at> wrote: > >> On Sat, 3 Oct 2015 10:13:36 -0700 >> Kyle Stanevich <kstanevich(a)imsa.edu> wrote: >> >> > Hi, >> > >> > I have attached all the output from my command line. Hopefully it will >> > be useful for you. >> > >> > Do you think that I will ever have a chance to flash this chip, or >> > should I go and buy another laptop? >> >> Hi, >> >> first of all you should not reboot before fixing the issue. >> If you made a backup first, you should try to write that instead. >> If that works you are at least safe... >> >> I am not familiar with the N21 but you probably have to disable a write >> protection. Also, chromebooks work best with google's (chromiumos') >> version of flashrom. >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > >

1 0

Re: [flashrom] MX25L25635E / 4 byte addressing
by Michaël Zweers 05 Oct '15

05 Oct '15

Hello, I have used the same patch set on trunk to flash W25Q256 (WSON version). I still need to build a system to check what was actually written. (I'll try to flash Openwrt to the chip and run in on a MT7620 with modded U-boot). If there is anything I can do to move this along, please let me know. Kind regards, Michaël Zweers On 21-9-2015 14:59, Peter Martini wrote: > On Tue, Sep 15, 2015 at 3:12 AM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at > <mailto:stefan.tauner@alumni.tuwien.ac.at>> wrote: > > On Tue, 15 Sep 2015 02:26:39 -0400 > Peter Martini <petercmartini(a)gmail.com > <mailto:petercmartini@gmail.com>> wrote: > > > Hello, > > > > I've checked out master from the flashrom svn repo, compiled, and was able > > to see my chip (MX25L25635E). The id wasn't recognized, but after a quick > > patch to copy a MX25L128... to ..L256.., I got it to successfully read the > > first 16MB of the chip - however, I can't get any further than that, > > because changing the values in the table to the right values moves me from > > 3 byte addressing to 4 byte addressing territory (if I understand this > > correctly), and it looks like there aren't any patches merged for that yet. > > > > Is there a patch set actively in the works? > > Nope, there isn't, at least nothing that I know about or that will hit > vanilla flashrom soon. > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > Thanks for the quick reply. I did some digging, and found a patch set > from January, resurrected and forward ported to the current tip of > flashrom on github.com/petermartini/flashrom > <http://github.com/petermartini/flashrom>, and confirmed it worked well > enough that it worked on my chipset. > > This was Boris' work, and I guess it was incomplete / petered out before > being committed; does it ring any bells? > > It seems the thread petered out around > http://www.flashrom.org/pipermail/flashrom/2015-January/013168.html. > > I'm happy to help, if I can, get that patch set merged in if there's > work to be done on it so I can upstream my chipset's specs. > > Thanks! > Peter > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

1 0

Re: [flashrom] trouble flashing EN25S64 on Lenovo N21 chromebook
by Stefan Tauner 05 Oct '15

05 Oct '15

On Sat, 3 Oct 2015 10:13:36 -0700 Kyle Stanevich <kstanevich(a)imsa.edu> wrote: > Hi, > > I have attached all the output from my command line. Hopefully it will > be useful for you. > > Do you think that I will ever have a chance to flash this chip, or > should I go and buy another laptop? Hi, first of all you should not reboot before fixing the issue. If you made a backup first, you should try to write that instead. If that works you are at least safe... I am not familiar with the N21 but you probably have to disable a write protection. Also, chromebooks work best with google's (chromiumos') version of flashrom. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

[PATCH] ft2232: Hack to delay SPI command after CS# assertion
by Nico Huber 04 Oct '15

04 Oct '15

Here's a tiny hack that I use to externally flash my X200s with an FT2232H. It delays the SPI command by repeating the CS# assertion command many times. Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- ft2232_spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 08742ec..a85925c 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -419,15 +419,16 @@ static int ft2232_spi_send_command(struct flashctx *flash, struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; + int i = 0, j, ret = 0, failed = 0; int bufsize; static int oldbufsize = 0; + const int extra_assert_time = 288; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); + bufsize = max(writecnt, 260) + 9 + extra_assert_time * 3; /* Never shrink. realloc() calls are expensive. */ if (bufsize > oldbufsize) { buf = realloc(buf, bufsize); @@ -446,9 +447,11 @@ static int ft2232_spi_send_command(struct flashctx *flash, * operations. */ msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ - buf[i++] = pindir; + for (j = 0; j <= extra_assert_time; ++j) { + buf[i++] = SET_BITS_LOW; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; + } if (writecnt) { buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; -- 2.4.6

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trouble flashing EN25S64 on Lenovo N21 chromebook
by Kyle Stanevich 03 Oct '15

03 Oct '15

Hi, I have attached all the output from my command line. Hopefully it will be useful for you. Do you think that I will ever have a chance to flash this chip, or should I go and buy another laptop? Thanks, Kyle Stanevich

1 0

A bunch of old parallel chips
by Xavier Bourgeois 30 Sep '15

30 Sep '15

I noticed a few chips that were not listed for all operations on the flashrom supported hardware webpage: - ASD AE29F2008, fake Winbond W29C020C found on a PCChips motherboard full of fake/remarkered chips, it looks like it was reported previously on the list, [0], [1], - AMIC A29002T, [2], - AMD Am27C010, not correctly detected, probe forced for Am29F010A/B (same signals/timings for reading). Electrical erase is impossible (UV-Light needed), programmation wasn't tried (this motherboard doesn't supply the 12.5V needed for Vpp), [3], - Macronix MX29F002T, [4], - SST SST29EE10, [5], Some chips (A29002T, MX29F002T) are already marked as OK on the supported hardware page, but were probably not already tested in the flashrom release I'm using. I also have a Winbond W29EE11 which wasn't detected by flashrom and seems pretty old and rare (I didn't manage to find the datasheet so I assumed the voltages and the pinout were the same...). From the bios sticker, it looks like it was from a socket 7 motherboard from the years 96~97. All these chips were tested on a MSI MS6147 Motherboard (Intel PIIX4 BX chipset with a 32-pin DIL socket), using flashrom v0.9.2-r1141 (Debian Squeeze). Thanks, [0]: http://www.flashrom.org/pipermail/flashrom/2009-August/000423.html [1]: http://monorailc.at/tmp/29F2008.tar.gz [2]: http://monorailc.at/tmp/a29002T.tar.gz [3]: http://monorailc.at/tmp/am27C10.tar.gz [4]: http://monorailc.at/tmp/mx29F002T.tar.gz [5]: http://monorailc.at/tmp/sst29EE10.tar.gz -- Xavier Bourgeois

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Re: [flashrom] CH341 patch request
by Stefan Tauner 30 Sep '15

30 Sep '15

On Wed, 23 Sep 2015 17:24:01 +0200 Ádám Attila Nagy <osiixy(a)gmail.com> wrote: > Hi, > just to avoid oblivion I send this mail as you have asked. > Thanks Hi Ádám, sorry that it took me so long... I have pushed my current patch set for the CH341A to my github repo: https://github.com/stefanct/flashrom/tree/ch341a I have forgotten what does not work yet, and the code itself is definitely not in good shape yet either but feel free to hack away on it :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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SST39VF040 on 3COM 3C905C:
by Xavier Bourgeois 30 Sep '15

30 Sep '15

The SST39VF040 is listed as untested on the flashrom supported hardware page. I tried it on a 3Com 3C905C (which limits to 128kbytes). All operations (probe, read, erase and write were done successfully for the first 128kbytes) [0]. I attached the NIC's bootrom [1], which was resized from 64kbytes to 512kbytes in order to be flashed. I also attached the same image which has been read after the flash. All the first 128kbytes are identical, and the data repeats until the end of the file. The network card is also able to boot from this eeprom. Thanks, [0]: http://monorailc.at/tmp/3c905c.tar.gz [1]: http://monorailc.at/tmp/3c905c_dump.tar.gz -- Xavier Bourgeois

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Supported flash chips: AT45DB321D tested Probe, Read, Erase, Write successfully
by Igor Kubinski 30 Sep '15

30 Sep '15

2 1

Issue Inquiry
by Jingfu Ju 28 Sep '15

28 Sep '15

Hi, There, I failed to update BIOS with commandflashrom -w -p internal xxx.bin and uploaded flashrom -v message for your reference. Please help me take a look. Thanks. Best Regards,Jingfu

1 0

CH341 patch request
by Ádám Attila Nagy 23 Sep '15

23 Sep '15

Hi, just to avoid oblivion I send this mail as you have asked. Thanks -- Nagy, Ádám Attila

1 0

Re: [flashrom] MX25L25635E / 4 byte addressing
by Stefan Tauner 21 Sep '15

21 Sep '15

On Tue, 15 Sep 2015 02:26:39 -0400 Peter Martini <petercmartini(a)gmail.com> wrote: > Hello, > > I've checked out master from the flashrom svn repo, compiled, and was able > to see my chip (MX25L25635E). The id wasn't recognized, but after a quick > patch to copy a MX25L128... to ..L256.., I got it to successfully read the > first 16MB of the chip - however, I can't get any further than that, > because changing the values in the table to the right values moves me from > 3 byte addressing to 4 byte addressing territory (if I understand this > correctly), and it looks like there aren't any patches merged for that yet. > > Is there a patch set actively in the works? Nope, there isn't, at least nothing that I know about or that will hit vanilla flashrom soon. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

sending my verbose log as requested...
by Matthew D. Frederes 18 Sep '15

18 Sep '15

[root@localhost ~]# flashrom -r current.bios -V flashrom v0.9.5.2-r1530 on Linux 2.6.32-573.el6.x86_64 (x86_64), built with libpci 3.1.4, GCC 4.4.6 20110731 (Red Hat 4.4.6-3), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2496M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1009 us, 10000 myus = 10006 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DP35DP" DMI string baseboard-version: "AAD81073-209" DMI string chassis-type: "Desktop" Found chipset "Intel ICH9R" with PCI ID 8086:2916. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa WARNING: Setting 0xdc from 0xa to 0xb on ICH9R failed. New value is 0xa. Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x2f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=47, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x00ff0035 FREG1: BIOS region (0x00035000-0x000fffff) is read-write. 0x5C: 0x00340003 FREG2: WARNING: Management Engine region (0x00003000-0x00034fff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0x004200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x0008 (OPTYPE) 0x98: 0x0000ab9f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002009 (LVSCC) LVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002009 (UVSCC) UVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 1024 kB. There is only one partition containing the whole address space (0x000000 - 0x0fffff). There are 256 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x67, id2 0x21, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x67, id2 0x21, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x67, id2 0x21, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x38, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x67, id2 0x21, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x67, id2 0x21, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x1a, id2 0x9e, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific). Reading flash... Reading 1048576 bytes starting at 0x000000. Transaction error between offset 0x00003000 and 0x0000303f (= 0x00003000 + 63)! HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 Read operation failed! FAILED. Restoring MMIO space at 0x7fb2d7a0e8a0 Restoring PCI config space for 00:1f:0 reg 0xdc [root@localhost ~]#

2 1

FS Esprimo E5730: reading rom does not seem to work if BIOS write protection is enabled
by Elmar Stellnberger 15 Sep '15

15 Sep '15

Today I have tried to read the BIOS image of my Fujitsu Siemens Esprimo E5730. flashrom has complained about the write protection as being set in force manually by the BIOS settings although I have just tried to read an image: > flashrom -p internal:ich_spi_mode=auto --read test.rom flashrom v0.9.7-r1711 on Linux 3.14.50-std460-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH10D". Enabling flash write... FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. FREG2: Warning: Management Engine region (0x00003000-0x002f7fff) is locked. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). OK. Found Winbond flash chip "W25X32" (4096 kB, SPI) at physical address 0xffc00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... Transaction error! Read operation failed! FAILED. More information can be found in the attachements.

2 2

MX25L25635E / 4 byte addressing
by Peter Martini 15 Sep '15

15 Sep '15

Hello, I've checked out master from the flashrom svn repo, compiled, and was able to see my chip (MX25L25635E). The id wasn't recognized, but after a quick patch to copy a MX25L128... to ..L256.., I got it to successfully read the first 16MB of the chip - however, I can't get any further than that, because changing the values in the table to the right values moves me from 3 byte addressing to 4 byte addressing territory (if I understand this correctly), and it looks like there aren't any patches merged for that yet. Is there a patch set actively in the works? (I saw some activity around this from January, from this link http://patchwork.coreboot.org/patch/4272/, but I'm not sure where that ended up). Thanks! Peter

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Re: [flashrom] Contribution: option to disable read_all_first
by Willy Tarreau 14 Sep '15

14 Sep '15

Hi David, On Mon, Sep 14, 2015 at 11:10:31AM -0700, David Hendricks wrote: > Hi Willy, > You might be interested in another approach that is used in the chromium > branch <https://chromium.googlesource.com/chromiumos/third_party/flashrom>. > The "--diff" longopt allows the user to supply a file to diff against the > -w argument. This is useful in cases where the user wishes to skip the > initial read step, and flashrom will figure out which blocks need to be > erased and written thereby eliminating unnecessary erase/write operations > as well. > > There is some documentation for it here: > https://sites.google.com/a/chromium.org/dev/chromium-os/packages/cros-flash… Thank you I'll take a look at it, it can indeed be another solution. The only thing is that it requires the creation of an extra file and I tend to find that it's not always convenient to have to create files for known patterns. However I think that it would be possible based on your approach to provide an option to replace the file with a known pattern for some cases (eg: full of 0xff or full of 0x00, which could be called "assume-clean" or "assume-dirty"), which would achieve the same result and at the same time not change the spirit of your latest work. Best regards, Willy

2 1

Contribution: option to disable read_all_first
by Willy Tarreau 14 Sep '15

14 Sep '15

Hello, I was bothered by having to read all the contents of an empty flash before programming just a boot loader to it. It's particularly long when using a buspirate board. I looked into the code to see how to bypass this and discovered it was already planned but not implemented due to the (presumably) complex API of the doit() function. I took a different route : I'm using 3 different write levels in write_it: - normal write (read first) - trusted write (no need to read but still erase) - fully trusted write (flash assumed to be clean) These ones are set using a new "-t" flag for which I have even updated the man page and indicated that it's not recommended. It worked well for me so I'm sending the patches assuming they'll be useful for someone else. BTW, to give you a bit more context, I was writing a 8MB flash to upgrade a small router from its 4MB one, so I just had to add 4MB of \xff after the existing image before flashing it. Best regards, Willy

2 1

flashrom can successfully read the BIOS image of my Amilo Xi3650 laptop
by Elmar Stellnberger 14 Sep '15

14 Sep '15

Lately I have tried > flashrom -p internal:laptop=force_I_want_a_brick --read Xi3650.rom on my Fujitsu Siemens Amilo Xi 3650 laptop and it has worked quite well. ... Found chipset "Intel ICH9M-E". Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address 0xffe00000. > sha256sum Xi3650.rom 8c5095d38bffe9b87d481ba8da395e48d9dcfadd43176979fd69e5da249b3763 Xi3650.rom BIOS (according to dmidecode) is Vendor: Phoenix Version: 1.0H-1646-0024 Release Date: 04/15/2010 I would love to see it under 'supported boards' in the future. More information can be found in the attachements.

1 0

Success: ASRock ION 330HT-BD
by Stefan Tauner 13 Sep '15

13 Sep '15

This is a small Atom-based media center from 2009. The board name is AMCP7AION-HT. I have successfully updated from the initial 1.00 to the last (and latest) version 1.20 and will add it myself to the wiki. ;) The -BD suffix is only indicating that there is a blueray player in the case. The mainboard and firmware is probably the same. http://www.asrock.com/nettop/NVIDIA/ION%20330HT-BD/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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