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[commit] r653 - trunk
by svn＠flashrom.org 14 Jul '09

14 Jul '09

Author: hailfinger Date: 2009-07-14 12:26:56 +0200 (Tue, 14 Jul 2009) New Revision: 653 Modified: trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.h trunk/wbsio_spi.c Log: Use a distinct return code for SPI commands with unsupported/invalid length. Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/ft2232_spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -201,6 +201,9 @@ unsigned char port_val = 0; int i, ret = 0; + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + buf = realloc(buf, writecnt + readcnt + 100); if (!buf) { fprintf(stderr, "Out of memory!\n"); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/ichspi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -599,10 +599,16 @@ { switch (spi_controller) { case SPI_CONTROLLER_VIA: + if (datalength > 16) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich9_run_opcode(op, offset, datalength, data); default: printf_debug("%s: unsupported chipset\n", __FUNCTION__); @@ -686,6 +692,7 @@ const unsigned char *writearr, unsigned char *readarr) { int a; + int result; int opcode_index = -1; const unsigned char cmd = *writearr; OPCODE *opcode; @@ -728,10 +735,10 @@ count = readcnt; } - if (run_opcode(*opcode, addr, count, data) != 0) { + result = run_opcode(*opcode, addr, count, data); + if (result) { printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); - return 1; } - return 0; + return result; } Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/it87spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -170,7 +170,7 @@ if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", __FUNCTION__, readcnt); - return 1; + return SPI_INVALID_LENGTH; } switch (writecnt) { case 1: @@ -200,7 +200,7 @@ default: printf("%s called with unsupported writecnt %i.\n", __FUNCTION__, writecnt); - return 1; + return SPI_INVALID_LENGTH; } /* * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/sb600spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -114,14 +114,14 @@ if (readcnt > 8) { printf("%s, SB600 SPI controller can not receive %d bytes, " - "which is limited with 8 bytes\n", __func__, readcnt); - return 1; + "it is limited to 8 bytes\n", __func__, readcnt); + return SPI_INVALID_LENGTH; } if (writecnt > 8) { - printf("%s, SB600 SPI controller can not sent %d bytes, " - "which is limited with 8 bytes\n", __func__, writecnt); - return 1; + printf("%s, SB600 SPI controller can not send %d bytes, " + "it is limited to 8 bytes\n", __func__, writecnt); + return SPI_INVALID_LENGTH; } mmio_writeb(cmd, sb600_spibar + 0); Modified: trunk/spi.h =================================================================== --- trunk/spi.h 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/spi.h 2009-07-14 10:26:56 UTC (rev 653) @@ -108,5 +108,6 @@ /* Error codes */ #define SPI_INVALID_OPCODE -2 #define SPI_INVALID_ADDRESS -3 +#define SPI_INVALID_LENGTH -4 #endif /* !__SPI_H__ */ Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/wbsio_spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -154,7 +154,8 @@ if (!mode) { fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n", __func__, writecnt, readcnt); - return 1; + /* Command type refers to the number of bytes read/written. */ + return SPI_INVALID_LENGTH; } OUTB(writearr[0], wbsio_spibase);

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[commit] r652 - trunk
by svn＠flashrom.org 13 Jul '09

13 Jul '09

Author: libv Date: 2009-07-13 14:40:17 +0200 (Mon, 13 Jul 2009) New Revision: 652 Modified: trunk/board_enable.c Log: Board enable for Asus A7V8X. GP51 is attached to both WP# and TBL#. Made possible by the quick response of ITE when asked for information, and the tenacious testing of Glenn Mueller. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Glenn Mueller <mechwarrior5(a)hotmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-12 12:06:18 UTC (rev 651) +++ trunk/board_enable.c 2009-07-13 12:40:17 UTC (rev 652) @@ -832,6 +832,44 @@ } /** + * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A + */ +static int board_asus_a7v8x(const char *name) +{ + uint16_t id, base; + uint8_t tmp; + + /* find the IT8703F */ + w836xx_ext_enter(0x2E); + id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); + w836xx_ext_leave(0x2E); + + if (id != 0x8701) { + fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n"); + return -1; + } + + /* Get the GP567 IO base */ + w836xx_ext_enter(0x2E); + sio_write(0x2E, 0x07, 0x0C); + base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + w836xx_ext_leave(0x2E); + + if (!base) { + fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO" + " Base.\n"); + return -1; + } + + /* Raise GP51. */ + tmp = INB(base); + tmp |= 0x02; + OUTB(tmp, base); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -860,6 +898,7 @@ {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},

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[PATCH] Convert SPI byte program to multicommand
by Carl-Daniel Hailfinger 12 Jul '09

12 Jul '09

Convert SPI byte program to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_byteprogram/flash.h =================================================================== --- flashrom-spi_multicommand_byteprogram/flash.h (Revision 650) +++ flashrom-spi_multicommand_byteprogram/flash.h (Arbeitskopie) @@ -446,9 +446,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); -void spi_byte_program(int address, uint8_t byte); -int spi_nbyte_program(int address, uint8_t *bytes, int len); -int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Index: flashrom-spi_multicommand_byteprogram/it87spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/it87spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/it87spi.c (Arbeitskopie) @@ -232,6 +232,7 @@ result = spi_write_enable(); if (result) return result; + /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { @@ -262,10 +263,7 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Index: flashrom-spi_multicommand_byteprogram/spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/spi.c (Arbeitskopie) @@ -154,21 +154,7 @@ result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -736,39 +722,80 @@ return spi_send_command(sizeof(cmd), 0, cmd, NULL); } -void spi_byte_program(int address, uint8_t byte) +int spi_byte_program(int addr, uint8_t byte) { - const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { - JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - byte - }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send Byte-Program */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_nbyte_program(int address, uint8_t *bytes, int len) { + int result; + /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, (address >> 16) & 0xff, (address >> 8) & 0xff, (address >> 0) & 0xff, }; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + if (!len) { + printf_debug ("%s called for zero-length write\n", __func__); + return 1; + } if (len > 256) { - printf_debug ("%s called for too long a write\n", - __FUNCTION__); + printf_debug ("%s called for too long a write\n", __func__); return 1; } memcpy(&cmd[4], bytes, len); - /* Send Byte-Program */ - return spi_send_command(4 + len, 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_disable_blockprotect(void) @@ -883,7 +910,6 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); Index: flashrom-spi_multicommand_byteprogram/ft2232_spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/ft2232_spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/ft2232_spi.c (Arbeitskopie) @@ -276,7 +276,6 @@ else l = total_size - i; - spi_write_enable(); if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); // spi_write_disable(); chip does this for us Index: flashrom-spi_multicommand_byteprogram/wbsio_spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/wbsio_spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/wbsio_spi.c (Arbeitskopie) @@ -200,11 +200,8 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } - result = spi_write_enable(); - if (result) - return result; for (pos = 0; pos < size; pos++) { - spi_byte_program(pos, buf[pos]); + result = spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Index: flashrom-spi_multicommand_byteprogram/sb600spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/sb600spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/sb600spi.c (Arbeitskopie) @@ -73,10 +73,7 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { spi_disable_blockprotect(); - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, *buf); + result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) printf("."); -- http://www.hailfinger.org/

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[commit] r651 - trunk
by svn＠flashrom.org 12 Jul '09

12 Jul '09

Author: hailfinger Date: 2009-07-12 14:06:18 +0200 (Sun, 12 Jul 2009) New Revision: 651 Modified: trunk/flash.h trunk/ft2232_spi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Convert SPI byte program to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested it on Epia-m700 worked okay. Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/flash.h 2009-07-12 12:06:18 UTC (rev 651) @@ -446,9 +446,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); -void spi_byte_program(int address, uint8_t byte); -int spi_nbyte_program(int address, uint8_t *bytes, int len); -int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/ft2232_spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -276,7 +276,6 @@ else l = total_size - i; - spi_write_enable(); if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); // spi_write_disable(); chip does this for us Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/it87spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -232,6 +232,7 @@ result = spi_write_enable(); if (result) return result; + /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { @@ -262,10 +263,7 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/sb600spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -73,10 +73,7 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { spi_disable_blockprotect(); - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, *buf); + result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) printf("."); Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -154,21 +154,7 @@ result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -736,39 +722,80 @@ return spi_send_command(sizeof(cmd), 0, cmd, NULL); } -void spi_byte_program(int address, uint8_t byte) +int spi_byte_program(int addr, uint8_t byte) { - const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { - JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - byte - }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send Byte-Program */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_nbyte_program(int address, uint8_t *bytes, int len) { + int result; + /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, (address >> 16) & 0xff, (address >> 8) & 0xff, (address >> 0) & 0xff, }; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + if (!len) { + printf_debug ("%s called for zero-length write\n", __func__); + return 1; + } if (len > 256) { - printf_debug ("%s called for too long a write\n", - __FUNCTION__); + printf_debug ("%s called for too long a write\n", __func__); return 1; } memcpy(&cmd[4], bytes, len); - /* Send Byte-Program */ - return spi_send_command(4 + len, 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_disable_blockprotect(void) @@ -883,7 +910,6 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/wbsio_spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -200,11 +200,8 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } - result = spi_write_enable(); - if (result) - return result; for (pos = 0; pos < size; pos++) { - spi_byte_program(pos, buf[pos]); + result = spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); }

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[PATCH] Convert SPI block erase to multicommand
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

Convert SPI block erase to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_blockerase/spi.c =================================================================== --- flashrom-spi_multicommand_blockerase/spi.c (Revision 648) +++ flashrom-spi_multicommand_blockerase/spi.c (Arbeitskopie) @@ -536,17 +536,30 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -566,17 +579,30 @@ */ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -615,18 +641,30 @@ /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE, }; int result; - - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_SE, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send SE (Sector Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ -- http://www.hailfinger.org/

2 3

[commit] r650 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-12 00:26:52 +0200 (Sun, 12 Jul 2009) New Revision: 650 Modified: trunk/spi.c Log: Convert SPI block erase to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Jakob writes: Tested it on my EPIA-m700 and it worked nice. Also double checked that one of the changed functions actually ran. Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 22:17:28 UTC (rev 649) +++ trunk/spi.c 2009-07-11 22:26:52 UTC (rev 650) @@ -536,17 +536,30 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -566,17 +579,30 @@ */ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -615,18 +641,30 @@ /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE, }; int result; - - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send SE (Sector Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */

1 0

[commit] r649 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: uwe Date: 2009-07-12 00:17:28 +0200 (Sun, 12 Jul 2009) New Revision: 649 Modified: trunk/flashrom.8 Log: Fix incorrect manpage (trivial). The flashrom manpage currently says "-w, --write: Write file into flash ROM (default when <file> is specified)". This is no longer true for recent flashrom versions, which only write if you explicitly use the -w option. Proof: $ flashrom coreboot.rom flashrom v0.9.0-r631 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found board "Kontron 986LCD-M", enabling flash write... OK. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. No operations were specified. Thus, fix manpage accordingly. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-07-11 19:39:11 UTC (rev 648) +++ trunk/flashrom.8 2009-07-11 22:17:28 UTC (rev 649) @@ -33,9 +33,7 @@ .BR <file> . .TP .B "\-w, \-\-write <file>" -Write file into flash ROM (default when -.B <file> -is specified). +Write file into flash ROM. .TP .B "\-n, \-\-noverify" Do

1 0

[PATCH] Add Winbond W25X16
by Hector Martin 11 Jul '09

11 Jul '09

Tested probing and reading only. The chip ID was already in flashchips.h. Signed-off-by: Hector Martin <hector(a)marcansoft.com> --- flashrom/flashchips.c (revision 645) +++ flashrom/flashchips.c (working copy) @@ -2795,6 +2795,22 @@ { .vendor = "Winbond", + .name = "W25x16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25X16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W29C011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, -- Hector Martin (hector(a)marcansoft.com) Public Key: http://www.marcansoft.com/marcan.asc

2 1

[commit] r648 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 21:39:11 +0200 (Sat, 11 Jul 2009) New Revision: 648 Modified: trunk/flashchips.c Log: Add Winbond W25X16. Tested probing and reading only. The chip ID was already in flashchips.h. Signed-off-by: Hector Martin <hector(a)marcansoft.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-11 19:28:36 UTC (rev 647) +++ trunk/flashchips.c 2009-07-11 19:39:11 UTC (rev 648) @@ -2795,6 +2795,22 @@ { .vendor = "Winbond", + .name = "W25x16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25X16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W29C011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID,

1 0

[PATCH] Convert SPI chip erase to multicommand
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

Convert SPI chip erase to use the multicommand infrastructure. This breaks ICH/VIA SPI. The good news is that once VIA/SPI are converted to multicommand, a lot of hacks can disappear. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_chiperase/spi.c =================================================================== --- flashrom-spi_multicommand_chiperase/spi.c (Revision 645) +++ flashrom-spi_multicommand_chiperase/spi.c (Arbeitskopie) @@ -417,21 +417,34 @@ int spi_chip_erase_60(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_60_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_60 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -449,21 +462,34 @@ int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_C7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. -- http://www.hailfinger.org/

2 4

[commit] r647 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 21:28:36 +0200 (Sat, 11 Jul 2009) New Revision: 647 Modified: trunk/spi.c Log: Convert SPI chip erase to use the multicommand infrastructure. Once the ICH/VIA SPI driver is converted to multicommand, a lot of hacks can disappear. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 18:05:42 UTC (rev 646) +++ trunk/spi.c 2009-07-11 19:28:36 UTC (rev 647) @@ -61,12 +61,30 @@ int spi_send_multicommand(struct spi_command *spicommands) { - int res = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !res) { - res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + int ret = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !ret) { + ret = spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); + /* This awful hack needs to be replaced with a multicommand + * capable ICH/VIA SPI driver. + */ + if ((ret == SPI_INVALID_OPCODE) && + ((spicommands->writearr[0] == JEDEC_WREN) || + (spicommands->writearr[0] == JEDEC_EWSR))) { + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_ICH9: + case SPI_CONTROLLER_VIA: + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + ret = 0; + default: + break; + } + } + spicommands++; } - return res; + return ret; } static int spi_rdid(unsigned char *readarr, int bytes) @@ -417,21 +435,34 @@ int spi_chip_erase_60(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_60_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_60 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -449,21 +480,34 @@ int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_C7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared.

1 0

test
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

test the list configuration

1 0

[commit] r646 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 20:05:42 +0200 (Sat, 11 Jul 2009) New Revision: 646 Modified: trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/it87spi.c Log: Add an optional flash port parameter for IT87* SPI controllers in standalone programmer mode. If the parameter is set, the IT87* SPI driver will set the I/O base port of the IT87* SPI controller interface to the port specified in the parameter. Usage: flashrom -p it87spi=port=0x820 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flash.h 2009-07-11 18:05:42 UTC (rev 646) @@ -479,6 +479,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); /* it87spi.c */ +extern char *it87opts; extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flashrom.8 2009-07-11 18:05:42 UTC (rev 646) @@ -184,6 +184,14 @@ .BR nic3com , .BR satasii . .sp +The it87spi has an optional parameter which will set the I/O base port of the +IT87* SPI controller interface to the port specified in the parameter. +For that you have to use the +.B "flashrom -p it87spi=port=portnum" +syntax where +.B portnum +is an I/O port number which must be a multiple of 8. +.sp The ft2232spi has an optional parameter specifying the controller type and interface/port it should support. For that you have to use the .B "flashrom -p ft2232spi=model,port=interface" Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flashrom.c 2009-07-11 18:05:42 UTC (rev 646) @@ -647,6 +647,8 @@ pcidev_bdf = strdup(optarg + 8); } else if (strncmp(optarg, "it87spi", 7) == 0) { programmer = PROGRAMMER_IT87SPI; + if (optarg[7] == '=') + it87opts = strdup(optarg + 8); } else if (strncmp(optarg, "ft2232spi", 9) == 0) { programmer = PROGRAMMER_FT2232SPI; if (optarg[9] == '=') Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/it87spi.c 2009-07-11 18:05:42 UTC (rev 646) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> * Copyright (C) 2008 coresystems GmbH * @@ -24,12 +24,14 @@ */ #include <string.h> +#include <stdlib.h> #include "flash.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +char *it87opts = NULL; uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; @@ -56,6 +58,7 @@ static uint16_t find_ite_spi_flash_port(uint16_t port) { uint8_t tmp = 0; + char *portpos = NULL; uint16_t id, flashport = 0; enter_conf_mode_ite(port); @@ -77,6 +80,9 @@ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); printf("LPC write to serial flash %sabled\n", (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ /* If any serial flash segment is enabled, enable writing. */ if ((tmp & 0xe) && (!(tmp & 1 << 4))) { printf("Enabling LPC write to serial flash\n"); @@ -89,6 +95,17 @@ flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); printf("Serial flash port 0x%04x\n", flashport); + if (it87opts && !strlen(it87opts)) { + free(it87opts); + it87opts = NULL; + } + if (it87opts && (portpos = strstr(it87opts, "port="))) { + portpos += 5; + flashport = strtol(portpos, (char **)NULL, 0); + printf("Forcing serial flash port 0x%04x\n", flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } } exit_conf_mode_ite(port); return flashport; @@ -206,10 +223,11 @@ } /* Page size is usually 256 bytes */ -static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) +static int it8716f_spi_page_program(struct flashchip *flash, int block, uint8_t *buf) { int i; int result; + chipaddr bios = flash->virtual_memory; result = spi_write_enable(); if (result) @@ -217,7 +235,7 @@ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { - bios[256 * block + i] = buf[256 * block + i]; + chip_writeb(buf[256 * block + i], bios + 256 * block + i); } OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. @@ -288,8 +306,7 @@ it8716f_spi_chip_write_1(flash, buf); } else { for (i = 0; i < total_size / 256; i++) { - it8716f_spi_page_program(i, buf, - (uint8_t *)flash->virtual_memory); + it8716f_spi_page_program(flash, i, buf); } }

1 0

[PATCH] Add SPI multicommand infrastructure
by Carl-Daniel Hailfinger 10 Jul '09

10 Jul '09

Add SPI multicommand infrastructure. Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand/flash.h =================================================================== --- flashrom-spi_multicommand/flash.h (Revision 643) +++ flashrom-spi_multicommand/flash.h (Arbeitskopie) @@ -350,7 +350,7 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* nic3com.c */ @@ -372,7 +372,7 @@ #define FTDI_FT4232H 0x6011 extern char *ft2232spi_param; int ft2232_spi_init(void); -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -414,14 +414,22 @@ SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, }; +struct spi_command { + unsigned int writecnt; + unsigned int readcnt; + const unsigned char *writearr; + unsigned char *readarr; +}; + extern enum spi_controller spi_controller; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(struct spi_command *spicommands); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -465,7 +473,7 @@ /* ichspi.c */ int ich_init_opcodes(void); -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); @@ -476,14 +484,14 @@ void exit_conf_mode_ite(uint16_t port); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); @@ -582,7 +590,7 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); Index: flashrom-spi_multicommand/it87spi.c =================================================================== --- flashrom-spi_multicommand/it87spi.c (Revision 643) +++ flashrom-spi_multicommand/it87spi.c (Arbeitskopie) @@ -141,7 +141,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; Index: flashrom-spi_multicommand/spi.c =================================================================== --- flashrom-spi_multicommand/spi.c (Revision 643) +++ flashrom-spi_multicommand/spi.c (Arbeitskopie) @@ -32,25 +32,25 @@ void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { switch (spi_controller) { case SPI_CONTROLLER_IT87XX: - return it8716f_spi_command(writecnt, readcnt, writearr, + return it8716f_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_SB600: - return sb600_spi_command(writecnt, readcnt, writearr, readarr); + return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_WBSIO: - return wbsio_spi_command(writecnt, readcnt, writearr, readarr); + return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_FT2232: - return ft2232_spi_command(writecnt, readcnt, writearr, readarr); + return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_DUMMY: - return dummy_spi_command(writecnt, readcnt, writearr, readarr); + return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -59,13 +59,23 @@ return 1; } +int spi_send_multicommand(struct spi_command *spicommands) +{ + int res = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !res) { + res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return res; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; printf_debug("RDID returned"); @@ -81,14 +91,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -102,14 +112,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); } if (ret) return ret; @@ -123,7 +133,7 @@ int result; /* Send WREN (Write Enable) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -150,7 +160,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -292,7 +302,7 @@ /* SB600 uses a different way to read status register. */ return sb600_read_status_register(); } else { - ret = spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) printf_debug("RDSR failed!\n"); } @@ -419,7 +429,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -451,7 +461,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -492,7 +502,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -522,7 +532,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -572,7 +582,7 @@ if (result) return result; /* Send SE (Sector Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -609,7 +619,7 @@ int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -641,7 +651,7 @@ { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -655,7 +665,7 @@ }; /* Send Byte-Program */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); } int spi_nbyte_program(int address, uint8_t *bytes, int len) @@ -676,7 +686,7 @@ memcpy(&cmd[4], bytes, len); /* Send Byte-Program */ - return spi_command(4 + len, 0, cmd, NULL); + return spi_send_command(4 + len, 0, cmd, NULL); } int spi_disable_blockprotect(void) @@ -712,7 +722,7 @@ }; /* Send Read */ - return spi_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(sizeof(cmd), len, cmd, bytes); } /* @@ -855,13 +865,13 @@ result = spi_write_enable(); if (result) return result; - spi_command(6, 0, w, NULL); + spi_send_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; - spi_command(3, 0, w, NULL); + spi_send_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } Index: flashrom-spi_multicommand/ft2232_spi.c =================================================================== --- flashrom-spi_multicommand/ft2232_spi.c (Revision 643) +++ flashrom-spi_multicommand/ft2232_spi.c (Arbeitskopie) @@ -193,7 +193,7 @@ return 0; } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -298,7 +298,7 @@ exit(1); } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { fprintf(stderr, "FT2232 SPI support was not compiled in\n"); Index: flashrom-spi_multicommand/wbsio_spi.c =================================================================== --- flashrom-spi_multicommand/wbsio_spi.c (Revision 643) +++ flashrom-spi_multicommand/wbsio_spi.c (Arbeitskopie) @@ -90,7 +90,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-spi_multicommand/dummyflasher.c =================================================================== --- flashrom-spi_multicommand/dummyflasher.c (Revision 643) +++ flashrom-spi_multicommand/dummyflasher.c (Arbeitskopie) @@ -141,7 +141,7 @@ return; } -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-spi_multicommand/sb600spi.c =================================================================== --- flashrom-spi_multicommand/sb600spi.c (Revision 643) +++ flashrom-spi_multicommand/sb600spi.c (Arbeitskopie) @@ -52,7 +52,7 @@ unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -103,7 +103,7 @@ ; } -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Index: flashrom-spi_multicommand/ichspi.c =================================================================== --- flashrom-spi_multicommand/ichspi.c (Revision 643) +++ flashrom-spi_multicommand/ichspi.c (Arbeitskopie) @@ -682,7 +682,7 @@ return rc; } -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int a; -- http://www.hailfinger.org/

2 2

[commit] r645 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 23:08:55 +0200 (Fri, 10 Jul 2009) New Revision: 645 Modified: trunk/dummyflasher.c trunk/flash.h trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Add SPI multicommand infrastructure. Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/dummyflasher.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ return; } -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/flash.h 2009-07-10 21:08:55 UTC (rev 645) @@ -350,7 +350,7 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* nic3com.c */ @@ -372,7 +372,7 @@ #define FTDI_FT4232H 0x6011 extern char *ft2232spi_param; int ft2232_spi_init(void); -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -414,14 +414,22 @@ SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, }; +struct spi_command { + unsigned int writecnt; + unsigned int readcnt; + const unsigned char *writearr; + unsigned char *readarr; +}; + extern enum spi_controller spi_controller; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(struct spi_command *spicommands); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -465,7 +473,7 @@ /* ichspi.c */ int ich_init_opcodes(void); -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); @@ -476,14 +484,14 @@ void exit_conf_mode_ite(uint16_t port); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); @@ -582,7 +590,7 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ft2232_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -193,7 +193,7 @@ return 0; } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -298,7 +298,7 @@ exit(1); } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { fprintf(stderr, "FT2232 SPI support was not compiled in\n"); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ichspi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -682,7 +682,7 @@ return rc; } -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int a; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/it87spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/sb600spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -52,7 +52,7 @@ unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -103,7 +103,7 @@ ; } -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -32,25 +32,25 @@ void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { switch (spi_controller) { case SPI_CONTROLLER_IT87XX: - return it8716f_spi_command(writecnt, readcnt, writearr, + return it8716f_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_SB600: - return sb600_spi_command(writecnt, readcnt, writearr, readarr); + return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_WBSIO: - return wbsio_spi_command(writecnt, readcnt, writearr, readarr); + return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_FT2232: - return ft2232_spi_command(writecnt, readcnt, writearr, readarr); + return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_DUMMY: - return dummy_spi_command(writecnt, readcnt, writearr, readarr); + return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -59,13 +59,23 @@ return 1; } +int spi_send_multicommand(struct spi_command *spicommands) +{ + int res = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !res) { + res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return res; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; printf_debug("RDID returned"); @@ -81,14 +91,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -102,14 +112,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); } if (ret) return ret; @@ -123,7 +133,7 @@ int result; /* Send WREN (Write Enable) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -150,7 +160,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -292,7 +302,7 @@ /* SB600 uses a different way to read status register. */ return sb600_read_status_register(); } else { - ret = spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) printf_debug("RDSR failed!\n"); } @@ -419,7 +429,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -451,7 +461,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -492,7 +502,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -522,7 +532,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -572,7 +582,7 @@ if (result) return result; /* Send SE (Sector Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -609,7 +619,7 @@ int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -641,7 +651,7 @@ { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -655,7 +665,7 @@ }; /* Send Byte-Program */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); } int spi_nbyte_program(int address, uint8_t *bytes, int len) @@ -676,7 +686,7 @@ memcpy(&cmd[4], bytes, len); /* Send Byte-Program */ - return spi_command(4 + len, 0, cmd, NULL); + return spi_send_command(4 + len, 0, cmd, NULL); } int spi_disable_blockprotect(void) @@ -712,7 +722,7 @@ }; /* Send Read */ - return spi_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(sizeof(cmd), len, cmd, bytes); } /* @@ -855,13 +865,13 @@ result = spi_write_enable(); if (result) return result; - spi_command(6, 0, w, NULL); + spi_send_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; - spi_command(3, 0, w, NULL); + spi_send_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/wbsio_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -90,7 +90,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i;

1 0

[commit] r644 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 22:19:48 +0200 (Fri, 10 Jul 2009) New Revision: 644 Modified: trunk/Makefile Log: Change tarball compression from gzip to bzip2. Set the user and group of all files to root for tar versions which support it. Add explanatory comments for supporting that feature with other tar versions. Use LC_ALL instead of LANG everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-07-08 14:50:36 UTC (rev 643) +++ trunk/Makefile 2009-07-10 20:19:48 UTC (rev 644) @@ -58,7 +58,7 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LANG=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) +SVNVERSION := $(shell LC_ALL=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) VERSION := 0.9.0-r$(SVNVERSION) @@ -67,10 +67,15 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") +FEATURE_CFLAGS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") -FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +FEATURE_LIBS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +# TAROPTIONS reduces information leakage from the packager's system. +# If other tar programs support command line arguments for setting uid/gid of +# stored files, they can be handled here as well. +TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") + %.o: %.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< @@ -137,9 +142,9 @@ @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ tarball: export - @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @tar cjf $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 -C $(EXPORTDIR)/ $(TAROPTIONS) flashrom-$(VERSION)/ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) - @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 .PHONY: all clean distclean dep compiler pciutils features export tarball

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Re: [flashrom] [Patch] superiotool: Add IT8703F support.
by Glenn Mueller 09 Jul '09

09 Jul '09

here it is. > Date: Thu, 9 Jul 2009 18:36:59 +0200 > To: coreboot(a)coreboot.org > CC: mechwarrior5(a)hotmail.com > Subject: [Patch] superiotool: Add IT8703F support. > From: libv(a)skynet.be > > Glenn, can you run this on your Asus A7V8X and attach the output? > > Thanks, > > Luc Verhaegen. _________________________________________________________________ Lauren found her dream laptop. Find the PC that’s right for you. http://www.microsoft.com/windows/choosepc/?ocid=ftp_val_wl_290

1 0

[Patch] Flag bad read/write on W39V040B.
by Luc Verhaegen 08 Jul '09

08 Jul '09

I found an extra chip on a k8m890 board i got off of ebay which was completely fubar. If there's a taker in euroland who wants to spend time on this, just give me a holler. Luc Verhaegen.

2 2

[commit] r643 - trunk
by svn＠flashrom.org 08 Jul '09

08 Jul '09

Author: libv Date: 2009-07-08 16:50:36 +0200 (Wed, 08 Jul 2009) New Revision: 643 Modified: trunk/flashchips.c Log: W39V040B: Flag Erase/Write as bad. Chip has now been properly tested in both my Jetway J7F5M and my EPIA-SP (known good board). Erase and write fail. Mark these operations as bad until i or someone else have time to fix this. Reported by Arvid Brodin <arvidb(a)kth.se>. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> M flashchips.c Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-06 22:58:46 UTC (rev 642) +++ trunk/flashchips.c 2009-07-08 14:50:36 UTC (rev 643) @@ -2881,7 +2881,7 @@ .model_id = W_39V040B, .total_size = 512, .page_size = 64*1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR | TEST_BAD_ERASE | TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec,

1 0

Flashrom does not work with J7F5M
by Arvid Brodin 07 Jul '09

07 Jul '09

Hi. I tested flashrom on my Jetway J7F5M motherboard. # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA CX700", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. No operations were specified. So probing seems to work ok, as do reading. Writing, however, does not work - the image on the flash chip remains unchanged (had a sweaty moment after the FAILED message before I had read the chip again and diffed it against the backed-up original image!). The "Protect flash part" option in BIOS is set to Disabled (I also tried Enabled, just to be sure). Is there any hope on getting flashrom support for this card? The AWDFLASH.EXE utility recommended for flashing by Jetway is "only" some sixty thousand bytes - any hints on reverse engineering this? The computer is head-, FD- and CDR-less and runs linux, so it's a chore to flash it with the d**n DOS utility... -- Arvid

2 7

https://www.ohloh.net/p/flashrom
by Luc Verhaegen 07 Jul '09

07 Jul '09

Go claim your contributions :) Luc Verhaegen.

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Re: [flashrom] Abit IP35 needs board enable.
by Luc Verhaegen 06 Jul '09

06 Jul '09

On Mon, Jul 06, 2009 at 08:18:32PM +0100, Richie Ward wrote: > Oh and I hope i used right program :) Is this ok? > > > Found Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e > > Register dump: > > idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f > > val ff a0 23 ff 00 4c 00 00 ff 50 00 7c c0 0a 01 00 ff > > def 00 a0 NA ff 00 MM 00 MM RR 50 00 00 RR e2 21 00 00 > > LDN 0x00 (Floppy) > > idx 30 60 61 70 74 f0 f1 f2 f4 f5 > > val 00 00 00 00 04 0e 00 ff 00 00 > > def 01 03 f0 06 02 8e 00 ff 00 00 > > LDN 0x01 (Parallel port) > > idx 30 60 61 70 74 f0 > > val 00 00 00 00 04 38 > > def 01 03 78 07 04 3f > > LDN 0x02 (COM1) > > idx 30 60 61 70 f0 > > val 00 00 00 00 00 > > def 01 03 f8 04 00 > > LDN 0x03 (COM2) > > idx 30 60 61 70 f0 f1 > > val 00 00 00 00 00 00 > > def 01 02 f8 03 00 00 > > LDN 0x05 (Keyboard) > > idx 30 60 61 62 63 70 72 f0 > > val 01 00 60 00 64 01 0c 80 > > def 01 00 60 00 64 01 0c 83 > > LDN 0x06 (Serial peripheral interface) > > idx 30 62 63 > > val 00 ff ff > > def 00 00 00 > > LDN 0x07 (GPIO 6) > > idx 30 f4 f5 f6 f7 > > val 07 ff ff ff ff > > def 00 ff 00 00 00 > > LDN 0x08 (WDTO#, PLED) > > idx 30 f5 f6 f7 > > val 00 ff 00 ff > > def 00 00 00 00 > > LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5) > > idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe > > val 0e ff 01 00 ff ff ff ff e3 ff 01 ff e3 00 00 c0 ff 20 00 00 > > def 00 ff 00 00 ff 00 00 00 00 00 00 ff 00 00 00 ff 00 00 00 00 > > LDN 0x0a (ACPI) > > idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe > > val 00 00 00 00 f0 04 00 00 1c 10 09 00 7d 00 00 00 08 00 > > def 00 00 01 00 ff 08 00 RR 1c 00 RR RR 7c 00 00 00 00 00 > > LDN 0x0b (Hardware monitor) > > idx 30 60 61 70 f0 f1 f2 > > val 01 02 90 02 81 ff 81 > > def 00 00 00 00 81 00 00 > > LDN 0x0c (PECI, SST) > > idx e0 e1 e2 e3 e4 e5 e8 f1 fe ff > > val 10 52 48 48 48 00 01 48 00 00 > > def 00 48 48 48 48 00 00 48 00 00 Yeah, looking through this now. Luc Verhaegen.

2 4

[commit] r642 - trunk
by svn＠flashrom.org 06 Jul '09

06 Jul '09

Author: libv Date: 2009-07-07 00:58:46 +0200 (Tue, 07 Jul 2009) New Revision: 642 Modified: trunk/board_enable.c Log: Board enable for Abit IP35. Raise GPIO 16 on ICH9R LPC Interface. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Richie Ward <RichieS(a)GMail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-04 15:10:41 UTC (rev 641) +++ trunk/board_enable.c 2009-07-06 22:58:46 UTC (rev 642) @@ -806,6 +806,32 @@ } /** + * Suited for Abit IP35: Intel P35 + ICH9R. + */ +static int board_abit_ip35(const char *name) +{ + struct pci_dev *dev; + uint16_t base; + uint8_t tmp; + + dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } + + /* get LPC GPIO base */ + base = pci_read_long(dev, 0x48) & 0x0000FFC0; + + /* Raise GPIO 16 */ + tmp = INB(base + 0x0E); + tmp |= 0x01; + OUTB(tmp, base + 0x0E); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -828,6 +854,7 @@ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2},

1 0

Abit IP35 needs board enable.
by Luc Verhaegen 06 Jul '09

06 Jul '09

Thanks to uwe for having the foresight of asking RichW on irc what his email was. lspci -vnn attached. Suggested matches: 2 port sata controller: 0x8086, 0x2926, 0x147b, 0x1084 marvell gigabit ethernet: 0x11ab, 0x4364, 0x147b, 0x1084 Board enable requires: a gpio line on the superio to be altered. logical device: 0x06 0xF0, 0xF1, 0xF2 then all get &= ~0x02 Richard, please provide the output of: superio -Vd so we can identify your superio completely and correctly. Luc Verhaegen.

2 2

Dashix, superio output
by Glenn Mueller 06 Jul '09

06 Jul '09

there is my superio output.The chip was not found, luc said this was still helpful though (sorry about replying directly to you I thought it would come straight to the mailing list). The chip is numbered ITE8703F-A _________________________________________________________________ Windows Live™: Keep your life in sync. http://windowslive.com/explore?ocid=TXT_TAGLM_WL_BR_life_in_synch_062009

1 0

Dashix from irc files
by Glenn Mueller 05 Jul '09

05 Jul '09

Hey guys hey are all the files you had me make (lspci output and such) and the bios that is on the board currently attempting to flash. let me know if you need anything else. _________________________________________________________________ Windows Live™: Keep your life in sync. http://windowslive.com/explore?ocid=TXT_TAGLM_WL_BR_life_in_synch_062009

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[commit] r641 - trunk
by svn＠flashrom.org 04 Jul '09

04 Jul '09

Author: uwe Date: 2009-07-04 17:10:41 +0200 (Sat, 04 Jul 2009) New Revision: 641 Modified: trunk/board_enable.c trunk/print.c Log: Add more URLs and board notes, fix a typo (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-03 23:51:19 UTC (rev 640) +++ trunk/board_enable.c 2009-07-04 15:10:41 UTC (rev 641) @@ -830,10 +830,10 @@ /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8-MX SE", board_asus_a7v8x_mx}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", board_biostar_p4m80_m4}, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-07-03 23:51:19 UTC (rev 640) +++ trunk/print.c 2009-07-04 15:10:41 UTC (rev 641) @@ -298,7 +298,7 @@ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, - { "Advantech", "PCM-5820", "http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8&…" }, + { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, @@ -324,7 +324,7 @@ { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, - { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100_Build_Tutorial" }, + { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, @@ -332,22 +332,22 @@ { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, - { "MSI", "MS-6570 (K7N2)", NULL }, - { "MSI", "MS-7065", NULL }, + { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, + { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, - { "MSI", "MS-7236 (945PL Neo3)", "http://global.msi.com.tw/index.php?func=prodmbspec&maincat_no=1&cat2_no=&ca…" }, - { "MSI", "MS-7255 (P4M890M)", "http://us.msi.com/product/p_spec.asp?model=P4M890M" }, - { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, + { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, + { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, + { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" }, { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm" }, { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm" }, { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm" }, - { "RCA", "RM4100", "http://www.settoplinux.org" }, + { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, - { "Thomson", "IP1000", "http://www.settoplinux.org" }, + { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610" }, { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html" }, @@ -366,7 +366,7 @@ { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597" }, { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566" }, { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605" }, - { "Tyan", "S5377", "http://www.tyan.com/product_board_detail.aspx?pid=601" }, + { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…" }, { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, @@ -377,8 +377,8 @@ { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, /* Verified working boards that DO need write-enables. */ - { "Acorp", "6A815EPD", NULL }, - { "agami", "Aruma", NULL }, + { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, + { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, @@ -389,7 +389,7 @@ { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, - { "GIGABYTE", "GA-2761GXDK", NULL }, + { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, @@ -398,25 +398,26 @@ { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "HP", "DL145 G3", NULL }, - { "IBM", "x3455", NULL }, - { "Intel", "D201GLY", NULL }, + { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…" }, + { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html" }, + { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm" }, { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, - { "MSI", "MS-6590 (KT4 Ultra)", NULL }, - { "MSI", "MS-6702E (K8T Neo2-F)",NULL }, + { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msicomputer.com/product/p_spec.asp?model=KT4_Ultra&class=mb" }, + { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msicomputer.com/product/p_spec.asp?model=K8T_Neo2-F&class=mb" }, { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, - { "MSI", "MS-7046", NULL }, - { "MSI", "MS-7135 (K8N Neo3)", NULL }, + { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, + { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=170&maincat_no=1" }, { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA M/MII/...", NULL }, - { "VIA", "EPIA SP", NULL }, - { "VIA", "PC3500G", NULL }, - + { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-MII link for now */ + { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ + { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, + { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, + /* Verified non-working boards (for now). */ { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, { "ASUS", "M3N78 Pro", "http://www.asus.com/product.aspx?P_ID=DVvm9CU0G1bCC4gp" }, @@ -427,10 +428,10 @@ { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/" }, { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, - { "DFI", "855GME-MGF", NULL }, + { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…" }, { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, - { "MSI", "MS-6178", NULL }, - { "MSI", "MS-7260 (K9N Neo)", "http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1" }, + { "MSI", "MS-6178", "http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no…" }, + { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255" }, { "PCCHIPS", "M537DMA33", "http://motherboards.mbarron.net/models/pcchips/m537dma.htm" }, { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English" }, { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/" }, @@ -447,7 +448,7 @@ { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, - { "IBM/Lenovo", "240", NULL }, + { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, { NULL, NULL, 0 }, }; @@ -465,6 +466,7 @@ { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, /* Verified non-working boards (for now). */ + { "ASUS", "M3N78 Pro", "SPI flash translation seems to be done in the NVIDIA MCP78 southbridge, but we don't have MCP78 datasheets." }, { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, @@ -473,7 +475,7 @@ /* Verified non-working laptops (for now). */ { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, - { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer." }, + { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },

1 0

[commit] r640 - trunk
by svn＠flashrom.org 03 Jul '09

03 Jul '09

Author: uwe Date: 2009-07-04 01:51:19 +0200 (Sat, 04 Jul 2009) New Revision: 640 Modified: trunk/print.c Log: Some flashrom printing changes: - Also print URLs of boards with board-enables. - Mark known-bad operations for chips red in the wiki. - Clarifiy a wiki message a bit. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-07-03 17:12:05 UTC (rev 639) +++ trunk/print.c 2009-07-03 23:51:19 UTC (rev 640) @@ -239,7 +239,7 @@ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ -semi-automatically generated by pasting '''flashrom -z''' output.<br />\ +generated by pasting '''flashrom -z''' output.<br />\ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ @@ -596,8 +596,9 @@ static void wiki_helper2(const char *heading, int cols) { - int i, j, boardcount = 0, color = 1; + int i, j, k, boardcount = 0, color = 1; struct board_pciid_enable *b; + const struct board_info_url *u = boards_url; for (b = board_pciid_enables; b->vendor_name != NULL; b++) boardcount++; @@ -612,9 +613,13 @@ if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) color = !color; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " - "%s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", - b[i].vendor_name, b[i].board_name, + k = url(b[i].vendor_name, b[i].board_name); + + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " + "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", + b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", + (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, + (k != -1 && u[k].url) ? "]" : "", (b[i].lb_vendor) ? "-m " : "—", (b[i].lb_vendor) ? b[i].lb_vendor : "", (b[i].lb_vendor) ? ":" : "", @@ -646,6 +651,7 @@ { int i = 0, c = 1, chipcount = 0; struct flashchip *f, *old = NULL; + uint32_t t; for (f = flashchips; f->name != NULL; f++) chipcount++; @@ -663,14 +669,19 @@ if (old != NULL && strcmp(old->vendor, f->vendor)) c = !c; + t = f->tested; printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, f->total_size, flashbuses_to_text(f->bustype), - ((f->tested & TEST_OK_PROBE) ? "OK" : (c) ? "?2" : "?"), - ((f->tested & TEST_OK_READ) ? "OK" : (c) ? "?2" : "?"), - ((f->tested & TEST_OK_ERASE) ? "OK" : (c) ? "?2" : "?"), - ((f->tested & TEST_OK_WRITE) ? "OK" : (c) ? "?2" : "?")); + (t & TEST_OK_PROBE) ? "OK" : + (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_READ) ? "OK" : + (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_ERASE) ? "OK" : + (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_WRITE) ? "OK" : + (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); /* Split table into three columns. */ if (i >= (chipcount / 3 + 1)) {

1 0

[commit] r639 - trunk
by svn＠flashrom.org 03 Jul '09

03 Jul '09

Author: uwe Date: 2009-07-03 19:12:05 +0200 (Fri, 03 Jul 2009) New Revision: 639 Modified: trunk/board_enable.c trunk/flashchips.c trunk/print.c Log: Mark the following boards as working: - VIA EPIA-M700 (reported by Jakob Bornecrantz <wallbraker(a)gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html - GIGABYTE GA-EX58-UD4P (reported by Warren Turkal <wt(a)penguintechs.org>) http://www.coreboot.org/pipermail/coreboot/2009-June/050199.html Mark as non-working: - ASUS Eee PC 701 4G (reported by Uwe Hermann <uwe(a)hermann-uwe.de>) There seems to be some SPI flash translation layer, likey done by the embedded controller on the laptop (ENE KB3310). The BIOS chip in this Eee PC model is Winbond 25X40VSIG btw. More info: http://beta.ivancover.com/wiki/index.php/Eee_PC_Research Mark this chip as tested: - ST M25P40 (reported by Jakob Bornecrantz <wallbraker(a)gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html Other: - Make the "Albatron PM266A" board detection print "Albatron PM266A*" as this enable will actually work for other PM266A* boards according to libv. However, the code was actually tested on "Albatron PM266A Pro". - Add some more board URLs / notes. - s/BioStar/Biostar/ as per vendor website. - Fix typo in print.c: s/A7V8-MX SE/A7V8X-MX SE/. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-01 00:02:23 UTC (rev 638) +++ trunk/board_enable.c 2009-07-03 17:12:05 UTC (rev 639) @@ -297,7 +297,7 @@ } /** - * Suited for EPoX EP-8K5A2 and Albatron PM266A. + * Suited for EPoX EP-8K5A2 and Albatron PM266A Pro. */ static int board_epox_ep_8k5a2(const char *name) { @@ -636,7 +636,7 @@ /** * Suited for: - * - BioStar P4M80-M4: Intel P4 + VIA P4M800 + VT8237 + * - Biostar P4M80-M4: Intel P4 + VIA P4M800 + VT8237 * - GIGABYTE GA-7VT600: AMD K7 + VIA KT600 + VT8237 */ static int board_biostar_p4m80_m4(const char *name) @@ -830,13 +830,13 @@ /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "BioStar", "P4M80-M4", board_biostar_p4m80_m4}, + {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", board_biostar_p4m80_m4}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, @@ -910,6 +910,7 @@ { "GIGABYTE", "GA-6ZMA", }, { "GIGABYTE", "GA-7ZM", }, { "GIGABYTE", "GA-EP35-DS3L", }, + { "GIGABYTE", "GA-EX58-UD4P", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, { "MSI", "MS-6570 (K7N2)", }, @@ -950,6 +951,7 @@ { "Tyan", "S5397", }, { "VIA", "EPIA-EX15000G", }, { "VIA", "EPIA-LN", }, + { "VIA", "EPIA-M700", }, { "VIA", "EPIA-NX15000G", }, { "VIA", "NAB74X0", }, { "VIA", "pc2500e", }, @@ -996,6 +998,7 @@ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ { "Acer", "Aspire One", }, + { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-01 00:02:23 UTC (rev 638) +++ trunk/flashchips.c 2009-07-03 17:12:05 UTC (rev 639) @@ -2289,7 +2289,7 @@ .model_id = ST_M25P40, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-07-01 00:02:23 UTC (rev 638) +++ trunk/print.c 2009-07-03 17:12:05 UTC (rev 639) @@ -328,6 +328,7 @@ { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, + { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, @@ -369,6 +370,7 @@ { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, + { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…" }, { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp" }, @@ -377,34 +379,34 @@ /* Verified working boards that DO need write-enables. */ { "Acorp", "6A815EPD", NULL }, { "agami", "Aruma", NULL }, - { "Albatron", "PM266A", NULL }, + { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, - { "ASUS", "A7V8-MX SE", NULL }, + { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, - { "ASUS", "P5A", NULL }, - { "BioStar", "P4M80-M4", NULL }, + { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, + { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, - { "EPoX", "EP-8K5A2", NULL }, - { "EPoX", "EP-BX3", NULL }, + { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, + { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, { "GIGABYTE", "GA-2761GXDK", NULL }, - { "GIGABYTE", "GA-7VT600", NULL }, + { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78G-DS3H", NULL }, - { "GIGABYTE", "GA-MA78GM-S2H", NULL }, + { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ + { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "HP", "DL145 G3", NULL }, { "IBM", "x3455", NULL }, { "Intel", "D201GLY", NULL }, - { "IWILL", "DK8-HTX", NULL }, + { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, - { "Mitac", "6513WU", NULL }, + { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, { "MSI", "MS-6590 (KT4 Ultra)", NULL }, { "MSI", "MS-6702E (K8T Neo2-F)",NULL }, - { "MSI", "MS-6712 (KT4V)", NULL }, + { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, { "MSI", "MS-7046", NULL }, { "MSI", "MS-7135 (K8N Neo3)", NULL }, { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, @@ -441,7 +443,9 @@ /* Verified non-working laptops (for now). */ { "Acer", "Aspire One", NULL }, + { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, + { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", NULL }, @@ -469,7 +473,9 @@ /* Verified non-working laptops (for now). */ { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, + { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, + { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, { NULL, NULL, 0 },

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[commit] r638 - trunk
by svn＠flashrom.org 30 Jun '09

30 Jun '09

Author: hailfinger Date: 2009-07-01 02:02:23 +0200 (Wed, 01 Jul 2009) New Revision: 638 Modified: trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/ft2232_spi.c Log: ft2232_spi: Allow runtime selection of FT2232H vs. FT4232H and interface A vs. B. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-30 12:41:00 UTC (rev 637) +++ trunk/flash.h 2009-07-01 00:02:23 UTC (rev 638) @@ -368,6 +368,9 @@ extern struct pcidev_status satas_sii[]; /* ft2232_spi.c */ +#define FTDI_FT2232H 0x6010 +#define FTDI_FT4232H 0x6011 +extern char *ft2232spi_param; int ft2232_spi_init(void); int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-06-30 12:41:00 UTC (rev 637) +++ trunk/flashrom.8 2009-07-01 00:02:23 UTC (rev 638) @@ -183,6 +183,23 @@ Currently the following programmers support this mechanism: .BR nic3com , .BR satasii . +.sp +The ft2232spi has an optional parameter specifying the controller type and +interface/port it should support. For that you have to use the +.B "flashrom -p ft2232spi=model,port=interface" +syntax where +.B model +can be any of +.B 2232H 4232H +and +.B interface +can be any of +.B A +.BR B . +The default model is +.B 4232H +and the default interface is +.BR B . .TP .B "\-h, \-\-help" Show a help text and exit. Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-30 12:41:00 UTC (rev 637) +++ trunk/flashrom.c 2009-07-01 00:02:23 UTC (rev 638) @@ -649,10 +649,12 @@ programmer = PROGRAMMER_IT87SPI; } else if (strncmp(optarg, "ft2232spi", 9) == 0) { programmer = PROGRAMMER_FT2232SPI; - } else if (strncmp(optarg, "serprog", 7) == 0) { - programmer = PROGRAMMER_SERPROG; - if (optarg[7] == '=') - serprog_param = strdup(optarg + 8); + if (optarg[9] == '=') + ft2232spi_param = strdup(optarg + 10); + } else if (strncmp(optarg, "serprog", 7) == 0) { + programmer = PROGRAMMER_SERPROG; + if (optarg[7] == '=') + serprog_param = strdup(optarg + 8); } else { printf("Error: Unknown programmer.\n"); exit(1); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-06-30 12:41:00 UTC (rev 637) +++ trunk/ft2232_spi.c 2009-07-01 00:02:23 UTC (rev 638) @@ -22,9 +22,12 @@ #include <stdint.h> #include <string.h> #include <stdlib.h> +#include <ctype.h> #include "flash.h" #include "spi.h" +char *ft2232spi_param = NULL; + #if FT2232_SPI_SUPPORT == 1 #include <ftdi.h> @@ -71,24 +74,56 @@ struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; unsigned char port_val = 0; + char *portpos = NULL; + int ft2232_type = FTDI_FT4232H; + enum ftdi_interface ft2232_interface = INTERFACE_B; - if (ftdi_init(ftdic) < 0) { fprintf(stderr, "ftdi_init failed\n"); return EXIT_FAILURE; } - // f = ftdi_usb_open(ftdic, 0x0403, 0x6010); // FT2232 - f = ftdi_usb_open(ftdic, 0x0403, 0x6011); // FT4232 + if (ft2232spi_param && !strlen(ft2232spi_param)) { + free(ft2232spi_param); + ft2232spi_param = NULL; + } + if (ft2232spi_param) { + if (strstr(ft2232spi_param, "2232")) + ft2232_type = FTDI_FT2232H; + if (strstr(ft2232spi_param, "4232")) + ft2232_type = FTDI_FT4232H; + portpos = strstr(ft2232spi_param, "port="); + if (portpos) { + portpos += 5; + switch (toupper(*portpos)) { + case 'A': + ft2232_interface = INTERFACE_A; + break; + case 'B': + ft2232_interface = INTERFACE_B; + break; + default: + fprintf(stderr, "Invalid interface specified, " + "using default.\n"); + } + } + free(ft2232spi_param); + } + printf_debug("Using device type %s ", + (ft2232_type == FTDI_FT2232H) ? "2232H" : "4232H"); + printf_debug("interface %s\n", + (ft2232_interface == INTERFACE_A) ? "A" : "B"); + f = ftdi_usb_open(ftdic, 0x0403, ft2232_type); + if (f < 0 && f != -5) { fprintf(stderr, "Unable to open ftdi device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); exit(-1); } - if (ftdi_set_interface(ftdic, INTERFACE_B) < 0) { - fprintf(stderr, "Unable to select FT2232 channel B: %s\n", + if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { + fprintf(stderr, "Unable to select interface: %s\n", ftdic->error_str); }

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Re: [flashrom] Compatibility: Thinkpad x200 / Intel ICH9M-E / Macronix MX25L6405
by Michael Stapelberg 29 Jun '09

29 Jun '09

Hi Carl-Daniel, * [22.06.09 13:22]: > > Found chip "Macronix MX25L6405" (8192 KB) at physical address 0xff800000. > This result was committed in flashrom revision 622. > Could you please retry reading with latest flashrom? It should either > throw an error or give you correct output. Here we go: $ sudo ./flashrom -r bios.copy flashrom v0.9.0-r636 No coreboot table found. Found chipset "Intel ICH9M-E", enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Macronix MX25L6405" (8192 KB, SPI) at physical address 0xff800000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Reading flash... done. The output is definitely wrong, the file bios.copy contains: 00000000 5a a5 f0 0f 01 00 04 04 06 02 10 02 20 01 00 00 |Z........... ...| 00000010 14 00 30 00 00 00 00 00 00 00 00 00 ff ff ff ff |..0.............| 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00000040 00 00 00 00 00 06 ff 07 01 00 f5 05 f6 05 f7 05 |................| 00000050 f8 05 ff 05 ff ff ff ff ff ff ff ff ff ff ff ff |................| 00000060 00 00 1b 1a 00 00 0d 0c 18 02 08 08 ff ff ff ff |................| 00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00000100 88 64 18 00 0f 01 00 00 ff ff ff ff ff ff ff ff |.d..............| 00000110 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00000200 78 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |x...............| 00000210 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00000ee0 c2 20 17 00 05 20 05 20 ef 30 17 00 05 20 05 20 |. ... . .0... . | 00000ef0 1f 48 00 00 15 20 15 20 ff ff ff ff ee 06 00 00 |.H... . ........| 00000f00 37 55 52 35 31 32 57 57 ff ff ff ff ff ff ff ff |7UR512WW........| 00000f10 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00001000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| * 00800000 Best regards, Michael

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Welcome to flashrom@flashrom.org!
by Carl-Daniel Hailfinger 29 Jun '09

29 Jun '09

Flashrom has grown up and it is time to set it free. Giving flashrom its own mailing list flashrom(a)flashrom.org and IRC channel irc.freenode.net/#flashrom will help flashrom become an independent project with its own community. Of course, flashrom is still part of the ever-growing family of coreboot related projects and will continue to use the coreboot project infrastructure. Godspeed, flashrom!

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