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[commit] r739 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: hailfinger Date: 2009-10-01 15:16:32 +0200 (Thu, 01 Oct 2009) New Revision: 739 Modified: trunk/sb600spi.c trunk/spi.c Log: Introduce proper error checking for SPI programming. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-10-01 13:15:01 UTC (rev 738) +++ trunk/sb600spi.c 2009-10-01 13:16:32 UTC (rev 739) @@ -48,9 +48,9 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; + int i; int total_size = flash->total_size * 1024; - int result; + int result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -63,10 +63,10 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { - result = spi_byte_program(i, *buf); + result = spi_nbyte_program(i, buf, 1); if (result) { - // spi_byte_program reported the error for us already - printf_debug("... continuing anyway.\n"); + fprintf(stderr, "Write error!\n"); + return result; } /* wait program complete. */ @@ -76,7 +76,7 @@ ; } printf(" done.\n"); - return rc; + return result; } static void reset_internal_fifo_pointer(void) Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-10-01 13:15:01 UTC (rev 738) +++ trunk/spi.c 2009-10-01 13:16:32 UTC (rev 739) @@ -970,7 +970,7 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; + int i, result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -981,7 +981,9 @@ } printf("done.\n"); for (i = 0; i < total_size; i++) { - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); + if (result) + return 1; while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); }

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[PATCH] eraseblocks for mx25
by Carl-Daniel Hailfinger 01 Oct '09

01 Oct '09

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> someone else please commit. Index: flashrom-eraseblocks_mx25/flashchips.c =================================================================== --- flashrom-eraseblocks_mx25/flashchips.c (Revision 719) +++ flashrom-eraseblocks_mx25/flashchips.c (Arbeitskopie) @@ -44,6 +44,11 @@ * .probe = Probe function * .probe_timing = Probe function delay * .erase = Chip erase function + * .block_erasers[] = Array of erase layouts and erase functions + * { + * .eraseblocks[] = Array of { blocksize, blockcount } + * .block_erase = Block erase function + * } * .write = Chip write function * .read = Chip read function */ @@ -1235,20 +1240,16 @@ { .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_52, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1274,16 +1275,13 @@ { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 2} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1304,6 +1302,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1320,6 +1337,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1336,6 +1372,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1352,6 +1407,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + }, { + .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D/MX25L1635D */ + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, Index: flashrom-eraseblocks_mx25/flashchips.h =================================================================== --- flashrom-eraseblocks_mx25/flashchips.h (Revision 719) +++ flashrom-eraseblocks_mx25/flashchips.h (Arbeitskopie) @@ -251,7 +251,7 @@ * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ +#define MX_25L512 0x2010 /* Same as MX25V512 */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 #define MX_25L4005 0x2013 /* MX25L4005{,A} */ -- http://www.hailfinger.org/

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[commit] r738 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: hailfinger Date: 2009-10-01 15:15:01 +0200 (Thu, 01 Oct 2009) New Revision: 738 Modified: trunk/flashchips.c trunk/flashchips.h Log: Add comments about the meaning of block erase related struct flashchip members. Cosmetics: Place curly brackets on a common line. Add MX25V512 as alias name to MX25L512. Add MX25V8005 as alias name to MX25L8005. Add erase block definitions for MX25L2005, MX25L4005, MX25L8005, MX25L1605 and change their status to TEST_OK_PRW where applicable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-30 18:29:55 UTC (rev 737) +++ trunk/flashchips.c 2009-10-01 13:15:01 UTC (rev 738) @@ -44,6 +44,11 @@ * .probe = Probe function * .probe_timing = Probe function delay * .erase = Chip erase function + * .block_erasers[] = Array of erase layouts and erase functions + * { + * .eraseblocks[] = Array of { blocksize, blockcount } + * .block_erase = Block erase function + * } * .write = Chip write function * .read = Chip read function */ @@ -1235,20 +1240,16 @@ { .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_52, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1274,16 +1275,13 @@ { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 2} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1303,7 +1301,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1316,10 +1333,29 @@ .model_id = MX_25L4005, .total_size = 512, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1332,10 +1368,29 @@ .model_id = MX_25L8005, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1348,10 +1403,29 @@ .model_id = MX_25L1605, .total_size = 2048, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + }, { + .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, Modified: trunk/flashchips.h =================================================================== --- trunk/flashchips.h 2009-09-30 18:29:55 UTC (rev 737) +++ trunk/flashchips.h 2009-10-01 13:15:01 UTC (rev 738) @@ -251,11 +251,11 @@ * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ +#define MX_25L512 0x2010 /* Same as MX25V512 */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 #define MX_25L4005 0x2013 /* MX25L4005{,A} */ -#define MX_25L8005 0x2014 +#define MX_25L8005 0x2014 /* Same as MX25V8005 */ #define MX_25L1605 0x2015 /* MX25L1605{,A,D} */ #define MX_25L3205 0x2016 /* MX25L3205{,A} */ #define MX_25L6405 0x2017 /* MX25L3205{,D} */

1 0

Re: [flashrom] 'ERASED FAILED!' messages for ICH2 / SST49LF0002A/B
by Allan Bjorklund 30 Sep '09

30 Sep '09

On Wed Sep 30 5:03 , Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> sent: > >> Output of superiotool -dV: >> >> superiotool r >> > >Can you tell us which superiotool revision this is? Straight from >subversion or from some distribution package? In theory, superiotool >should have printed a revision number. It was from this web page, which I assume is the current svn snapshot: http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool I chose the zip archive link near the bottom of the page to retrieve the source. --Allan

2 1

[PATCH] Add -p gfxnvidia for flashing NVIDIA graphics cards
by Uwe Hermann 30 Sep '09

30 Sep '09

See patch. Please do NOT try write/erase on any important cards yet, it doesn't seem to fully work properly yet and you could "brick" your card. I tested a "RIVA TNT2 Model 64/Model 64 Pro", which successfully identified and read a Winbond W29C011 chip, but erase and write behaved incorrect and I finally bricked the card. Will look into recovery soon (likely will work via software I assume, no hardware hacking strictly required I think/hope, we'll see). As for the list of supported cards: I have no idea which of those may work (i.e. have the same flash programming interface), maybe none, maybe all of them (and lots more NVIDIA cards), we'll see as soon as others test more cards. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 3

[commit] r737 - trunk
by svn＠flashrom.org 30 Sep '09

30 Sep '09

Author: uwe Date: 2009-09-30 20:29:55 +0200 (Wed, 30 Sep 2009) New Revision: 737 Added: trunk/gfxnvidia.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/pcidev.c Log: Add initial support for flashing some NVIDIA graphics cards. The new option is '-p gfxnvidia', rest of the interface is as usual. I tested a successful identify and read on a "RIVA TNT2 Model 64/Model 64 Pro" card for now, erase and write did NOT work properly so far! Please do not attempt to write/erase cards yet, unless you can recover! In addition to the NVIDIA handling code it was required to call programmer_shutdown() in a lot more places, otherwise the graphics card will be disabled in the init function, but never enabled again as the shutdown function is not called. The shutdown handling may be changed to use atexit() later. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/Makefile 2009-09-30 18:29:55 UTC (rev 737) @@ -74,6 +74,9 @@ # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes +# Always enable NVIDIA graphics cards for now. +CONFIG_GFXNVIDIA ?= yes + # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes @@ -107,6 +110,11 @@ OBJS += nic3com.o endif +ifeq ($(CONFIG_GFXNVIDIA), yes) +FEATURE_CFLAGS += -D'GFXNVIDIA_SUPPORT=1' +OBJS += gfxnvidia.o +endif + ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' OBJS += satasii.o Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flash.h 2009-09-30 18:29:55 UTC (rev 737) @@ -88,6 +88,9 @@ #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif +#if GFXNVIDIA_SUPPORT == 1 + PROGRAMMER_GFXNVIDIA, +#endif #if DRKAISER_SUPPORT == 1 PROGRAMMER_DRKAISER, #endif @@ -437,6 +440,13 @@ uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +/* gfxnvidia.c */ +int gfxnvidia_init(void); +int gfxnvidia_shutdown(void); +void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); +uint8_t gfxnvidia_chip_readb(const chipaddr addr); +extern struct pcidev_status gfx_nvidia[]; + /* drkaiser.c */ int drkaiser_init(void); int drkaiser_shutdown(void); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flashrom.8 2009-09-30 18:29:55 UTC (rev 737) @@ -140,6 +140,8 @@ .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp +.BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)" +.sp .BR "* drkaiser" " (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards)" .sp .BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controllers)" @@ -180,6 +182,7 @@ .sp Currently the following programmers support this mechanism: .BR nic3com , +.BR gfxnvidia , .BR satasii . .sp The it87spi programmer has an optional parameter which will set the I/O base Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flashrom.c 2009-09-30 18:29:55 UTC (rev 737) @@ -92,6 +92,25 @@ }, #endif +#if GFXNVIDIA_SUPPORT == 1 + { + .name = "gfxnvidia", + .init = gfxnvidia_init, + .shutdown = gfxnvidia_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + #if DRKAISER_SUPPORT == 1 { .name = "drkaiser", @@ -824,6 +843,9 @@ #if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); #endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs(gfx_nvidia); +#endif #if DRKAISER_SUPPORT == 1 print_supported_pcidevs(drkaiser_pcidev); #endif @@ -868,6 +890,7 @@ for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) printf(" %s", flashes[i]->name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); + programmer_shutdown(); exit(1); } else if (!flashes[0]) { printf("No EEPROM/flash device found.\n"); @@ -890,6 +913,7 @@ return read_flash(flashes[0], filename); } // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } @@ -935,12 +959,14 @@ if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } if (!filename && !erase_it) { printf("Error: No filename specified.\n"); // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } @@ -956,6 +982,7 @@ fprintf(stderr, "Erase is not working on this chip. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -963,11 +990,14 @@ } if (erase_flash(flash)) { emergency_help_message(); + programmer_shutdown(); return 1; } } else if (read_it) { - if (read_flash(flash, filename)) + if (read_flash(flash, filename)) { + programmer_shutdown(); return 1; + } } else { struct stat image_stat; @@ -976,6 +1006,7 @@ "and erase is needed for write. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -985,6 +1016,7 @@ fprintf(stderr, "Write is not working on this chip. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -992,14 +1024,17 @@ } if ((image = fopen(filename, "r")) == NULL) { perror(filename); + programmer_shutdown(); exit(1); } if (fstat(fileno(image), &image_stat) != 0) { perror(filename); + programmer_shutdown(); exit(1); } if (image_stat.st_size != flash->total_size * 1024) { fprintf(stderr, "Error: Image size doesn't match\n"); + programmer_shutdown(); exit(1); } @@ -1008,6 +1043,7 @@ fclose(image); if (numbytes != size) { fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); + programmer_shutdown(); return 1; } } @@ -1022,12 +1058,14 @@ printf("Writing flash chip... "); if (!flash->write) { fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n"); + programmer_shutdown(); return 1; } ret = flash->write(flash, buf); if (ret) { fprintf(stderr, "FAILED!\n"); emergency_help_message(); + programmer_shutdown(); return 1; } else { printf("COMPLETE.\n"); Added: trunk/gfxnvidia.c =================================================================== --- trunk/gfxnvidia.c (rev 0) +++ trunk/gfxnvidia.c 2009-09-30 18:29:55 UTC (rev 737) @@ -0,0 +1,104 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define PCI_VENDOR_ID_NVIDIA 0x10de + +uint8_t *nvidia_bar; + +struct pcidev_status gfx_nvidia[] = { + {0x10de, 0x0010, PCI_NT, "NVIDIA", "Mutara V08 [NV2]" }, + {0x10de, 0x0018, PCI_NT, "NVIDIA", "RIVA 128" }, + {0x10de, 0x0020, PCI_NT, "NVIDIA", "RIVA TNT" }, + {0x10de, 0x0028, PCI_NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, + {0x10de, 0x0029, PCI_NT, "NVIDIA", "RIVA TNT2 Ultra" }, + {0x10de, 0x002c, PCI_NT, "NVIDIA", "Vanta/Vanta LT" }, + {0x10de, 0x002d, PCI_OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, + {0x10de, 0x00a0, PCI_NT, "NVIDIA", "Aladdin TNT2" }, + {0x10de, 0x0100, PCI_NT, "NVIDIA", "GeForce 256" }, + {0x10de, 0x0101, PCI_NT, "NVIDIA", "GeForce DDR" }, + {0x10de, 0x0103, PCI_NT, "NVIDIA", "Quadro" }, + {0x10de, 0x0110, PCI_NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0111, PCI_NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0112, PCI_NT, "NVIDIA", "GeForce2 GO" }, + {0x10de, 0x0113, PCI_NT, "NVIDIA", "Quadro2 MXR" }, + {0x10de, 0x0150, PCI_NT, "NVIDIA", "GeForce2 GTS/Pro" }, + {0x10de, 0x0151, PCI_NT, "NVIDIA", "GeForce2 GTS" }, + {0x10de, 0x0152, PCI_NT, "NVIDIA", "GeForce2 Ultra" }, + {0x10de, 0x0153, PCI_NT, "NVIDIA", "Quadro2 Pro" }, + {0x10de, 0x0200, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0201, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0202, PCI_NT, "NVIDIA", "GeForce 3 nFX Ultra" }, + {0x10de, 0x0203, PCI_NT, "NVIDIA", "Quadro 3 DDC" }, + + {}, +}; + +int gfxnvidia_init(void) +{ + uint32_t reg32; + + get_io_perms(); + + io_base_addr = pcidev_init(PCI_VENDOR_ID_NVIDIA, PCI_BASE_ADDRESS_0, + gfx_nvidia, programmer_param); + io_base_addr += 0x300000; + printf("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); + + /* Allow access to flash interface (will disable screen). */ + reg32 = pci_read_long(pcidev_dev, 0x50); + reg32 &= ~(1 << 0); + pci_write_long(pcidev_dev, 0x50, reg32); + + nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int gfxnvidia_shutdown(void) +{ + uint32_t reg32; + + /* Disallow access to flash interface (and re-enable screen). */ + reg32 = pci_read_long(pcidev_dev, 0x50); + reg32 |= (1 << 0); + pci_write_long(pcidev_dev, 0x50, reg32); + + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) +{ + mmio_writeb(val, nvidia_bar + addr); +} + +uint8_t gfxnvidia_chip_readb(const chipaddr addr) +{ + return mmio_readb(nvidia_bar + addr); +} Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/pcidev.c 2009-09-30 18:29:55 UTC (rev 737) @@ -28,7 +28,8 @@ struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs) +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, + struct pcidev_status *devs) { int i; uint32_t addr; @@ -37,12 +38,16 @@ if (dev->device_id != devs[i].device_id) continue; - /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ + /* + * Don't use dev->base_addr[x] (as value for 'bar'), won't + * work on older libpci. + */ addr = pci_read_long(dev, bar) & ~0x03; printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, dev->vendor_id, - dev->device_id, dev->bus, dev->dev, dev->func); + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); if (devs[i].status == PCI_NT) { printf("===\nThis PCI device is UNTESTED. Please " @@ -57,7 +62,8 @@ return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf) +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, + struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; char *msg = NULL;

1 0

motherboard report: GA-MA770T-UD3P
by Kevin Sopp 28 Sep '09

28 Sep '09

Flashing the bios on the Gigabyte GA-MA770T-UD3P worked out of the box.

2 2

[commit] r736 - trunk
by svn＠flashrom.org 28 Sep '09

28 Sep '09

Author: hailfinger Date: 2009-09-28 15:15:16 +0200 (Mon, 28 Sep 2009) New Revision: 736 Added: trunk/bitbang_spi.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.c Log: This is the bitbanging SPI driver infrastructure. If you want support for a particular piece of hardware, just fill in a few functions in spi_bitbang_master_table. That's it. On top of this, the RayeR SPI flasher should be supportable in ~20 LOC. Tested, trace looks OK. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/Makefile 2009-09-28 13:15:16 UTC (rev 736) @@ -68,6 +68,9 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes +# Bitbanging SPI infrastructure is not used yet. +CONFIG_BITBANG_SPI ?= no + # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -94,6 +97,11 @@ endif endif +ifeq ($(CONFIG_BITBANG_SPI), yes) +FEATURE_CFLAGS += -D'BITBANG_SPI_SUPPORT=1' +OBJS += bitbang_spi.o +endif + ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o Added: trunk/bitbang_spi.c =================================================================== --- trunk/bitbang_spi.c (rev 0) +++ trunk/bitbang_spi.c 2009-09-28 13:15:16 UTC (rev 736) @@ -0,0 +1,161 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" +#include "spi.h" + +/* Length of half a clock period in usecs */ +int bitbang_half_period = 0; + +enum spi_bitbang_master spi_bitbang_master = SPI_BITBANG_INVALID; + +const struct spi_bitbang_master_entry spi_bitbang_master_table[] = { + {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ +}; + +const int spi_bitbang_master_count = ARRAY_SIZE(spi_bitbang_master_table); + +void bitbang_set_cs(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_cs(val); +} + +void bitbang_set_sck(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_sck(val); +} + +void bitbang_set_mosi(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_mosi(val); +} + +int bitbang_get_miso(void) +{ + return spi_bitbang_master_table[spi_bitbang_master].get_miso(); +} + +int bitbang_spi_init(void) +{ + bitbang_set_cs(1); + bitbang_set_sck(0); + buses_supported = CHIP_BUSTYPE_SPI; + return 0; +} + +uint8_t bitbang_spi_readwrite_byte(uint8_t val) +{ + uint8_t ret = 0; + int i; + + for (i = 7; i >= 0; i--) { + bitbang_set_mosi((val >> i) & 1); + programmer_delay(bitbang_half_period); + bitbang_set_sck(1); + ret <<= 1; + ret |= bitbang_get_miso(); + programmer_delay(bitbang_half_period); + bitbang_set_sck(0); + } + return ret; +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *bufout = NULL; + static unsigned char *bufin = NULL; + static int oldbufsize = 0; + int bufsize = max(writecnt + readcnt, 260); + int i; + + /* Arbitrary size limitation here. We're only constrained by memory. */ + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + + if (bufsize != oldbufsize) { + bufout = realloc(bufout, bufsize); + if (!bufout) { + fprintf(stderr, "Out of memory!\n"); + if (bufin) + free(bufin); + exit(1); + } + bufin = realloc(bufout, bufsize); + if (!bufin) { + fprintf(stderr, "Out of memory!\n"); + if (bufout) + free(bufout); + exit(1); + } + } + + memcpy(bufout, writearr, writecnt); + /* Shift out 0x00 while reading data. */ + memset(bufout + writecnt, 0x00, readcnt); + /* Make sure any non-read data is 0xff. */ + memset(bufin + writecnt, 0xff, readcnt); + + bitbang_set_cs(0); + for (i = 0; i < readcnt + writecnt; i++) { + bufin[i] = bitbang_spi_readwrite_byte(bufout[i]); + } + programmer_delay(bitbang_half_period); + bitbang_set_cs(1); + programmer_delay(bitbang_half_period); + memcpy(readarr, bufin + writecnt, readcnt); + + return 0; +} + +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64k bytes. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + + printf_debug("total_size is %d\n", total_size); + for (i = 0; i < total_size; i += 256) { + int l, r; + if (i + 256 <= total_size) + l = 256; + else + l = total_size - i; + + if ((r = spi_nbyte_program(i, &buf[i], l))) { + fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); + return 1; + } + + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + /* loop */; + } + + return 0; +} Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/flash.h 2009-09-28 13:15:16 UTC (rev 736) @@ -145,6 +145,21 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); +enum spi_bitbang_master { + SPI_BITBANG_INVALID /* This must always be the last entry. */ +}; + +extern const int spi_bitbang_master_count; + +extern enum spi_bitbang_master spi_bitbang_master; + +struct spi_bitbang_master_entry { + void (*set_cs) (int val); + void (*set_sck) (int val); + void (*set_mosi) (int val); + int (*get_miso) (void); +}; + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { @@ -444,6 +459,14 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +/* bitbang_spi.c */ +extern int bitbang_half_period; +extern const struct spi_bitbang_master_entry spi_bitbang_master_table[]; +int bitbang_spi_init(void); +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); + /* flashrom.c */ extern char *programmer_param; extern int verbose; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/flashrom.c 2009-09-28 13:15:16 UTC (rev 736) @@ -693,6 +693,12 @@ fprintf(stderr, "SPI programmer table miscompilation!\n"); exit(1); } +#if BITBANG_SPI_SUPPORT == 1 + if (spi_bitbang_master_count - 1 != SPI_BITBANG_INVALID) { + fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); + exit(1); + } +#endif setbuf(stdout, NULL); while ((opt = getopt_long(argc, argv, optstring,

1 0

Success: flashing BIOS on MSI K9AG Neo2-Digital (MS-7368)
by christian.ch.heinz＠gmail.com 28 Sep '09

28 Sep '09

Hello flashrom people, here is a quick success report on using flashrom with the MS-7368 (revision 1.0; I don't believe there are any later revisions, but I'm not sure). The exact flashrom version used was v0.9.1, SVN revision r721. In particular, I first upgraded the BIOS from version 1.9 to 1.10 (named 1.A on the MSI website), then downgraded to 1.7 and re-upgraded to 1.8 and finally to 1.10 again, with a reboot following each flashing. I also played around with a few of the flashrom options and everything worked flawlessly OOTB. Some details: # ./flashrom -r ... flashrom v0.9.1-runknown No coreboot table found. Found chipset "AMD SB600", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Reading flash... done. # ./superiotool superiotool r4623 Found Fintek F71882FG/F71883FG (vid=0x3419, id=0x4105) at 0x4e Platform: Linux 2.6.30-ARCH x86_64 AMD Athlon(tm) Dual Core Processor 4850e Probably nothing more to add, except that flashrom absolutely rocks :) Thanks and kudos, ch

2 1

flashrom works with an asus M3A78-EM
by Joshua Roys 28 Sep '09

28 Sep '09

# flashrom -w M3A78-EM-1902.ROM flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... done. Programming flash................................ done. COMPLETE. Verifying flash... VERIFIED. Thanks, Joshua Roys

2 1

3C905CX-TX-M not supported (But flashrom thinks it is).
by Marko Kraljevic 25 Sep '09

25 Sep '09

Hi, the other day I got a 3C905CX-TX-M NIC. I don't have the computer I tested it on up and running right now, but it is non-functional. Flashrom can not detect the AT49BV512 on it. A forced read delivers all 0xFF's, which I assume it is pulling out of the ether. I guess it *could* be blank; It seems unlikely to not autodetect and function on a forced read though. Anyways, this wouldn't be an issue, but the PCI device ID is the same as the 3C905C-TX [dev_id 0x9200] (*iirc - it might be one of the other supported 3C905 NICs*), so flashrom reports it as a supported NIC. I guess there should be a note somewhere, specifying that flashrom doesn't support 3com NICs with the newer, smaller, BGA package ASIC. Here's a photo of the card. On mine the flash is soldered on, but I believe I've seen socketed versions in the past. If they're all soldered on, I guess it doesn't matter much - apart from saving someone the time of soldering on a socket. http://electrontube.org/open/3com_mod/3C905CX-TX-M.jpg I'll try and get that computer back up this weekend and post the output. Mark

3 5

[commit] r735 - trunk
by svn＠flashrom.org 24 Sep '09

24 Sep '09

Author: uwe Date: 2009-09-25 03:31:51 +0200 (Fri, 25 Sep 2009) New Revision: 735 Modified: trunk/print_wiki.c Log: Enable drkaiser programmer support in wiki output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-09-25 01:22:42 UTC (rev 734) +++ trunk/print_wiki.c 2009-09-25 01:31:51 UTC (rev 735) @@ -541,7 +541,7 @@ print_supported_pcidevs_wiki(nics_3com); #endif #if DRKAISER_SUPPORT == 1 - /* FIXME: drkaiser_pcidev is missing here. */ + print_supported_pcidevs_wiki(drkaiser_pcidev); #endif #if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii);

1 0

[commit] r734 - trunk
by svn＠flashrom.org 24 Sep '09

24 Sep '09

Author: uwe Date: 2009-09-25 03:22:42 +0200 (Fri, 25 Sep 2009) New Revision: 734 Modified: trunk/board_enable.c trunk/print.c trunk/print_wiki.c Log: Mark the following boards as OK: - ASUS M3A78-EM (reported by Christian Heinz <christian.ch.heinz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000629.html - MSI MS-7368 (K9AG Neo2-Digital) (reported by Joshua Roys <roysjosh(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000632.html - GIGABYTE GA-MA770T-UD3P (reported by Kevin Sopp <baraclese(a)googlemail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000529.html - Elitegroup P6VAP-A+ Tested by Uwe Hermann <uwe(a)hermann-uwe.de> on hardware. Maximum supported chip size in this board is 256 KB. Small changes in print.c were required to adjust for longer board names. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/board_enable.c 2009-09-25 01:22:42 UTC (rev 734) @@ -1064,6 +1064,7 @@ { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, { "ASUS", "M2V", }, + { "ASUS", "M3A78-EM", }, { "ASUS", "P2B", }, { "ASUS", "P2B-D", }, { "ASUS", "P2B-DS", }, @@ -1075,6 +1076,7 @@ { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, + { "Elitegroup", "P6VAP-A+", }, { "GIGABYTE", "GA-6BXC", }, { "GIGABYTE", "GA-6BXDU", }, { "GIGABYTE", "GA-6ZMA", }, @@ -1083,6 +1085,7 @@ { "GIGABYTE", "GA-EX58-UD4P", }, { "GIGABYTE", "GA-MA78GPM-DS2H", }, { "GIGABYTE", "GA-MA790GP-DS4H", }, + { "GIGABYTE", "GA-MA770T-UD3P", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, { "MSI", "MS-6570 (K7N2)", }, @@ -1091,6 +1094,7 @@ { "MSI", "MS-7236 (945PL Neo3)", }, { "MSI", "MS-7255 (P4M890M)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", }, { "NEC", "PowerMate 2000", }, { "PC Engines", "Alix.1c", }, { "PC Engines", "Alix.2c2", }, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/print.c 2009-09-25 01:22:42 UTC (rev 734) @@ -181,7 +181,7 @@ for (j = 0; j < 25 - strlen(b[i].vendor); j++) printf(" "); printf("%s", b[i].name); - for (j = 0; j < 23 - strlen(b[i].name); j++) + for (j = 0; j < 28 - strlen(b[i].name); j++) printf(" "); printf("\n"); } @@ -196,7 +196,7 @@ boardcount++; printf("\nSupported boards which need write-enable code (total: %d):" - "\n\nVendor: Board: " + "\n\nVendor: Board: " "Required option:\n\n", boardcount); for (i = 0; b[i].vendor_name != NULL; i++) { @@ -204,7 +204,7 @@ for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) printf(" "); printf("%s", b[i].board_name); - for (j = 0; j < 25 - strlen(b[i].board_name); j++) + for (j = 0; j < 30 - strlen(b[i].board_name); j++) printf(" "); if (b[i].lb_vendor != NULL) printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/print_wiki.c 2009-09-25 01:22:42 UTC (rev 734) @@ -119,6 +119,7 @@ { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, { "ASUS", "M2V", "http://asus.com/Product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, + { "ASUS", "M3A78-EM", "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D" }, { "ASUS", "P2B", "http://www.motherboard.cz/mb/asus/P2B.htm" }, { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, @@ -130,6 +131,7 @@ { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, @@ -137,6 +139,7 @@ { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-MA770T-UD3P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, @@ -145,6 +148,7 @@ { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241" }, { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" },

1 0

[commit] r733 - trunk
by svn＠flashrom.org 24 Sep '09

24 Sep '09

Author: uwe Date: 2009-09-25 03:09:18 +0200 (Fri, 25 Sep 2009) New Revision: 733 Modified: trunk/flashchips.c Log: Mark the SST SST49LF003A/B as read-tested. See http://www.coreboot.org/pipermail/coreboot/2009-July/050675.html. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-25 01:05:06 UTC (rev 732) +++ trunk/flashchips.c 2009-09-25 01:09:18 UTC (rev 733) @@ -2132,7 +2132,7 @@ .model_id = SST_49LF003A, .total_size = 384, .page_size = 64 * 1024, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PR, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub,

1 0

[commit] r732 - trunk
by svn＠flashrom.org 24 Sep '09

24 Sep '09

Author: uwe Date: 2009-09-25 03:05:06 +0200 (Fri, 25 Sep 2009) New Revision: 732 Modified: trunk/chipset_enable.c Log: Add chipset support for VIA VT82C596 by adding a PCI ID (trivial). This is successfully tested by me on the Elitegroup P6VAP-A+ board. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-09-23 22:01:33 UTC (rev 731) +++ trunk/chipset_enable.c 2009-09-25 01:05:06 UTC (rev 732) @@ -1046,6 +1046,7 @@ {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},

1 0

actual bios settings
by Bart Swinnen 24 Sep '09

24 Sep '09

Hi Does flashrom normally also reads actual BIOS setting of a board? I'm trying flashrom on IEI Wafer-LX-800 It finds PMC Pm49FL004 device and I can read it. It gives me a 512k bin file. If I write this file to another board of its kind, I still have the actual settings of that board and not the one stored in the board where I had the bin from. Am I missing something? Kind regards Bart Swinnen

3 4

[PATCH] Switch SST49LF004A/B to blockwise erase
by Carl-Daniel Hailfinger 23 Sep '09

23 Sep '09

Switch SST49LF004A/B to block erase, remove the hack which simulated (unsupported) chip erase. Annotate SST49LF004B quirks for TBL#. Add TEST_OK_PRW which is useful when a PREW chip gets a new erase routine. Change a few erase function prototypes to use unsigned int instead of int. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst49lf004b_eraseblocks/flash.h =================================================================== --- flashrom-sst49lf004b_eraseblocks/flash.h (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/flash.h (Arbeitskopie) @@ -225,6 +225,7 @@ #define TEST_OK_WRITE (1 << 3) #define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) #define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) +#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) #define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) #define TEST_OK_MASK 0x0f @@ -596,8 +597,8 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, int blocksize); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size); @@ -657,6 +658,7 @@ /* sst_fwhub.c */ int probe_sst_fwhub(struct flashchip *flash); int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); /* w39v040c.c */ Index: flashrom-sst49lf004b_eraseblocks/jedec.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/jedec.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/jedec.c (Arbeitskopie) @@ -175,7 +175,7 @@ return 0; } -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize) +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; @@ -204,7 +204,7 @@ return 0; } -int erase_block_jedec(struct flashchip *flash, unsigned int block, int blocksize) +int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) { chipaddr bios = flash->virtual_memory; Index: flashrom-sst49lf004b_eraseblocks/flashchips.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/flashchips.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/flashchips.c (Arbeitskopie) @@ -2141,6 +2141,9 @@ }, { + /* Contrary to the data sheet, TBL# on the SST49LF004B affects the top 128kB (instead of 64kB) + * and is only honored for 64k block erase, but not 4k sector erase. + */ .vendor = "SST", .name = "SST49LF004A/B", .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ @@ -2148,10 +2151,23 @@ .model_id = SST_49LF004A, .total_size = 512, .page_size = 64 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ - .erase = erase_sst_fwhub, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_sector_jedec, /* missing unlock */ + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */ + }, + }, .write = write_sst_fwhub, .read = read_memmapped, }, Index: flashrom-sst49lf004b_eraseblocks/sst_fwhub.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/sst_fwhub.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/sst_fwhub.c (Arbeitskopie) @@ -94,7 +94,7 @@ return 1; } -int erase_sst_fwhub_block(struct flashchip *flash, int offset, int page_size) +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size) { uint8_t blockstatus = clear_sst_fwhub_block_lock(flash, offset); -- http://www.hailfinger.org/

2 4

[commit] r731 - trunk
by svn＠flashrom.org 23 Sep '09

23 Sep '09

Author: hailfinger Date: 2009-09-24 00:01:33 +0200 (Thu, 24 Sep 2009) New Revision: 731 Modified: trunk/flash.h trunk/flashchips.c trunk/jedec.c trunk/sst_fwhub.c Log: Switch SST49LF004A/B to block erase, remove the hack which simulated (unsupported) chip erase. Annotate SST49LF004B quirks for TBL#. Add TEST_OK_PRW which is useful when a PREW chip gets a new erase routine. Change a few erase function prototypes to use unsigned int instead of int. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/flash.h 2009-09-23 22:01:33 UTC (rev 731) @@ -225,6 +225,7 @@ #define TEST_OK_WRITE (1 << 3) #define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) #define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) +#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) #define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) #define TEST_OK_MASK 0x0f @@ -596,8 +597,8 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, int blocksize); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size); @@ -657,6 +658,7 @@ /* sst_fwhub.c */ int probe_sst_fwhub(struct flashchip *flash); int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); /* w39v040c.c */ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/flashchips.c 2009-09-23 22:01:33 UTC (rev 731) @@ -2141,6 +2141,9 @@ }, { + /* Contrary to the data sheet, TBL# on the SST49LF004B affects the top 128kB (instead of 64kB) + * and is only honored for 64k block erase, but not 4k sector erase. + */ .vendor = "SST", .name = "SST49LF004A/B", .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ @@ -2151,7 +2154,20 @@ .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ - .erase = erase_sst_fwhub, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_sector_jedec, /* missing unlock */ + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */ + }, + }, .write = write_sst_fwhub, .read = read_memmapped, }, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/jedec.c 2009-09-23 22:01:33 UTC (rev 731) @@ -175,7 +175,7 @@ return 0; } -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize) +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; @@ -204,7 +204,7 @@ return 0; } -int erase_block_jedec(struct flashchip *flash, unsigned int block, int blocksize) +int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) { chipaddr bios = flash->virtual_memory; Modified: trunk/sst_fwhub.c =================================================================== --- trunk/sst_fwhub.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/sst_fwhub.c 2009-09-23 22:01:33 UTC (rev 731) @@ -94,7 +94,7 @@ return 1; } -int erase_sst_fwhub_block(struct flashchip *flash, int offset, int page_size) +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size) { uint8_t blockstatus = clear_sst_fwhub_block_lock(flash, offset);

1 0

[PATCH] Change status of SST49LF020A to TEST_OK_PREW
by Nils 23 Sep '09

23 Sep '09

The attached patch changes the status of the SST49LF020A to TEST_OK_PREW. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> I tested it on the Wyse Winterm S50 see attached test results. Thanks, Nils.

2 1

[commit] r730 - trunk
by svn＠flashrom.org 23 Sep '09

23 Sep '09

Author: hailfinger Date: 2009-09-23 23:58:34 +0200 (Wed, 23 Sep 2009) New Revision: 730 Modified: trunk/flashchips.c Log: Change the status of the SST49LF020A to TEST_OK_PREW. I tested it on the Wyse Winterm S50 see attached test results. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-23 02:09:23 UTC (rev 729) +++ trunk/flashchips.c 2009-09-23 21:58:34 UTC (rev 730) @@ -2244,7 +2244,7 @@ .model_id = SST_49LF020A, .total_size = 256, .page_size = 4 * 1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .erase = erase_49lf040,

1 0

Re: [flashrom] flashrom failure on Shuttle barebone
by Ulf Mehlig 23 Sep '09

23 Sep '09

00:00.0 Memory controller [0580]: nVidia Corporation CK804 Memory Controller [10de:005e] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 5e 00 06 00 b0 00 a3 00 80 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 97 12 36 50 08 e0 e0 01 22 00 11 11 d0 00 00 00 50: 23 06 7f 80 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 00 00 70: 44 44 00 00 d0 09 00 00 00 00 00 00 88 00 00 00 80: 13 ff 88 00 fa 00 00 00 03 00 00 00 61 00 00 00 90: 0e 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation CK804 ISA Bridge [10de:0050] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 50 00 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 97 12 36 50 00 f0 ff fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 01 40 00 00 01 44 00 00 01 48 00 00 00 01 f9 ff 70: 10 00 ff ff 41 00 00 00 00 00 44 19 00 d2 20 01 80: 09 d0 00 12 01 08 00 00 c0 00 00 01 00 00 00 00 90: 00 00 00 00 00 00 00 00 21 64 87 a9 de bc 00 00 a0: 03 00 10 41 00 00 00 00 00 00 00 00 00 00 00 00 b0: 90 02 ef 02 00 00 00 00 00 00 00 00 00 00 00 00 c0: 35 82 80 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 14 10 01 00 00 00 d0 00 80 38 00 00 61 44 44 11 f0: 5a ff 5f bf 00 00 00 c0 10 ff ff ff 00 00 30 07 00:01.1 SMBus [0c05]: nVidia Corporation CK804 SMBus [10de:0052] (rev a2) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 12 Region 0: I/O ports at e400 [size=32] Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus 00: de 10 52 00 01 00 b0 00 a2 00 05 0c 00 00 80 00 10: 01 e4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4c 00 00 41 4c 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0c 01 03 01 40: 97 12 36 50 01 00 02 c0 00 00 00 00 00 00 00 00 50: 01 4c 00 00 41 4c 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005a] (rev a2) (prog-if 10 [OHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at d8204000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 5a 00 07 00 b0 00 a2 10 03 0c 00 00 80 00 10: 00 40 20 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 40: 97 12 36 50 01 00 02 fe 00 00 00 00 00 00 00 00 50: 07 00 00 00 1d 47 40 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 03 0d 30 07 00:02.1 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005b] (rev a3) (prog-if 20 [EHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at feb00000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: de 10 5b 00 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 00 b0 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 40: 97 12 36 50 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 3f 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 e4 00 80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 33 00 11 22 44 00 00 00 ff 03 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 ff ff ff 05 11 30 07 00:06.0 IDE interface [0101]: nVidia Corporation CK804 IDE [10de:0053] (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: AMD_IDE 00: de 10 53 00 05 00 b0 00 a2 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f0 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 97 12 36 50 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 01 00 00 00 00 00 a8 a8 a8 20 2a 00 99 20 60: 00 00 00 c5 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 10 e0 63 33 00 00 02 10 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 ff ff ff 0a 15 30 07 00:07.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0054] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at d800 [size=16] Region 5: Memory at d8202000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 54 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00 20: 01 d8 00 00 00 20 20 d8 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 40: 97 12 36 50 01 00 02 00 00 00 00 00 00 00 00 00 50: 17 00 00 15 00 00 00 00 a8 20 a8 20 66 00 20 20 60: 00 c7 00 c7 51 0c 00 00 08 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 c0 00 a0 4d 1e 00 00 02 04 00 80 c4 2f 90: 00 00 02 08 00 00 00 00 06 00 06 10 00 00 01 01 a0: 50 01 00 7c 00 00 00 00 00 00 00 00 33 bb aa 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 02 a8 d0: 0a 00 02 04 42 00 00 00 00 00 00 00 01 00 00 e0 e0: 0a 00 02 04 42 00 00 00 00 00 00 00 89 32 c1 e0 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 09 46 32 07 00:08.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0055] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c400 [size=16] Region 5: Memory at d8201000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 55 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00 20: 01 c4 00 00 00 10 20 d8 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: de 10 84 cb 01 00 02 00 00 00 00 00 00 00 00 00 50: 17 00 00 15 00 00 00 00 a8 a8 a8 a8 aa 00 99 99 60: 00 00 00 00 51 0c 00 00 08 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 06 00 06 10 00 00 01 01 a0: 50 01 00 00 00 00 00 00 00 00 00 00 33 bb aa 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 02 a8 d0: 0a 00 02 04 42 00 00 00 00 00 00 00 44 61 01 01 e0: 0a 00 02 04 42 00 00 00 00 00 00 00 b1 88 85 00 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 00 00 30 07 00:09.0 PCI bridge [0604]: nVidia Corporation CK804 PCI Bridge [10de:005c] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=32 I/O behind bridge: 0000a000-0000afff Memory behind bridge: d8100000-d81fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR+ BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- 00: de 10 5c 00 07 01 a0 00 a2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 20 a0 a0 80 a2 20: 10 d8 10 d8 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 02 40: 00 00 07 00 01 00 02 00 07 00 00 00 00 00 44 01 50: 00 00 fe 7f 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 02 00 00 02 a0 00 00 00 00 00 00 08 00 00 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Bridge [0680]: nVidia Corporation CK804 Ethernet Controller [10de:0057] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at d8200000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Kernel driver in use: forcedeth 00: de 10 57 00 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 00 20 d8 01 b0 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 01 14 40: 97 12 36 50 01 00 02 fe 00 01 00 00 0a 00 00 10 50: 05 64 84 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0f 00 00 00 08 00 02 a8 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 11 00 00 00 40 ff ff ff 05 25 32 07 00:0b.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x2, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 8, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 21 34 01 03 90: 00 00 41 10 80 0c 40 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 4, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 02 90: 00 00 41 10 00 05 20 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 01 90: 00 00 81 10 00 05 10 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: d8000000-d80fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d7ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 91 91 00 00 20: 00 d8 00 d8 01 d0 f1 d7 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 0e 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 01 35 01 00 90: 00 00 01 11 80 25 08 00 c0 01 40 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 01 00 e4 00 00 00 20 c8 00 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 69 01 61 01 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 e0 00 80 ff ef 00 03 b0 fe 00 80 c0 fe 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 80 00 00 d3 fe 00 c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 20 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 de e0 07 00 de e0 07 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 07 00 00 00 00 00 00 00 42 35 82 13 31 0b 00 00 90: 80 8e 05 38 07 07 7b 3e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 4e 64 12 46 2d 00 00 00 df ef 00 08 ef 63 eb 32 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 68 d0 c8 05 86 52 42 b8 31 c2 ae 86 0c 09 78 09 e0: 20 40 88 32 48 02 18 00 c5 13 13 00 80 09 69 30 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 00 08 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 eb 68 6f 60: bb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1a 22 00 00 80: 00 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 20 82 89 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3f 00 00 20 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 01 a7 0d 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 20 04 57 0c 19 11 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV370 5B60 [Radeon X300 (PCIE)] [1002:5b60] (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. Device [1462:0320] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at 9000 [size=256] Region 2: Memory at d8030000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at d8000000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: radeonfb 00: 02 10 60 5b 07 00 10 00 00 00 00 03 08 00 80 00 10: 08 00 00 d0 01 90 00 00 00 00 03 d8 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 20 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 0c 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 20 03 50: 01 58 02 06 00 00 00 00 10 80 01 00 a0 04 2c 01 60: 10 08 00 00 01 ad 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.1 Display controller [0380]: ATI Technologies Inc RV370 [Radeon X300SE] [1002:5b70] Subsystem: Micro-Star International Co., Ltd. Device [1462:0321] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: Memory at d8020000 (32-bit, non-prefetchable) [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 00: 02 10 70 5b 00 00 10 00 00 00 80 03 08 00 00 00 10: 00 00 02 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 21 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 02 06 00 00 00 00 10 00 01 00 80 04 00 00 60: 00 00 00 00 01 ad 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:06.0 Multimedia audio controller [0401]: VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller [1412:1724] (rev 01) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at a000 [size=32] Region 1: I/O ports at a400 [size=128] Capabilities: [80] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ICE1724 00: 12 14 24 17 05 00 10 02 01 00 01 04 00 20 00 00 10: 01 a0 00 00 01 a4 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:07.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] (rev 80) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at d8100000 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at a800 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: firewire_ohci 00: 06 11 44 30 07 00 10 02 80 10 00 0c 08 20 00 00 10: 00 00 10 d8 01 a8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 44 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 00 20 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 02 e4 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- Dr. Ulf Mehlig · Laboratório de Biologia Vegetal Instituto de Estudos Costeiros (IECOS) Universidade Federal do Pará, Campus Bragança · Brazil ----------------------------------------------------------------------

3 2

[PATCH_v2] Enable flashrom on Wyse Winterm S50.
by Nils 22 Sep '09

22 Sep '09

Enable flashrom on Wyse Winterm S50. On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so flashrom doesn`t detect the cs5536. This patch is adding the cs5536 isa id [1022:2090] for chip detect. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> nils@debian:~/flashrom$ sudo flashrom flashrom v0.9.1-r727 No coreboot table found. Found chipset "AMD CS5536_2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF020A" (256 KB, LPC) at physical address 0xfffc0000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === No operations were specified. nils@debian:~/flashrom$ Nils

2 1

[commit] r729 - trunk
by svn＠flashrom.org 22 Sep '09

22 Sep '09

Author: hailfinger Date: 2009-09-23 04:09:23 +0200 (Wed, 23 Sep 2009) New Revision: 729 Modified: trunk/chipset_enable.c Log: Enable flashrom on Wyse Winterm S50. On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so flashrom doesn`t detect the cs5536. This patch is adding the cs5536 isa id [1022:2090] for chip detect. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-09-23 02:05:12 UTC (rev 728) +++ trunk/chipset_enable.c 2009-09-23 02:09:23 UTC (rev 729) @@ -972,6 +972,7 @@ {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},

1 0

dell s1850
by ron minnich 22 Sep '09

22 Sep '09

Using my GPIO finder posted earlier, I have the gpio needed to enable flashing on the dell. I would like to get a patch together but have not done this mainboard enable thing. I would like to do this in the most-approved manner. Basically need to match the dell mainboard, find the 8086:24d0 bridge, look up a BAR, and twiddle one little gpio line. The northbridge looks like this: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 4a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 34 3e 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 suggestions welcome. ron

2 7

[commit] r728 - trunk
by svn＠flashrom.org 22 Sep '09

22 Sep '09

Author: hailfinger Date: 2009-09-23 04:05:12 +0200 (Wed, 23 Sep 2009) New Revision: 728 Modified: trunk/board_enable.c Log: This enables flashing the Dell S1850 under Linux. This code has been tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-09-18 15:50:56 UTC (rev 727) +++ trunk/board_enable.c 2009-09-23 02:05:12 UTC (rev 728) @@ -569,6 +569,17 @@ } /** + * Suited for the Dell S1850. All parameters except the last one are documented + * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last + * parameter (GPIO number) has to be in the range [16,31] according to said + * Intel Datasheet and was found by exhaustive search. + */ +static int ich5_gpio23_raise(const char *name) +{ + return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); +} + +/** * Suited for MSI MS-7046. */ static int ich6_gpio19_raise(const char *name) @@ -992,6 +1003,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},

1 0

[Patch] Board enable for Shuttle FN25 (SN25P).
by Luc Verhaegen 22 Sep '09

22 Sep '09

1 0

Re: [flashrom] flashrom failure on Shuttle barebone
by Ulf Mehlig 22 Sep '09

22 Sep '09

00:00.0 Memory controller [0580]: nVidia Corporation CK804 Memory Controller [10de:005e] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 5e 00 06 00 b0 00 a3 00 80 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation CK804 ISA Bridge [10de:0050] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 50 00 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 SMBus [0c05]: nVidia Corporation CK804 SMBus [10de:0052] (rev a2) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 12 Region 0: I/O ports at e400 [size=32] Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus 00: de 10 52 00 01 00 b0 00 a2 00 05 0c 00 00 80 00 10: 01 e4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4c 00 00 41 4c 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0c 01 03 01 00:02.0 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005a] (rev a2) (prog-if 10 [OHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at d8204000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 5a 00 07 00 b0 00 a2 10 03 0c 00 00 80 00 10: 00 40 20 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 00:02.1 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005b] (rev a3) (prog-if 20 [EHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at feb00000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: de 10 5b 00 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 00 b0 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 00:06.0 IDE interface [0101]: nVidia Corporation CK804 IDE [10de:0053] (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: AMD_IDE 00: de 10 53 00 05 00 b0 00 a2 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f0 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 00:07.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0054] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at d800 [size=16] Region 5: Memory at d8202000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 54 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00 20: 01 d8 00 00 00 20 20 d8 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 00:08.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0055] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c400 [size=16] Region 5: Memory at d8201000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 55 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00 20: 01 c4 00 00 00 10 20 d8 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 00:09.0 PCI bridge [0604]: nVidia Corporation CK804 PCI Bridge [10de:005c] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=32 I/O behind bridge: 0000a000-0000afff Memory behind bridge: d8100000-d81fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR+ BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- 00: de 10 5c 00 07 01 a0 00 a2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 20 a0 a0 80 a2 20: 10 d8 10 d8 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 02 00:0a.0 Bridge [0680]: nVidia Corporation CK804 Ethernet Controller [10de:0057] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at d8200000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Kernel driver in use: forcedeth 00: de 10 57 00 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 00 20 d8 01 b0 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 01 14 00:0b.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x2, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 8, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 00:0c.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 4, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 00:0d.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 00:0e.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: d8000000-d80fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d7ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 91 91 00 00 20: 00 d8 00 d8 01 d0 f1 d7 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 0e 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV370 5B60 [Radeon X300 (PCIE)] [1002:5b60] (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. Device [1462:0320] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at 9000 [size=256] Region 2: Memory at d8030000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at d8000000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: radeonfb 00: 02 10 60 5b 07 00 10 00 00 00 00 03 08 00 80 00 10: 08 00 00 d0 01 90 00 00 00 00 03 d8 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 20 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 0c 01 00 00 01:00.1 Display controller [0380]: ATI Technologies Inc RV370 [Radeon X300SE] [1002:5b70] Subsystem: Micro-Star International Co., Ltd. Device [1462:0321] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: Memory at d8020000 (32-bit, non-prefetchable) [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 00: 02 10 70 5b 00 00 10 00 00 00 80 03 08 00 00 00 10: 00 00 02 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 21 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00 05:06.0 Multimedia audio controller [0401]: VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller [1412:1724] (rev 01) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at a000 [size=32] Region 1: I/O ports at a400 [size=128] Capabilities: [80] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ICE1724 00: 12 14 24 17 05 00 10 02 01 00 01 04 00 20 00 00 10: 01 a0 00 00 01 a4 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 01 00 00 05:07.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] (rev 80) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at d8100000 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at a800 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: firewire_ohci 00: 06 11 44 30 07 00 10 02 80 10 00 0c 08 20 00 00 10: 00 00 10 d8 01 a8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 44 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 00 20 -- Dr. Ulf Mehlig · Laboratório de Biologia Vegetal Instituto de Estudos Costeiros (IECOS) Universidade Federal do Pará, Campus Bragança · Brazil ----------------------------------------------------------------------

1 0

flashrom failure on Shuttle barebone
by Ulf Mehlig 22 Sep '09

22 Sep '09

I courageously tried to flash my Shuttle xpc SN25P10-H3Ih00-13's bios via flashrom after writing my original bios to a file ("flashrom -r test.img"). Then, I tried to write the most recent flash image provided by Shuttle to the bios, which failed. Writing back the previously saved file failed, too, with a different error message. The machine is still switched on. Of course, _any_ help is appreciated! Ulf ulf-pc:~# flashrom flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. No operations were specified. ulf-pc:~# flashrom -w /tmp/floppy/fn25s02a.bin flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: 0007 at address: 0x00070000 COMPLETE. Verifying flash... VERIFY FAILED at 0x00005455! Expected=0xff, Read=0xaa, failed byte count from 0x00000000-0x0007ffff: 0x50d2 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! ulf-pc:~# flashrom -w test.img flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x0006b000! Expected=0xff, Read=0x00, failed byte count from 0x00060000-0x0006ffff: 0x3e21 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! -- Dr. Ulf Mehlig · Laboratório de Biologia Vegetal Instituto de Estudos Costeiros (IECOS) Universidade Federal do Pará, Campus Bragança · Brazil ----------------------------------------------------------------------

3 2

Patchwork update script
by Carl-Daniel Hailfinger 21 Sep '09

21 Sep '09

Hi, here's the script I'm using to set the status of flashrom patches in patchwork to "Accepted". The web interface only allows you to set the status, but it does not allow you to set a commit ID. With pwclient (part of patchwork) you can do that. My script simply retrieves a patch (-p0) for a given numeric commit ID (without leading r), hashes it with the special patchwork hash (which is somewhat tolerant of context and order changes), then uses pwclient to set the patch status for that hash to "Accepted" and the commit ID to "r$1". If the patch (-p0) can't be found, it retrieves a patch (-p1) for the commit ID. Usage: update-patchwork 1234 You might want to adjust a few paths for coreboot usage and for your local installation. Requirements for this script: - A local patchwork source (or installation) - ~/.pwclientrc (downloaded from the patchwork web interface) Where can you get .pwclientrc? Go to http://patchwork.coreboot.org/project/ and log in. Then click on your preferred project, then click on "project info". There you find: "Sample patchwork client configuration for this project: .pwclientrc." Download .pwclientrc and fill in your patchwork password, then store it in your $HOME. I hope this helps others reduce patchwork maintenance efforts. Regards, Carl-Daniel #!/bin/bash # Install this script as update-patchwork in your $PATH # and call it with the revision number as parameter. test -z "$1" && { echo "No revision provided."; exit 1; } revision="$1" hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/trunk/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo "No matching patch in patchwork found." exit 1 -- http://www.hailfinger.org/

1 0

[PATCH] Fix flashrom memory leaks
by Carl-Daniel Hailfinger 19 Sep '09

19 Sep '09

The pattern of foo = realloc(foo, size); causes a memory leak if realloc fails because realloc does not free foo in case of failure, but foo will be NULL after a failure, so there is no way to access or free the original foo. Fix unchecked [mc]alloc return values as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-memleak/flash.h =================================================================== --- flashrom-memleak/flash.h (Revision 725) +++ flashrom-memleak/flash.h (Arbeitskopie) @@ -323,7 +323,7 @@ void print_supported_chipsets(void); void print_supported_boards(void); void print_supported_pcidevs(struct pcidev_status *devs); -void print_wiki_tables(void); +int print_wiki_tables(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); Index: flashrom-memleak/ft2232_spi.c =================================================================== --- flashrom-memleak/ft2232_spi.c (Revision 725) +++ flashrom-memleak/ft2232_spi.c (Arbeitskopie) @@ -193,14 +193,17 @@ { struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; + unsigned char *newbuf = NULL; int i, ret = 0; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; - buf = realloc(buf, writecnt + readcnt + 100); - if (!buf) { + newbuf = realloc(buf, writecnt + readcnt + 100); + if (!newbuf) { fprintf(stderr, "Out of memory!\n"); + free(buf); + buf = NULL; exit(1); } Index: flashrom-memleak/flashrom.c =================================================================== --- flashrom-memleak/flashrom.c (Revision 725) +++ flashrom-memleak/flashrom.c (Arbeitskopie) @@ -282,9 +282,12 @@ char *strcat_realloc(char *dest, const char *src) { - dest = realloc(dest, strlen(dest) + strlen(src) + 1); - if (!dest) + char *newdest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!newdest) { + free(dest); + fprintf(stderr, "Could not allocate memory!\n"); return NULL; + } strcat(dest, src); return dest; } @@ -459,6 +462,10 @@ printf("Error: No filename specified.\n"); return 1; } + if (!buf) { + fprintf(stderr, "Could not allocate memory!\n"); + exit(1); + } if ((image = fopen(filename, "w")) == NULL) { perror(filename); exit(1); @@ -829,7 +836,8 @@ #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { - print_wiki_tables(); + if (print_wiki_tables()) + exit(1); exit(0); } #endif @@ -944,6 +952,10 @@ size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); + if (!buf) { + fprintf(stderr, "Could not allocate memory!\n"); + exit(1); + } if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { Index: flashrom-memleak/print_wiki.c =================================================================== --- flashrom-memleak/print_wiki.c (Revision 725) +++ flashrom-memleak/print_wiki.c (Arbeitskopie) @@ -353,7 +353,7 @@ printf("\n|}\n\n|}\n"); } -static void wiki_helper(const char *heading, const char *status, +static int wiki_helper(const char *heading, const char *status, int cols, const struct board_info boards[]) { int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; @@ -362,6 +362,10 @@ char *notes = calloc(1, 1); char tmp[900 + 1]; + if (!notes) { + fprintf(stderr, "Could not allocate memory!\n"); + return 1; + } for (b = boards; b->vendor != NULL; b++) boardcount++; @@ -388,6 +392,10 @@ snprintf((char *)&tmp, 900, "<sup>%d</sup> %s<br />\n", 1 + num_notes++, boards_notes[c].note); notes = strcat_realloc(notes, (char *)&tmp); + if (!notes) { + return 1; + } + } else { printf("\n"); } @@ -404,6 +412,8 @@ if (num_notes > 0) printf("\n<small>\n%s</small>\n", notes); free(notes); + + return 0; } static void wiki_helper2(const char *heading, int cols) @@ -447,16 +457,21 @@ printf("\n|}\n\n|}\n"); } -void print_supported_boards_wiki(void) +int print_supported_boards_wiki(void) { printf("%s", board_intro); - wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); + if (wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok)) + return 1; wiki_helper2("Known good (with write-enable code in flashrom)", 3); - wiki_helper("Not supported (yet)", "No", 3, boards_bad); + if (wiki_helper("Not supported (yet)", "No", 3, boards_bad)) + return 1; printf("%s", laptop_intro); - wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); - wiki_helper("Not supported (yet)", "No", 1, laptops_bad); + if (wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok)) + return 1; + if (wiki_helper("Not supported (yet)", "No", 1, laptops_bad)) + return 1; + return 0; } void print_supported_chips_wiki(void) @@ -524,14 +539,15 @@ } } -void print_wiki_tables(void) +int print_wiki_tables(void) { time_t t = time(NULL); printf(wiki_header, ctime(&t), flashrom_version); print_supported_chips_wiki(); print_supported_chipsets_wiki(); - print_supported_boards_wiki(); + if (print_supported_boards_wiki()) + return 1; printf("%s", programmer_section); #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); @@ -543,5 +559,6 @@ print_supported_pcidevs_wiki(satas_sii); #endif printf("\n|}\n"); + return 0; } Index: flashrom-memleak/print.c =================================================================== --- flashrom-memleak/print.c (Revision 725) +++ flashrom-memleak/print.c (Arbeitskopie) @@ -31,25 +31,48 @@ char *flashbuses_to_text(enum chipbustype bustype) { char *ret = calloc(1, 1); + if (!ret) { + fprintf(stderr, "Could not allocate memory!\n"); + return NULL; + } if (bustype == CHIP_BUSTYPE_UNKNOWN) { ret = strcat_realloc(ret, "Unknown,"); + if (!ret) + return NULL; /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ } else if (bustype == CHIP_BUSTYPE_NONSPI) { ret = strcat_realloc(ret, "Non-SPI,"); + if (!ret) + return NULL; } else { - if (bustype & CHIP_BUSTYPE_PARALLEL) + if (bustype & CHIP_BUSTYPE_PARALLEL) { ret = strcat_realloc(ret, "Parallel,"); - if (bustype & CHIP_BUSTYPE_LPC) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_LPC) { ret = strcat_realloc(ret, "LPC,"); - if (bustype & CHIP_BUSTYPE_FWH) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_FWH) { ret = strcat_realloc(ret, "FWH,"); - if (bustype & CHIP_BUSTYPE_SPI) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_SPI) { ret = strcat_realloc(ret, "SPI,"); - if (bustype == CHIP_BUSTYPE_NONE) + if (!ret) + return NULL; + } + if (bustype == CHIP_BUSTYPE_NONE) { ret = strcat_realloc(ret, "None,"); + if (!ret) + return NULL; + } } /* Kill last comma. */ ret[strlen(ret) - 1] = '\0'; -- http://www.hailfinger.org/

4 6

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

Hi Mike, On 18.09.2009 18:55, Spangler, Mike T wrote: > I've corrected my email and am now sending to the group. > Thanks. >> Of course I'd prefer it if you tried to flash coreboot (new name of >> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >> have the factory BIOS around somewhere. Is it the one at >> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >> > > I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice. > So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512 > This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does. >> Hmm ok. I think we have enough docs to iterate through all possible >> board enables. How many of these boards do you have (in case we trash >> the ROM of one of them)? >> > > The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. > Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board. Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by ron minnich 18 Sep '09

18 Sep '09

Note that you could still use coreboot + seabios + gpxe, which works very well here at sandia. That said, an "arima HDAMA" is a changing thing. I suppose they might have added a write enable GPIO at some point. You could use the note I sent to this list recently about how to probe the GPIOs for a write enable. ron

1 0

[RFC] Output and progress bars
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

To librarize flashrom, we have to move away from printf to generic printing functions. I'd like to classify messages into four severity levels: * Error (out of memory, write failed, ...) * Warning (chipset init incomplete, ...) * Notice (chip detected, flashing successful) * Debug I also would like to differentiate between controller related and flashchip related messages. E.g. one might be interested in verbose probing output, but not in full SB600 SPI debugging for every command sent. Since all messages above debug level are shown anyway, this differentiation makes most sense if only applied to debug messages. Suggested set of message functions (all with printk syntax): msg_err msg_warn msg_notice msg_debug_controller msg_debug_flash Progress printing is done with dots, equals, numbers, sometimes with, sometimes without backspace for beautification. Some focus on percentage, others focus on addresses. With a maxval parameter, we can handle policy on a case-by-case basis. Suggested progress bar function: progressbar(int curval, int maxval) Comments appreciated. Regards, Carl-Daniel -- http://www.hailfinger.org/

4 7

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

[bouncing to list] On 18.09.2009 13:47, Carl-Daniel Hailfinger wrote: > Hi Mike, > > was it intentional that you only sent the data to me? It would be great > to have that data on the list. If possible, please forward your mail to > the list so other developers can help as well. > > On 18.09.2009 07:26, Spangler, Mike T wrote: > >> Thanks for getting back to me. David Hendricks has been giving me some >> direction also, but has kind of exhausted his ideas. He suggested that >> I try something around revision 2000, because he thought that he was >> able to flash an ARIMA board successfully with that version. I also >> tried revision 2341 which had references in the Changelog to ARIMA. >> Turns out the results were identical. The results of rev 2000/2341 is >> that it flashes about 99% of the locations on the PLCC correctly. >> Below I will give you some output from the flashrom -w command. Also, >> I've included a comparison between the file I used to write to the >> flash chip and a new file that I reread from the flashed chip. >> > > I analyzed the output and the only difference is that the new flashrom > version detects the problem and the old version ignores it... > > >> First I will give you what you wanted to know. The chip was originally >> factory bios. It was either flashed to LinuxBios with lbflash or with >> a standalone benchtop flasher. I'm trying to flash the chip back to >> factory bios. >> > > Of course I'd prefer it if you tried to flash coreboot (new name of > LinuxBIOS) to these boards, but that's your choice. Anyway, you said you > have the factory BIOS around somewhere. Is it the one at > http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? > > >> Output from superiotool -dV >> >> Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV >> superiotool r >> Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e >> Register dump: >> LDN 0x07 (GPIO) >> idx 30 60 61 70 71 74 75 f0 f1 f2 >> val 00 00 00 00 03 04 04 00 44 01 >> def 00 00 00 00 03 04 04 00 00 00 >> > > Hmm ok. I think we have enough docs to iterate through all possible > board enables. How many of these boards do you have (in case we trash > the ROM of one of them)? > > Regards, > Carl-Daniel > > -- http://www.hailfinger.org/

1 0

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 18 Sep '09

18 Sep '09

Carl - I've corrected my email and am now sending to the group. > Of course I'd prefer it if you tried to flash coreboot (new name of > LinuxBIOS) to these boards, but that's your choice. Anyway, you said you > have the factory BIOS around somewhere. Is it the one at > http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > Hmm ok. I think we have enough docs to iterate through all possible > board enables. How many of these boards do you have (in case we trash > the ROM of one of them)? The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. Mike -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 4:47 AM To: Spangler, Mike T Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, was it intentional that you only sent the data to me? It would be great to have that data on the list. If possible, please forward your mail to the list so other developers can help as well. On 18.09.2009 07:26, Spangler, Mike T wrote: > Thanks for getting back to me. David Hendricks has been giving me some > direction also, but has kind of exhausted his ideas. He suggested that > I try something around revision 2000, because he thought that he was > able to flash an ARIMA board successfully with that version. I also > tried revision 2341 which had references in the Changelog to ARIMA. > Turns out the results were identical. The results of rev 2000/2341 is > that it flashes about 99% of the locations on the PLCC correctly. > Below I will give you some output from the flashrom -w command. Also, > I've included a comparison between the file I used to write to the > flash chip and a new file that I reread from the flashed chip. I analyzed the output and the only difference is that the new flashrom version detects the problem and the old version ignores it... > First I will give you what you wanted to know. The chip was originally > factory bios. It was either flashed to LinuxBios with lbflash or with > a standalone benchtop flasher. I'm trying to flash the chip back to > factory bios. Of course I'd prefer it if you tried to flash coreboot (new name of LinuxBIOS) to these boards, but that's your choice. Anyway, you said you have the factory BIOS around somewhere. Is it the one at http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? > Output from superiotool -dV > > Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV > superiotool r > Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e > Register dump: > LDN 0x07 (GPIO) > idx 30 60 61 70 71 74 75 f0 f1 f2 > val 00 00 00 00 03 04 04 00 44 01 > def 00 00 00 00 03 04 04 00 00 00 Hmm ok. I think we have enough docs to iterate through all possible board enables. How many of these boards do you have (in case we trash the ROM of one of them)? Regards, Carl-Daniel

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 18 Sep '09

18 Sep '09

Carl-Daniel - Thanks for getting back to me. David Hendricks has been giving me some direction also, but has kind of exhausted his ideas. He suggested that I try something around revision 2000, because he thought that he was able to flash an ARIMA board successfully with that version. I also tried revision 2341 which had references in the Changelog to ARIMA. Turns out the results were identical. The results of rev 2000/2341 is that it flashes about 99% of the locations on the PLCC correctly. Below I will give you some output from the flashrom -w command. Also, I've included a comparison between the file I used to write to the flash chip and a new file that I reread from the flashed chip. First I will give you what you wanted to know. The chip was originally factory bios. It was either flashed to LinuxBios with lbflash or with a standalone benchtop flasher. I'm trying to flash the chip back to factory bios. Output from superiotool -dV Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0003, id=0x11e1 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 2a 2b 2c 2d 2e val e1 11 00 03 00 00 00 0f 00 00 10 00 58 00 def e1 11 00 03 00 00 00 NA 00 MM 00 00 00 RR LDN 0x00 (Floppy) idx 30 60 61 70 71 74 75 f0 f1 val 00 03 f2 06 03 02 04 24 00 def 00 03 f2 06 03 02 04 24 00 LDN 0x01 (Parallel port) idx 30 60 61 70 71 74 75 f0 val 00 02 78 07 02 04 04 f2 def 00 02 78 07 02 04 04 f2 LDN 0x02 (COM2) idx 30 60 61 70 71 74 75 f0 val 00 02 f8 03 03 04 04 02 def 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 def 00 03 f8 04 03 04 04 02 LDN 0x04 (System wake-up control (SWC)) idx 30 60 61 70 71 74 75 val 00 00 00 00 03 04 04 def 00 00 00 00 03 04 04 LDN 0x05 (Mouse) idx 30 70 71 74 75 val 00 0c 02 04 04 def 00 0c 02 04 04 LDN 0x06 (Keyboard) idx 30 60 61 62 63 70 71 74 75 f0 val 01 00 60 00 64 01 02 04 04 40 def 01 00 60 00 64 01 02 04 04 40 LDN 0x07 (GPIO) idx 30 60 61 70 71 74 75 f0 f1 f2 val 00 00 00 00 03 04 04 00 44 01 def 00 00 00 00 03 04 04 00 00 00 LDN 0x08 (ACCESS.bus (ACB)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x09 (Fan speed control and monitor (FSCM)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x0a (Watchdog timer) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 02 def 00 00 00 00 03 04 04 02 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xe1, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Output from rev 2341: Node20:~/coreboot-v2/util/flashrom # ./flashrom -w /root/arima.flash Calibrating delay loop... ok Found LinuxBIOS table at: 00000500 vendor id: ARIMA part id: HDAMA Enabling flash write on AMD8111...OK SST49LF004A/B found at physical address: 0xfff80000 Flash part is SST49LF004A/B Flash image seems to be a legacy BIOS. Disabling checks. Programming Page: 0007 at address: 0x00070000 Node20:~/coreboot-v2/util/flashrom # Flash file comparison: Column 1 Byte # in Flash file Column 2 Data read from flash after flashing Column 3 Data from the file used to flash, ie, /root/arima.flash from above command. Note: From flashrom version 0.9.1 we get this error - ERASE FAILED at 0x0007f000! Expected=0xff, Read=0x00, failed byte count from 0x00070000-0x0007ffff: 0x1000 This corresponds to 520192(x7f000) location, which is close to 520193 below. 21846 252 377 520193 0 272 520194 0 377 520198 0 17 520199 0 60 520200 0 376 520201 0 301 520202 0 146 520203 0 45 520204 0 377 520205 0 367 520206 0 377 520207 0 377 520208 0 146 520209 0 367 520210 0 330 520211 0 146 520212 0 3 520213 0 370 520214 0 353 520215 0 271 520216 0 377 520217 0 343 520218 0 17 520219 0 176 520220 0 330 520221 0 213 520222 0 303 520223 0 17 520224 0 156 520225 0 330 520226 0 17 520227 0 156 520228 0 355 520229 0 17 520230 0 176 520231 0 310 520232 0 17 520233 0 156 520234 0 360 520235 0 146 520236 0 201 520237 0 371 520238 0 16 520239 0 2 520242 0 167 520243 0 156 520244 0 146 520245 0 321 520246 0 345 520247 0 146 520248 0 213 520249 0 335 520250 0 146 520251 0 207 520252 0 361 520253 0 17 520254 0 176 520255 0 310 520256 0 146 520257 0 17 520258 0 275 520259 0 310 520260 0 164 520261 0 120 520262 0 146 520263 0 17 520264 0 263 520265 0 310 520266 0 17 520267 0 156 520268 0 310 520269 0 146 520270 0 203 520271 0 301 520272 0 1 520273 0 146 520274 0 63 520275 0 377 520276 0 146 520277 0 17 520278 0 253 520279 0 317 520280 0 146 520281 0 3 520282 0 337 520283 0 146 520284 0 367 520285 0 337 520286 0 146 520287 0 207 520288 0 361 520289 0 146 520290 0 213 520291 0 305 520292 0 146 520293 0 213 520294 0 325 520295 0 146 520296 0 301 520297 0 340 520298 0 10 520299 0 146 520300 0 301 520301 0 352 520302 0 30 520303 0 14 520304 0 6 520305 0 17 520306 0 60 520307 0 376 520308 0 301 520309 0 146 520310 0 213 520311 0 307 520312 0 146 520313 0 213 520314 0 327 520315 0 146 520316 0 301 520317 0 340 520318 0 10 520319 0 146 520320 0 301 520321 0 352 520322 0 30 520323 0 17 520324 0 272 520325 0 350 520326 0 13 520327 0 17 520328 0 60 520329 0 146 520330 0 213 520331 0 353 520332 0 376 520333 0 301 520334 0 200 520335 0 371 520336 0 16 520337 0 166 520338 0 247 520339 0 146 520340 0 207 520341 0 361 520342 0 146 520343 0 207 520344 0 361 520345 0 17 520346 0 176 520347 0 310 520348 0 146 520349 0 13 520350 0 300 520351 0 370 520352 0 164 520353 0 1 520354 0 371 520355 0 17 520356 0 176 520357 0 363 520358 0 17 520359 0 156 520360 0 313 520361 0 17 520362 0 176 520363 0 355 520364 0 17 520365 0 176 520366 0 333 520367 0 377 520368 0 343 520369 0 146 520370 0 17 520371 0 313 520372 0 17 520373 0 156 520374 0 333 520375 0 146 520376 0 270 520380 0 340 520381 0 17 520382 0 156 520383 0 320 520384 0 146 520385 0 271 520386 0 20 520388 0 1 520389 0 300 520390 0 17 520391 0 62 520392 0 146 520393 0 45 520394 0 377 520395 0 377 520396 0 343 520397 0 377 520398 0 146 520399 0 15 520402 0 10 520404 0 17 520405 0 60 520406 0 146 520407 0 271 520408 0 377 520409 0 2 520412 0 146 520413 0 63 520414 0 300 520415 0 146 520416 0 63 520417 0 322 520418 0 264 520419 0 14 520420 0 17 520421 0 60 520422 0 62 520423 0 344 520424 0 261 520426 0 17 520427 0 60 520428 0 376 520429 0 301 520430 0 200 520431 0 371 520432 0 20 520433 0 165 520434 0 367 520435 0 261 520436 0 120 520437 0 17 520438 0 60 520439 0 261 520440 0 130 520441 0 17 520442 0 60 520443 0 261 520444 0 131 520445 0 17 520446 0 60 520447 0 261 520448 0 150 520449 0 17 520450 0 60 520451 0 376 520452 0 301 520453 0 200 520454 0 371 520455 0 160 520456 0 165 520457 0 367 520458 0 146 520459 0 271 520460 0 26 520462 0 1 520463 0 300 520464 0 17 520465 0 60 520466 0 376 520467 0 301 520468 0 200 520469 0 371 520470 0 32 520471 0 165 520472 0 367 520473 0 261 520474 0 32 520475 0 17 520476 0 60 520477 0 261 520478 0 35 520479 0 17 520480 0 60 520481 0 146 520482 0 271 520483 0 20 520485 0 1 520486 0 300 520487 0 17 520488 0 62 520489 0 146 520490 0 15 520493 0 34 520495 0 17 520496 0 60 520497 0 146 520498 0 271 520499 0 120 520500 0 2 520503 0 146 520504 0 270 520505 0 36 520506 0 36 520507 0 36 520508 0 36 520509 0 146 520510 0 213 520511 0 320 520512 0 17 520513 0 60 520514 0 261 520515 0 130 520516 0 17 520517 0 60 520518 0 63 520519 0 311 520520 0 216 520521 0 341 520522 0 214 520523 0 341 520524 0 301 520525 0 301 520526 0 13 520527 0 201 520528 0 301 520529 0 104 520530 0 301 520531 0 273 520532 0 130 520533 0 361 520534 0 351 520535 0 75 520536 0 2 520537 0 270 520538 0 377 520539 0 377 520540 0 146 520541 0 100 520542 0 146 520543 0 321 520544 0 350 520545 0 17 520546 0 156 520547 0 340 520548 0 146 520549 0 203 520550 0 370 520552 0 164 520553 0 36 520554 0 146 520555 0 271 520558 0 200 520560 0 146 520561 0 73 520562 0 301 520563 0 167 520564 0 23 520565 0 146 520566 0 17 520567 0 272 520568 0 344 520569 0 6 520570 0 163 520571 0 4 520572 0 146 520573 0 301 520574 0 341 520575 0 4 520576 0 17 520577 0 176 520578 0 302 520579 0 146 520580 0 73 520581 0 321 520582 0 166 520583 0 12 520584 0 146 520585 0 17 520586 0 272 520587 0 364 520588 0 5 520589 0 146 520590 0 17 520591 0 272 520592 0 364 520593 0 6 520594 0 146 520595 0 17 520596 0 272 520597 0 344 520598 0 5 520599 0 163 520600 0 177 520601 0 17 520602 0 176 520603 0 327 520604 0 146 520605 0 301 520606 0 357 520607 0 11 520608 0 146 520609 0 73 520610 0 307 520611 0 162 520612 0 3 520613 0 146 520614 0 213 520615 0 307 520616 0 17 520617 0 156 520618 0 310 520619 0 146 520620 0 63 520621 0 355 520622 0 146 520623 0 271 520625 0 2 520628 0 273 520629 0 271 520630 0 361 520631 0 351 520632 0 140 520633 0 376 520634 0 146 520635 0 213 520636 0 361 520637 0 17 520638 0 176 520639 0 310 520640 0 146 520641 0 213 520642 0 320 520643 0 146 520644 0 301 520645 0 340 520646 0 11 520647 0 146 520648 0 301 520649 0 352 520650 0 27 520651 0 146 520652 0 271 520653 0 32 520655 0 1 520656 0 300 520657 0 17 520658 0 60 520659 0 146 520660 0 275 520663 0 200 520665 0 146 520666 0 17 520667 0 272 520668 0 344 520669 0 6 520670 0 163 520671 0 4 520672 0 146 520673 0 301 520674 0 345 520675 0 4 520676 0 17 520677 0 176 520678 0 342 520679 0 17 520680 0 176 520681 0 300 520682 0 146 520683 0 53 520684 0 302 520685 0 17 520686 0 204 520687 0 235 520689 0 17 520690 0 156 520691 0 310 520692 0 146 520693 0 213 520694 0 316 520695 0 273 520696 0 374 520697 0 361 520698 0 351 520699 0 35 520700 0 376 520701 0 17 520702 0 176 520703 0 310 520704 0 146 520705 0 3 520706 0 305 520707 0 146 520708 0 213 520709 0 320 520710 0 146 520711 0 301 520712 0 340 520713 0 11 520714 0 146 520715 0 301 520716 0 352 520717 0 27 520718 0 146 520719 0 271 520720 0 35 520722 0 1 520723 0 300 520724 0 17 520725 0 60 520726 0 353 520727 0 147 520728 0 17 520729 0 176 520730 0 300 520731 0 17 520732 0 156 520733 0 310 520734 0 146 520735 0 63 520736 0 355 520737 0 146 520738 0 271 520740 0 2 520743 0 273 520744 0 54 520745 0 362 520746 0 351 520747 0 355 520748 0 375 520749 0 17 520750 0 176 520751 0 300 520752 0 17 520753 0 176 520754 0 327 520755 0 146 520756 0 301 520757 0 357 520758 0 11 520759 0 146 520760 0 73 520761 0 307 520762 0 162 520763 0 17 520764 0 146 520765 0 213 520766 0 307 520767 0 146 520768 0 213 520769 0 360 520770 0 273 520771 0 107 520772 0 362 520773 0 351 520774 0 206 520775 0 375 520776 0 146 520777 0 213 520778 0 306 520779 0 146 520780 0 213 520781 0 320 520782 0 146 520783 0 301 520784 0 340 520785 0 11 520786 0 146 520787 0 301 520788 0 352 520789 0 27 520790 0 146 520791 0 271 520792 0 32 520794 0 1 520795 0 300 520796 0 17 520797 0 60 520798 0 17 520799 0 176 520800 0 300 520801 0 146 520802 0 275 520805 0 200 520807 0 146 520808 0 73 520809 0 305 520810 0 166 520811 0 42 520812 0 146 520813 0 213 520814 0 320 520815 0 146 520816 0 301 520817 0 340 520818 0 11 520819 0 146 520820 0 301 520821 0 352 520822 0 27 520823 0 146 520824 0 271 520825 0 35 520827 0 1 520828 0 300 520829 0 17 520830 0 60 520831 0 146 520832 0 271 520833 0 20 520835 0 1 520836 0 300 520837 0 17 520838 0 62 520839 0 146 520840 0 17 520841 0 272 520842 0 350 520843 0 25 520844 0 17 520845 0 60 520846 0 17 520847 0 176 520848 0 333 520849 0 146 520850 0 17 520851 0 313 520852 0 377 520853 0 343 520854 0 17 520855 0 156 520856 0 303 520857 0 146 520858 0 270 520859 0 1 520863 0 17 520864 0 242 520865 0 44 520866 0 116 520867 0 75 520868 0 100 520869 0 17 520870 0 165 520871 0 6 520872 0 273 520873 0 255 520874 0 362 520875 0 351 520876 0 311 520877 0 353 520878 0 146 520879 0 17 520880 0 272 520881 0 344 520882 0 11 520883 0 17 520884 0 202 520885 0 261 520887 0 63 520888 0 311 520889 0 216 520890 0 341 520891 0 273 520892 0 300 520893 0 362 520894 0 351 520895 0 224 520896 0 354 520897 0 17 520898 0 203 520899 0 230 520901 0 214 520902 0 341 520903 0 301 520904 0 301 520905 0 13 520906 0 201 520907 0 301 520908 0 224 520909 0 302 520910 0 273 520911 0 323 520912 0 362 520913 0 351 520914 0 302 520916 0 146 520917 0 17 520918 0 272 520919 0 340 520920 0 31 520921 0 17 520922 0 203 520923 0 200 520925 0 261 520926 0 220 520927 0 273 520928 0 344 520929 0 362 520930 0 351 520931 0 261 520933 0 146 520934 0 15 520936 0 1 520939 0 273 520940 0 360 520941 0 362 520942 0 351 520943 0 5 520944 0 1 520945 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524205 0 374 524206 0 272 524207 0 370 524208 0 14 524209 0 146 524210 0 357 524211 0 346 524212 0 355 524213 0 272 524214 0 374 524215 0 14 524216 0 146 524217 0 213 524218 0 370 524219 0 146 524220 0 355 524221 0 146 524222 0 213 524223 0 320 524224 0 146 524225 0 213 524226 0 307 524227 0 377 524228 0 343 524229 0 146 524230 0 213 524231 0 372 524232 0 44 524233 0 374 524234 0 272 524235 0 370 524236 0 14 524237 0 146 524238 0 357 524239 0 346 524240 0 355 524241 0 272 524242 0 374 524243 0 14 524244 0 146 524245 0 227 524246 0 146 524247 0 357 524248 0 146 524249 0 213 524250 0 320 524251 0 146 524252 0 213 524253 0 307 524254 0 377 524255 0 343 524257 0 42 524258 0 20 524259 0 144 524260 0 164 524261 0 377 524262 0 377 524267 0 60 524268 0 276 524273 0 351 524274 0 42 524275 0 325 524281 0 352 524282 0 202 524283 0 325 524285 0 360 -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Thursday, September 17, 2009 8:16 AM To: Spangler, Mike T Cc: flashrom Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, I edit the low below for brevity. On 10.09.2009 08:16, Spangler, Mike T wrote: > Tried 0.9.1-r710. Looks like its different, but it probably trashed the chip. No big deal.... > > node0:~ # flashrom -V -w arima.flash > flashrom v0.9.1-r710 > Found candidate at: 00000500-00000db0 > Found coreboot table at 0x00000500. > coreboot table found at 0x500. > coreboot header(24) checksum: bbc7 table(2224) checksum: a9cd entries: 13 > Vendor ID: ARIMA, part ID: HDAMA > Found chipset "AMD AMD8111", enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Calibrating delay loop... 654M loops per second, 100 myus = 194 us. OK. > Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 > Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > ERASE FAILED at 0x0007f000! Expected=0xff, Read=0x00, failed byte count from 0x00070000-0x0007ffff: 0x1000 > The issue you're facing is simple, but you might have to do a bit of work to fix it. You need special handling code for the flash boot block write protection on your board, commonly called board_enable. Don't worry, we can help you with that. First, do you know how the ROM image was flashed in the first place? flashrom? flash_and_burn? lbflash? /dev/bios? That will help us find any existing source code and save us the trouble of toggling loads of GPIOs. The output of "superiotool -dV" will be useful as well. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] ICH SPI Preop handling
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

The current ICH SPI preop handling is a hack which spews lots of warnings, but still yields correct results. With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich9_multicommand_preop/ichspi.c =================================================================== --- flashrom-ich9_multicommand_preop/ichspi.c (Revision 725) +++ flashrom-ich9_multicommand_preop/ichspi.c (Arbeitskopie) @@ -745,18 +745,25 @@ int ich_spi_send_multicommand(struct spi_command *spicommands) { int ret = 0; + int oppos, preoppos; while ((spicommands->writecnt || spicommands->readcnt) && !ret) { + /* Will the next loop iteration be taken? */ + if ((spicommands + 1)->writecnt || (spicommands + 1)->readcnt) { + preoppos = find_preop(curopcodes, spicommands->writearr[0]); + oppos = find_opcode(curopcodes, (spicommands + 1)->writearr[0]); + /* Is the current op a preop for the next op? */ + if ((oppos != -1) && (preoppos != -1) && + (curopcodes->opcode[oppos].atomic == preoppos)) { + printf_debug("opcode 0x%02x will be run as PREOP\n", + spicommands->writearr[0]); + ret = 0; + spicommands++; + continue; + } + } + ret = ich_spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); - /* This awful hack needs to be smarter. - */ - if ((ret == SPI_INVALID_OPCODE) && - ((spicommands->writearr[0] == JEDEC_WREN) || - (spicommands->writearr[0] == JEDEC_EWSR))) { - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - ret = 0; - } spicommands++; } return ret; -- http://www.hailfinger.org/

2 9

[commit] r727 - trunk
by svn＠flashrom.org 18 Sep '09

18 Sep '09

Author: hailfinger Date: 2009-09-18 17:50:56 +0200 (Fri, 18 Sep 2009) New Revision: 727 Modified: trunk/flash.h trunk/ichspi.c trunk/spi.c Log: The current ICH SPI preop handling is a hack which spews lots of warnings, but still yields correct results. With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: FENG Yu Ning <fengyuning1984(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/flash.h 2009-09-18 15:50:56 UTC (rev 727) @@ -498,7 +498,7 @@ struct spi_programmer { int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *spicommands); + int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -514,7 +514,7 @@ int probe_spi_res(struct flashchip *flash); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *spicommands); +int spi_send_multicommand(struct spi_command *cmds); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -539,7 +539,7 @@ uint32_t spi_get_valid_read_addr(void); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *spicommands); +int default_spi_send_multicommand(struct spi_command *cmds); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); @@ -565,7 +565,7 @@ const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); -int ich_spi_send_multicommand(struct spi_command *spicommands); +int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ extern uint16_t it8716f_flashport; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/ichspi.c 2009-09-18 15:50:56 UTC (rev 727) @@ -742,22 +742,29 @@ return result; } -int ich_spi_send_multicommand(struct spi_command *spicommands) +int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !ret) { - ret = ich_spi_send_command(spicommands->writecnt, spicommands->readcnt, - spicommands->writearr, spicommands->readarr); - /* This awful hack needs to be smarter. - */ - if ((ret == SPI_INVALID_OPCODE) && - ((spicommands->writearr[0] == JEDEC_WREN) || - (spicommands->writearr[0] == JEDEC_EWSR))) { - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - ret = 0; - } - spicommands++; + int oppos, preoppos; + for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { + /* Is the next command valid or a terminator? */ + if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { + preoppos = find_preop(curopcodes, cmds->writearr[0]); + oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + /* Is the opcode of the current command listed in the + * ICH struct OPCODES as associated preopcode for the + * opcode of the next command? + */ + if ((oppos != -1) && (preoppos != -1) && + (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { + printf_debug("opcode 0x%02x will be run as PREOP\n", + cmds->writearr[0]); + continue; + } + } + + ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, + cmds->writearr, cmds->readarr); } return ret; } Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/spi.c 2009-09-18 15:50:56 UTC (rev 727) @@ -118,7 +118,7 @@ writearr, readarr); } -int spi_send_multicommand(struct spi_command *spicommands) +int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { fprintf(stderr, "%s called, but SPI is unsupported on this " @@ -126,7 +126,7 @@ return 1; } - return spi_programmer[spi_controller].multicommand(spicommands); + return spi_programmer[spi_controller].multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -148,13 +148,12 @@ return spi_send_multicommand(cmd); } -int default_spi_send_multicommand(struct spi_command *spicommands) +int default_spi_send_multicommand(struct spi_command *cmds) { int result = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !result) { - result = spi_send_command(spicommands->writecnt, spicommands->readcnt, - spicommands->writearr, spicommands->readarr); - spicommands++; + for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { + result = spi_send_command(cmds->writecnt, cmds->readcnt, + cmds->writearr, cmds->readarr); } return result; } @@ -494,7 +493,7 @@ int spi_chip_erase_60(struct flashchip *flash) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -518,7 +517,7 @@ return result; } - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -540,7 +539,7 @@ int spi_chip_erase_c7(struct flashchip *flash) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -564,7 +563,7 @@ return result; } - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); return result; @@ -596,7 +595,7 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -614,7 +613,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -640,7 +639,7 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -658,7 +657,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); return result; @@ -702,7 +701,7 @@ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -720,7 +719,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -779,7 +778,7 @@ int spi_write_status_register(int status) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_EWSR_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_EWSR }, @@ -797,7 +796,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -808,7 +807,7 @@ int spi_byte_program(int addr, uint8_t byte) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -826,7 +825,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -844,7 +843,7 @@ (address >> 8) & 0xff, (address >> 0) & 0xff, }; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -873,7 +872,7 @@ memcpy(&cmd[4], bytes, len); - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__);

1 0

[commit] r726 - trunk
by svn＠flashrom.org 18 Sep '09

18 Sep '09

Author: uwe Date: 2009-09-18 15:38:14 +0200 (Fri, 18 Sep 2009) New Revision: 726 Modified: trunk/flashrom.c Log: Fix copy-paste errors by s/CONFIG_PRINT_WIKI/PRINT_WIKI_SUPPORT/. Trivial, and build-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-16 12:19:03 UTC (rev 725) +++ trunk/flashrom.c 2009-09-18 13:38:14 UTC (rev 726) @@ -581,7 +581,7 @@ " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" " -L | --list-supported: print supported devices\n" -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 " -z | --list-supported-wiki: print supported devices in wiki syntax\n" #endif " -p | --programmer <name>: specify the programmer device"); @@ -637,13 +637,13 @@ int force = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, list_supported = 0; -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 int list_supported_wiki = 0; #endif int operation_specified = 0; int ret = 0, i; -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 const char *optstring = "rRwvnVEfc:m:l:i:p:Lzh"; #else const char *optstring = "rRwvnVEfc:m:l:i:p:Lh"; @@ -661,7 +661,7 @@ {"layout", 1, 0, 'l'}, {"image", 1, 0, 'i'}, {"list-supported", 0, 0, 'L'}, -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 {"list-supported-wiki", 0, 0, 'z'}, #endif {"programmer", 1, 0, 'p'}, @@ -766,7 +766,7 @@ case 'L': list_supported = 1; break; -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 case 'z': list_supported_wiki = 1; break; @@ -827,7 +827,7 @@ exit(0); } -#if CONFIG_PRINT_WIKI == 1 +#if PRINT_WIKI_SUPPORT == 1 if (list_supported_wiki) { print_wiki_tables(); exit(0);

1 0

[PATCH]Enable flashrom on Wyse Winterm S50.
by Nils 18 Sep '09

18 Sep '09

Hi Carl-Daniel, Thanks for the review. The CS5536 host bridge PCI ID doesn`t show in lspci and that is the reason the standard CS5536 detection routine doesn`t work. lspci -tvnn: -[0000:00]-+-01.0 National Semiconductor Corporation Geode GX2 Host Bridge [100b:0028] +-01.1 National Semiconductor Corporation Geode GX2 Graphics Processor [100b:0030] +-0e.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] +-0f.0 Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] +-0f.2 Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] +-0f.3 Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] +-0f.4 Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] \-0f.5 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] I tried a similar patch with the CS5536 ISA ID [1022:2090] and that also works. Is that O.K. or is it better to patch the original CS5536 routine to detect the CS5536 chip with different processors? Regards, Nils.

2 1

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 17 Sep '09

17 Sep '09

Hi Mike, I edit the low below for brevity. On 10.09.2009 08:16, Spangler, Mike T wrote: > Tried 0.9.1-r710. Looks like its different, but it probably trashed the chip. No big deal.... > > node0:~ # flashrom -V -w arima.flash > flashrom v0.9.1-r710 > Found candidate at: 00000500-00000db0 > Found coreboot table at 0x00000500. > coreboot table found at 0x500. > coreboot header(24) checksum: bbc7 table(2224) checksum: a9cd entries: 13 > Vendor ID: ARIMA, part ID: HDAMA > Found chipset "AMD AMD8111", enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Calibrating delay loop... 654M loops per second, 100 myus = 194 us. OK. > Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 > Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > ERASE FAILED at 0x0007f000! Expected=0xff, Read=0x00, failed byte count from 0x00070000-0x0007ffff: 0x1000 > The issue you're facing is simple, but you might have to do a bit of work to fix it. You need special handling code for the flash boot block write protection on your board, commonly called board_enable. Don't worry, we can help you with that. First, do you know how the ROM image was flashed in the first place? flashrom? flash_and_burn? lbflash? /dev/bios? That will help us find any existing source code and save us the trouble of toggling loads of GPIOs. The output of "superiotool -dV" will be useful as well. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH]Enable flashrom on Wyse Winterm S50.
by Nils 17 Sep '09

17 Sep '09

Hi, First off all I want to thank all flashrom and coreboot members for their great work! With the help of the little attached patch I was able to Probe, Read, Write and Verify a ST49LF020A flashchip on my Wyse Winterm S50 Thin Client with Geode GX500 (GX2) processor and CS5536 companion chip. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> I hope its the right patch. Thanks, Nils.

2 1

[RFC] libflashrom design choices
by Carl-Daniel Hailfinger 16 Sep '09

16 Sep '09

Hi, since the request to turn flashrom into a library pops up from time to time, we have to make sure the flashrom code doesn't have any nasty surprises. - We have to decide on a design for fatal errors after initalization is over. Some code uses exit(1) for any fatal errors after init, but that it not really a valid choice for a library. After all, the caller may want to clean up some stuff outside libflashrom. - Kill all uses of exit(1) inside init code. The programmer_init code has proper error handling and the caller must check its return code. I have a patch for this. - Memory leaks. We didn't have to care because everything was freed automatically upon exit. I have a patch for the leaks I found from a cursory glance at the code. - Global error variable? - Grouping all global variables into a single struct to avoid namespace pollution. - Adding struct flashchip to every function or relying on a global variable. - Thread safety? - Which symbols (variables/functions) should be exported in the library interface? - Consistent prefix for exported functions (namespace pollution)? - message level functions (print_debug/print_warn/print_err/print) instead of printf and friends so the library user can decide how/if to display these messages. After all the stuff above is solved, we can think about librarizing flashrom. There are probably quite a few additional issues I didn't list above. Comments are appreciated. Patches are welcome. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 7

[PATCH] Compile out wiki output on request
by Carl-Daniel Hailfinger 16 Sep '09

16 Sep '09

Compile out wiki output on request and move wiki stuff into a separate file. This is useful for libflashrom (you don't need wiki output in a coreboot payload). Please note that the patch below was created by using svn cp print.c print_wiki.c, then deleting code from each file. As a result, you only see the deleted code in the patch instead of the added code in print_wiki.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-wiki_compileout/Makefile =================================================================== --- flashrom-wiki_compileout/Makefile (Revision 724) +++ flashrom-wiki_compileout/Makefile (Arbeitskopie) @@ -83,6 +83,9 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes +# Always enable wiki printing for now. +CONFIG_PRINT_WIKI ?= yes + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -118,6 +121,11 @@ OBJS += drkaiser.o endif +ifeq ($(CONFIG_PRINT_WIKI), yes) +FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' +OBJS += print_wiki.o +endif + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) Index: flashrom-wiki_compileout/flashrom.c =================================================================== --- flashrom-wiki_compileout/flashrom.c (Revision 724) +++ flashrom-wiki_compileout/flashrom.c (Arbeitskopie) @@ -581,7 +581,9 @@ " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" " -L | --list-supported: print supported devices\n" +#if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki: print supported devices in wiki syntax\n" +#endif " -p | --programmer <name>: specify the programmer device"); for (p = 0; p < PROGRAMMER_INVALID; p++) { @@ -634,10 +636,18 @@ int option_index = 0; int force = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int dont_verify_it = 0, list_supported = 0, list_supported_wiki = 0; + int dont_verify_it = 0, list_supported = 0; +#if CONFIG_PRINT_WIKI == 1 + int list_supported_wiki = 0; +#endif int operation_specified = 0; int ret = 0, i; +#if CONFIG_PRINT_WIKI == 1 + const char *optstring = "rRwvnVEfc:m:l:i:p:Lzh"; +#else + const char *optstring = "rRwvnVEfc:m:l:i:p:Lh"; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, {"write", 0, 0, 'w'}, @@ -651,7 +661,9 @@ {"layout", 1, 0, 'l'}, {"image", 1, 0, 'i'}, {"list-supported", 0, 0, 'L'}, +#if CONFIG_PRINT_WIKI == 1 {"list-supported-wiki", 0, 0, 'z'}, +#endif {"programmer", 1, 0, 'p'}, {"help", 0, 0, 'h'}, {"version", 0, 0, 'R'}, @@ -683,7 +695,7 @@ } setbuf(stdout, NULL); - while ((opt = getopt_long(argc, argv, "rRwvnVEfc:m:l:i:p:Lzh", + while ((opt = getopt_long(argc, argv, optstring, long_options, &option_index)) != EOF) { switch (opt) { case 'r': @@ -754,9 +766,11 @@ case 'L': list_supported = 1; break; +#if CONFIG_PRINT_WIKI == 1 case 'z': list_supported_wiki = 1; break; +#endif case 'p': for (programmer = 0; programmer < PROGRAMMER_INVALID; programmer++) { name = programmer_table[programmer].name; @@ -813,10 +827,12 @@ exit(0); } +#if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { print_wiki_tables(); exit(0); } +#endif if (read_it && write_it) { printf("Error: -r and -w are mutually exclusive.\n"); Index: flashrom-wiki_compileout/print_wiki.c =================================================================== --- flashrom-wiki_compileout/print_wiki.c (Revision 724) +++ flashrom-wiki_compileout/print_wiki.c (Arbeitskopie) @@ -37,204 +37,6 @@ const char *note; }; -/* - * Return a string corresponding to the bustype parameter. - * Memory is obtained with malloc() and can be freed with free(). - */ -char *flashbuses_to_text(enum chipbustype bustype) -{ - char *ret = calloc(1, 1); - if (bustype == CHIP_BUSTYPE_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown,"); - /* - * FIXME: Once all chipsets and flash chips have been updated, NONSPI - * will cease to exist and should be eliminated here as well. - */ - } else if (bustype == CHIP_BUSTYPE_NONSPI) { - ret = strcat_realloc(ret, "Non-SPI,"); - } else { - if (bustype & CHIP_BUSTYPE_PARALLEL) - ret = strcat_realloc(ret, "Parallel,"); - if (bustype & CHIP_BUSTYPE_LPC) - ret = strcat_realloc(ret, "LPC,"); - if (bustype & CHIP_BUSTYPE_FWH) - ret = strcat_realloc(ret, "FWH,"); - if (bustype & CHIP_BUSTYPE_SPI) - ret = strcat_realloc(ret, "SPI,"); - if (bustype == CHIP_BUSTYPE_NONE) - ret = strcat_realloc(ret, "None,"); - } - /* Kill last comma. */ - ret[strlen(ret) - 1] = '\0'; - ret = realloc(ret, strlen(ret) + 1); - return ret; -} - -#define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0) - -static int digits(int n) -{ - int i; - - if (!n) - return 1; - - for (i = 0; n; ++i) - n /= 10; - - return i; -} - -void print_supported_chips(void) -{ - int okcol = 0, pos = 0, i, chipcount = 0; - struct flashchip *f; - - for (f = flashchips; f->name != NULL; f++) { - if (GENERIC_DEVICE_ID == f->model_id) - continue; - okcol = max(okcol, strlen(f->vendor) + 1 + strlen(f->name)); - } - okcol = (okcol + 7) & ~7; - - for (f = flashchips; f->name != NULL; f++) - chipcount++; - - printf("\nSupported flash chips (total: %d):\n\n", chipcount); - POS_PRINT("Vendor: Device:"); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); - } - - printf("Tested OK:\tKnown BAD: Size/KB: Type:\n\n"); - printf("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); - - for (f = flashchips; f->name != NULL; f++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) - continue; - - printf("%s", f->vendor); - for (i = 0; i < 10 - strlen(f->vendor); i++) - printf(" "); - printf("%s", f->name); - - pos = 10 + strlen(f->name); - while (pos < okcol) { - printf("\t"); - pos += 8 - (pos % 8); - } - if ((f->tested & TEST_OK_MASK)) { - if ((f->tested & TEST_OK_PROBE)) - POS_PRINT("P "); - if ((f->tested & TEST_OK_READ)) - POS_PRINT("R "); - if ((f->tested & TEST_OK_ERASE)) - POS_PRINT("E "); - if ((f->tested & TEST_OK_WRITE)) - POS_PRINT("W "); - } - while (pos < okcol + 9) { - printf("\t"); - pos += 8 - (pos % 8); - } - if ((f->tested & TEST_BAD_MASK)) { - if ((f->tested & TEST_BAD_PROBE)) - printf("P "); - if ((f->tested & TEST_BAD_READ)) - printf("R "); - if ((f->tested & TEST_BAD_ERASE)) - printf("E "); - if ((f->tested & TEST_BAD_WRITE)) - printf("W "); - } - - printf("\t %d", f->total_size); - for (i = 0; i < 10 - digits(f->total_size); i++) - printf(" "); - printf("%s\n", flashbuses_to_text(f->bustype)); - } -} - -void print_supported_chipsets(void) -{ - int i, j, chipsetcount = 0; - const struct penable *c = chipset_enables; - - for (i = 0; c[i].vendor_name != NULL; i++) - chipsetcount++; - - printf("\nSupported chipsets (total: %d):\n\nVendor: " - "Chipset: PCI IDs:\n\n", chipsetcount); - - for (i = 0; c[i].vendor_name != NULL; i++) { - printf("%s", c[i].vendor_name); - for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) - printf(" "); - printf("%s", c[i].device_name); - for (j = 0; j < 25 - strlen(c[i].device_name); j++) - printf(" "); - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, - (c[i].status == OK) ? "" : " (untested)"); - } -} - -void print_supported_boards_helper(const struct board_info *b, const char *msg) -{ - int i, j, boardcount = 0; - - for (i = 0; b[i].vendor != NULL; i++) - boardcount++; - - printf("\n%s (total: %d):\n\n", msg, boardcount); - - for (i = 0; b[i].vendor != NULL; i++) { - printf("%s", b[i].vendor); - for (j = 0; j < 25 - strlen(b[i].vendor); j++) - printf(" "); - printf("%s", b[i].name); - for (j = 0; j < 23 - strlen(b[i].name); j++) - printf(" "); - printf("\n"); - } -} - -void print_supported_boards(void) -{ - int i, j, boardcount = 0; - struct board_pciid_enable *b = board_pciid_enables; - - for (i = 0; b[i].vendor_name != NULL; i++) - boardcount++; - - printf("\nSupported boards which need write-enable code (total: %d):" - "\n\nVendor: Board: " - "Required option:\n\n", boardcount); - - for (i = 0; b[i].vendor_name != NULL; i++) { - printf("%s", b[i].vendor_name); - for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) - printf(" "); - printf("%s", b[i].board_name); - for (j = 0; j < 25 - strlen(b[i].board_name); j++) - printf(" "); - if (b[i].lb_vendor != NULL) - printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); - else - printf("(none, board is autodetected)\n"); - } - - print_supported_boards_helper(boards_ok, - "Supported boards which don't need write-enable code"); - print_supported_boards_helper(boards_bad, - "Boards which have been verified to NOT work yet"); - print_supported_boards_helper(laptops_ok, - "Laptops which have been verified to work"); - print_supported_boards_helper(laptops_bad, - "Laptops which have been verified to NOT work yet"); -} - const char *wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Index: flashrom-wiki_compileout/print.c =================================================================== --- flashrom-wiki_compileout/print.c (Revision 724) +++ flashrom-wiki_compileout/print.c (Arbeitskopie) @@ -21,22 +21,9 @@ #include <string.h> #include <stdlib.h> -#include <time.h> #include "flash.h" #include "flashchips.h" -struct board_info_url { - const char *vendor; - const char *name; - const char *url; -}; - -struct board_info_notes { - const char *vendor; - const char *name; - const char *note; -}; - /* * Return a string corresponding to the bustype parameter. * Memory is obtained with malloc() and can be freed with free(). @@ -234,512 +221,3 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } - -const char *wiki_header = "= Supported devices =\n\n\ -<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ -Please do '''not''' edit these tables in the wiki directly, they are \ -generated by pasting '''flashrom -z''' output.<br />\ -'''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; - -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ -|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; - -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Status\n\n"; - -const char *board_th2 = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ -! align=\"left\" | Status\n\n"; - -const char *board_intro = "\ -\n== Supported mainboards ==\n\n\ -In general, it is very likely that flashrom works out of the box even if your \ -mainboard is not listed below.\n\nThis is a list of mainboards where we have \ -verified that they either do or do not need any special initialization to \ -make flashrom work (given flashrom supports the respective chipset and flash \ -chip), or that they do not yet work at all. If they do not work, support may \ -or may not be added later.\n\n\ -Mainboards which don't appear in the list may or may not work (we don't \ -know, someone has to give it a try). Please report any further verified \ -mainboards on the [[Mailinglist|mailing list]].\n"; - -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ -! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ -|- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ -| Probe\n| Read\n| Write\n| Erase\n\n"; - -const char *programmer_section = "\ -\n== Supported programmers ==\n\nThis is a list \ -of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ -valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ -smaller\" valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; - -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ -In general, flashing laptops is more difficult because laptops\n\n\ -* often use the flash chip for stuff besides the BIOS,\n\ -* often have special protection stuff which has to be handled by flashrom,\n\ -* often use flash translation circuits which need drivers in flashrom.\n\n\ -<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#ff6666; align:right; border:1px solid #000000;\">\n\ -'''IMPORTANT:''' At this point we recommend to '''not''' use flashrom on \ -untested laptops unless you have a means to recover from a flashing that goes \ -wrong (a working backup flash chip and/or good soldering skills).\n</div>\n"; - -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_url boards_url[] = { - /* Verified working boards that don't need write-enables. */ - { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, - { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, - { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, - { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, - { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, - { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, - { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, - { "ASUS", "A7V8X-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=64&l4=0&model=229&modelm…" }, - { "ASUS", "A8N-E", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&model…" }, - { "ASUS", "A8NE-FM/S", "http://www.hardwareschotte.de/hardware/preise/proid_1266090/preis_ASUS+A8NE…" }, - { "ASUS", "A8N-SLI", "http://asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK" }, - { "ASUS", "A8N-SLI Premium", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=148&l4=0&model=539&model…" }, - { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU" }, - { "ASUS", "A8V-E Deluxe", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&model…" }, - { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, - { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, - { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, - { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, - { "ASUS", "M2V", "http://asus.com/Product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, - { "ASUS", "P2B", "http://www.motherboard.cz/mb/asus/P2B.htm" }, - { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, - { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, - { "ASUS", "P2B-F", "http://www.motherboard.cz/mb/asus/P2B-F.htm" }, - { "ASUS", "P2L97-S", "http://www.motherboard.cz/mb/asus/P2L97-S.htm" }, - { "ASUS", "P5B-Deluxe", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-Deluxe/" }, - { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, - { "ASUS", "P5L-MX", "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH" }, - { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, - { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, - { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, - { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, - { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, - { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "Intel", "EP80759", NULL }, - { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, - { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, - { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, - { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, - { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, - { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, - { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, - { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, - { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, - { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" }, - { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm" }, - { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm" }, - { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm" }, - { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, - { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, - { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, - { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, - { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, - { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, - { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610" }, - { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html" }, - { "Tyan", "S2466", "http://www.tyan.com/product_board_detail.aspx?pid=461" }, - { "Tyan", "S2881", "http://www.tyan.com/product_board_detail.aspx?pid=115" }, - { "Tyan", "S2882", "http://www.tyan.com/product_board_detail.aspx?pid=121" }, - { "Tyan", "S2882-D", "http://www.tyan.com/product_board_detail.aspx?pid=127" }, - { "Tyan", "S2891", "http://www.tyan.com/product_board_detail.aspx?pid=144" }, - { "Tyan", "S2892", "http://www.tyan.com/product_board_detail.aspx?pid=145" }, - { "Tyan", "S2895", "http://www.tyan.com/archive/products/html/thunderk8we.html" }, - { "Tyan", "S3095", "http://www.tyan.com/product_board_detail.aspx?pid=181" }, - { "Tyan", "S5180", "http://www.tyan.com/product_board_detail.aspx?pid=456" }, - { "Tyan", "S5191", "http://www.tyan.com/product_board_detail.aspx?pid=343" }, - { "Tyan", "S5197", "http://www.tyan.com/product_board_detail.aspx?pid=349" }, - { "Tyan", "S5211", "http://www.tyan.com/product_board_detail.aspx?pid=591" }, - { "Tyan", "S5211-1U", "http://www.tyan.com/product_board_detail.aspx?pid=593" }, - { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597" }, - { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566" }, - { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605" }, - { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…" }, - { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, - { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…" }, - { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp" }, - { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - - /* Verified working boards that DO need write-enables. */ - { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, - { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, - { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ - { "AOpen", "vKM400Am-S", "http://usa.aopen.com/products_detail.aspx?Auno=824" }, - { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, - { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, - { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k" }, - { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, - { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, - { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g" }, - { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, - { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, - { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, - { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, - { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, - { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, - { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ - { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ - { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…" }, - { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html" }, - { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm" }, - { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, - { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, - { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, - { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msicomputer.com/product/p_spec.asp?model=KT4_Ultra&class=mb" }, - { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msicomputer.com/product/p_spec.asp?model=K8T_Neo2-F&class=mb" }, - { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, - { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, - { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=170&maincat_no=1" }, - { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, - { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, - { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, - { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-MII link for now */ - { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ - { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, - - /* Verified non-working boards (for now). */ - { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, - { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, - { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm" }, - { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/" }, - { "ASUS", "P5B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/" }, - { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/" }, - { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, - { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, - { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…" }, - { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, - { "MSI", "MS-6178", "http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no…" }, - { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255" }, - { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English" }, - { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/" }, - { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, - { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, - { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, - - /* Verified working laptops. */ - { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…" }, - - /* Verified non-working laptops (for now). */ - { "Acer", "Aspire One", NULL }, - { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, - { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, - { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, - { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, - { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, - - { NULL, NULL, 0 }, -}; - -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_notes boards_notes[] = { - /* Verified working boards that don't need write-enables. */ - { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, - { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, - { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, - { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, - { "GIGABYTE", "GA-7ZM", "Works fine iff you remove jumper JP9 on the board and disable the flash protection BIOS option." }, - - /* Verified working boards that DO need write-enables. */ - { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, - - /* Verified non-working boards (for now). */ - { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, - { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, - - /* Verified working laptops. */ - /* None which need comments, yet... */ - - /* Verified non-working laptops (for now). */ - { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, - { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, - { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, - { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, - { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, - - { NULL, NULL, 0 }, -}; - -static int url(const char *vendor, const char *board) -{ - int i; - const struct board_info_url *b = boards_url; - - for (i = 0; b[i].vendor != NULL; i++) { - if (!strcmp(vendor, b[i].vendor) && !strcmp(board, b[i].name)) - return i; - } - - return -1; -} - -static int note(const char *vendor, const char *board) -{ - int i; - const struct board_info_notes *n = boards_notes; - - for (i = 0; n[i].vendor != NULL; i++) { - if (!strcmp(vendor, n[i].vendor) && !strcmp(board, n[i].name)) - return i; - } - - return -1; -} - -void print_supported_chipsets_wiki(void) -{ - int i, j, enablescount = 0, color = 1; - const struct penable *e; - - for (e = chipset_enables; e->vendor_name != NULL; e++) - enablescount++; - - printf("\n== Supported chipsets ==\n\nTotal amount of supported " - "chipsets: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n| " - "valign=\"top\"|\n\n%s", enablescount, chipset_th); - - e = chipset_enables; - for (i = 0, j = 0; e[i].vendor_name != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(e[i].vendor_name, e[i - 1].vendor_name)) - color = !color; - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " - "|| %04x:%04x || %s\n", (color) ? "eeeeee" : "dddddd", - e[i].vendor_name, e[i].device_name, - e[i].vendor_id, e[i].device_id, - (e[i].status == OK) ? "{{OK}}" : "?"); - - /* Split table in three columns. */ - if (j >= (enablescount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); -} - -static void wiki_helper(const char *heading, const char *status, - int cols, const struct board_info boards[]) -{ - int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; - const struct board_info *b; - const struct board_info_url *u = boards_url; - char *notes = calloc(1, 1); - char tmp[900 + 1]; - - for (b = boards; b->vendor != NULL; b++) - boardcount++; - - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" - "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th); - - for (i = 0, j = 0, b = boards; b[i].vendor != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor, b[i - 1].vendor)) - color = !color; - - k = url(b[i].vendor, b[i].name); - c = note(b[i].vendor, b[i].name); - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" - " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, - (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", - b[i].name, (k != -1 && u[k].url) ? "]" : "", status); - - if (c != -1) { - printf("<sup>%d</sup>\n", num_notes + 1); - snprintf((char *)&tmp, 900, "<sup>%d</sup> %s<br />\n", - 1 + num_notes++, boards_notes[c].note); - notes = strcat_realloc(notes, (char *)&tmp); - } else { - printf("\n"); - } - - /* Split table in 'cols' columns. */ - if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); - - if (num_notes > 0) - printf("\n<small>\n%s</small>\n", notes); - free(notes); -} - -static void wiki_helper2(const char *heading, int cols) -{ - int i, j, k, boardcount = 0, color = 1; - struct board_pciid_enable *b; - const struct board_info_url *u = boards_url; - - for (b = board_pciid_enables; b->vendor_name != NULL; b++) - boardcount++; - - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" - "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th2); - - b = board_pciid_enables; - for (i = 0, j = 0; b[i].vendor_name != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) - color = !color; - - k = url(b[i].vendor_name, b[i].board_name); - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " - "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", - b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, - (k != -1 && u[k].url) ? "]" : "", - (b[i].lb_vendor) ? "-m " : "—", - (b[i].lb_vendor) ? b[i].lb_vendor : "", - (b[i].lb_vendor) ? ":" : "", - (b[i].lb_vendor) ? b[i].lb_part : ""); - - /* Split table in three columns. */ - if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); -} - -void print_supported_boards_wiki(void) -{ - printf("%s", board_intro); - wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); - wiki_helper2("Known good (with write-enable code in flashrom)", 3); - wiki_helper("Not supported (yet)", "No", 3, boards_bad); - - printf("%s", laptop_intro); - wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); - wiki_helper("Not supported (yet)", "No", 1, laptops_bad); -} - -void print_supported_chips_wiki(void) -{ - int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; - uint32_t t; - - for (f = flashchips; f->name != NULL; f++) - chipcount++; - - printf("\n== Supported chips ==\n\nTotal amount of supported " - "chips: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n" - "| valign=\"top\"|\n\n%s", chipcount, chip_th); - - for (f = flashchips; f->name != NULL; f++, i++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) - continue; - - /* Alternate colors if the vendor changes. */ - if (old != NULL && strcmp(old->vendor, f->vendor)) - c = !c; - - t = f->tested; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " - "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", - (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, - f->total_size, flashbuses_to_text(f->bustype), - (t & TEST_OK_PROBE) ? "OK" : - (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_READ) ? "OK" : - (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_ERASE) ? "OK" : - (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_WRITE) ? "OK" : - (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); - - /* Split table into three columns. */ - if (i >= (chipcount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); - i = 0; - } - - old = f; - } - - printf("\n|}\n\n|}\n"); -} - -void print_supported_pcidevs_wiki(struct pcidev_status *devs) -{ - int i = 0; - static int c = 0; - - /* Alternate colors if the vendor changes. */ - c = !c; - - for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " - "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", - devs[i].vendor_name, devs[i].device_name, - devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? (c) ? "?2" : "?" : "OK"); - } -} - -void print_wiki_tables(void) -{ - time_t t = time(NULL); - - printf(wiki_header, ctime(&t), flashrom_version); - print_supported_chips_wiki(); - print_supported_chipsets_wiki(); - print_supported_boards_wiki(); - printf("%s", programmer_section); -#if NIC3COM_SUPPORT == 1 - print_supported_pcidevs_wiki(nics_3com); -#endif -#if DRKAISER_SUPPORT == 1 - /* FIXME: drkaiser_pcidev is missing here. */ -#endif -#if SATASII_SUPPORT == 1 - print_supported_pcidevs_wiki(satas_sii); -#endif - printf("\n|}\n"); -} - -- http://www.hailfinger.org/

2 2

[commit] r725 - trunk
by svn＠flashrom.org 16 Sep '09

16 Sep '09

Author: hailfinger Date: 2009-09-16 14:19:03 +0200 (Wed, 16 Sep 2009) New Revision: 725 Added: trunk/print_wiki.c Modified: trunk/Makefile trunk/flashrom.c trunk/print.c Log: Compile out wiki output on request and move wiki stuff into a separate file. This is useful for libflashrom (you don't need wiki output in a coreboot payload). Wiki output is now disabled by default. If you want to enable it, run make CONFIG_PRINT_WIKI=yes Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-16 10:09:21 UTC (rev 724) +++ trunk/Makefile 2009-09-16 12:19:03 UTC (rev 725) @@ -83,6 +83,9 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes +# Always enable wiki printing for now. +CONFIG_PRINT_WIKI ?= no + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -118,6 +121,11 @@ OBJS += drkaiser.o endif +ifeq ($(CONFIG_PRINT_WIKI), yes) +FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' +OBJS += print_wiki.o +endif + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-16 10:09:21 UTC (rev 724) +++ trunk/flashrom.c 2009-09-16 12:19:03 UTC (rev 725) @@ -581,7 +581,9 @@ " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" " -L | --list-supported: print supported devices\n" +#if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki: print supported devices in wiki syntax\n" +#endif " -p | --programmer <name>: specify the programmer device"); for (p = 0; p < PROGRAMMER_INVALID; p++) { @@ -634,10 +636,18 @@ int option_index = 0; int force = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int dont_verify_it = 0, list_supported = 0, list_supported_wiki = 0; + int dont_verify_it = 0, list_supported = 0; +#if CONFIG_PRINT_WIKI == 1 + int list_supported_wiki = 0; +#endif int operation_specified = 0; int ret = 0, i; +#if CONFIG_PRINT_WIKI == 1 + const char *optstring = "rRwvnVEfc:m:l:i:p:Lzh"; +#else + const char *optstring = "rRwvnVEfc:m:l:i:p:Lh"; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, {"write", 0, 0, 'w'}, @@ -651,7 +661,9 @@ {"layout", 1, 0, 'l'}, {"image", 1, 0, 'i'}, {"list-supported", 0, 0, 'L'}, +#if CONFIG_PRINT_WIKI == 1 {"list-supported-wiki", 0, 0, 'z'}, +#endif {"programmer", 1, 0, 'p'}, {"help", 0, 0, 'h'}, {"version", 0, 0, 'R'}, @@ -683,7 +695,7 @@ } setbuf(stdout, NULL); - while ((opt = getopt_long(argc, argv, "rRwvnVEfc:m:l:i:p:Lzh", + while ((opt = getopt_long(argc, argv, optstring, long_options, &option_index)) != EOF) { switch (opt) { case 'r': @@ -754,9 +766,11 @@ case 'L': list_supported = 1; break; +#if CONFIG_PRINT_WIKI == 1 case 'z': list_supported_wiki = 1; break; +#endif case 'p': for (programmer = 0; programmer < PROGRAMMER_INVALID; programmer++) { name = programmer_table[programmer].name; @@ -813,10 +827,12 @@ exit(0); } +#if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { print_wiki_tables(); exit(0); } +#endif if (read_it && write_it) { printf("Error: -r and -w are mutually exclusive.\n"); Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-09-16 10:09:21 UTC (rev 724) +++ trunk/print.c 2009-09-16 12:19:03 UTC (rev 725) @@ -21,22 +21,9 @@ #include <string.h> #include <stdlib.h> -#include <time.h> #include "flash.h" #include "flashchips.h" -struct board_info_url { - const char *vendor; - const char *name; - const char *url; -}; - -struct board_info_notes { - const char *vendor; - const char *name; - const char *note; -}; - /* * Return a string corresponding to the bustype parameter. * Memory is obtained with malloc() and can be freed with free(). @@ -234,512 +221,3 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } - -const char *wiki_header = "= Supported devices =\n\n\ -<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ -Please do '''not''' edit these tables in the wiki directly, they are \ -generated by pasting '''flashrom -z''' output.<br />\ -'''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; - -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ -|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; - -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Status\n\n"; - -const char *board_th2 = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ -! align=\"left\" | Status\n\n"; - -const char *board_intro = "\ -\n== Supported mainboards ==\n\n\ -In general, it is very likely that flashrom works out of the box even if your \ -mainboard is not listed below.\n\nThis is a list of mainboards where we have \ -verified that they either do or do not need any special initialization to \ -make flashrom work (given flashrom supports the respective chipset and flash \ -chip), or that they do not yet work at all. If they do not work, support may \ -or may not be added later.\n\n\ -Mainboards which don't appear in the list may or may not work (we don't \ -know, someone has to give it a try). Please report any further verified \ -mainboards on the [[Mailinglist|mailing list]].\n"; - -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ -! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ -|- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ -| Probe\n| Read\n| Write\n| Erase\n\n"; - -const char *programmer_section = "\ -\n== Supported programmers ==\n\nThis is a list \ -of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ -valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ -smaller\" valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; - -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ -In general, flashing laptops is more difficult because laptops\n\n\ -* often use the flash chip for stuff besides the BIOS,\n\ -* often have special protection stuff which has to be handled by flashrom,\n\ -* often use flash translation circuits which need drivers in flashrom.\n\n\ -<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#ff6666; align:right; border:1px solid #000000;\">\n\ -'''IMPORTANT:''' At this point we recommend to '''not''' use flashrom on \ -untested laptops unless you have a means to recover from a flashing that goes \ -wrong (a working backup flash chip and/or good soldering skills).\n</div>\n"; - -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_url boards_url[] = { - /* Verified working boards that don't need write-enables. */ - { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, - { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, - { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, - { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, - { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, - { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, - { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, - { "ASUS", "A7V8X-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=64&l4=0&model=229&modelm…" }, - { "ASUS", "A8N-E", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&model…" }, - { "ASUS", "A8NE-FM/S", "http://www.hardwareschotte.de/hardware/preise/proid_1266090/preis_ASUS+A8NE…" }, - { "ASUS", "A8N-SLI", "http://asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK" }, - { "ASUS", "A8N-SLI Premium", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=148&l4=0&model=539&model…" }, - { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU" }, - { "ASUS", "A8V-E Deluxe", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&model…" }, - { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, - { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, - { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, - { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, - { "ASUS", "M2V", "http://asus.com/Product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, - { "ASUS", "P2B", "http://www.motherboard.cz/mb/asus/P2B.htm" }, - { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, - { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, - { "ASUS", "P2B-F", "http://www.motherboard.cz/mb/asus/P2B-F.htm" }, - { "ASUS", "P2L97-S", "http://www.motherboard.cz/mb/asus/P2L97-S.htm" }, - { "ASUS", "P5B-Deluxe", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-Deluxe/" }, - { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, - { "ASUS", "P5L-MX", "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH" }, - { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, - { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, - { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, - { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, - { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, - { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "Intel", "EP80759", NULL }, - { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, - { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, - { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, - { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, - { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, - { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, - { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, - { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, - { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, - { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" }, - { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm" }, - { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm" }, - { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm" }, - { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, - { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, - { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, - { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, - { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, - { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, - { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610" }, - { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html" }, - { "Tyan", "S2466", "http://www.tyan.com/product_board_detail.aspx?pid=461" }, - { "Tyan", "S2881", "http://www.tyan.com/product_board_detail.aspx?pid=115" }, - { "Tyan", "S2882", "http://www.tyan.com/product_board_detail.aspx?pid=121" }, - { "Tyan", "S2882-D", "http://www.tyan.com/product_board_detail.aspx?pid=127" }, - { "Tyan", "S2891", "http://www.tyan.com/product_board_detail.aspx?pid=144" }, - { "Tyan", "S2892", "http://www.tyan.com/product_board_detail.aspx?pid=145" }, - { "Tyan", "S2895", "http://www.tyan.com/archive/products/html/thunderk8we.html" }, - { "Tyan", "S3095", "http://www.tyan.com/product_board_detail.aspx?pid=181" }, - { "Tyan", "S5180", "http://www.tyan.com/product_board_detail.aspx?pid=456" }, - { "Tyan", "S5191", "http://www.tyan.com/product_board_detail.aspx?pid=343" }, - { "Tyan", "S5197", "http://www.tyan.com/product_board_detail.aspx?pid=349" }, - { "Tyan", "S5211", "http://www.tyan.com/product_board_detail.aspx?pid=591" }, - { "Tyan", "S5211-1U", "http://www.tyan.com/product_board_detail.aspx?pid=593" }, - { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597" }, - { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566" }, - { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605" }, - { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…" }, - { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, - { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…" }, - { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp" }, - { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - - /* Verified working boards that DO need write-enables. */ - { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, - { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, - { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ - { "AOpen", "vKM400Am-S", "http://usa.aopen.com/products_detail.aspx?Auno=824" }, - { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, - { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, - { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k" }, - { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, - { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, - { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g" }, - { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, - { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, - { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, - { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, - { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, - { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, - { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, - { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ - { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ - { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…" }, - { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html" }, - { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm" }, - { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, - { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, - { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, - { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msicomputer.com/product/p_spec.asp?model=KT4_Ultra&class=mb" }, - { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msicomputer.com/product/p_spec.asp?model=K8T_Neo2-F&class=mb" }, - { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, - { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, - { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=170&maincat_no=1" }, - { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, - { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, - { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, - { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-MII link for now */ - { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ - { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, - - /* Verified non-working boards (for now). */ - { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, - { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, - { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm" }, - { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/" }, - { "ASUS", "P5B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/" }, - { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/" }, - { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, - { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, - { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…" }, - { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, - { "MSI", "MS-6178", "http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no…" }, - { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255" }, - { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English" }, - { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/" }, - { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, - { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, - { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, - - /* Verified working laptops. */ - { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…" }, - - /* Verified non-working laptops (for now). */ - { "Acer", "Aspire One", NULL }, - { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, - { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, - { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, - { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, - { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, - - { NULL, NULL, 0 }, -}; - -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_notes boards_notes[] = { - /* Verified working boards that don't need write-enables. */ - { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, - { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, - { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, - { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, - { "GIGABYTE", "GA-7ZM", "Works fine iff you remove jumper JP9 on the board and disable the flash protection BIOS option." }, - - /* Verified working boards that DO need write-enables. */ - { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, - - /* Verified non-working boards (for now). */ - { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, - { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, - - /* Verified working laptops. */ - /* None which need comments, yet... */ - - /* Verified non-working laptops (for now). */ - { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, - { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, - { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, - { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, - { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, - - { NULL, NULL, 0 }, -}; - -static int url(const char *vendor, const char *board) -{ - int i; - const struct board_info_url *b = boards_url; - - for (i = 0; b[i].vendor != NULL; i++) { - if (!strcmp(vendor, b[i].vendor) && !strcmp(board, b[i].name)) - return i; - } - - return -1; -} - -static int note(const char *vendor, const char *board) -{ - int i; - const struct board_info_notes *n = boards_notes; - - for (i = 0; n[i].vendor != NULL; i++) { - if (!strcmp(vendor, n[i].vendor) && !strcmp(board, n[i].name)) - return i; - } - - return -1; -} - -void print_supported_chipsets_wiki(void) -{ - int i, j, enablescount = 0, color = 1; - const struct penable *e; - - for (e = chipset_enables; e->vendor_name != NULL; e++) - enablescount++; - - printf("\n== Supported chipsets ==\n\nTotal amount of supported " - "chipsets: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n| " - "valign=\"top\"|\n\n%s", enablescount, chipset_th); - - e = chipset_enables; - for (i = 0, j = 0; e[i].vendor_name != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(e[i].vendor_name, e[i - 1].vendor_name)) - color = !color; - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " - "|| %04x:%04x || %s\n", (color) ? "eeeeee" : "dddddd", - e[i].vendor_name, e[i].device_name, - e[i].vendor_id, e[i].device_id, - (e[i].status == OK) ? "{{OK}}" : "?"); - - /* Split table in three columns. */ - if (j >= (enablescount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); -} - -static void wiki_helper(const char *heading, const char *status, - int cols, const struct board_info boards[]) -{ - int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; - const struct board_info *b; - const struct board_info_url *u = boards_url; - char *notes = calloc(1, 1); - char tmp[900 + 1]; - - for (b = boards; b->vendor != NULL; b++) - boardcount++; - - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" - "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th); - - for (i = 0, j = 0, b = boards; b[i].vendor != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor, b[i - 1].vendor)) - color = !color; - - k = url(b[i].vendor, b[i].name); - c = note(b[i].vendor, b[i].name); - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" - " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, - (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", - b[i].name, (k != -1 && u[k].url) ? "]" : "", status); - - if (c != -1) { - printf("<sup>%d</sup>\n", num_notes + 1); - snprintf((char *)&tmp, 900, "<sup>%d</sup> %s<br />\n", - 1 + num_notes++, boards_notes[c].note); - notes = strcat_realloc(notes, (char *)&tmp); - } else { - printf("\n"); - } - - /* Split table in 'cols' columns. */ - if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); - - if (num_notes > 0) - printf("\n<small>\n%s</small>\n", notes); - free(notes); -} - -static void wiki_helper2(const char *heading, int cols) -{ - int i, j, k, boardcount = 0, color = 1; - struct board_pciid_enable *b; - const struct board_info_url *u = boards_url; - - for (b = board_pciid_enables; b->vendor_name != NULL; b++) - boardcount++; - - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" - "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th2); - - b = board_pciid_enables; - for (i = 0, j = 0; b[i].vendor_name != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) - color = !color; - - k = url(b[i].vendor_name, b[i].board_name); - - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " - "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", - b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, - (k != -1 && u[k].url) ? "]" : "", - (b[i].lb_vendor) ? "-m " : "—", - (b[i].lb_vendor) ? b[i].lb_vendor : "", - (b[i].lb_vendor) ? ":" : "", - (b[i].lb_vendor) ? b[i].lb_part : ""); - - /* Split table in three columns. */ - if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); -} - -void print_supported_boards_wiki(void) -{ - printf("%s", board_intro); - wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); - wiki_helper2("Known good (with write-enable code in flashrom)", 3); - wiki_helper("Not supported (yet)", "No", 3, boards_bad); - - printf("%s", laptop_intro); - wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); - wiki_helper("Not supported (yet)", "No", 1, laptops_bad); -} - -void print_supported_chips_wiki(void) -{ - int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; - uint32_t t; - - for (f = flashchips; f->name != NULL; f++) - chipcount++; - - printf("\n== Supported chips ==\n\nTotal amount of supported " - "chips: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n" - "| valign=\"top\"|\n\n%s", chipcount, chip_th); - - for (f = flashchips; f->name != NULL; f++, i++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) - continue; - - /* Alternate colors if the vendor changes. */ - if (old != NULL && strcmp(old->vendor, f->vendor)) - c = !c; - - t = f->tested; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " - "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", - (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, - f->total_size, flashbuses_to_text(f->bustype), - (t & TEST_OK_PROBE) ? "OK" : - (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_READ) ? "OK" : - (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_ERASE) ? "OK" : - (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), - (t & TEST_OK_WRITE) ? "OK" : - (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); - - /* Split table into three columns. */ - if (i >= (chipcount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); - i = 0; - } - - old = f; - } - - printf("\n|}\n\n|}\n"); -} - -void print_supported_pcidevs_wiki(struct pcidev_status *devs) -{ - int i = 0; - static int c = 0; - - /* Alternate colors if the vendor changes. */ - c = !c; - - for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " - "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", - devs[i].vendor_name, devs[i].device_name, - devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? (c) ? "?2" : "?" : "OK"); - } -} - -void print_wiki_tables(void) -{ - time_t t = time(NULL); - - printf(wiki_header, ctime(&t), flashrom_version); - print_supported_chips_wiki(); - print_supported_chipsets_wiki(); - print_supported_boards_wiki(); - printf("%s", programmer_section); -#if NIC3COM_SUPPORT == 1 - print_supported_pcidevs_wiki(nics_3com); -#endif -#if DRKAISER_SUPPORT == 1 - /* FIXME: drkaiser_pcidev is missing here. */ -#endif -#if SATASII_SUPPORT == 1 - print_supported_pcidevs_wiki(satas_sii); -#endif - printf("\n|}\n"); -} - Copied: trunk/print_wiki.c (from rev 724, trunk/print.c) =================================================================== --- trunk/print_wiki.c (rev 0) +++ trunk/print_wiki.c 2009-09-16 12:19:03 UTC (rev 725) @@ -0,0 +1,547 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdlib.h> +#include <time.h> +#include "flash.h" +#include "flashchips.h" + +struct board_info_url { + const char *vendor; + const char *name; + const char *url; +}; + +struct board_info_notes { + const char *vendor; + const char *name; + const char *note; +}; + +const char *wiki_header = "= Supported devices =\n\n\ +<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ +background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ +Please do '''not''' edit these tables in the wiki directly, they are \ +generated by pasting '''flashrom -z''' output.<br />\ +'''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; + +const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ +|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ +! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ +! align=\"left\" | Status\n\n"; + +const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ +valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ +! align=\"left\" | Mainboard\n! align=\"left\" | Status\n\n"; + +const char *board_th2 = "{| border=\"0\" style=\"font-size: smaller\" \ +valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ +! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ +! align=\"left\" | Status\n\n"; + +const char *board_intro = "\ +\n== Supported mainboards ==\n\n\ +In general, it is very likely that flashrom works out of the box even if your \ +mainboard is not listed below.\n\nThis is a list of mainboards where we have \ +verified that they either do or do not need any special initialization to \ +make flashrom work (given flashrom supports the respective chipset and flash \ +chip), or that they do not yet work at all. If they do not work, support may \ +or may not be added later.\n\n\ +Mainboards which don't appear in the list may or may not work (we don't \ +know, someone has to give it a try). Please report any further verified \ +mainboards on the [[Mailinglist|mailing list]].\n"; + +const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ +valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ +! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ +! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ +|- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ +| Probe\n| Read\n| Write\n| Erase\n\n"; + +const char *programmer_section = "\ +\n== Supported programmers ==\n\nThis is a list \ +of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ +valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ +smaller\" valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ +! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ +! align=\"left\" | Status\n\n"; + +const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ +In general, flashing laptops is more difficult because laptops\n\n\ +* often use the flash chip for stuff besides the BIOS,\n\ +* often have special protection stuff which has to be handled by flashrom,\n\ +* often use flash translation circuits which need drivers in flashrom.\n\n\ +<div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ +background-color:#ff6666; align:right; border:1px solid #000000;\">\n\ +'''IMPORTANT:''' At this point we recommend to '''not''' use flashrom on \ +untested laptops unless you have a means to recover from a flashing that goes \ +wrong (a working backup flash chip and/or good soldering skills).\n</div>\n"; + +/* Please keep these lists alphabetically ordered by vendor/board. */ +const struct board_info_url boards_url[] = { + /* Verified working boards that don't need write-enables. */ + { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, + { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…" }, + { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, + { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, + { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, + { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, + { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, + { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, + { "ASUS", "A7V8X-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=64&l4=0&model=229&modelm…" }, + { "ASUS", "A8N-E", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&model…" }, + { "ASUS", "A8NE-FM/S", "http://www.hardwareschotte.de/hardware/preise/proid_1266090/preis_ASUS+A8NE…" }, + { "ASUS", "A8N-SLI", "http://asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK" }, + { "ASUS", "A8N-SLI Premium", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=148&l4=0&model=539&model…" }, + { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU" }, + { "ASUS", "A8V-E Deluxe", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&model…" }, + { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, + { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, + { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, + { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, + { "ASUS", "M2V", "http://asus.com/Product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, + { "ASUS", "P2B", "http://www.motherboard.cz/mb/asus/P2B.htm" }, + { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, + { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, + { "ASUS", "P2B-F", "http://www.motherboard.cz/mb/asus/P2B-F.htm" }, + { "ASUS", "P2L97-S", "http://www.motherboard.cz/mb/asus/P2L97-S.htm" }, + { "ASUS", "P5B-Deluxe", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-Deluxe/" }, + { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, + { "ASUS", "P5L-MX", "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH" }, + { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, + { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, + { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, + { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, + { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, + { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, + { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "Intel", "EP80759", NULL }, + { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, + { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, + { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, + { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, + { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, + { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, + { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, + { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, + { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, + { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" }, + { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm" }, + { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm" }, + { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm" }, + { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, + { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, + { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, + { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, + { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, + { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, + { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610" }, + { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html" }, + { "Tyan", "S2466", "http://www.tyan.com/product_board_detail.aspx?pid=461" }, + { "Tyan", "S2881", "http://www.tyan.com/product_board_detail.aspx?pid=115" }, + { "Tyan", "S2882", "http://www.tyan.com/product_board_detail.aspx?pid=121" }, + { "Tyan", "S2882-D", "http://www.tyan.com/product_board_detail.aspx?pid=127" }, + { "Tyan", "S2891", "http://www.tyan.com/product_board_detail.aspx?pid=144" }, + { "Tyan", "S2892", "http://www.tyan.com/product_board_detail.aspx?pid=145" }, + { "Tyan", "S2895", "http://www.tyan.com/archive/products/html/thunderk8we.html" }, + { "Tyan", "S3095", "http://www.tyan.com/product_board_detail.aspx?pid=181" }, + { "Tyan", "S5180", "http://www.tyan.com/product_board_detail.aspx?pid=456" }, + { "Tyan", "S5191", "http://www.tyan.com/product_board_detail.aspx?pid=343" }, + { "Tyan", "S5197", "http://www.tyan.com/product_board_detail.aspx?pid=349" }, + { "Tyan", "S5211", "http://www.tyan.com/product_board_detail.aspx?pid=591" }, + { "Tyan", "S5211-1U", "http://www.tyan.com/product_board_detail.aspx?pid=593" }, + { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597" }, + { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566" }, + { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605" }, + { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…" }, + { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, + { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, + { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, + { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…" }, + { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, + { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, + { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp" }, + { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, + + /* Verified working boards that DO need write-enables. */ + { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, + { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, + { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ + { "AOpen", "vKM400Am-S", "http://usa.aopen.com/products_detail.aspx?Auno=824" }, + { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, + { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, + { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k" }, + { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, + { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, + { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g" }, + { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, + { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, + { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, + { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, + { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, + { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, + { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, + { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ + { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ + { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…" }, + { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html" }, + { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm" }, + { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, + { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, + { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, + { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msicomputer.com/product/p_spec.asp?model=KT4_Ultra&class=mb" }, + { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msicomputer.com/product/p_spec.asp?model=K8T_Neo2-F&class=mb" }, + { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, + { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, + { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=170&maincat_no=1" }, + { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, + { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, + { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, + { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, + { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-MII link for now */ + { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ + { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, + { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, + + /* Verified non-working boards (for now). */ + { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, + { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, + { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, + { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm" }, + { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/" }, + { "ASUS", "P5B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/" }, + { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/" }, + { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, + { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, + { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…" }, + { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, + { "MSI", "MS-6178", "http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no…" }, + { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255" }, + { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English" }, + { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/" }, + { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, + { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, + { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, + + /* Verified working laptops. */ + { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…" }, + + /* Verified non-working laptops (for now). */ + { "Acer", "Aspire One", NULL }, + { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, + { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, + { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, + { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, + { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, + + { NULL, NULL, 0 }, +}; + +/* Please keep these lists alphabetically ordered by vendor/board. */ +const struct board_info_notes boards_notes[] = { + /* Verified working boards that don't need write-enables. */ + { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, + { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, + { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, + { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, + { "GIGABYTE", "GA-7ZM", "Works fine iff you remove jumper JP9 on the board and disable the flash protection BIOS option." }, + + /* Verified working boards that DO need write-enables. */ + { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, + + /* Verified non-working boards (for now). */ + { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, + { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, + + /* Verified working laptops. */ + /* None which need comments, yet... */ + + /* Verified non-working laptops (for now). */ + { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, + { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, + { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, + { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, + { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, + + { NULL, NULL, 0 }, +}; + +static int url(const char *vendor, const char *board) +{ + int i; + const struct board_info_url *b = boards_url; + + for (i = 0; b[i].vendor != NULL; i++) { + if (!strcmp(vendor, b[i].vendor) && !strcmp(board, b[i].name)) + return i; + } + + return -1; +} + +static int note(const char *vendor, const char *board) +{ + int i; + const struct board_info_notes *n = boards_notes; + + for (i = 0; n[i].vendor != NULL; i++) { + if (!strcmp(vendor, n[i].vendor) && !strcmp(board, n[i].name)) + return i; + } + + return -1; +} + +void print_supported_chipsets_wiki(void) +{ + int i, j, enablescount = 0, color = 1; + const struct penable *e; + + for (e = chipset_enables; e->vendor_name != NULL; e++) + enablescount++; + + printf("\n== Supported chipsets ==\n\nTotal amount of supported " + "chipsets: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n| " + "valign=\"top\"|\n\n%s", enablescount, chipset_th); + + e = chipset_enables; + for (i = 0, j = 0; e[i].vendor_name != NULL; i++, j++) { + /* Alternate colors if the vendor changes. */ + if (i > 0 && strcmp(e[i].vendor_name, e[i - 1].vendor_name)) + color = !color; + + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " + "|| %04x:%04x || %s\n", (color) ? "eeeeee" : "dddddd", + e[i].vendor_name, e[i].device_name, + e[i].vendor_id, e[i].device_id, + (e[i].status == OK) ? "{{OK}}" : "?"); + + /* Split table in three columns. */ + if (j >= (enablescount / 3 + 1)) { + printf("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); + j = 0; + } + } + + printf("\n|}\n\n|}\n"); +} + +static void wiki_helper(const char *heading, const char *status, + int cols, const struct board_info boards[]) +{ + int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; + const struct board_info *b; + const struct board_info_url *u = boards_url; + char *notes = calloc(1, 1); + char tmp[900 + 1]; + + for (b = boards; b->vendor != NULL; b++) + boardcount++; + + printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" + "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", + heading, boardcount, board_th); + + for (i = 0, j = 0, b = boards; b[i].vendor != NULL; i++, j++) { + /* Alternate colors if the vendor changes. */ + if (i > 0 && strcmp(b[i].vendor, b[i - 1].vendor)) + color = !color; + + k = url(b[i].vendor, b[i].name); + c = note(b[i].vendor, b[i].name); + + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" + " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, + (k != -1 && u[k].url) ? "[" : "", + (k != -1 && u[k].url) ? u[k].url : "", + b[i].name, (k != -1 && u[k].url) ? "]" : "", status); + + if (c != -1) { + printf("<sup>%d</sup>\n", num_notes + 1); + snprintf((char *)&tmp, 900, "<sup>%d</sup> %s<br />\n", + 1 + num_notes++, boards_notes[c].note); + notes = strcat_realloc(notes, (char *)&tmp); + } else { + printf("\n"); + } + + /* Split table in 'cols' columns. */ + if (j >= (boardcount / cols + 1)) { + printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th); + j = 0; + } + } + + printf("\n|}\n\n|}\n"); + + if (num_notes > 0) + printf("\n<small>\n%s</small>\n", notes); + free(notes); +} + +static void wiki_helper2(const char *heading, int cols) +{ + int i, j, k, boardcount = 0, color = 1; + struct board_pciid_enable *b; + const struct board_info_url *u = boards_url; + + for (b = board_pciid_enables; b->vendor_name != NULL; b++) + boardcount++; + + printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" + "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", + heading, boardcount, board_th2); + + b = board_pciid_enables; + for (i = 0, j = 0; b[i].vendor_name != NULL; i++, j++) { + /* Alternate colors if the vendor changes. */ + if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) + color = !color; + + k = url(b[i].vendor_name, b[i].board_name); + + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " + "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", + b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", + (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, + (k != -1 && u[k].url) ? "]" : "", + (b[i].lb_vendor) ? "-m " : "—", + (b[i].lb_vendor) ? b[i].lb_vendor : "", + (b[i].lb_vendor) ? ":" : "", + (b[i].lb_vendor) ? b[i].lb_part : ""); + + /* Split table in three columns. */ + if (j >= (boardcount / cols + 1)) { + printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); + j = 0; + } + } + + printf("\n|}\n\n|}\n"); +} + +void print_supported_boards_wiki(void) +{ + printf("%s", board_intro); + wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); + wiki_helper2("Known good (with write-enable code in flashrom)", 3); + wiki_helper("Not supported (yet)", "No", 3, boards_bad); + + printf("%s", laptop_intro); + wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); + wiki_helper("Not supported (yet)", "No", 1, laptops_bad); +} + +void print_supported_chips_wiki(void) +{ + int i = 0, c = 1, chipcount = 0; + struct flashchip *f, *old = NULL; + uint32_t t; + + for (f = flashchips; f->name != NULL; f++) + chipcount++; + + printf("\n== Supported chips ==\n\nTotal amount of supported " + "chips: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n" + "| valign=\"top\"|\n\n%s", chipcount, chip_th); + + for (f = flashchips; f->name != NULL; f++, i++) { + /* Don't print "unknown XXXX SPI chip" entries. */ + if (!strncmp(f->name, "unknown", 7)) + continue; + + /* Alternate colors if the vendor changes. */ + if (old != NULL && strcmp(old->vendor, f->vendor)) + c = !c; + + t = f->tested; + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " + "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", + (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, + f->total_size, flashbuses_to_text(f->bustype), + (t & TEST_OK_PROBE) ? "OK" : + (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_READ) ? "OK" : + (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_ERASE) ? "OK" : + (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_OK_WRITE) ? "OK" : + (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); + + /* Split table into three columns. */ + if (i >= (chipcount / 3 + 1)) { + printf("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); + i = 0; + } + + old = f; + } + + printf("\n|}\n\n|}\n"); +} + +void print_supported_pcidevs_wiki(struct pcidev_status *devs) +{ + int i = 0; + static int c = 0; + + /* Alternate colors if the vendor changes. */ + c = !c; + + for (i = 0; devs[i].vendor_name != NULL; i++) { + printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " + "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", + devs[i].vendor_name, devs[i].device_name, + devs[i].vendor_id, devs[i].device_id, + (devs[i].status == PCI_NT) ? (c) ? "?2" : "?" : "OK"); + } +} + +void print_wiki_tables(void) +{ + time_t t = time(NULL); + + printf(wiki_header, ctime(&t), flashrom_version); + print_supported_chips_wiki(); + print_supported_chipsets_wiki(); + print_supported_boards_wiki(); + printf("%s", programmer_section); +#if NIC3COM_SUPPORT == 1 + print_supported_pcidevs_wiki(nics_3com); +#endif +#if DRKAISER_SUPPORT == 1 + /* FIXME: drkaiser_pcidev is missing here. */ +#endif +#if SATASII_SUPPORT == 1 + print_supported_pcidevs_wiki(satas_sii); +#endif + printf("\n|}\n"); +} +

1 0

[PATCH] Compile out external programmers on request
by Carl-Daniel Hailfinger 16 Sep '09

16 Sep '09

Allow to exclude each of the external programmer drivers from being compiled in. Example make commandline if you want only internal programmers: make CONFIG_FT2232SPI=no CONFIG_SERPROG=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_DUMMY=no Of course, all of the CONFIG_* symbols can be mixed and matched as needed. CONFIG_FT2232SPI is special because even if it is enabled, make will check if the headers are available and skip it otherwise. Compilation for all combinations works for me, and the internal consistency checks of flashrom are happy as well. We probably should think about outsourcing ft2232spi probing and libpci probing and make variable setting to a small configure script. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-external_compileout/flash.h =================================================================== --- flashrom-external_compileout/flash.h (Revision 721) +++ flashrom-external_compileout/flash.h (Arbeitskopie) @@ -82,10 +82,18 @@ enum programmer { PROGRAMMER_INTERNAL, +#if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, +#endif +#if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, +#endif +#if DRKAISER_SUPPORT == 1 PROGRAMMER_DRKAISER, +#endif +#if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, +#endif PROGRAMMER_IT87SPI, #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, @@ -375,10 +383,11 @@ uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); void internal_delay(int usecs); -int fallback_shutdown(void); +int noop_shutdown(void); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); -void fallback_chip_writeb(uint8_t val, chipaddr addr); +uint8_t noop_chip_readb(const chipaddr addr); +void noop_chip_writeb(uint8_t val, chipaddr addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); @@ -474,7 +483,9 @@ #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif +#if DUMMY_SUPPORT == 1 SPI_CONTROLLER_DUMMY, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; Index: flashrom-external_compileout/spi.c =================================================================== --- flashrom-external_compileout/spi.c (Revision 721) +++ flashrom-external_compileout/spi.c (Arbeitskopie) @@ -91,12 +91,14 @@ }, #endif +#if DUMMY_SUPPORT == 1 { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, .read = NULL, .write_256 = NULL, }, +#endif {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; @@ -301,7 +303,9 @@ #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif +#if DUMMY_SUPPORT == 1 case SPI_CONTROLLER_DUMMY: +#endif return probe_spi_rdid_generic(flash, 4); default: printf_debug("4b ID not supported on this SPI controller\n"); Index: flashrom-external_compileout/Makefile =================================================================== --- flashrom-external_compileout/Makefile (Revision 721) +++ flashrom-external_compileout/Makefile (Arbeitskopie) @@ -49,8 +49,7 @@ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - dummyflasher.o pcidev.o nic3com.o satasii.o ft2232_spi.o \ - print.o drkaiser.o + pcidev.o print.o all: pciutils features dep $(PROGRAM) @@ -67,8 +66,23 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' # Always enable serprog for now. Needs to be disabled on Windows. -CONFIG_SERPROG = yes +CONFIG_SERPROG ?= yes +# Always enable 3Com NICs for now. +CONFIG_NIC3COM ?= yes + +# Always enable SiI SATA controllers for now. +CONFIG_SATASII ?= yes + +# Always enable FT2232 SPI dongles for now. +CONFIG_FT2232SPI ?= yes + +# Always enable dummy tracing for now. +CONFIG_DUMMY ?= yes + +# Always enable Dr. Kaiser for now. +CONFIG_DRKAISER ?= yes + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -77,10 +91,33 @@ endif endif +ifeq ($(CONFIG_NIC3COM), yes) +FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' +OBJS += nic3com.o +endif + +ifeq ($(CONFIG_SATASII), yes) +FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' +OBJS += satasii.o +endif + +ifeq ($(CONFIG_FT2232SPI), yes) +# This is a totally ugly hack. FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") - FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +OBJS += ft2232_spi.o +endif +ifeq ($(CONFIG_DUMMY), yes) +FEATURE_CFLAGS += -D'DUMMY_SUPPORT=1' +OBJS += dummyflasher.o +endif + +ifeq ($(CONFIG_DRKAISER), yes) +FEATURE_CFLAGS += -D'DRKAISER_SUPPORT=1' +OBJS += drkaiser.o +endif + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) Index: flashrom-external_compileout/flashrom.c =================================================================== --- flashrom-external_compileout/flashrom.c (Revision 721) +++ flashrom-external_compileout/flashrom.c (Arbeitskopie) @@ -54,6 +54,7 @@ .delay = internal_delay, }, +#if DUMMY_SUPPORT == 1 { .name = "dummy", .init = dummy_init, @@ -70,7 +71,9 @@ .chip_writen = dummy_chip_writen, .delay = internal_delay, }, +#endif +#if NIC3COM_SUPPORT == 1 { .name = "nic3com", .init = nic3com_init, @@ -87,7 +90,9 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif +#if DRKAISER_SUPPORT == 1 { .name = "drkaiser", .init = drkaiser_init, @@ -104,7 +109,9 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif +#if SATASII_SUPPORT == 1 { .name = "satasii", .init = satasii_init, @@ -121,18 +128,19 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif { .name = "it87spi", .init = it87spi_init, - .shutdown = fallback_shutdown, + .shutdown = noop_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = dummy_chip_readb, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = fallback_chip_writeb, + .chip_writeb = noop_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, @@ -143,14 +151,14 @@ { .name = "ft2232spi", .init = ft2232_spi_init, - .shutdown = fallback_shutdown, + .shutdown = noop_shutdown, /* Missing shutdown */ .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = dummy_chip_readb, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = fallback_chip_writeb, + .chip_writeb = noop_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, @@ -793,9 +801,15 @@ print_supported_boards(); printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); +#if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); +#endif +#if DRKAISER_SUPPORT == 1 print_supported_pcidevs(drkaiser_pcidev); +#endif +#if SATASII_SUPPORT == 1 print_supported_pcidevs(satas_sii); +#endif exit(0); } Index: flashrom-external_compileout/internal.c =================================================================== --- flashrom-external_compileout/internal.c (Revision 721) +++ flashrom-external_compileout/internal.c (Arbeitskopie) @@ -222,8 +222,8 @@ } } -/* Fallback shutdown() for programmers which don't need special handling */ -int fallback_shutdown(void) +/* No-op shutdown() for programmers which don't need special handling */ +int noop_shutdown(void) { return 0; } @@ -231,19 +231,26 @@ /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { + /* FIXME: Should return phys_addr. */ return 0; } -/* Fallback unmap() for programmers which don't need special handling */ +/* No-op/fallback unmap() for programmers which don't need special handling */ void fallback_unmap(void *virt_addr, size_t len) { } -/* No-op fallback for drivers not supporting addr/data pair accesses */ -void fallback_chip_writeb(uint8_t val, chipaddr addr) +/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ +uint8_t noop_chip_readb(const chipaddr addr) { + return 0xff; } +/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ +void noop_chip_writeb(uint8_t val, chipaddr addr) +{ +} + /* Little-endian fallback for drivers not supporting 16 bit accesses */ void fallback_chip_writew(uint16_t val, chipaddr addr) { Index: flashrom-external_compileout/print.c =================================================================== --- flashrom-external_compileout/print.c (Revision 721) +++ flashrom-external_compileout/print.c (Arbeitskopie) @@ -731,8 +731,15 @@ print_supported_chipsets_wiki(); print_supported_boards_wiki(); printf("%s", programmer_section); +#if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); +#endif +#if DRKAISER_SUPPORT == 1 + /* FIXME: drkaiser_pcidev is missing here. */ +#endif +#if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii); +#endif printf("\n|}\n"); } -- http://www.hailfinger.org/

3 4

[commit] r724 - trunk
by svn＠flashrom.org 16 Sep '09

16 Sep '09

Author: hailfinger Date: 2009-09-16 12:09:21 +0200 (Wed, 16 Sep 2009) New Revision: 724 Modified: trunk/Makefile trunk/flash.h trunk/flashrom.c trunk/internal.c trunk/print.c trunk/spi.c Log: Allow to exclude each of the external programmer drivers from being compiled in. Example make commandline if you want only internal programmers: make CONFIG_FT2232SPI=no CONFIG_SERPROG=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_DUMMY=no Of course, all of the CONFIG_* symbols can be mixed and matched as needed. CONFIG_FT2232SPI is special because even if it is enabled, make will check if the headers are available and skip it otherwise. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/Makefile 2009-09-16 10:09:21 UTC (rev 724) @@ -49,8 +49,7 @@ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - dummyflasher.o pcidev.o nic3com.o satasii.o ft2232_spi.o \ - print.o drkaiser.o + pcidev.o print.o all: pciutils features dep $(PROGRAM) @@ -67,8 +66,23 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' # Always enable serprog for now. Needs to be disabled on Windows. -CONFIG_SERPROG = yes +CONFIG_SERPROG ?= yes +# Always enable 3Com NICs for now. +CONFIG_NIC3COM ?= yes + +# Always enable SiI SATA controllers for now. +CONFIG_SATASII ?= yes + +# Always enable FT2232 SPI dongles for now. +CONFIG_FT2232SPI ?= yes + +# Always enable dummy tracing for now. +CONFIG_DUMMY ?= yes + +# Always enable Dr. Kaiser for now. +CONFIG_DRKAISER ?= yes + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -77,10 +91,33 @@ endif endif +ifeq ($(CONFIG_NIC3COM), yes) +FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' +OBJS += nic3com.o +endif + +ifeq ($(CONFIG_SATASII), yes) +FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' +OBJS += satasii.o +endif + +ifeq ($(CONFIG_FT2232SPI), yes) +# This is a totally ugly hack. FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") - FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +OBJS += ft2232_spi.o +endif +ifeq ($(CONFIG_DUMMY), yes) +FEATURE_CFLAGS += -D'DUMMY_SUPPORT=1' +OBJS += dummyflasher.o +endif + +ifeq ($(CONFIG_DRKAISER), yes) +FEATURE_CFLAGS += -D'DRKAISER_SUPPORT=1' +OBJS += drkaiser.o +endif + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/flash.h 2009-09-16 10:09:21 UTC (rev 724) @@ -82,10 +82,18 @@ enum programmer { PROGRAMMER_INTERNAL, +#if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, +#endif +#if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, +#endif +#if DRKAISER_SUPPORT == 1 PROGRAMMER_DRKAISER, +#endif +#if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, +#endif PROGRAMMER_IT87SPI, #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, @@ -375,10 +383,11 @@ uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); void internal_delay(int usecs); -int fallback_shutdown(void); +int noop_shutdown(void); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); -void fallback_chip_writeb(uint8_t val, chipaddr addr); +uint8_t noop_chip_readb(const chipaddr addr); +void noop_chip_writeb(uint8_t val, chipaddr addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); @@ -474,7 +483,9 @@ #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif +#if DUMMY_SUPPORT == 1 SPI_CONTROLLER_DUMMY, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/flashrom.c 2009-09-16 10:09:21 UTC (rev 724) @@ -54,6 +54,7 @@ .delay = internal_delay, }, +#if DUMMY_SUPPORT == 1 { .name = "dummy", .init = dummy_init, @@ -70,7 +71,9 @@ .chip_writen = dummy_chip_writen, .delay = internal_delay, }, +#endif +#if NIC3COM_SUPPORT == 1 { .name = "nic3com", .init = nic3com_init, @@ -87,7 +90,9 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif +#if DRKAISER_SUPPORT == 1 { .name = "drkaiser", .init = drkaiser_init, @@ -104,7 +109,9 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif +#if SATASII_SUPPORT == 1 { .name = "satasii", .init = satasii_init, @@ -121,18 +128,19 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif { .name = "it87spi", .init = it87spi_init, - .shutdown = fallback_shutdown, + .shutdown = noop_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = dummy_chip_readb, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = fallback_chip_writeb, + .chip_writeb = noop_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, @@ -143,14 +151,14 @@ { .name = "ft2232spi", .init = ft2232_spi_init, - .shutdown = fallback_shutdown, + .shutdown = noop_shutdown, /* Missing shutdown */ .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = dummy_chip_readb, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = fallback_chip_writeb, + .chip_writeb = noop_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, @@ -793,9 +801,15 @@ print_supported_boards(); printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); +#if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); +#endif +#if DRKAISER_SUPPORT == 1 print_supported_pcidevs(drkaiser_pcidev); +#endif +#if SATASII_SUPPORT == 1 print_supported_pcidevs(satas_sii); +#endif exit(0); } Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/internal.c 2009-09-16 10:09:21 UTC (rev 724) @@ -222,8 +222,8 @@ } } -/* Fallback shutdown() for programmers which don't need special handling */ -int fallback_shutdown(void) +/* No-op shutdown() for programmers which don't need special handling */ +int noop_shutdown(void) { return 0; } @@ -231,19 +231,26 @@ /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { + /* FIXME: Should return phys_addr. */ return 0; } -/* Fallback unmap() for programmers which don't need special handling */ +/* No-op/fallback unmap() for programmers which don't need special handling */ void fallback_unmap(void *virt_addr, size_t len) { } -/* No-op fallback for drivers not supporting addr/data pair accesses */ -void fallback_chip_writeb(uint8_t val, chipaddr addr) +/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ +uint8_t noop_chip_readb(const chipaddr addr) { + return 0xff; } +/* No-op chip_writeb() for drivers not supporting addr/data pair accesses */ +void noop_chip_writeb(uint8_t val, chipaddr addr) +{ +} + /* Little-endian fallback for drivers not supporting 16 bit accesses */ void fallback_chip_writew(uint16_t val, chipaddr addr) { Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/print.c 2009-09-16 10:09:21 UTC (rev 724) @@ -731,8 +731,15 @@ print_supported_chipsets_wiki(); print_supported_boards_wiki(); printf("%s", programmer_section); +#if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); +#endif +#if DRKAISER_SUPPORT == 1 + /* FIXME: drkaiser_pcidev is missing here. */ +#endif +#if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii); +#endif printf("\n|}\n"); } Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-09-16 08:26:59 UTC (rev 723) +++ trunk/spi.c 2009-09-16 10:09:21 UTC (rev 724) @@ -91,12 +91,14 @@ }, #endif +#if DUMMY_SUPPORT == 1 { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, .read = NULL, .write_256 = NULL, }, +#endif {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; @@ -301,7 +303,9 @@ #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif +#if DUMMY_SUPPORT == 1 case SPI_CONTROLLER_DUMMY: +#endif return probe_spi_rdid_generic(flash, 4); default: printf_debug("4b ID not supported on this SPI controller\n");

1 0

[PATCH] LLVM/clang code review
by Stefan Reinauer 16 Sep '09

16 Sep '09

Hi, this patch fixes all 27 flashrom source code issues reported by LLVM/clang's scan-build (r79326, new build on the way). Temporary URL of the findings: http://coresystems.de/~stepan/flashrom-scanbuild/ Stefan This patch cleans up flashrom so that it passes LLVM/clang's scan-build without warnings. It also drops a completely unnecessary goto in ft2232_spi.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: serprog.c =================================================================== --- serprog.c (revision 721) +++ serprog.c (working copy) @@ -95,7 +95,7 @@ whether the command is supported before doing it */ static int sp_check_avail_automatic = 0; -static void sp_die(char *msg) +static void __attribute__((noreturn)) sp_die(char *msg) { perror(msg); exit(1); Index: sharplhf00l04.c =================================================================== --- sharplhf00l04.c (revision 721) +++ sharplhf00l04.c (working copy) @@ -73,7 +73,6 @@ uint8_t wait_lhf00l04(chipaddr bios) { uint8_t status; - uint8_t id1, id2; chip_writeb(0x70, bios); if ((chip_readb(bios) & 0x80) == 0) { // it's busy @@ -82,13 +81,13 @@ status = chip_readb(bios); - // put another command to get out of status register mode + // put another command to get out of status register mode. chip_writeb(0x90, bios); programmer_delay(10); - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + chip_readb(bios); // vendor ID + chip_readb(bios + 0x01); // device ID // this is needed to jam it out of "read id" mode chip_writeb(0xAA, bios + 0x5555); Index: ft2232_spi.c =================================================================== --- ft2232_spi.c (revision 721) +++ ft2232_spi.c (working copy) @@ -70,7 +70,6 @@ int f; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; - unsigned char port_val = 0; char *portpos = NULL; int ft2232_type = FTDI_FT4232H; enum ftdi_interface ft2232_interface = INTERFACE_B; @@ -175,9 +174,8 @@ * dir: 0x0b CS=output, DI=input, DO=output, SK=output */ #define CS_BIT 0x08 - buf[0] = SET_BITS_LOW; - buf[1] = (port_val = CS_BIT); + buf[1] = CS_BIT; buf[2] = 0x0b; if (send_buf(ftdic, buf, 3)) return -1; @@ -195,7 +193,6 @@ { struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; - unsigned char port_val = 0; int i, ret = 0; if (writecnt > 65536 || readcnt > 65536) @@ -213,10 +210,11 @@ * as possible together. if we're not expecting to * read, we can assert CS, write, and deassert CS all * in one shot. if reading, we do three separate - * operations. */ + * operations. + */ printf_debug("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = (port_val &= ~CS_BIT); + buf[i++] = 0 & ~CS_BIT; /* assertive */ buf[i++] = 0x0b; if (writecnt) { @@ -236,20 +234,19 @@ buf[i++] = ((readcnt - 1) >> 8) & 0xff; ret = send_buf(ftdic, buf, i); i = 0; - if (ret) goto deassert_cs; + if (ret == 0) { + /* FIXME: This is unreliable. There's no guarantee that we read + * the response directly after sending the read command. + * We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + } - /* FIXME: This is unreliable. There's no guarantee that we read - * the response directly after sending the read command. - * We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - } -deassert_cs: printf_debug("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = (port_val |= CS_BIT); + buf[i++] = CS_BIT; buf[i++] = 0x0b; if (send_buf(ftdic, buf, i)) return -1; Index: sst28sf040.c =================================================================== --- sst28sf040.c (revision 721) +++ sst28sf040.c (working copy) @@ -30,28 +30,24 @@ static void protect_28sf040(chipaddr bios) { - uint8_t tmp; - - tmp = chip_readb(bios + 0x1823); - tmp = chip_readb(bios + 0x1820); - tmp = chip_readb(bios + 0x1822); - tmp = chip_readb(bios + 0x0418); - tmp = chip_readb(bios + 0x041B); - tmp = chip_readb(bios + 0x0419); - tmp = chip_readb(bios + 0x040A); + chip_readb(bios + 0x1823); + chip_readb(bios + 0x1820); + chip_readb(bios + 0x1822); + chip_readb(bios + 0x0418); + chip_readb(bios + 0x041B); + chip_readb(bios + 0x0419); + chip_readb(bios + 0x040A); } static void unprotect_28sf040(chipaddr bios) { - uint8_t tmp; - - tmp = chip_readb(bios + 0x1823); - tmp = chip_readb(bios + 0x1820); - tmp = chip_readb(bios + 0x1822); - tmp = chip_readb(bios + 0x0418); - tmp = chip_readb(bios + 0x041B); - tmp = chip_readb(bios + 0x0419); - tmp = chip_readb(bios + 0x041A); + chip_readb(bios + 0x1823); + chip_readb(bios + 0x1820); + chip_readb(bios + 0x1822); + chip_readb(bios + 0x0418); + chip_readb(bios + 0x041B); + chip_readb(bios + 0x0419); + chip_readb(bios + 0x041A); } static int erase_sector_28sf040(struct flashchip *flash, unsigned long address, int sector_size) Index: stm50flw0x0x.c =================================================================== --- stm50flw0x0x.c (revision 721) +++ stm50flw0x0x.c (working copy) @@ -54,19 +54,17 @@ static void wait_stm50flw0x0x(chipaddr bios) { - uint8_t id1; - // id2; - chip_writeb(0x70, bios); if ((chip_readb(bios) & 0x80) == 0) { // it's busy while ((chip_readb(bios) & 0x80) == 0) ; } + // put another command to get out of status register mode chip_writeb(0x90, bios); programmer_delay(10); - id1 = chip_readb(bios); + chip_readb(bios); // Read device ID (to make sure?) // this is needed to jam it out of "read id" mode chip_writeb(0xAA, bios + 0x5555); Index: sb600spi.c =================================================================== --- sb600spi.c (revision 721) +++ sb600spi.c (working copy) @@ -64,6 +64,11 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { result = spi_byte_program(i, *buf); + if (result) { + // spi_byte_program reported the error for us already + printf_debug("... continuing anyway.\n"); + } + /* wait program complete. */ if (i % 0x8000 == 0) printf("."); Index: 82802ab.c =================================================================== --- 82802ab.c (revision 721) +++ 82802ab.c (working copy) @@ -30,16 +30,15 @@ #include <stdlib.h> #include "flash.h" -// I need that Berkeley bit-map printer void print_82802ab_status(uint8_t status) { - printf("%s", status & 0x80 ? "Ready:" : "Busy:"); - printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); - printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); - printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); - printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); - printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); - printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); + printf_debug("%s", status & 0x80 ? "Ready:" : "Busy:"); + printf_debug("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); + printf_debug("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); + printf_debug("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); + printf_debug("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); + printf_debug("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); + printf_debug("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); } int probe_82802ab(struct flashchip *flash) @@ -98,20 +97,19 @@ // clear status register chip_writeb(0x50, bios); - //printf("Erase at %p\n", bios); + // clear write protect - //printf("write protect is at %p\n", (wrprotect)); - //printf("write protect is 0x%x\n", *(wrprotect)); chip_writeb(0, wrprotect); - //printf("write protect is 0x%x\n", *(wrprotect)); // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); programmer_delay(10); + // now let's see what the register is status = wait_82802ab(flash->virtual_memory); - //print_82802ab_status(status); + print_82802ab_status(status); + if (check_erased_range(flash, offset, flash->page_size)) { fprintf(stderr, "ERASE FAILED!\n"); return -1;

4 9

[commit] r723 - trunk
by svn＠flashrom.org 16 Sep '09

16 Sep '09

Author: stepan Date: 2009-09-16 10:26:59 +0200 (Wed, 16 Sep 2009) New Revision: 723 Modified: trunk/82802ab.c trunk/ft2232_spi.c trunk/sb600spi.c Log: This patch cleans up flashrom so that it passes LLVM/clang's scan-build without warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/82802ab.c =================================================================== --- trunk/82802ab.c 2009-09-16 08:18:08 UTC (rev 722) +++ trunk/82802ab.c 2009-09-16 08:26:59 UTC (rev 723) @@ -33,13 +33,13 @@ // I need that Berkeley bit-map printer void print_82802ab_status(uint8_t status) { - printf("%s", status & 0x80 ? "Ready:" : "Busy:"); - printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); - printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); - printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); - printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); - printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); - printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); + printf_debug("%s", status & 0x80 ? "Ready:" : "Busy:"); + printf_debug("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); + printf_debug("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); + printf_debug("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); + printf_debug("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); + printf_debug("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); + printf_debug("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); } int probe_82802ab(struct flashchip *flash) @@ -98,20 +98,19 @@ // clear status register chip_writeb(0x50, bios); - //printf("Erase at %p\n", bios); + // clear write protect - //printf("write protect is at %p\n", (wrprotect)); - //printf("write protect is 0x%x\n", *(wrprotect)); chip_writeb(0, wrprotect); - //printf("write protect is 0x%x\n", *(wrprotect)); // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); programmer_delay(10); + // now let's see what the register is status = wait_82802ab(flash->virtual_memory); - //print_82802ab_status(status); + print_82802ab_status(status); + if (check_erased_range(flash, offset, flash->page_size)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-09-16 08:18:08 UTC (rev 722) +++ trunk/ft2232_spi.c 2009-09-16 08:26:59 UTC (rev 723) @@ -70,7 +70,6 @@ int f; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; - unsigned char port_val = 0; char *portpos = NULL; int ft2232_type = FTDI_FT4232H; enum ftdi_interface ft2232_interface = INTERFACE_B; @@ -175,9 +174,8 @@ * dir: 0x0b CS=output, DI=input, DO=output, SK=output */ #define CS_BIT 0x08 - buf[0] = SET_BITS_LOW; - buf[1] = (port_val = CS_BIT); + buf[1] = CS_BIT; buf[2] = 0x0b; if (send_buf(ftdic, buf, 3)) return -1; @@ -195,7 +193,6 @@ { struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; - unsigned char port_val = 0; int i, ret = 0; if (writecnt > 65536 || readcnt > 65536) @@ -213,10 +210,11 @@ * as possible together. if we're not expecting to * read, we can assert CS, write, and deassert CS all * in one shot. if reading, we do three separate - * operations. */ + * operations. + */ printf_debug("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = (port_val &= ~CS_BIT); + buf[i++] = 0 & ~CS_BIT; /* assertive */ buf[i++] = 0x0b; if (writecnt) { @@ -236,20 +234,19 @@ buf[i++] = ((readcnt - 1) >> 8) & 0xff; ret = send_buf(ftdic, buf, i); i = 0; - if (ret) goto deassert_cs; + if (ret == 0) { + /* FIXME: This is unreliable. There's no guarantee that we read + * the response directly after sending the read command. + * We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + } - /* FIXME: This is unreliable. There's no guarantee that we read - * the response directly after sending the read command. - * We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - } -deassert_cs: printf_debug("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = (port_val |= CS_BIT); + buf[i++] = CS_BIT; buf[i++] = 0x0b; if (send_buf(ftdic, buf, i)) return -1; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-09-16 08:18:08 UTC (rev 722) +++ trunk/sb600spi.c 2009-09-16 08:26:59 UTC (rev 723) @@ -64,6 +64,11 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { result = spi_byte_program(i, *buf); + if (result) { + // spi_byte_program reported the error for us already + printf_debug("... continuing anyway.\n"); + } + /* wait program complete. */ if (i % 0x8000 == 0) printf(".");

1 0

[commit] r722 - trunk
by svn＠flashrom.org 16 Sep '09

16 Sep '09

Author: stepan Date: 2009-09-16 10:18:08 +0200 (Wed, 16 Sep 2009) New Revision: 722 Modified: trunk/serprog.c trunk/sharplhf00l04.c trunk/sst28sf040.c trunk/stm50flw0x0x.c Log: this patch fixes all 27 flashrom source code issues reported by LLVM/clang's scan-build (r79326, new build on the way). Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> This commit fixes only some of the issues, those that were Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/serprog.c =================================================================== --- trunk/serprog.c 2009-09-09 00:58:19 UTC (rev 721) +++ trunk/serprog.c 2009-09-16 08:18:08 UTC (rev 722) @@ -95,7 +95,7 @@ whether the command is supported before doing it */ static int sp_check_avail_automatic = 0; -static void sp_die(char *msg) +static void __attribute__((noreturn)) sp_die(char *msg) { perror(msg); exit(1); Modified: trunk/sharplhf00l04.c =================================================================== --- trunk/sharplhf00l04.c 2009-09-09 00:58:19 UTC (rev 721) +++ trunk/sharplhf00l04.c 2009-09-16 08:18:08 UTC (rev 722) @@ -73,7 +73,6 @@ uint8_t wait_lhf00l04(chipaddr bios) { uint8_t status; - uint8_t id1, id2; chip_writeb(0x70, bios); if ((chip_readb(bios) & 0x80) == 0) { // it's busy @@ -82,13 +81,13 @@ status = chip_readb(bios); - // put another command to get out of status register mode + // put another command to get out of status register mode. chip_writeb(0x90, bios); programmer_delay(10); - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + chip_readb(bios); // vendor ID + chip_readb(bios + 0x01); // device ID // this is needed to jam it out of "read id" mode chip_writeb(0xAA, bios + 0x5555); Modified: trunk/sst28sf040.c =================================================================== --- trunk/sst28sf040.c 2009-09-09 00:58:19 UTC (rev 721) +++ trunk/sst28sf040.c 2009-09-16 08:18:08 UTC (rev 722) @@ -30,28 +30,24 @@ static void protect_28sf040(chipaddr bios) { - uint8_t tmp; - - tmp = chip_readb(bios + 0x1823); - tmp = chip_readb(bios + 0x1820); - tmp = chip_readb(bios + 0x1822); - tmp = chip_readb(bios + 0x0418); - tmp = chip_readb(bios + 0x041B); - tmp = chip_readb(bios + 0x0419); - tmp = chip_readb(bios + 0x040A); + chip_readb(bios + 0x1823); + chip_readb(bios + 0x1820); + chip_readb(bios + 0x1822); + chip_readb(bios + 0x0418); + chip_readb(bios + 0x041B); + chip_readb(bios + 0x0419); + chip_readb(bios + 0x040A); } static void unprotect_28sf040(chipaddr bios) { - uint8_t tmp; - - tmp = chip_readb(bios + 0x1823); - tmp = chip_readb(bios + 0x1820); - tmp = chip_readb(bios + 0x1822); - tmp = chip_readb(bios + 0x0418); - tmp = chip_readb(bios + 0x041B); - tmp = chip_readb(bios + 0x0419); - tmp = chip_readb(bios + 0x041A); + chip_readb(bios + 0x1823); + chip_readb(bios + 0x1820); + chip_readb(bios + 0x1822); + chip_readb(bios + 0x0418); + chip_readb(bios + 0x041B); + chip_readb(bios + 0x0419); + chip_readb(bios + 0x041A); } static int erase_sector_28sf040(struct flashchip *flash, unsigned long address, int sector_size) Modified: trunk/stm50flw0x0x.c =================================================================== --- trunk/stm50flw0x0x.c 2009-09-09 00:58:19 UTC (rev 721) +++ trunk/stm50flw0x0x.c 2009-09-16 08:18:08 UTC (rev 722) @@ -54,19 +54,17 @@ static void wait_stm50flw0x0x(chipaddr bios) { - uint8_t id1; - // id2; - chip_writeb(0x70, bios); if ((chip_readb(bios) & 0x80) == 0) { // it's busy while ((chip_readb(bios) & 0x80) == 0) ; } + // put another command to get out of status register mode chip_writeb(0x90, bios); programmer_delay(10); - id1 = chip_readb(bios); + chip_readb(bios); // Read device ID (to make sure?) // this is needed to jam it out of "read id" mode chip_writeb(0xAA, bios + 0x5555);

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