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ASUS A8V support
by Aaron Smith 23 Oct '09

23 Oct '09

I'd like to report that flashrom worked great in upgrading the BIOS on my ASUS A8V motherboard. The product page is here: http://www.asus.com/product.aspx?P_ID=Yw0JOuUibSPSWxMo I see other A8V models listed on the wiki, but don't see this one listed. Let me know if you need any other info. Thanks, @@ron

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[PATCH] Silence ICH preop debug message
by Carl-Daniel Hailfinger 22 Oct '09

22 Oct '09

Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_preop_silence/ichspi.c =================================================================== --- flashrom-ich_preop_silence/ichspi.c (Revision 752) +++ flashrom-ich_preop_silence/ichspi.c (Arbeitskopie) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + (curopcodes->opcode[oppos].atomic - 1 == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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[commit] r753 - trunk
by svn＠flashrom.org 22 Oct '09

22 Oct '09

Author: hailfinger Date: 2009-10-22 17:07:30 +0200 (Thu, 22 Oct 2009) New Revision: 753 Modified: trunk/ichspi.c Log: Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-10-21 12:05:50 UTC (rev 752) +++ trunk/ichspi.c 2009-10-22 15:07:30 UTC (rev 753) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + ((curopcodes->opcode[oppos].atomic - 1) == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,

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bios flash succeeded on ASUS P5L-MX (untested flash part)
by Linda 22 Oct '09

22 Oct '09

Dear coreboot team, I just succesfully flashed my bios on a ASUS P5L-MX motherboard. flashrom detects two flash chips, SST25VF040B and SST25VF040B.REMS with the -c option I chose the first, without the -c option flashrom would not perform any action. I'd be happy to give more information if needed. Thanks for making this very nice tool :-) Kind regards Linda Polman 1. writing: 2. ======================================================================================== 3. 4. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -wV LMX1103.ROM 5. flashrom v0.9.1-r706 6. No coreboot table found. 7. Found chipset "Intel ICH7/ICH7R", enabling flash write... 8. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 9. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 10. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 11. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 12. 0xffd80000/0xff980000 FWH IDSEL: 0x2 13. 0xffd00000/0xff900000 FWH IDSEL: 0x2 14. 0xffc80000/0xff880000 FWH IDSEL: 0x3 15. 0xffc00000/0xff800000 FWH IDSEL: 0x3 16. 0xff700000/0xff300000 FWH IDSEL: 0x4 17. 0xff600000/0xff200000 FWH IDSEL: 0x5 18. 0xff500000/0xff100000 FWH IDSEL: 0x6 19. 0xff400000/0xff000000 FWH IDSEL: 0x7 20. 0xfff80000/0xffb80000 FWH decode enabled 21. 0xfff00000/0xffb00000 FWH decode disabled 22. 0xffe80000/0xffa80000 FWH decode disabled 23. 0xffe00000/0xffa00000 FWH decode disabled 24. 0xffd80000/0xff980000 FWH decode disabled 25. 0xffd00000/0xff900000 FWH decode disabled 26. 0xffc80000/0xff880000 FWH decode disabled 27. 0xffc00000/0xff800000 FWH decode disabled 28. 0xff700000/0xff300000 FWH decode disabled 29. 0xff600000/0xff200000 FWH decode disabled 30. 0xff500000/0xff100000 FWH decode disabled 31. 0xff400000/0xff000000 FWH decode disabled 32. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 33. 34. Root Complex Register Block address = 0xfed1c000 35. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 36. Top Swap : not enabled 37. SPIBAR = 0xfed1c000 + 0x3020 38. 0x00: 0x0004 (SPIS) 39. 0x02: 0x4260 (SPIC) 40. 0x04: 0x00000000 (SPIA) 41. 0x08: 0xbf8d25bf (SPID0) 42. 0x0c: 0x00000000 (SPID0+4) 43. 0x10: 0x00000000 (SPID1) 44. 0x14: 0x0000471d (SPID1+4) 45. 0x18: 0x50120000 (SPID2) 46. 0x1c: 0x00495100 (SPID2+4) 47. 0x20: 0x00000100 (SPID3) 48. 0x24: 0x00000040 (SPID3+4) 49. 0x28: 0x30363041 (SPID4) 50. 0x2c: 0x30303035 (SPID4+4) 51. 0x30: 0x00000000 (SPID5) 52. 0x34: 0x00000000 (SPID5+4) 53. 0x38: 0x00ffaaea (SPID6) 54. 0x3c: 0x2f3830f0 (SPID6+4) 55. 0x40: 0x302f3532 (SPID7) 56. 0x44: 0x00fc0036 (SPID7+4) 57. 0x50: 0x00000000 (BBAR) 58. 0x54: 0x0006 (PREOP) 59. 0x56: 0x463b (OPTYPE) 60. 0x58: 0x05d80302 (OPMENU) 61. 0x5c: 0xc79f0190 (OPMENU+4) 62. 0x60: 0x00000000 (PBR0) 63. 0x64: 0x00000000 (PBR1) 64. 0x68: 0x00000000 (PBR2) 65. 0x6c: 0x00000000 (PBR3) 66. 67. Programming OPCODES... 68. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 69. done 70. SPI Read Configuration: prefetching disabled, caching enabled, OK. 71. This chipset supports the following protocols: SPI. 72. Calibrating delay loop... 626M loops per second, 100 myus = 157 us. OK. 73. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 74. Chip status register is 00 75. Chip status register: Block Protect Write Disable (BPL) is not set 76. Chip status register: Auto Address Increment Programming (AAI) is not set 77. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 78. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 79. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 80. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 81. Chip status register: Write Enable Latch (WEL) is not set 82. Chip status register: Write In Progress (WIP/BUSY) is not set 83. Resulting block protection : none 84. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 85. === 86. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 87. Please email a report to flashrom(a)flashrom.org if any of the above operations 88. work correctly for you with this flash part. Please include the flashrom 89. output with the additional -V option for all operations you tested (-V, -rV, 90. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 91. === 92. Flash image seems to be a legacy BIOS. Disabling checks. 93. Writing flash chip... Erasing flash before programming... Invalid OPCODE 0x06 94. due to SPI master limitation, ignoring and hoping it will be run as PREOP 95. done. 96. Invalid OPCODE 0x06 97. due to SPI master limitation, ignoring and hoping it will be run as PREOP 98. Invalid OPCODE 0x06 99. due to SPI master limitation, ignoring and hoping it will be run as PREOP 100. Invalid OPCODE 0x06 101. due to SPI master limitation, ignoring and hoping it will be run as PREOP 102. Invalid OPCODE 0x06 103. due to SPI master limitation, ignoring and hoping it will be run as PREOP 104. Invalid OPCODE 0x06 105. due to SPI master limitation, ignoring and hoping it will be run as PREOP 106. Invalid OPCODE 0x06 107. due to SPI master limitation, ignoring and hoping it will be run as PREOP 108. Invalid OPCODE 0x06 109. due to SPI master limitation, ignoring and hoping it will be run as PREOP 110. Invalid OPCODE 0x06 111. due to SPI master limitation, ignoring and hoping it will be run as PREOP 112. Invalid OPCODE 0x06 113. due to SPI master limitation, ignoring and hoping it will be run as PREOP 114. 115. <few hundred times more the same error line> 116. 117. Invalid OPCODE 0x06 118. due to SPI master limitation, ignoring and hoping it will be run as PREOP 119. Invalid OPCODE 0x06 120. due to SPI master limitation, ignoring and hoping it will be run as PREOP 121. Invalid OPCODE 0x06 122. due to SPI master limitation, ignoring and hoping it will be run as PREOP 123. COMPLETE. 124. Verifying flash... VERIFIED. 125. 126. 127. 128. ====================================================================================== 129. Checking: 130. 131. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -vV LMX1103.ROM 132. flashrom v0.9.1-r706 133. No coreboot table found. 134. Found chipset "Intel ICH7/ICH7R", enabling flash write... 135. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 136. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 137. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 138. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 139. 0xffd80000/0xff980000 FWH IDSEL: 0x2 140. 0xffd00000/0xff900000 FWH IDSEL: 0x2 141. 0xffc80000/0xff880000 FWH IDSEL: 0x3 142. 0xffc00000/0xff800000 FWH IDSEL: 0x3 143. 0xff700000/0xff300000 FWH IDSEL: 0x4 144. 0xff600000/0xff200000 FWH IDSEL: 0x5 145. 0xff500000/0xff100000 FWH IDSEL: 0x6 146. 0xff400000/0xff000000 FWH IDSEL: 0x7 147. 0xfff80000/0xffb80000 FWH decode enabled 148. 0xfff00000/0xffb00000 FWH decode disabled 149. 0xffe80000/0xffa80000 FWH decode disabled 150. 0xffe00000/0xffa00000 FWH decode disabled 151. 0xffd80000/0xff980000 FWH decode disabled 152. 0xffd00000/0xff900000 FWH decode disabled 153. 0xffc80000/0xff880000 FWH decode disabled 154. 0xffc00000/0xff800000 FWH decode disabled 155. 0xff700000/0xff300000 FWH decode disabled 156. 0xff600000/0xff200000 FWH decode disabled 157. 0xff500000/0xff100000 FWH decode disabled 158. 0xff400000/0xff000000 FWH decode disabled 159. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 160. 161. Root Complex Register Block address = 0xfed1c000 162. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 163. Top Swap : not enabled 164. SPIBAR = 0xfed1c000 + 0x3020 165. 0x00: 0x0004 (SPIS) 166. 0x02: 0x7f10 (SPIC) 167. 0x04: 0x0007ffc0 (SPIA) 168. 0x08: 0x0000004d (SPID0) 169. 0x0c: 0x00000000 (SPID0+4) 170. 0x10: 0x00000000 (SPID1) 171. 0x14: 0x0000471d (SPID1+4) 172. 0x18: 0x50120000 (SPID2) 173. 0x1c: 0x00495100 (SPID2+4) 174. 0x20: 0x00000100 (SPID3) 175. 0x24: 0x00000040 (SPID3+4) 176. 0x28: 0x30363041 (SPID4) 177. 0x2c: 0x30303035 (SPID4+4) 178. 0x30: 0x00000000 (SPID5) 179. 0x34: 0x00000000 (SPID5+4) 180. 0x38: 0x00ffaaea (SPID6) 181. 0x3c: 0x2f3231f0 (SPID6+4) 182. 0x40: 0x302f3231 (SPID7) 183. 0x44: 0x00fc0037 (SPID7+4) 184. 0x50: 0x00000000 (BBAR) 185. 0x54: 0x0006 (PREOP) 186. 0x56: 0x463b (OPTYPE) 187. 0x58: 0x05d80302 (OPMENU) 188. 0x5c: 0xc79f0190 (OPMENU+4) 189. 0x60: 0x00000000 (PBR0) 190. 0x64: 0x00000000 (PBR1) 191. 0x68: 0x00000000 (PBR2) 192. 0x6c: 0x00000000 (PBR3) 193. 194. Programming OPCODES... 195. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 196. done 197. SPI Read Configuration: prefetching disabled, caching enabled, OK. 198. This chipset supports the following protocols: SPI. 199. Calibrating delay loop... 784M loops per second, 100 myus = 197 us. OK. 200. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 201. Chip status register is 00 202. Chip status register: Block Protect Write Disable (BPL) is not set 203. Chip status register: Auto Address Increment Programming (AAI) is not set 204. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 205. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 206. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 207. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 208. Chip status register: Write Enable Latch (WEL) is not set 209. Chip status register: Write In Progress (WIP/BUSY) is not set 210. Resulting block protection : none 211. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 212. === 213. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 214. Please email a report to flashrom(a)flashrom.org if any of the above operations 215. work correctly for you with this flash part. Please include the flashrom 216. output with the additional -V option for all operations you tested (-V, -rV, 217. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 218. === 219. Flash image seems to be a legacy BIOS. Disabling checks. 220. Verifying flash... VERIFIED.

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lspci -vvnnxxx for Asrock P4i65GV
by Idwer Vollering 21 Oct '09

21 Oct '09

This pretty much is an attempt to save the board from this thread: http://www.coreboot.org/pipermail/flashrom/2009-October/thread.html#775 --- Sending a lspci -vvnnxxx, as requested by libv on irc. Board: http://www.asrock.com/MB/overview.asp?Model=P4i65GV lspci -vvnnxxx: 00:00.0 Host bridge [0600]: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] (rev 02) Subsystem: ASRock Incorporation Device [1849:2570] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at fe800000 (32-bit, prefetchable) [size=4M] Capabilities: [e4] Vendor Specific Information <?> Kernel driver in use: agpgart-intel Kernel modules: intel-agp 00: 86 80 70 25 06 00 90 20 02 00 00 06 00 00 00 00 10: 08 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 70 25 30: 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 34 00 40 80 1c 00 00 00 00 00 00 00 00 00 60: 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 01 00 00 33 33 00 00 00 00 00 00 0a 38 00 a0: 02 00 30 00 17 42 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 3f 00 00 00 00 00 00 00 20 10 00 00 c0: 00 00 00 00 80 1f 0e 20 00 01 00 00 00 00 00 00 d0: 02 28 04 0e 0b 0d 00 00 00 00 00 00 00 00 40 01 e0: 00 00 00 00 09 00 06 11 00 02 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:02.0 VGA compatible controller [0300]: Intel Corporation 82865G Integrated Graphics Controller [8086:2572] (rev 02) Subsystem: ASRock Incorporation Device [1849:2572] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at fe780000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at ec00 [size=8] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: intelfb 00: 86 80 72 25 07 00 90 00 02 00 00 03 00 00 00 00 10: 08 00 00 f0 00 00 78 fe 01 ec 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 72 25 30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 e0 23 e0 11 00 00 00 00 00 00 00 00 50: 00 00 34 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 01 02 ff 00 00 00 71 02 10 20 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 51 ff ff 51 ff ff 00 00 b0: 02 04 00 00 44 00 00 00 d5 1b ff 9f 7b 40 59 00 c0: 00 00 00 00 80 1f 0e 20 00 00 00 00 00 00 00 00 d0: 01 00 21 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 00 00 09 00 06 11 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at dc00 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d2 24 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 dc 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at e000 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d4 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 06 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at e400 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d7 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e4 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.3 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at e800 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 de 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] (rev 02) (prog-if 20) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 23 Region 0: Memory at fe77bc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 dd 24 06 01 90 02 02 20 03 0c 00 00 00 00 10: 00 bc 77 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 dd 3f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 55 55 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 80 00 00 88 83 40 00 66 0f 05 00 06 14 00 00 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev c2) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fe500000-fe5fffff Prefetchable memory behind bridge: 20000000-200fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: 86 80 4e 24 07 01 80 00 c2 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 b0 b0 80 02 20: 50 fe 50 fe 00 20 00 20 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 00 40: 02 28 30 76 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 64 73 00 00 00 00 00 50 01 34 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 53 31 00:1f.0 ISA bridge [0601]: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Kernel modules: iTCO_wdt, intel-rng 00: 86 80 d0 24 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 10 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 04 00 00 10 00 00 00 60: 8a 8a 85 86 d0 00 00 00 8a 80 8a 8b 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 02 00 00 39 00 00 00 0d 00 00 00 00 03 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 86 21 02 00 02 00 00 00 04 00 00 00 00 00 00 00 e0: 00 00 00 80 00 00 08 14 33 22 11 00 00 00 67 45 f0: 00 00 44 00 04 00 00 00 66 0f 05 3e 00 00 00 00 00:1f.1 IDE interface [0101]: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at fc00 [size=16] Region 5: Memory at 20100000 (32-bit, non-prefetchable) [size=1K] Kernel driver in use: ata_piix 00: 86 80 db 24 07 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 fc 00 00 00 00 10 20 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40: 07 e3 37 e3 b0 00 00 00 0d 00 01 22 00 00 00 00 50: 00 00 00 00 30 10 00 00 00 00 00 00 00 00 00 00 60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 10 Region 4: I/O ports at 0400 [size=32] Kernel modules: i2c-i801 00: 86 80 d3 24 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.5 Multimedia audio controller [0401]: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] (rev 02) Subsystem: ASRock Incorporation Device [1849:9739] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 0: I/O ports at d800 [size=256] Region 1: I/O ports at d400 [size=64] Region 2: Memory at fe77b800 (32-bit, non-prefetchable) [size=512] Region 3: Memory at fe77b400 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: Intel ICH Kernel modules: snd-intel8x0 00: 86 80 d5 24 07 00 90 02 02 00 01 04 00 00 00 00 10: 01 d8 00 00 01 d4 00 00 00 b8 77 fe 00 b4 77 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 97 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 01:03.0 Ethernet controller [0200]: Intel Corporation 82541PI Gigabit Ethernet Controller [8086:107c] (rev 05) Subsystem: Intel Corporation Device [8086:1376] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (63750ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at fe5e0000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fe5c0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at bc00 [size=64] Expansion ROM at 20000000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=00:00.0 64bit- 133MHz- SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=8 RSCEM- 266MHz- 533MHz- Kernel driver in use: e1000 Kernel modules: e1000 00: 86 80 7c 10 17 00 30 02 05 00 00 02 08 20 00 00 10: 00 00 5e fe 00 00 5c fe 01 bc 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 76 13 30: 00 00 fe ff dc 00 00 00 00 00 00 00 0a 01 ff 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 e4 22 c8 e0: 00 20 00 28 07 00 02 00 00 00 40 00 00 00 00 00 f0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) Subsystem: ASRock Incorporation Device [1849:8139] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at b800 [size=256] Region 1: Memory at fe5bfc00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too Kernel modules: 8139too, 8139cp 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 b8 00 00 00 fc 5b fe 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Re: [flashrom] [Patch] Board enable for Shuttle FN25 (SN25P).
by Luc Verhaegen 21 Oct '09

21 Oct '09

On Sat, Oct 10, 2009 at 09:31:17PM -0300, Ulf Mehlig wrote: > Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > rebooting worked, also after re-flashing with the latest BIOS from > Shuttles Website; the ethernet address was preserved on reboot. > > Seems to be everything ok, then. > > Thanks again! Ulf > > On Wed, 2009-09-23 at 10:26 -0300, Luc Verhaegen wrote: > > On Wed, Sep 23, 2009 at 10:14:47AM -0300, Ulf Mehlig wrote: > > > Thanks for the patch, and many thanks again for helping me out > > > yesterday! > > > > > > All the best, Ulf > > > > > > > Does it work? If so, reply with: Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > so that it can be committed. > > > > Also, carldani is about to send in a patch for your bios chip, i am not > > sure how to test this, but he can explain this. > > > > Luc Verhaegen. Thanks: -> r752. Luc Verhaegen.

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[commit] r752 - trunk
by svn＠flashrom.org 21 Oct '09

21 Oct '09

Author: libv Date: 2009-10-21 14:05:50 +0200 (Wed, 21 Oct 2009) New Revision: 752 Modified: trunk/board_enable.c Log: Board enable for Shuttle FN25 (SN25P). Shuttle SFF PC is SN25P, board FN25, AMD socket 939 with an nForce4 chipset. Config register 0x92 on the ISA bridge needs to be cleared for TBL# to be raised. No information about individual bits of this register is currently available. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Ulf Mehlig <ulf(a)ufpa.br> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-19 18:15:36 UTC (rev 751) +++ trunk/board_enable.c 2009-10-21 12:05:50 UTC (rev 752) @@ -400,6 +400,26 @@ } /** + * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). + */ +static int board_shuttle_fn25(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ + if (!dev) { + fprintf(stderr, + "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + return -1; + } + + /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ + pci_write_byte(dev, 0x92, 0); + + return 0; +} + +/** * No docs, so we are just guessing that these might be individual gpio lines. */ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) @@ -1086,6 +1106,7 @@ {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, + {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},

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[commit] r751 - trunk
by svn＠flashrom.org 19 Oct '09

19 Oct '09

Author: hailfinger Date: 2009-10-19 20:15:36 +0200 (Mon, 19 Oct 2009) New Revision: 751 Modified: trunk/jedec.c Log: Remove confusing out-of-date comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-10-06 20:25:48 UTC (rev 750) +++ trunk/jedec.c 2009-10-19 18:15:36 UTC (rev 751) @@ -114,9 +114,6 @@ chip_writeb(0x55, bios + 0x2AAA); programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - /* Older chips may need up to 100 us to respond. The ATMEL 29C020 - * needs 10 ms according to the data sheet. - */ programmer_delay(probe_timing_enter); /* Read product ID */

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Re: [flashrom] Winbond W25X16 successful programming
by Maurizio Cavalli 19 Oct '09

19 Oct '09

Hi. I downloaded the latest snapshot of flashrom as you suggested, and you will find the new log in the attached file. There is yet a lot of "opcode 0x06 will be run as PREOP" lines: I deleted all of them but the first sequences. If you need them, let me known. I can rerun the program anytime, and if this little job can help you, I will do it. About the code for the PentiumM/82855GME: I'm sorry, but I have nothing to submit. Is was a my personal attempt to port linuxbios, but the activity was (too soon ?) stopped. The development tree was moved into the "old things limbo", from where it was deleted by a mistyped answer during disk maintenance. Anyway, thanks. Regards Maurizio Cavalli Sviluppo Software CONTROL SYSTEMS S.r.l. Via del Brolo, 14 26100 CREMONA (Italy) tel +39 0372 471806 fax +39 0372 471823 www.controlsystems-srl.it -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Fri 10/16/2009 12:45 PM To: Maurizio Cavalli Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Winbond W25X16 successful programming Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User's Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Flashrom MSI KT4V support.
by Luc Verhaegen 17 Oct '09

17 Oct '09

Hi Sean, I have some questions about your kt4v/kt4ultra board enable: 1) I am about to move some code from many vt823x based board enables to the chipset enable. Your board enable has some "similar" code, but not quite, and it now forms the only anomaly. Can you send me the output of: dd if=/dev/mem of=/tmp/kt4v_system.rom bs=64k count=1 skip=15 so i can have a dig through the top segment of your AMI BIOS to verify this code? 2) I am about to tighten up the board enable matching table. * both the coreboot ids will disappear. * we need a second set for the kt4v. Can you send in lspci -vvnnxxx on both boards? Thanks, Luc Verhaegen.

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Re: [flashrom] Winbond W25X16 successful programming
by Carl-Daniel Hailfinger 16 Oct '09

16 Oct '09

Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User’s Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Winbond W25X16 successful programming
by Maurizio Cavalli 16 Oct '09

16 Oct '09

I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. Board: ROE RIVER Evaluation Board from Intel (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit Users Manual - Document number: 320436-002) BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. Kernel: Linux 2.6.30.2 SMP, compiled from source tree Host system: Debian 5.0 (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) I hope this mail will be useful for you Best regards Maurizio Cavalli Sviluppo Software CONTROL SYSTEMS S.r.l. Via del Brolo, 14 26100 CREMONA (Italy) tel +39 0372 471806 fax +39 0372 471823 www.controlsystems-srl.it

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Re: [flashrom] Is K7S6A supported by flashrom? 2nd Reply.
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

Hi David, thanks for the info. Please keep the flashrom mailing list in CC (hit "reply all") so others can chime in on the discussion. Regards, Carl-Daniel On 14.10.2009 20:33, spirals wrote: > Hi Carl-Daniel, Have just restarted after a full covers off eye-ball > of the board is definatly is the K&S6A (v1.0) board, pene also looked > (my eyes are not as good as they were) and she confirmed 1.0 and > _/*not 1.0A*/_ regards, (dja.) > > Carl-Daniel Hailfinger wrote: >> Hi Dave, >> >> On 13.10.2009 21:53, David J Aldridge wrote: >> >>> Ran flashrom and it reports "No EEPROM/flash device found", same >>> with -m ecs:k7s5a. >>> >> >> Please send the output of "flashrom -V", "lspci -nnvvvxxx", "superiotool >> -dV" and if tell us if your board is >> K7S6A (V1.0) >> or >> K7S6A (V1.0A) >> >> Luc: BIOS downloads are here (not sure which PCB is the one Dave has): >> http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C… >> >> http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=238&… >> >> >> Regards, >> Carl-Daniel >> >> > -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Sometimes-working board submission: Siemens D2703
by Stefaan 15 Oct '09

15 Oct '09

Hi! I've just spent some quality time with my Siemens D2703-board. Sometimes flashing works, sometimes it doesn't. I've done lots of power cycling and also soft reboots, changing and resetting BIOS settings, ... but I could not discern a determining factor. The short log of a working flash looks like this: flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB600", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Atmel AT26DF081A" (1024 KB, SPI) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... done. Programming flash................................ done. COMPLETE. Verifying flash... VERIFIED. The top verbose output of a working write looks like: flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB600", enabling flash write... SPI base address is at 0xffefff80 AltSpiCSEnable=0, SpiRomEnable=0, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=0, SpiOpEnInLpcMode=0 SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=0, DropOneClkOnRd=0 GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for GPIO GPIO32 used for SPI_CS GPIO47 used for SPI_CLK ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 451M loops per second, 100 myus = 185 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. ... The top verbose output of a non-working log: flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB600", enabling flash write... SPI base address is at 0x0 ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH. Calibrating delay loop... 454M loops per second, 100 myus = 185 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. ... So somehow, SPI seems to be detected intermittently. Retrying without a reboot has never (up till now) solved the problem. I hope my report is helpful. If you desire any additional information, you need only ask :) Many thanks, I really like your flashrom project, and am looking forward to using it more often, Stefaan

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[Fwd: Re: Is K7S6A supported by flashrom? 2nd Reply.]
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

forwarded. -------- Original Message -------- Subject: Re: [flashrom] Is K7S6A supported by flashrom? 2nd Reply. Date: Wed, 14 Oct 2009 19:33:44 +0100 From: spirals <spirals(a)eircom.net> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> References: <4AD4DABF.8050509(a)eircom.net> <4AD4EF17.80507(a)gmx.net> Hi Carl-Daniel, Have just restarted after a full covers off eye-ball of the board is definatly is the K&S6A (v1.0) board, pene also looked (my eyes are not as good as they were) and she confirmed 1.0 and _/*not 1.0A*/_ regards, (dja.) Carl-Daniel Hailfinger wrote: > Hi Dave, > > On 13.10.2009 21:53, David J Aldridge wrote: > >> Ran flashrom and it reports "No EEPROM/flash device found", same with >> -m ecs:k7s5a. >> > > Please send the output of "flashrom -V", "lspci -nnvvvxxx", "superiotool > -dV" and if tell us if your board is > K7S6A (V1.0) > or > K7S6A (V1.0A) > > Luc: BIOS downloads are here (not sure which PCB is the one Dave has): > http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C… > http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=238&… > > Regards, > Carl-Daniel > > -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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[Fwd: Re: Is K7S6A supported by flashrom?]
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

forwarded. -------- Original Message -------- Subject: Re: [flashrom] Is K7S6A supported by flashrom? Date: Wed, 14 Oct 2009 11:08:42 +0100 From: spirals <spirals(a)eircom.net> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> References: <4AD4DABF.8050509(a)eircom.net> <4AD4EF17.80507(a)gmx.net> Hi Carl-Daniel, Thank you for the reply, I have attached the output from the 3 tools and as as far as I know I have the K7S6A (V1.0) board. I will do a full shutdown tonight and eye ball the board again but that's what my notebook says. In the release notes for the updated patch it states the ROM type as W49F002U12BN not certain if the extra bicharacters on the end beyondW49F002U of the type number relate to its capacity (256K*8) as I am a bit rusty having been been retired for some 10 years now. I have now downloaded the source code and compiled it as check I have all the headers etc. That works but same symptoms. Thank you for your help, regards (dja.) Carl-Daniel Hailfinger wrote: > Hi Dave, > > On 13.10.2009 21:53, David J Aldridge wrote: > >> Ran flashrom and it reports "No EEPROM/flash device found", same with >> -m ecs:k7s5a. >> > > Please send the output of "flashrom -V", "lspci -nnvvvxxx", "superiotool > -dV" and if tell us if your board is > K7S6A (V1.0) > or > K7S6A (V1.0A) > > Luc: BIOS downloads are here (not sure which PCB is the one Dave has): > http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C… > http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=238&… > > Regards, > Carl-Daniel > > -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers." superiotool r3125 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x7373, rev=0x73 Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x2) at 0x2e Register dump: idx 07 20 21 22 23 24 val 08 87 05 02 00 f1 def NA 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 10 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 0a def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 00 00 00 80 00 0a 00 c0 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 01 02 01 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 01 03 30 0a 00 def 00 03 00 0a 00 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x2) at 0x4e Register dump: idx 07 20 21 22 23 24 val 08 87 05 02 00 f1 def NA 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 10 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 0a def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 00 00 00 80 00 0a 00 c0 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 01 02 01 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 01 03 30 0a 00 def 00 03 00 0a 00 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0x73, rev=0x73 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0x73, rev=0x73 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0x73/0x03, rev=0x73 Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0x73/0x03, rev=0x73 Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0x73/0x03, rev=0x73 Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0x73/0x03, rev=0x73 Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Calibrating delay loop... 321M loops per second. OK. No coreboot table found. WARNING: No chipset found. Flash detection will most likely fail. Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A25L40P, 512 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A49LF040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for AMIC Technology A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI chipset detected Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset detected Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset detected Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset detected Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset detected Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset detected Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset detected Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset detected Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI chipset detected Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x42, id2 0xb1, id1 parity violation Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI chipset detected No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. 00:00.0 Host bridge [0600]: Silicon Integrated Systems [SiS] 745 Host [1039:0745] (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 32 Region 0: Memory at e0000000 (32-bit, non-prefetchable) [size=64M] Capabilities: [c0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Kernel driver in use: agpgart-sis Kernel modules: sis-agp 00: 39 10 45 07 07 00 10 22 01 00 00 06 00 20 80 00 10: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 07 e4 77 f7 aa d4 e8 f0 46 79 08 03 12 d5 03 00 60: 6b 6b 6d 6d 03 00 00 00 01 50 18 22 00 81 3f 00 70: 04 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 02 40 30 03 85 00 80 01 20 0c 00 04 00 00 00 00 90: 00 00 19 37 43 01 00 05 00 2e b3 40 00 00 00 20 a0: 42 cb 34 01 aa 00 00 00 00 00 00 00 00 00 00 04 b0: 00 00 00 00 7b 02 6f 6b 5a 1a 49 fa 15 f5 00 4a c0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 d0: 02 40 31 00 09 ff ff 00 60 60 aa 00 00 80 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: Silicon Integrated Systems [SiS] Virtual PCI-to-PCI bridge (AGP) [1039:0001] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 99 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: e4000000-e6ffffff Prefetchable memory behind bridge: 50000000-500fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: 39 10 01 00 07 01 00 00 00 00 04 06 00 63 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 c0 c0 00 20 20: 00 e4 f0 e6 00 50 00 50 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 ISA bridge [0601]: Silicon Integrated Systems [SiS] SiS85C503/5513 (LPC Bridge) [1039:0018] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Kernel modules: i2c-sis630 00: 39 10 18 00 0f 00 00 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: da 89 80 05 0b 22 31 0d 10 00 00 00 11 20 04 01 50: 11 28 02 01 61 0a 66 00 00 00 12 00 a6 0b b6 00 60: 80 80 80 0b 40 c1 0a 10 09 80 00 02 d0 00 00 00 70: 00 00 00 00 00 50 00 ec 00 00 00 00 06 00 01 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 SMBus [0c05]: Silicon Integrated Systems [SiS] SiS961/2 SMBus Controller [1039:0016] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 0 Region 4: I/O ports at 5080 [size=32] Kernel driver in use: sis96x_smbus Kernel modules: i2c-sis96x 00: 39 10 16 00 01 00 00 02 00 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.2 USB Controller [0c03]: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] (rev 07) (prog-if 10 [OHCI]) Subsystem: Elitegroup Computer Systems Device [1019:0a41] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max), Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at e8002000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd Kernel modules: ohci-hcd 00: 39 10 01 70 07 00 80 02 07 10 03 0c 08 20 00 00 10: 00 20 00 e8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 41 0a 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 50 40: 00 00 00 00 54 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.3 USB Controller [0c03]: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] (rev 07) (prog-if 10 [OHCI]) Subsystem: Elitegroup Computer Systems Device [1019:0a41] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at e8000000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd Kernel modules: ohci-hcd 00: 39 10 01 70 07 00 80 02 07 10 03 0c 08 20 00 00 10: 00 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 41 0a 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 50 40: 00 00 00 00 54 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.5 IDE interface [0101]: Silicon Integrated Systems [SiS] 5513 [IDE] [1039:5513] (rev d0) (prog-if 80 [Master]) Subsystem: Elitegroup Computer Systems Device [1019:0a41] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 128 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at 4000 [size=16] Kernel driver in use: SIS_IDE Kernel modules: sis5513 00: 39 10 13 55 07 00 00 00 d0 80 01 01 00 80 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 40 00 00 00 00 00 00 00 00 00 00 19 10 41 0a 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 31 81 31 81 31 85 31 85 28 01 e6 ff 00 02 00 02 50: 01 00 01 06 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.7 Multimedia audio controller [0401]: Silicon Integrated Systems [SiS] AC'97 Sound Controller [1039:7012] (rev a0) Subsystem: Elitegroup Computer Systems Device [1019:0a41] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (13000ns min, 2750ns max) Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at d800 [size=256] Region 1: I/O ports at dc00 [size=64] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: Intel ICH Kernel modules: snd-intel8x0 00: 39 10 12 70 05 00 90 02 a0 00 01 04 00 20 00 00 10: 01 d8 00 00 01 dc 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 41 0a 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 03 34 0b 40: 04 00 00 00 00 00 00 00 01 00 42 c0 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 Ethernet controller [0200]: 3Com Corporation 3c905C-TX/TX-M [Tornado] [10b7:9200] (rev 74) Subsystem: 3Com Corporation 3C905CX-TX/TX-M Fast Etherlink for PC Management NIC [10b7:1000] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (2500ns min, 2500ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at e000 [size=128] Region 1: Memory at e8001000 (32-bit, non-prefetchable) [size=128] [virtual] Expansion ROM at 50100000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- Kernel driver in use: 3c59x Kernel modules: 3c59x 00: b7 10 00 92 07 00 10 02 74 00 00 02 08 20 00 00 10: 01 e0 00 00 00 10 00 e8 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 b7 10 00 10 30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 0a 0a 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 fe e0: 00 40 00 b7 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 SCSI storage controller [0100]: Initio Corporation INI-935 Fast Wide SCSI Adapter [1101:9401] (rev 01) Subsystem: Device [9292:0202] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at e400 [size=256] Region 1: Memory at e8003000 (32-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at 50120000 [disabled] [size=32K] Kernel driver in use: initio Kernel modules: initio 00: 01 11 01 94 07 00 00 02 01 00 00 01 08 20 00 00 10: 01 e4 00 00 00 30 00 e8 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 92 92 02 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: f7 3f ff ff ff ff ff ff 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 01 01 00 00 00 00 04 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc 3D Rage Pro AGP 1X/2X [1002:4742] (rev 5c) (prog-if 00 [VGA controller]) Subsystem: ATI Technologies Inc Rage Pro Turbo AGP 2X [1002:0084] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (2000ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at e4000000 (32-bit, non-prefetchable) [size=16M] Region 1: I/O ports at c000 [size=256] Region 2: Memory at e6000000 (32-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at 50000000 [disabled] [size=128K] Capabilities: [50] AGP version 1.0 Status: RQ=256 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> 00: 02 10 42 47 87 00 90 02 5c 00 00 03 08 20 00 00 10: 00 00 00 e4 01 c0 00 00 00 00 00 e6 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 84 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 09 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 00 10 00 03 02 00 ff 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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flashe réussie sur carte asus
by rvb 12 Oct '09

12 Oct '09

carte asus : P4C800-E Deluxe chipset : intel 875P + ICH5R bios : 1023.001 (asus) flashe réussie

1 0

Successfully erased and flashed my GIGABYTE GA-G33M-DS2R
by Benjamin BELLEC 11 Oct '09

11 Oct '09

Hi, I used flashrom to flash my motherboard : a GIGABYTE GA-G33M-DS2R. Here is the needed log. One core of my CPU during the flash was at 100% and a very fat log was created (95 Mio) due to this line repeated roughtly 2 millions times: *Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP* And lspci indicate (in the Ethernet section) a "GA-EP45-DS5 Motherboard" but it's wrong. If you need more information just ask me, but write to my private email address since I don't subscribe to the mailing list. Thanks to flashrom team, Benjamin BELLEC

1 0

Successfully erased and flashed my GIGABYTE GA-MA78G-DS3H
by yulrottmann＠bitel.net 11 Oct '09

11 Oct '09

Hi, I used flashrom to flash my new OEM BIOS. My board is a GIGABYTE GA-MA78G-DS3H (Revision 1). Thanks for this really nice tool. :) Flashrom told me that I should confirm on this list if I successfully erased the BIOS: "This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help!" That is what I'm doing here, the log file is attached. I erased my flash, then read out and it was deleted. Then I flashed a new BIOS and rebooted my system. Now I use the new BIOS, F8 instead of F6. There are two things I noticed: - Flashrom tells: "Disabling flash write protection for board "GIGABYTE GA-MA78GM-S2H"... Serial flash segment 0xfffe0000-0xffffffff enabled" This is not my mainboard, I have a DS3H, but it works anyway. - When writing to the chip, there is a break where it is not clear what flashrom does: "[...] Writing flash chip... Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... SUCCESS. done. [HERE IS A CA. 3 MINUTES BREAK] COMPLETE. Verifying flash... VERIFIED." Maybe you should add a "still in progress" or similar. "Done" looks like it has completed the whole process. Also the CPU uses 100% while flashing/erasing/verifying, I don't know it this is normal. If you need more information just ask me, but write to my private email address since I don't subscribe to the mailing list. Thanks, Yul Rottmann

1 0

[commit] r750 - trunk
by svn＠flashrom.org 06 Oct '09

06 Oct '09

Author: uwe Date: 2009-10-06 22:25:48 +0200 (Tue, 06 Oct 2009) New Revision: 750 Modified: trunk/print_wiki.c Log: Add missing NVIDIA PCI IDs to wiki output. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-10-06 20:23:29 UTC (rev 749) +++ trunk/print_wiki.c 2009-10-06 20:25:48 UTC (rev 750) @@ -547,6 +547,9 @@ #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); #endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs_wiki(gfx_nvidia); +#endif #if DRKAISER_SUPPORT == 1 print_supported_pcidevs_wiki(drkaiser_pcidev); #endif

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[commit] r749 - trunk
by svn＠flashrom.org 06 Oct '09

06 Oct '09

Author: uwe Date: 2009-10-06 22:23:29 +0200 (Tue, 06 Oct 2009) New Revision: 749 Modified: trunk/board_enable.c trunk/print.c trunk/print_wiki.c Log: Mark the following boards as supported (no board-enable needed): - MSI MS-6153 (reported by Uwe Hermann <uwe(a)hermann-uwe.de>) Tested by me on hardware. The board decodes max. 256 KB. - MSI MS-6156 (reported by Uwe Hermann <uwe(a)hermann-uwe.de>) Tested by me on hardware. The board decodes max. 256 KB. Also, fix Dell PowerEdge 1850 name and add some more board URLs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-06 13:00:00 UTC (rev 748) +++ trunk/board_enable.c 2009-10-06 20:23:29 UTC (rev 749) @@ -617,10 +617,10 @@ } /** - * Suited for the Dell S1850. All parameters except the last one are documented - * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last - * parameter (GPIO number) has to be in the range [16,31] according to said - * Intel Datasheet and was found by exhaustive search. + * Suited for the Dell PowerEdge 1850. All parameters except the last one are + * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The + * last parameter (GPIO number) has to be in the range [16,31] according to + * said Intel datasheet and was found by exhaustive search. */ static int ich5_gpio23_raise(const char *name) { @@ -1058,7 +1058,7 @@ {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-10-06 13:00:00 UTC (rev 748) +++ trunk/print.c 2009-10-06 20:23:29 UTC (rev 749) @@ -270,6 +270,8 @@ { "GIGABYTE", "GA-MA770T-UD3P", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, + { "MSI", "MS-6153", }, + { "MSI", "MS-6156", }, { "MSI", "MS-6570 (K7N2)", }, { "MSI", "MS-7065", }, { "MSI", "MS-7168 (Orion)", }, Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-10-06 13:00:00 UTC (rev 748) +++ trunk/print_wiki.c 2009-10-06 20:23:29 UTC (rev 749) @@ -142,6 +142,8 @@ { "GIGABYTE", "GA-MA770T-UD3P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, + { "MSI", "MS-6153", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p…" }, + { "MSI", "MS-6156", "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/boards/Motherboards/…" }, { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, @@ -190,6 +192,7 @@ { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, /* Verified working boards that DO need write-enables. */ + { "Abit", "IP35", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…" }, { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ @@ -197,13 +200,17 @@ { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k" }, + { "ASUS", "A7V8X", "http://www.asus.com/product.aspx?P_ID=qfpaGrAy2kLVo0f2" }, { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g" }, + { "ASUS", "P5ND2-SLI Deluxe", "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5" }, { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, + { "Dell", "PowerEdge 1850", "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm" }, { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, + { "EPoX", "EP-8RDA3+", "http://www.epox.com/product.asp?ID=EP-8RDA3plus" }, { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" },

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6A815EPD lspci
by Jonathan A. Kollasch 06 Oct '09

06 Oct '09

Hi, Attached is lspci -vvnnxxxx output for a Acorp 6A815EPD. The 3Com NIC and ATI video are not part of the motherboard. Jonathan Kollasch

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[Patch] Board enable for Asus P4B266LM.
by Luc Verhaegen 06 Oct '09

06 Oct '09

Allan, please try this patch. If this works, please reply with: Acked-by: Allan Bjorklund <abjork(a)speakeasy.net> Thanks, Luc Verhaegen.

2 1

Tightening up the board enable table.
by Luc Verhaegen 06 Oct '09

06 Oct '09

We have had board enable routines and our board enable table for more than two years now. And thanks to the good work of carldani and uwe and the release(s) (one done, one pending) this list is growing fast. We have 47 boards in our board enable table today. Board enables have the following format today: <pci id set 1> <pci id set 2> <coreboot name> <pretty print name> <board enable callback> one pci id set is the following: <vendor> <device> <card/subsystem vendor> <card/subsystem device> While most of the time, the vendor and device ids are fixed, the subsystem pair is set by the bios. It can be write-once or it can be locked by some other bit in the device config space. Because subsystem ids are relatively new to the pci spec (second half of the 90s iirc), not all vendors have been using them. Most last-millenium boards will not have them filled in. Or often vendor bioses just copy main ids over. Many consumer board makers today do their job really well while embedded board makers tend to ignore subsystem ids. Because of what i saw in my unichrome graphics driver (where i started using subsystem ids in 2004 to see which outputs were wired up), i knew that matching a single device was never going to work. So two were added here, but we only require a single set to be filled in. There is a situation with some gigabyte boards for which carldani suggested to add a third set, which is imho a good solution, but we are trying to hold this one off until we really need it. After the pair of pci ids, there are the board names. The coreboot name is used two-fold. On a coreboot rom, this name is matched to the coreboot info. On a legacy bios, the user can provide the board name on the command line and therefor force flashrom to use a specific board enable. In both cases, the device and vendor ids of pci devices are matched as well as a safeguard. So, three ways of matching boards: * main ids + subsystem ids. * legacy bios + command line name + main ids (ignoring subsystem ids). * coreboot + coreboot name + main ids (ignoring subsystem ids). Now that we have a more sizable table and a bigger and quickly growing userbase, i believe that we should look into tightening this up. We are no longer part of the main coreboot project and are reaching a changed public now with the exposure we are getting. Average Joe User might end up abusing our board enable table and land himself in trouble and then will blame us. While we of course are not liable, it is still bad publicity and something we should try to avoid. We also can see how board matches have been written over time, and i believe that we should be stricter about them. Quite a few people have just added a single main pci id, and then added a coreboot name to the table as this was the absolute minimal effort required to make it work for them. This is how humans are, and how humans will continue to be, so we should make it harder for this to happen. So in order to make it safer for Average Joe User, and in order to force developers to be less lazy here, i propose some changes; * require 2 sets of pci-ids. Can anyone name a motherboard which has only a single pci device that even comes close to our target hardware (in as far as we have target hardware). By requiring 2 sets, we improve safety and we force developers to be less lazy. * if one value of any of the 4 subsystem ids is filled in, assume that the rest should be matched as is. When subsystem ids are not filled in correctly, they sometimes remain null. Null values should not mean "match anything" they should mean null when even one of the value is valid. I am a bit weary of adding a #define for 0xFFFF (the pciid "match anything"). I do not wish to encourage people to create an entry like: blah, blah, 0xFFFF, 0xFFFF, blah, blah, 0xFFFF, 0xFFFF and get away with it. Multiple similar boards should be matched separately. And, since we usually have more than just a few pci devices in our device tree, chances are extremely good that at least two of them can be matched in some way or another, without a catchall. * on legacy bioses, do not allow both pci subsystem ids and a name. The most efficient way to do this seems the following: If a name is provided, we should go over the table, checking for devices with both subsystem id sets nulled, and try to match the name. If the name matches, try to match main pci ids. * Add separate logic for coreboot name matching. This to still allow subsystem ids to be present, and thus to offset the previous point. We really will end up with three different ways of matching boards. Apart from actual code changes, we should apply the following: * Be extremely weary of patches. * We need at least an lspci -vvnnxxxx. We have started to do this anyway now, collecting info for our current table, while retaining info for future table alteration. * Do not accept missing subsystem ids for recent boards. Motherboards of this millenium tend to have subsystem ids filled in. * Usage of a coreboot name when coreboot is supported. Why would a coreboot developer set a separate write protect on the rom? The board enable could be valid though, but not for flash write protection. If developers want to bring up a board, and have this write protection disabling as a todo, then they can hack their own code into flashrom. Even if we only apply some of the above, we still need to clean up our board enable table. Here is a list of boards with questionable matching, as a quick list. I will be digging each of them out properly and try to contact the original authors for more information. If you are the original author and happen to be reading this, then by all means, feel free to contact us right away. Acorp 6A815EPD agami Aruma Artec Group DBE61 Artec Group DBE62 GIGABYTE GA-2761GXDK GIGABYTE GA-M57SLI-S4 GIGABYTE GA-M61P-S3 GIGABYTE GA-MA790FX-DQ6 HP DL145 G3 IBM x3455 IWILL DK8-HTX Kontron 986LCD-M Kontron 986LCD-M (yes, twice) MSI MS-6590 (KT4 Ultra) MSI MS-6712 (KT4V) MSI MS-7135 (K8N Neo3) VIA EPIA-N/NL VIA PC3500G The following two devices are known to be valid, as they predate pci subsystem ids: the ASUS P5A (which i own) and the EPoX EP-BX3. Luc Verhaegen.

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Re: [flashrom] [commit] r748 - trunk
by Carl-Daniel Hailfinger 06 Oct '09

06 Oct '09

On 06.10.2009 15:00, svn(a)flashrom.org wrote: > Author: uwe > New Revision: 748 > > Modified: > trunk/board_enable.c > trunk/print.c > Log: > Upon popular request, move board support tables to print.c. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Thanks! Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r748 - trunk
by svn＠flashrom.org 06 Oct '09

06 Oct '09

Author: uwe Date: 2009-10-06 15:00:00 +0200 (Tue, 06 Oct 2009) New Revision: 748 Modified: trunk/board_enable.c trunk/print.c Log: Upon popular request, move board support tables to print.c. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-06 11:32:21 UTC (rev 747) +++ trunk/board_enable.c 2009-10-06 13:00:00 UTC (rev 748) @@ -1015,6 +1015,12 @@ } /** + * Below is the list of boards which need a special "board enable" code in + * flashrom before their ROM chip can be accessed/written to. + * + * NOTE: Please add boards that _don't_ need such enables or don't work yet + * to the respective tables in print.c. Thanks! + * * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -1091,149 +1097,6 @@ { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ }; -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info boards_ok[] = { - /* Verified working boards that don't need write-enables. */ - { "Abit", "AX8", }, - { "Abit", "Fatal1ty F-I90HD", }, - { "Advantech", "PCM-5820", }, - { "ASI", "MB-5BLMP", }, - { "ASRock", "A770CrossFire", }, - { "ASUS", "A7N8X Deluxe", }, - { "ASUS", "A7N8X-E Deluxe", }, - { "ASUS", "A7V400-MX", }, - { "ASUS", "A7V8X-MX", }, - { "ASUS", "A8N-E", }, - { "ASUS", "A8NE-FM/S", }, - { "ASUS", "A8N-SLI", }, - { "ASUS", "A8N-SLI Premium", }, - { "ASUS", "A8V Deluxe", }, - { "ASUS", "A8V-E Deluxe", }, - { "ASUS", "A8V-E SE", }, - { "ASUS", "M2A-MX", }, - { "ASUS", "M2A-VM", }, - { "ASUS", "M2N-E", }, - { "ASUS", "M2V", }, - { "ASUS", "M3A78-EM", }, - { "ASUS", "P2B", }, - { "ASUS", "P2B-D", }, - { "ASUS", "P2B-DS", }, - { "ASUS", "P2B-F", }, - { "ASUS", "P2L97-S", }, - { "ASUS", "P5B-Deluxe", }, - { "ASUS", "P5KC", }, - { "ASUS", "P5L-MX", }, - { "ASUS", "P6T Deluxe V2", }, - { "A-Trend", "ATC-6220", }, - { "BCOM", "WinNET100", }, - { "Elitegroup", "P6VAP-A+", }, - { "GIGABYTE", "GA-6BXC", }, - { "GIGABYTE", "GA-6BXDU", }, - { "GIGABYTE", "GA-6ZMA", }, - { "GIGABYTE", "GA-7ZM", }, - { "GIGABYTE", "GA-EP35-DS3L", }, - { "GIGABYTE", "GA-EX58-UD4P", }, - { "GIGABYTE", "GA-MA78GPM-DS2H", }, - { "GIGABYTE", "GA-MA790GP-DS4H", }, - { "GIGABYTE", "GA-MA770T-UD3P", }, - { "Intel", "EP80759", }, - { "Jetway", "J7F4K1G5D-PB", }, - { "MSI", "MS-6570 (K7N2)", }, - { "MSI", "MS-7065", }, - { "MSI", "MS-7168 (Orion)", }, - { "MSI", "MS-7236 (945PL Neo3)", }, - { "MSI", "MS-7255 (P4M890M)", }, - { "MSI", "MS-7345 (P35 Neo2-FIR)", }, - { "MSI", "MS-7368 (K9AG Neo2-Digital)", }, - { "NEC", "PowerMate 2000", }, - { "PC Engines", "Alix.1c", }, - { "PC Engines", "Alix.2c2", }, - { "PC Engines", "Alix.2c3", }, - { "PC Engines", "Alix.3c3", }, - { "PC Engines", "Alix.3d3", }, - { "RCA", "RM4100", }, - { "Sun", "Blade x6250", }, - { "Supermicro", "H8QC8", }, - { "Thomson", "IP1000", }, - { "TriGem", "Lomita", }, - { "T-Online", "S-100", }, - { "Tyan", "iS5375-1U", }, - { "Tyan", "S1846", }, - { "Tyan", "S2466", }, - { "Tyan", "S2881", }, - { "Tyan", "S2882", }, - { "Tyan", "S2882-D", }, - { "Tyan", "S2891", }, - { "Tyan", "S2892", }, - { "Tyan", "S2895", }, - { "Tyan", "S3095", }, - { "Tyan", "S5180", }, - { "Tyan", "S5191", }, - { "Tyan", "S5197", }, - { "Tyan", "S5211", }, - { "Tyan", "S5211-1U", }, - { "Tyan", "S5220", }, - { "Tyan", "S5375", }, - { "Tyan", "S5376G2NR/S5376WAG2NR", }, - { "Tyan", "S5377", }, - { "Tyan", "S5397", }, - { "VIA", "EPIA-EX15000G", }, - { "VIA", "EPIA-LN", }, - { "VIA", "EPIA-M700", }, - { "VIA", "EPIA-NX15000G", }, - { "VIA", "NAB74X0", }, - { "VIA", "pc2500e", }, - { "VIA", "VB700X", }, - - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info boards_bad[] = { - /* Verified non-working boards (for now). */ - { "Abit", "IS-10", }, - { "ASRock", "K7VT4A+", }, - { "ASUS", "MEW-AM", }, - { "ASUS", "MEW-VM", }, - { "ASUS", "P3B-F", }, - { "ASUS", "P5B", }, - { "ASUS", "P5BV-M", }, - { "Biostar", "M6TBA", }, - { "Boser", "HS-6637", }, - { "DFI", "855GME-MGF", }, - { "FIC", "VA-502", }, - { "MSI", "MS-6178", }, - { "MSI", "MS-7260 (K9N Neo)", }, - { "Soyo", "SY-5VD", }, - { "Sun", "Fire x4150", }, - { "Sun", "Fire x4200", }, - { "Sun", "Fire x4540", }, - { "Sun", "Fire x4600", }, - - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info laptops_ok[] = { - /* Verified working laptops. */ - { "Lenovo", "3000 V100 TF05Cxx", }, - - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info laptops_bad[] = { - /* Verified non-working laptops (for now). */ - { "Acer", "Aspire One", }, - { "ASUS", "Eee PC 701 4G", }, - { "Dell", "Latitude CPi A366XT", }, - { "HP/Compaq", "nx9010", }, - { "IBM/Lenovo", "Thinkpad T40p", }, - { "IBM/Lenovo", "240", }, - - {}, -}; - /** * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-10-06 11:32:21 UTC (rev 747) +++ trunk/print.c 2009-10-06 13:00:00 UTC (rev 748) @@ -221,3 +221,148 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } + + +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info boards_ok[] = { + /* Verified working boards that don't need write-enables. */ + { "Abit", "AX8", }, + { "Abit", "Fatal1ty F-I90HD", }, + { "Advantech", "PCM-5820", }, + { "ASI", "MB-5BLMP", }, + { "ASRock", "A770CrossFire", }, + { "ASUS", "A7N8X Deluxe", }, + { "ASUS", "A7N8X-E Deluxe", }, + { "ASUS", "A7V400-MX", }, + { "ASUS", "A7V8X-MX", }, + { "ASUS", "A8N-E", }, + { "ASUS", "A8NE-FM/S", }, + { "ASUS", "A8N-SLI", }, + { "ASUS", "A8N-SLI Premium", }, + { "ASUS", "A8V Deluxe", }, + { "ASUS", "A8V-E Deluxe", }, + { "ASUS", "A8V-E SE", }, + { "ASUS", "M2A-MX", }, + { "ASUS", "M2A-VM", }, + { "ASUS", "M2N-E", }, + { "ASUS", "M2V", }, + { "ASUS", "M3A78-EM", }, + { "ASUS", "P2B", }, + { "ASUS", "P2B-D", }, + { "ASUS", "P2B-DS", }, + { "ASUS", "P2B-F", }, + { "ASUS", "P2L97-S", }, + { "ASUS", "P5B-Deluxe", }, + { "ASUS", "P5KC", }, + { "ASUS", "P5L-MX", }, + { "ASUS", "P6T Deluxe V2", }, + { "A-Trend", "ATC-6220", }, + { "BCOM", "WinNET100", }, + { "Elitegroup", "P6VAP-A+", }, + { "GIGABYTE", "GA-6BXC", }, + { "GIGABYTE", "GA-6BXDU", }, + { "GIGABYTE", "GA-6ZMA", }, + { "GIGABYTE", "GA-7ZM", }, + { "GIGABYTE", "GA-EP35-DS3L", }, + { "GIGABYTE", "GA-EX58-UD4P", }, + { "GIGABYTE", "GA-MA78GPM-DS2H", }, + { "GIGABYTE", "GA-MA790GP-DS4H", }, + { "GIGABYTE", "GA-MA770T-UD3P", }, + { "Intel", "EP80759", }, + { "Jetway", "J7F4K1G5D-PB", }, + { "MSI", "MS-6570 (K7N2)", }, + { "MSI", "MS-7065", }, + { "MSI", "MS-7168 (Orion)", }, + { "MSI", "MS-7236 (945PL Neo3)", }, + { "MSI", "MS-7255 (P4M890M)", }, + { "MSI", "MS-7345 (P35 Neo2-FIR)", }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", }, + { "NEC", "PowerMate 2000", }, + { "PC Engines", "Alix.1c", }, + { "PC Engines", "Alix.2c2", }, + { "PC Engines", "Alix.2c3", }, + { "PC Engines", "Alix.3c3", }, + { "PC Engines", "Alix.3d3", }, + { "RCA", "RM4100", }, + { "Sun", "Blade x6250", }, + { "Supermicro", "H8QC8", }, + { "Thomson", "IP1000", }, + { "TriGem", "Lomita", }, + { "T-Online", "S-100", }, + { "Tyan", "iS5375-1U", }, + { "Tyan", "S1846", }, + { "Tyan", "S2466", }, + { "Tyan", "S2881", }, + { "Tyan", "S2882", }, + { "Tyan", "S2882-D", }, + { "Tyan", "S2891", }, + { "Tyan", "S2892", }, + { "Tyan", "S2895", }, + { "Tyan", "S3095", }, + { "Tyan", "S5180", }, + { "Tyan", "S5191", }, + { "Tyan", "S5197", }, + { "Tyan", "S5211", }, + { "Tyan", "S5211-1U", }, + { "Tyan", "S5220", }, + { "Tyan", "S5375", }, + { "Tyan", "S5376G2NR/S5376WAG2NR", }, + { "Tyan", "S5377", }, + { "Tyan", "S5397", }, + { "VIA", "EPIA-EX15000G", }, + { "VIA", "EPIA-LN", }, + { "VIA", "EPIA-M700", }, + { "VIA", "EPIA-NX15000G", }, + { "VIA", "NAB74X0", }, + { "VIA", "pc2500e", }, + { "VIA", "VB700X", }, + + {}, +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info boards_bad[] = { + /* Verified non-working boards (for now). */ + { "Abit", "IS-10", }, + { "ASRock", "K7VT4A+", }, + { "ASUS", "MEW-AM", }, + { "ASUS", "MEW-VM", }, + { "ASUS", "P3B-F", }, + { "ASUS", "P5B", }, + { "ASUS", "P5BV-M", }, + { "Biostar", "M6TBA", }, + { "Boser", "HS-6637", }, + { "DFI", "855GME-MGF", }, + { "FIC", "VA-502", }, + { "MSI", "MS-6178", }, + { "MSI", "MS-7260 (K9N Neo)", }, + { "Soyo", "SY-5VD", }, + { "Sun", "Fire x4150", }, + { "Sun", "Fire x4200", }, + { "Sun", "Fire x4540", }, + { "Sun", "Fire x4600", }, + + {}, +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info laptops_ok[] = { + /* Verified working laptops. */ + { "Lenovo", "3000 V100 TF05Cxx", }, + + {}, +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info laptops_bad[] = { + /* Verified non-working laptops (for now). */ + { "Acer", "Aspire One", }, + { "ASUS", "Eee PC 701 4G", }, + { "Dell", "Latitude CPi A366XT", }, + { "HP/Compaq", "nx9010", }, + { "IBM/Lenovo", "Thinkpad T40p", }, + { "IBM/Lenovo", "240", }, + + {}, +}; +

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[commit] r747 - trunk
by svn＠flashrom.org 06 Oct '09

06 Oct '09

Author: libv Date: 2009-10-06 13:32:21 +0200 (Tue, 06 Oct 2009) New Revision: 747 Modified: trunk/chipset_enable.c Log: Mark NVIDIA Nforce4/MCP04 as tested. Oops. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-05 18:46:35 UTC (rev 746) +++ trunk/chipset_enable.c 2009-10-06 11:32:21 UTC (rev 747) @@ -1018,7 +1018,7 @@ {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, - {0x10de, 0x0030, NT, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, + {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},

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Re: [flashrom] non-working board report for Asrock K7S41GX with flashrom r711
by Luc Verhaegen 06 Oct '09

06 Oct '09

On Mon, Oct 05, 2009 at 11:34:14PM +0100, Putlinuxonit wrote: > Hi Luc, > > Find attached. > > Keep up the good work. I am able to easily find the int16h hook, but once there i am unable to track down the code for ah=0xE0. You should get a multimeter out and check whether your bios chip really has one of its write protection lines set. Luc Verhaegen.

1 0

Board enable for EPoX EP-8RDA3+ lspci fix
by . . 05 Oct '09

05 Oct '09

Hi, seems hotmail leaves out parts of the lspci output, so pastebinned it here: http://coreboot.pastebin.com/f22a57659 Link should stay 'forever'. Thanks, Anol. _________________________________________________________________ With Windows Live, you can organize, edit, and share your photos. http://www.microsoft.com/middleeast/windows/windowslive/products/photo-gall…

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[commit] r746 - trunk
by svn＠flashrom.org 05 Oct '09

05 Oct '09

Author: libv Date: 2009-10-05 20:46:35 +0200 (Mon, 05 Oct 2009) New Revision: 746 Modified: trunk/board_enable.c Log: Board enable for EPoX EP-8RDA3+. SocketA + nForce2 + MCP2. Motherboard includes a second ethernet controller and an Agere firewire controller with valid subsystem ids, so these are used for matching the board. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Eddie Vanhove <moonraket(a)hotmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-05 16:07:00 UTC (rev 745) +++ trunk/board_enable.c 2009-10-05 18:46:35 UTC (rev 746) @@ -454,7 +454,24 @@ return 0; } +/** + * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. + */ +static int board_epox_ep_8rda3plus(const char *name) +{ + struct pci_dev *dev; + dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x31); + + return 0; +} + static int board_hp_dl145_g3_enable(const char *name) { /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ @@ -1038,6 +1055,7 @@ {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable},

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Re: [flashrom] Board support for ASUS P5ND2-SLI Deluxe.
by Luc Verhaegen 05 Oct '09

05 Oct '09

On Mon, Oct 05, 2009 at 03:24:47PM +0200, Martin S. wrote: > On Mon, 2009-10-05 at 13:52 +0200, Luc Verhaegen wrote: > > Can you attach the output of lspci -vvnnxxx? > > > > Attached. > > > I will soon send in a patch for the chipset enable. > > > > Got it. Going to test now. > > > When the full lspci is provided, i will be able to quickly provide you > > with a board enable for your board. > > > > Oh, and about your blog entry: my first linux box was a SuSE 6.0, but > > undoubtedly Stepan can easily trump that as i believe he was working > > for SuSE (already/still) at the time. > > Nice, looking for evidence. ;) > > > Also, please use your real and full name for acknowledging patches later > > on. > > Sure. Thanks for your efforts. Here is the board specific patch. Also included is your lspci for the ml. Luc Verhaegen.

2 2

[commit] r745 - trunk
by svn＠flashrom.org 05 Oct '09

05 Oct '09

Author: libv Date: 2009-10-05 18:07:00 +0200 (Mon, 05 Oct 2009) New Revision: 745 Modified: trunk/board_enable.c Log: Board enable for ASUS P5ND2-SLI Deluxe. This patch reorganises the board_ga_k8n_sli to create nvidia_mcp_gpio_raise, a more general routine to set these bits. Without docs, i can only assume that these memory area are gpio lines. Then it becomes easy to add support for this nForce4 SLI board. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Martin Szulecki <opensuse(a)sukimashita.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-05 16:04:47 UTC (rev 744) +++ trunk/board_enable.c 2009-10-05 16:07:00 UTC (rev 745) @@ -400,13 +400,30 @@ } /** + * No docs, so we are just guessing that these might be individual gpio lines. + */ +static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) +{ + uint16_t base; + uint8_t tmp; + + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + + base += 0xC0; + + /* if anyone knows more about nvidia mcps, feel free to explain this */ + tmp = INB(base + offset); + tmp &= ~0x0F; + tmp |= 0x05; + OUTB(tmp, base + offset); +} + +/** * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. */ static int board_ga_k8n_sli(const char *name) { struct pci_dev *dev; - uint32_t base; - uint8_t tmp; dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ if (!dev) { @@ -414,16 +431,30 @@ return -1; } - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + nvidia_mcp_gpio_raise(dev, 0x21); - /* if anyone knows more about nvidia lpcs, feel free to explain this */ - tmp = INB(base + 0xE1); - tmp |= 0x05; - OUTB(tmp, base + 0xE1); + return 0; +} +/** + * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. + */ +static int board_asus_p5nd2_sli(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x10); + return 0; } + static int board_hp_dl145_g3_enable(const char *name) { /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ @@ -1002,6 +1033,7 @@ {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},

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Chipset enable for nVidia nForce4/MCP4.
by Luc Verhaegen 05 Oct '09

05 Oct '09

Please test whether your board is matched correctly. When the board enable gets provided, please apply that on top of this patch, and if both work correctly, reply to both mails with Acked-by: Martin ##DeineRichtigeNachname## <info(a)sukimashita.com> Also, the pci id matched here is not in the pciids.sf.net database. You might want to work with them to get your pciids in their list (my guess is that they need you to dig through some windows driver .inf files.) Thanks, Luc Verhaegen.

2 2

[commit] r744 - trunk
by svn＠flashrom.org 05 Oct '09

05 Oct '09

Author: libv Date: 2009-10-05 18:04:47 +0200 (Mon, 05 Oct 2009) New Revision: 744 Modified: trunk/chipset_enable.c Log: Chipset support for the nVidia nForce 4. Add pciids for the new isa bridge, and hook it to the nforce2 chipset enable. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Martin Szulecki <opensuse(a)sukimashita.com> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-03 17:08:02 UTC (rev 743) +++ trunk/chipset_enable.c 2009-10-05 16:04:47 UTC (rev 744) @@ -1018,6 +1018,7 @@ {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x10de, 0x0030, NT, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},

1 0

"ERASED FAILED!" messages for ICH2 / SST49LF0002A/B
by Allan Bjorklund 05 Oct '09

05 Oct '09

Hello, I'm wanting to upgrade the BIOS on an older machine that I have. A Sony Vaio (PCV-RX650(UC)), with an ASUSTeK mother board (P4B266LM Rev: 1.xx), running Linux kernel 2.6.28. Running flashrom (today's trunk version) with no arguments gives this: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. No operations were specified. I saved a copy of my existing BIOS image with: flashrom -r original_bios.bin That appears to work, as the file is the same size as the updated BIOS .bin file I downloaded from the vendor's site. To test writing, I attempted to write the original BIOS image back with flashrom -w original_bios.bin, and here is the output: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00003fff: 0x3fa4 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! If I do a flashrom -v original_bios.bin, I get: flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. And reading a second copy and doing a binary diff shows no differences, so my BIOS checks out as not being damaged. (At least, I think so.) So, any advice on what to look for/change to make this work? Thanks. --Allan

4 4

Board support for ASUS P5ND2-SLI Deluxe.
by Luc Verhaegen 05 Oct '09

05 Oct '09

Can you attach the output of lspci -vvnnxxx? I will soon send in a patch for the chipset enable. When the full lspci is provided, i will be able to quickly provide you with a board enable for your board. Oh, and about your blog entry: my first linux box was a SuSE 6.0, but undoubtedly Stepan can easily trump that as i believe he was working for SuSE (already/still) at the time. Also, please use your real and full name for acknowledging patches later on. Luc Verhaegen.

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Re: [flashrom] [coreboot] #131: New flashrom motherboard support
by Martin S. 05 Oct '09

05 Oct '09

On Mon, 2009-10-05 at 01:45 +0000, coreboot wrote: > #131: New flashrom motherboard support > ---------------------------------+------------------------------------------ > Reporter: anonymous | Owner: somebody > Type: enhancement | Status: new > Priority: trivial | Milestone: flashrom v1.0 > Component: flashrom | Version: > Keywords: flashrom asus | Dependencies: > Patchstatus: there is no patch | > ---------------------------------+------------------------------------------ > > Comment(by hailfinger): > > Please send a short mail to flashrom(a)flashrom.org which has a link to this > ticket and mentions that you're the person with the "ASUS P5ND2-SLI > Deluxe". This will make it easier for us to stay in touch with you. > Thanks. > Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131#comment:4> It's me. ;) Cheers. --- Martin S.

1 0

Data regarding GA-MA790GP-UD4H board
by Yair K. 04 Oct '09

04 Oct '09

Hi, Per discussion in IRC, I'm attaching "flashrom -V" and "lspci -nnvx" output. Flashrom 0.9.0 flashing works. Hopefully the attached files will help with autodetection. Yours, Yair K.

2 1

flashing results for the MS-7094 board
by Jelle Geerts 04 Oct '09

04 Oct '09

Hello, I've ran flashrom -v {-E,-r,-v,-w} on my MS-7094 board. For more info regarding the board, please see http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p… I've attached the results to this e-mail. Reading/verifying/writing worked fine. Erasing however, didn't go so well, as you can see in the attached log. BTW, two thumbs up to the flashrom developers: the Award flash utility did not work (kept saying 'Unknown flash type'), but flashrom did. ;) HTH, Jelle Geerts

3 2

Non-working board submission: Asrock K7VT4A+
by Putlinuxonit 04 Oct '09

04 Oct '09

Hi, I've tested this board with flashrom-0.9.0-r695 as well as superiotool r4424. Also contained are dumps from* #lspci -vvnnxxxx*, *#dmidecode* and *#lshw*. i tried a forced read via *#flashrom -f -r -c SST39SF020A oldfirmware.bin*and provide the dumps as well though that maybe useless as i was warned. A lot of the info is probably duplicated but is provided for the sake of completeness. Bios: AMI > Board: Asrock K7VT4A+ > Flash Chip: SST39SF020A (PLCC) > Chipset: Via VT8235 > Enjoy!, Udu E. Ogah .~~~~~~~~~~.

2 1

Asus M4A79T deluxe
by Sander Sweers 04 Oct '09

04 Oct '09

Hello Flashrom people, I just successfully did a flash from linux for the first time ever, yeah :-) Attached are the logs (bzipped) for flashrom -V -rV and flashrom -V -wV. I hope this help you guys adding official support for this motherboards. If you need more info please let me know. Greets Sander

1 0

Re: [flashrom] [coreboot] [PATCH]Remove non-CBFS
by Carl-Daniel Hailfinger 03 Oct '09

03 Oct '09

[adding flashrom(a)flashrom.org to CC] On 03.10.2009 18:40, Peter Stuge wrote: > Carl-Daniel Hailfinger wrote: > >> Given that flashrom already has a generic image layout feature, I >> propose to have cbfstool spit out an image layout file which is >> then read by flashrom. This makes flashrom independent of CBFS and >> that's a good thing (think upgrade). >> > > This is trivial to implement and might be a good first step, but it's > absolutely horrible from a usability perspective; > > The user would need to keep track of and understand no less than two > tools, AND an intermediary layout file, in order to perform the > single task of partial firmware update. > The user has to understand cbfstool and lar anyway right now if he/she wants to do anything useful with fallback/normal. The user also has to understand flashrom to flash the resulting image. The user will not directly inspect the ROM image, nor will he/she directly inspect the layout file. > I think it is quite neccessary for flashrom to understand CBFS (and > LAR, for v3 users). > What about WPH and other formats from proprietary BIOS vendors? Flashrom has more users who deal with WPH and related formats than it has users who deal with CBFS or LAR. IIRC the Unix philosophy is roughly "Create programs that do one thing and do it well. Use simple programs together." I like that philosophy. One option would be to have cbfstool and lar execute the flashrom binary. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH] Clean up and fix libz detection
by Carl-Daniel Hailfinger 03 Oct '09

03 Oct '09

There is no need to tell people to install libz if flashrom doesn't need libz. So far, the only case where libz is needed is when a library (libpci) pulls in libz and even then it only happens if libpci is available in a static version only and said static version has libz requirements. Check for libpci separately and don't require libz if it isn't needed. Clarify the README. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-libz_detection/Makefile =================================================================== --- flashrom-libz_detection/Makefile (Revision 742) +++ flashrom-libz_detection/Makefile (Arbeitskopie) @@ -41,7 +41,7 @@ LDFLAGS += -L/usr/local/lib endif -LIBS += -lpci -lz +LIBS += -lpci OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o \ @@ -142,6 +142,9 @@ OBJS += print_wiki.o endif +# We could use PULLED_IN_LIBS, but that would be ugly. +FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) @@ -157,7 +160,7 @@ rm -f $(PROGRAM) *.o distclean: clean - rm -f .dependencies .features + rm -f .dependencies .features .libdeps dep: @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies @@ -175,17 +178,36 @@ @rm -f .test.c .test pciutils: compiler - @printf "Checking for pciutils and zlib... " + @printf "Checking for libpci headers... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) $(LDFLAGS) .test.c -o .test $(LIBS) >/dev/null 2>&1 && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test + @$(CC) -c $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ + echo "found." || ( echo "not found."; echo; \ + echo "Please install libpci headers (package pciutils-devel)."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o; exit 1) + @printf "Checking for libpci... " + @$(shell ( echo "#include <pci/pci.h>"; \ + echo "int main(int argc, char **argv)"; \ + echo "{ return 0; }"; ) > .test1.c ) + @$(CC) $(CFLAGS) $(LDFLAGS) .test1.c -o .test1 $(LIBS) >/dev/null 2>&1 && \ + echo "found." || ( echo "not found."; echo; \ + echo "Please install libpci (package pciutils)."; \ + echo "See README for more information."; echo; \ + rm -f .test1.c .test1; exit 1) + @printf "Checking if libpci is sufficient... " + @printf "" > .libdeps + @$(CC) $(LDFLAGS) .test.o -o .test $(LIBS) >/dev/null 2>&1 && \ + echo "yes." || ( echo "no."; \ + printf "Checking if libz is present and supplies all needed symbols..."; \ + $(CC) $(LDFLAGS) .test.o -o .test $(LIBS) -lz >/dev/null 2>&1 && \ + ( echo "yes."; echo "NEEDLIBZ := yes" > .libdeps ) || ( echo "no."; echo; \ + echo "Please install libz."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o .test; exit 1) ) + @rm -f .test.c .test.o .test .test1.c .test1 .features: features Index: flashrom-libz_detection/README =================================================================== --- flashrom-libz_detection/README (Revision 742) +++ flashrom-libz_detection/README (Arbeitskopie) @@ -38,7 +38,7 @@ Linux et al: - * pciutils + * pciutils / libpci * pciutils-devel / pciutils-dev / libpci-dev * zlib-devel / zlib1g-dev (only needed if libpci is static) @@ -79,13 +79,16 @@ In order to install flashrom and the manpage into /usr/local, type: - sudo make install + make install For installation in a different directory use DESTDIR, e.g. like this: - sudo make DESTDIR=/usr install + make DESTDIR=/usr install +If you have insufficient permissions for the destination directory, use sudo +by adding sudo in front of the commands above. + Usage / Options --------------- -- http://www.hailfinger.org/

2 2

[commit] r743 - trunk
by svn＠flashrom.org 03 Oct '09

03 Oct '09

Author: hailfinger Date: 2009-10-03 19:08:02 +0200 (Sat, 03 Oct 2009) New Revision: 743 Modified: trunk/Makefile trunk/README Log: There is no need to tell people to install libz if flashrom doesn't need libz. So far, the only case where libz is needed is when a library (libpci) pulls in libz and even then it only happens if libpci is available in a static version only and said static version has libz requirements. Check for libpci separately and don't require libz if it isn't needed. Clarify the README. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-10-01 18:40:02 UTC (rev 742) +++ trunk/Makefile 2009-10-03 17:08:02 UTC (rev 743) @@ -41,7 +41,7 @@ LDFLAGS += -L/usr/local/lib endif -LIBS += -lpci -lz +LIBS += -lpci OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o \ @@ -142,6 +142,9 @@ OBJS += print_wiki.o endif +# We could use PULLED_IN_LIBS, but that would be ugly. +FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) @@ -157,7 +160,7 @@ rm -f $(PROGRAM) *.o distclean: clean - rm -f .dependencies .features + rm -f .dependencies .features .libdeps dep: @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies @@ -175,17 +178,36 @@ @rm -f .test.c .test pciutils: compiler - @printf "Checking for pciutils and zlib... " + @printf "Checking for libpci headers... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) $(LDFLAGS) .test.c -o .test $(LIBS) >/dev/null 2>&1 && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test + @$(CC) -c $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ + echo "found." || ( echo "not found."; echo; \ + echo "Please install libpci headers (package pciutils-devel)."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o; exit 1) + @printf "Checking for libpci... " + @$(shell ( echo "#include <pci/pci.h>"; \ + echo "int main(int argc, char **argv)"; \ + echo "{ return 0; }"; ) > .test1.c ) + @$(CC) $(CFLAGS) $(LDFLAGS) .test1.c -o .test1 $(LIBS) >/dev/null 2>&1 && \ + echo "found." || ( echo "not found."; echo; \ + echo "Please install libpci (package pciutils)."; \ + echo "See README for more information."; echo; \ + rm -f .test1.c .test1; exit 1) + @printf "Checking if libpci is sufficient... " + @printf "" > .libdeps + @$(CC) $(LDFLAGS) .test.o -o .test $(LIBS) >/dev/null 2>&1 && \ + echo "yes." || ( echo "no."; \ + printf "Checking if libz is present and supplies all needed symbols..."; \ + $(CC) $(LDFLAGS) .test.o -o .test $(LIBS) -lz >/dev/null 2>&1 && \ + ( echo "yes."; echo "NEEDLIBZ := yes" > .libdeps ) || ( echo "no."; echo; \ + echo "Please install libz."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test.o .test; exit 1) ) + @rm -f .test.c .test.o .test .test1.c .test1 .features: features Modified: trunk/README =================================================================== --- trunk/README 2009-10-01 18:40:02 UTC (rev 742) +++ trunk/README 2009-10-03 17:08:02 UTC (rev 743) @@ -38,7 +38,7 @@ Linux et al: - * pciutils + * pciutils / libpci * pciutils-devel / pciutils-dev / libpci-dev * zlib-devel / zlib1g-dev (only needed if libpci is static) @@ -79,13 +79,16 @@ In order to install flashrom and the manpage into /usr/local, type: - sudo make install + make install For installation in a different directory use DESTDIR, e.g. like this: - sudo make DESTDIR=/usr install + make DESTDIR=/usr install +If you have insufficient permissions for the destination directory, use sudo +by adding sudo in front of the commands above. + Usage / Options ---------------

1 0

flashrom test flashrom v0.9.1-r710
by Buckeyne, Thomas 02 Oct '09

02 Oct '09

This was tested on a "custom" mainboard Of interest to the flashrom group would be that this worked on "Intel ICH9M-E", Chip set with an Atmel "AT25DF641" 8MB chip this was a "./flashrom -r save.img" -V >./flashrom-trace.txt === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Reading flash... done. <<flashrom-trace.txt>> After save of SPI rom image I did a cmp -l between what I put on it with a ms-dos fpt.exe program and the saved image => compare came out identical I will send more traces as I do write ... etc. If you need / want more info I will do what I can to get it for you Thomas Buckeyne Sr Firmware Eng. Bally Technologies 6601 South Bermuda Road Las Vegas, NV 89119 Direct 702.584.7109 Main 702.584.7700

2 1

[commit] r742 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: uwe Date: 2009-10-01 20:40:02 +0200 (Thu, 01 Oct 2009) New Revision: 742 Modified: trunk/flashrom.c trunk/ft2232_spi.c Log: Cosmetics and small coding style fixes (trivial). Also, introduce BITMODE_BITBANG_SPI to eliminate a magic value. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-01 14:51:25 UTC (rev 741) +++ trunk/flashrom.c 2009-10-01 18:40:02 UTC (rev 742) @@ -563,12 +563,12 @@ return ret; } -void emergency_help_message() +void emergency_help_message(void) { fprintf(stderr, "Your flash chip is in an unknown state.\n" - "Get help on IRC at irc.freenode.net channel #flashrom or\n" - "mail flashrom(a)flashrom.org\n" - "------------------------------------------------------------\n" + "Get help on IRC at irc.freenode.net (channel #flashrom) or\n" + "mail flashrom(a)flashrom.org!\n--------------------" + "-----------------------------------------------------------\n" "DO NOT REBOOT OR POWEROFF!\n"); } Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-10-01 14:51:25 UTC (rev 741) +++ trunk/ft2232_spi.c 2009-10-01 18:40:02 UTC (rev 742) @@ -29,15 +29,20 @@ #include "spi.h" #include <ftdi.h> -/* the 'H' chips can run internally at either 12Mhz or 60Mhz. - * the non-H chips can only run at 12Mhz. */ +/* + * The 'H' chips can run internally at either 12MHz or 60MHz. + * The non-H chips can only run at 12MHz. + */ #define CLOCK_5X 1 -/* in either case, the divisor is a simple integer clock divider. - * if CLOCK_5X is set, this divisor divides 30Mhz, else it - * divides 6Mhz */ -#define DIVIDE_BY 3 // e.g. '3' will give either 10Mhz or 2Mhz spi clock +/* + * In either case, the divisor is a simple integer clock divider. + * If CLOCK_5X is set, this divisor divides 30MHz, else it divides 6MHz. + */ +#define DIVIDE_BY 3 /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */ +#define BITMODE_BITBANG_NORMAL 1 +#define BITMODE_BITBANG_SPI 2 static struct ftdi_context ftdic_context; @@ -76,7 +81,7 @@ if (ftdi_init(ftdic) < 0) { fprintf(stderr, "ftdi_init failed\n"); - return EXIT_FAILURE; + return EXIT_FAILURE; // TODO } if (programmer_param && !strlen(programmer_param)) { @@ -113,9 +118,9 @@ f = ftdi_usb_open(ftdic, 0x0403, ft2232_type); if (f < 0 && f != -5) { - fprintf(stderr, "Unable to open ftdi device: %d (%s)\n", f, + fprintf(stderr, "Unable to open FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); - exit(-1); + exit(-1); // TODO } if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { @@ -124,7 +129,7 @@ } if (ftdi_usb_reset(ftdic) < 0) { - fprintf(stderr, "Unable to reset ftdi device\n"); + fprintf(stderr, "Unable to reset FTDI device\n"); } if (ftdi_set_latency_timer(ftdic, 2) < 0) { @@ -135,13 +140,13 @@ fprintf(stderr, "Unable to set chunk size\n"); } - if (ftdi_set_bitmode(ftdic, 0x00, 2) < 0) { - fprintf(stderr, "Unable to set bitmode\n"); + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { + fprintf(stderr, "Unable to set bitmode to SPI\n"); } #if CLOCK_5X printf_debug("Disable divide-by-5 front stage\n"); - buf[0] = 0x8a; /* disable divide-by-5 */ + buf[0] = 0x8a; /* Disable divide-by-5. */ if (send_buf(ftdic, buf, 1)) return -1; #define MPSSE_CLK 60.0 @@ -154,16 +159,16 @@ printf_debug("Set clock divisor\n"); buf[0] = 0x86; /* command "set divisor" */ /* valueL/valueH are (desired_divisor - 1) */ - buf[1] = (DIVIDE_BY-1) & 0xff; - buf[2] = ((DIVIDE_BY-1) >> 8) & 0xff; + buf[1] = (DIVIDE_BY - 1) & 0xff; + buf[2] = ((DIVIDE_BY - 1) >> 8) & 0xff; if (send_buf(ftdic, buf, 3)) return -1; printf("SPI clock is %fMHz\n", - (double)(MPSSE_CLK / (((DIVIDE_BY-1) + 1) * 2))); + (double)(MPSSE_CLK / (((DIVIDE_BY - 1) + 1) * 2))); - /* Disconnect TDI/DO to TDO/DI for Loopback */ - printf_debug("No loopback of tdi/do tdo/di\n"); + /* Disconnect TDI/DO to TDO/DI for loopback. */ + printf_debug("No loopback of TDI/DO TDO/DI\n"); buf[0] = 0x85; if (send_buf(ftdic, buf, 1)) return -1; @@ -180,7 +185,7 @@ if (send_buf(ftdic, buf, 3)) return -1; - printf_debug("\nft2232 chosen\n"); + // printf_debug("\nft2232 chosen\n"); buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_FT2232; @@ -193,7 +198,7 @@ { struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; - int i, ret = 0; + int i = 0, ret = 0; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; @@ -201,15 +206,13 @@ buf = realloc(buf, writecnt + readcnt + 100); if (!buf) { fprintf(stderr, "Out of memory!\n"); - exit(1); + exit(1); // -1 } - i = 0; - - /* minimize USB transfers by packing as many commands - * as possible together. if we're not expecting to - * read, we can assert CS, write, and deassert CS all - * in one shot. if reading, we do three separate + /* + * Minimize USB transfers by packing as many commands as possible + * together. If we're not expecting to read, we can assert CS#, write, + * and deassert CS# all in one shot. If reading, we do three separate * operations. */ printf_debug("Assert CS#\n"); @@ -221,11 +224,12 @@ buf[i++] = 0x11; buf[i++] = (writecnt - 1) & 0xff; buf[i++] = ((writecnt - 1) >> 8) & 0xff; - memcpy(buf+i, writearr, writecnt); + memcpy(buf + i, writearr, writecnt); i += writecnt; } - /* optionally terminate this batch of commands with a + /* + * Optionally terminate this batch of commands with a * read command, then do the fetch of the results. */ if (readcnt) { @@ -235,13 +239,13 @@ ret = send_buf(ftdic, buf, i); i = 0; if (ret == 0) { - /* FIXME: This is unreliable. There's no guarantee that we read - * the response directly after sending the read command. - * We may be scheduled out etc. + /* + * FIXME: This is unreliable. There's no guarantee that + * we read the response directly after sending the read + * command. We may be scheduled out etc. */ ret = get_buf(ftdic, readarr, readcnt); } - } printf_debug("De-assert CS#\n"); @@ -266,7 +270,7 @@ int i; spi_disable_blockprotect(); - /* Erase first */ + /* Erase first. */ printf("Erasing flash before programming... "); if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); @@ -285,7 +289,7 @@ fprintf(stderr, "%s: write fail %d\n", __func__, r); return 1; } - + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) /* loop */; }

1 0

[PATCH] Bitbanging SPI driver
by Carl-Daniel Hailfinger 01 Oct '09

01 Oct '09

This is a bitbanging SPI driver without hardware support. If you want support for a particular piece of hardware, just fill in a few functions. That's it. Tested, trace looks OK. Not 0.9.1 material. If I get an ack, I'll commit after 0.9.1. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi/flash.h =================================================================== --- flashrom-bitbang_spi/flash.h (Revision 682) +++ flashrom-bitbang_spi/flash.h (Arbeitskopie) @@ -90,6 +90,7 @@ #if SERPROG_SUPPORT == 1 PROGRAMMER_SERPROG, #endif + PROGRAMMER_BITBANGSPI, PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -390,6 +391,12 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +/* bitbang_spi.c */ +int bitbang_spi_init(void); +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); + /* flashrom.c */ extern char *programmer_param; extern int verbose; @@ -428,6 +435,7 @@ SPI_CONTROLLER_WBSIO, SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, + SPI_CONTROLLER_BITBANG, }; struct spi_command { unsigned int writecnt; Index: flashrom-bitbang_spi/bitbang_spi.c =================================================================== --- flashrom-bitbang_spi/bitbang_spi.c (Revision 0) +++ flashrom-bitbang_spi/bitbang_spi.c (Revision 0) @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" +#include "spi.h" + +#if BITBANG_SPI_SUPPORT == 1 + +/* Length of half a clock period in usecs */ +int bitbang_half_period = 0; + +/* Empty functions, need to be replaced with actual driver implementation. */ +void bitbang_set_cs(int val) +{ +} + +void bitbang_set_sck(int val) +{ +} + +void bitbang_set_mosi(int val) +{ +} + +int bitbang_get_miso(void) +{ + return 1; +} + +int bitbang_spi_init(void) +{ + bitbang_set_cs(1); + bitbang_set_sck(0); + + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_BITBANG; + + return 0; +} + +uint8_t bitbang_spi_readwrite_byte(uint8_t val) +{ + uint8_t ret = 0; + int i; + + for (i = 7; i >= 0; i--) { + bitbang_set_mosi((val >> i) & 1); + programmer_delay(bitbang_half_period); + bitbang_set_sck(1); + ret <<= 1; + ret |= bitbang_get_miso(); + programmer_delay(bitbang_half_period); + bitbang_set_sck(0); + } + return ret; +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *bufout = NULL; + static unsigned char *bufin = NULL; + static int oldbufsize = 0; + int bufsize = max(writecnt + readcnt, 260); + int i; + + /* Arbitrary size limitation here. We're only constrained by memory. */ + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + + if (bufsize != oldbufsize) { + bufout = realloc(bufout, bufsize); + if (!bufout) { + fprintf(stderr, "Out of memory!\n"); + if (bufin) + free(bufin); + exit(1); + } + bufin = realloc(bufout, bufsize); + if (!bufin) { + fprintf(stderr, "Out of memory!\n"); + if (bufout) + free(bufout); + exit(1); + } + } + + memcpy(bufout, writearr, writecnt); + /* Shift out 0x00 while reading data. */ + memset(bufout + writecnt, 0x00, readcnt); + /* Make sure any non-read data is 0xff. */ + memset(bufin + writecnt, 0xff, readcnt); + + bitbang_set_cs(0); + for (i = 0; i < readcnt + writecnt; i++) { + bufin[i] = bitbang_spi_readwrite_byte(bufout[i]); + } + programmer_delay(bitbang_half_period); + bitbang_set_cs(1); + programmer_delay(bitbang_half_period); + memcpy(readarr, bufin + writecnt, readcnt); + + return 0; +} + +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64k bytes. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + + printf_debug("total_size is %d\n", total_size); + for (i = 0; i < total_size; i += 256) { + int l, r; + if (i + 256 <= total_size) + l = 256; + else + l = total_size - i; + + if ((r = spi_nbyte_program(i, &buf[i], l))) { + fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); + return 1; + } + + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + /* loop */; + } + + return 0; +} + +#else +int bitbang_spi_init(void) +{ + fprintf(stderr, "Bitbanging SPI support was not compiled in\n"); + exit(1); +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + fprintf(stderr, "Bitbanging SPI support was not compiled in\n"); + exit(1); +} + +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + fprintf(stderr, "Bitbanging SPI support was not compiled in\n"); + exit(1); +} + +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +{ + fprintf(stderr, "Bitbanging SPI support was not compiled in\n"); + exit(1); +} +#endif Index: flashrom-bitbang_spi/spi.c =================================================================== --- flashrom-bitbang_spi/spi.c (Revision 682) +++ flashrom-bitbang_spi/spi.c (Arbeitskopie) @@ -95,6 +95,13 @@ .read = NULL, .write_256 = NULL, }, + + { /* SPI_CONTROLLER_BITBANG */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, }; Index: flashrom-bitbang_spi/Makefile =================================================================== --- flashrom-bitbang_spi/Makefile (Revision 682) +++ flashrom-bitbang_spi/Makefile (Arbeitskopie) @@ -67,11 +67,19 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG = yes +# Bitbanging SPI is not yet ready. +CONFIG_BITBANG_SPI = yes + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o endif +ifeq ($(CONFIG_BITBANG_SPI), yes) +FEATURE_CFLAGS += -D'BITBANG_SPI_SUPPORT=1' +OBJS += bitbang_spi.o +endif + FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") Index: flashrom-bitbang_spi/flashrom.c =================================================================== --- flashrom-bitbang_spi/flashrom.c (Revision 682) +++ flashrom-bitbang_spi/flashrom.c (Arbeitskopie) @@ -158,6 +158,23 @@ }, #endif + { + .name = "bitbangspi", + .init = bitbang_spi_init, + .shutdown = fallback_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = dummy_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = fallback_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; @@ -512,7 +529,7 @@ " -z | --list-supported-wiki: print supported devices in wiki syntax\n" " -p | --programmer <name>: specify the programmer device\n" " (internal, dummy, nic3com, satasii,\n" - " it87spi, ft2232spi, serprog)\n" + " it87spi, ft2232spi, serprog, bitbangspi)\n" " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" -- http://www.hailfinger.org/

2 6

[commit] r741 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: hailfinger Date: 2009-10-01 16:51:25 +0200 (Thu, 01 Oct 2009) New Revision: 741 Modified: trunk/bitbang_spi.c trunk/flash.h trunk/flashrom.c Log: Make bitbang_spi naming consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/bitbang_spi.c =================================================================== --- trunk/bitbang_spi.c 2009-10-01 14:11:43 UTC (rev 740) +++ trunk/bitbang_spi.c 2009-10-01 14:51:25 UTC (rev 741) @@ -26,40 +26,40 @@ #include "spi.h" /* Length of half a clock period in usecs */ -int bitbang_half_period = 0; +int bitbang_spi_half_period = 0; -enum spi_bitbang_master spi_bitbang_master = SPI_BITBANG_INVALID; +enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; -const struct spi_bitbang_master_entry spi_bitbang_master_table[] = { - {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ +const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { + {}, /* This entry corresponds to BITBANG_SPI_INVALID. */ }; -const int spi_bitbang_master_count = ARRAY_SIZE(spi_bitbang_master_table); +const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table); -void bitbang_set_cs(int val) +void bitbang_spi_set_cs(int val) { - spi_bitbang_master_table[spi_bitbang_master].set_cs(val); + bitbang_spi_master_table[bitbang_spi_master].set_cs(val); } -void bitbang_set_sck(int val) +void bitbang_spi_set_sck(int val) { - spi_bitbang_master_table[spi_bitbang_master].set_sck(val); + bitbang_spi_master_table[bitbang_spi_master].set_sck(val); } -void bitbang_set_mosi(int val) +void bitbang_spi_set_mosi(int val) { - spi_bitbang_master_table[spi_bitbang_master].set_mosi(val); + bitbang_spi_master_table[bitbang_spi_master].set_mosi(val); } -int bitbang_get_miso(void) +int bitbang_spi_get_miso(void) { - return spi_bitbang_master_table[spi_bitbang_master].get_miso(); + return bitbang_spi_master_table[bitbang_spi_master].get_miso(); } int bitbang_spi_init(void) { - bitbang_set_cs(1); - bitbang_set_sck(0); + bitbang_spi_set_cs(1); + bitbang_spi_set_sck(0); buses_supported = CHIP_BUSTYPE_SPI; return 0; } @@ -70,13 +70,13 @@ int i; for (i = 7; i >= 0; i--) { - bitbang_set_mosi((val >> i) & 1); - programmer_delay(bitbang_half_period); - bitbang_set_sck(1); + bitbang_spi_set_mosi((val >> i) & 1); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(1); ret <<= 1; - ret |= bitbang_get_miso(); - programmer_delay(bitbang_half_period); - bitbang_set_sck(0); + ret |= bitbang_spi_get_miso(); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(0); } return ret; } @@ -117,13 +117,13 @@ /* Make sure any non-read data is 0xff. */ memset(bufin + writecnt, 0xff, readcnt); - bitbang_set_cs(0); + bitbang_spi_set_cs(0); for (i = 0; i < readcnt + writecnt; i++) { bufin[i] = bitbang_spi_readwrite_byte(bufout[i]); } - programmer_delay(bitbang_half_period); - bitbang_set_cs(1); - programmer_delay(bitbang_half_period); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_cs(1); + programmer_delay(bitbang_spi_half_period); memcpy(readarr, bufin + writecnt, readcnt); return 0; @@ -149,7 +149,7 @@ l = total_size - i; if ((r = spi_nbyte_program(i, &buf[i], l))) { - fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); + fprintf(stderr, "%s: write fail %d\n", __func__, r); return 1; } Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-10-01 14:11:43 UTC (rev 740) +++ trunk/flash.h 2009-10-01 14:51:25 UTC (rev 741) @@ -148,15 +148,15 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); -enum spi_bitbang_master { - SPI_BITBANG_INVALID /* This must always be the last entry. */ +enum bitbang_spi_master { + BITBANG_SPI_INVALID /* This must always be the last entry. */ }; -extern const int spi_bitbang_master_count; +extern const int bitbang_spi_master_count; -extern enum spi_bitbang_master spi_bitbang_master; +extern enum bitbang_spi_master bitbang_spi_master; -struct spi_bitbang_master_entry { +struct bitbang_spi_master_entry { void (*set_cs) (int val); void (*set_sck) (int val); void (*set_mosi) (int val); @@ -470,8 +470,8 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); /* bitbang_spi.c */ -extern int bitbang_half_period; -extern const struct spi_bitbang_master_entry spi_bitbang_master_table[]; +extern int bitbang_spi_half_period; +extern const struct bitbang_spi_master_entry bitbang_spi_master_table[]; int bitbang_spi_init(void); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-01 14:11:43 UTC (rev 740) +++ trunk/flashrom.c 2009-10-01 14:51:25 UTC (rev 741) @@ -713,7 +713,7 @@ exit(1); } #if BITBANG_SPI_SUPPORT == 1 - if (spi_bitbang_master_count - 1 != SPI_BITBANG_INVALID) { + if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); exit(1); }

1 0

[commit] r740 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: uwe Date: 2009-10-01 16:11:43 +0200 (Thu, 01 Oct 2009) New Revision: 740 Modified: trunk/Makefile Log: Disable NVIDIA flashing support for now, erase/write is not properly working, yet. This needs more testing and investigation (partly timing related, it seems). Reads did work in multiple cases, though. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-10-01 13:16:32 UTC (rev 739) +++ trunk/Makefile 2009-10-01 14:11:43 UTC (rev 740) @@ -74,8 +74,8 @@ # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes -# Always enable NVIDIA graphics cards for now. -CONFIG_GFXNVIDIA ?= yes +# Disable NVIDIA graphics cards for now, write/erase don't work properly. +CONFIG_GFXNVIDIA ?= no # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes

1 0

[PATCH] Introduce proper error checking for SPI programming
by Carl-Daniel Hailfinger 01 Oct '09

01 Oct '09

Introduce proper error checking for SPI programming. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_program_errorcheck/spi.c =================================================================== --- flashrom-spi_program_errorcheck/spi.c (Revision 725) +++ flashrom-spi_program_errorcheck/spi.c (Arbeitskopie) @@ -971,7 +971,7 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; + int i, result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -982,7 +982,9 @@ } printf("done.\n"); for (i = 0; i < total_size; i++) { - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); + if (result) + return 1; while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Index: flashrom-spi_program_errorcheck/sb600spi.c =================================================================== --- flashrom-spi_program_errorcheck/sb600spi.c (Revision 725) +++ flashrom-spi_program_errorcheck/sb600spi.c (Arbeitskopie) @@ -48,9 +48,9 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; + int i; int total_size = flash->total_size * 1024; - int result; + int result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -63,10 +63,10 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { - result = spi_byte_program(i, *buf); + result = spi_nbyte_program(i, buf, 1); if (result) { - // spi_byte_program reported the error for us already - printf_debug("... continuing anyway.\n"); + fprintf(stderr, "Write error!\n"); + return result; } /* wait program complete. */ @@ -76,7 +76,7 @@ ; } printf(" done.\n"); - return rc; + return result; } static void reset_internal_fifo_pointer(void) -- http://www.hailfinger.org/

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