- flashrom - mail.coreboot.org

Gigabyte 7ZXE Rev 1.0
by Charles M 21 Dec '09

21 Dec '09

Here's the flashrom, lspci and superiotool information for the Gigabyte 7ZXE motherboard. From Gigabytes web site it looks like there have been at least a couple of revisions of this motherboard. This is revision 1.0. The link to Gigabyte's information on this site is: http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI… Cheers, Charles

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MSI KM2M Combo
by Charles M 21 Dec '09

21 Dec '09

The MSI KM2M Combo is a Socket A (462) motherboard that sports 2 SDRAM and 2 DDR-SDRAM memory slots, 3 PCI slots and 1 AGP slot. I've attached the flashrom,lspci, and superiotool information for this board. Cheers, Charles

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[PATCH] Intel Poulsbo chipset support
by Adam Jurkowski 21 Dec '09

21 Dec '09

Add support for Intel Poulsbo chipset. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl>

3 6

ECS K7SOM+ motherboard
by Charles M 21 Dec '09

21 Dec '09

We semi-frequently see these ECS K7SOM+ motherboards and usually end up tossing them because the CPU soldered to the motherboard. The ECS web site dynamically generates pages but the manual still appears if you select Motherboard > Onboard and the K7SOM+. I've attached the flashrom, lspci and superiotool output. If anyone has further questions about the motherboard please email me directly and I'll investigate further. Charles McColm

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Acer Ali 1631
by Charles M 21 Dec '09

21 Dec '09

This motherboard came to us in a beige box, so I can't comment on the particular model of motherboard. It shows as an Acer Ali 1631 as the Motherboard Model and Hsing Tech Enterprises as the motherboard OEM. Cheers, Charles

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Intel D850GB "Intel Desktop Board"
by Charles M 21 Dec '09

21 Dec '09

The Intel D850GB has the words "Intel Desktop Board" imprinted on the motherboard, but it's pretty far from being a general user desktop motherboard. It sports 4 RAMBUS 600/800 slots and what looks to be a non-standard connector for power button and LEDs (but most cases could be rigged to fit). This motherboard is a single CPU Socket 423 motherboard. The manual can be found: http://www.intel.com/support/motherboards/desktop/d850gb/sb/cs-013247.htm If anyone has further questions about the motherboard please email me directly and I'll investigate further. Cheers, Charles

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[PATCH] Boards: Fix several issues with nvidia_mcp_gpio_set.
by Luc Verhaegen 21 Dec '09

21 Dec '09

- CK804, MCP04, MCP2 use the isa bridges.. - Newer nvidia mcp's do use the smbus controllers (Found by Michael Karcher). - gpio line check breaks EPoX EP-8RDA3+, and should be wider. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index 8b5ed95..2c58927 100644 --- a/board_enable.c +++ b/board_enable.c @@ -440,20 +440,30 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) uint16_t base; uint8_t tmp; - if ((gpio < 0) || (gpio > 31)) { + if ((gpio < 0) || (gpio > 0x40)) { fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + /* First, check the ISA Bridge */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: - fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); + /* Newer MCPs use the SMBus Controller */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0264: /* MCP51 */ + break; + default: + fprintf(stderr, + "\nERROR: no nVidia LPC/SMBus controller found.\n"); return -1; + } + break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ -- 1.6.0.2 --lrZ03NoBR/3+SXJZ--

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Board enable requested
by Bill Maidment 21 Dec '09

21 Dec '09

Hello there. My motherboard is a Gigabyte GA-M51GM-S2G no version number apparent. The requested diagnostics are attached. BIOS downloads are available from http://www.giga-byte.com/Support/Motherboard/BIOS_Model.aspx?ProductID=2281 Please let me know when the board enable patch is available. Many thanks for the excellent service. Regards Bill -- Bill Maidment Maidment Enterprises Pty Ltd www.maidment.vu Consultant to Elgas Ltd Phone: 02 9904 3364

3 2

ASUS CUV4X-C
by Charles M 21 Dec '09

21 Dec '09

The ASUS CUV4X comes in a few varieties that our Computer Refurbishing project sees. This one is the -C version. Asus uses dynamic pages to distribute manuals, etc., and the manual from this baby can be found at http://support.asus.com/. This board is a socket 370 (Pentium III/Celeron) motherboard. If more data is required please email me and I can look into detailing the system more. (see attached flashrom,lspci,superiotools info). Charles McColm

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[commit] r809 - trunk
by svn＠flashrom.org 21 Dec '09

21 Dec '09

Author: libv Date: 2009-12-21 16:30:46 +0100 (Mon, 21 Dec 2009) New Revision: 809 Modified: trunk/chipset_enable.c Log: Chipset: Add support for Intel Poulsbo chipset. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-12-18 08:37:55 UTC (rev 808) +++ trunk/chipset_enable.c 2009-12-21 15:30:46 UTC (rev 809) @@ -5,6 +5,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger + * Copyright (C) 2009 Kontron Modular Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -391,6 +392,26 @@ return enable_flash_ich(dev, name, 0xdc); } +static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) +{ + uint16_t old, new; + int err; + + if ((err = enable_flash_ich(dev, name, 0xd8)) != 0) + return err; + + old = pci_read_byte(dev, 0xd9); + printf_debug("BIOS Prefetch Enable: %sabled, ", + (old & 1) ? "en" : "dis"); + new = old & ~1; + + if (new != old) + pci_write_byte(dev, 0xd9, new); + + return 0; +} + + #define ICH_STRAP_RSVD 0x00 #define ICH_STRAP_SPI 0x01 #define ICH_STRAP_PCI 0x02 @@ -1155,6 +1176,7 @@ {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */

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Fail to flash BIOS under ICH9R with descriptor mode
by eugenehsu 21 Dec '09

21 Dec '09

Hi I used the flashrom with SB ICH9R and flash chip SST SST25VF016B, and the descriptor mode is activated. The software version is flashrom-0.9.1 and pciutils-3.1.4. I failed to flash the BIOS. Please refer to the messages: =========================== DiskStation> ./flashrom -E flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x001fffff: 0x3000 ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x00 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! =========================== BTW, please find the "flashrom -E -V" messages in the attachment. Do you know how to solve this problem ? Thanks for your help. Eugene

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[PATCH] Board: Add Gigabyte M51GM.
by Luc Verhaegen 21 Dec '09

21 Dec '09

The board ids match the M55Plus, but guess what, they require the same board enable ;) Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index 8b5ed95..91d27ac 100644 --- a/board_enable.c +++ b/board_enable.c @@ -445,11 +445,12 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { - case 0x0030: /* CK804 */ - case 0x0050: /* MCP04 */ + case 0x0030: /* MCP04 */ + case 0x0050: /* CK804 */ case 0x0060: /* MCP2 */ + case 0x0260: /* MCP51 */ break; default: fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); @@ -494,6 +495,14 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for Gigabyte GA-M51GM-S2G: nVidia MCP51. + */ +static int nvidia_mcp_gpio3B_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x3B, 0x01); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1251,6 +1260,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, + {0x10DE, 0x02FA, 0x1458, 0x5000, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, "GIGABYTE", "GA-M51GM/M55plus", nvidia_mcp_gpio3B_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, -- 1.6.0.2 --AhhlLboLdkugWU4S--

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Re: [flashrom] Scary error message
by Luc Verhaegen 21 Dec '09

21 Dec '09

On Sun, Dec 20, 2009 at 05:01:38PM -0800, Fraser Hanson wrote: > OK, tonight I checked out the latest flashrom from svn, patched it and > compiled it. > > I then tried to flash my bios with my original bios. > > The flash failed, as follows: > > fraser@ged:~/bios/flashrom$ sudo ./flashrom -w ../stock-bios.bin > flashrom v0.9.1-r808 > No coreboot table found. > Found chipset "NVIDIA CK804", enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Disabling flash write protection for board "MSI K8N Neo4-F"... > ERROR: no nVidia SMBus controller found. > FAILED! > Calibrating delay loop... OK. > Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Programming page: ERASE FAILED at 0x00000000! > Expected=0xff, Read=0x49, failed byte count from > 0x00000000-0x0000ffff: 0x599 > ERASE FAILED! > ERASE FAILED! > FAILED! > Your flash chip is in an unknown state. > Get help on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! Ah, urgh, nvidia mcp gpio code is busted. Here is an updated patch. Luc Verhaegen.

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[PATCH] Board: Add MSI K8N Neo4.
by Luc Verhaegen 21 Dec '09

21 Dec '09

Fix up nvidia_mcp_gpio_set while we are at it. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index 8b5ed95..fa71818 100644 --- a/board_enable.c +++ b/board_enable.c @@ -445,10 +445,10 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { - case 0x0030: /* CK804 */ - case 0x0050: /* MCP04 */ + case 0x0030: /* MCP04 */ + case 0x0050: /* CK804 */ case 0x0060: /* MCP2 */ break; default: @@ -470,6 +470,14 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) } /** + * Suited for MSI K8N Neo4: nVidia CK804. + */ +static int nvidia_mcp_gpio2_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x02, 1); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) @@ -1267,6 +1275,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --DocE+STaALJfprDB--

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ASUS P4P800 SE
by Charles M 20 Dec '09

20 Dec '09

The ASUS P4P800 motherboard has a few variations - I've seen a few of these LGA755 boards come in (for repair - yikes), is the P4P800 SE variant. I have the physical paper manual and access to the motherboard. Cheers, Charles

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Foxconn 946GZ7MA-KS2H (LGA775)
by Charles M 20 Dec '09

20 Dec '09

This motherboard actually resides in our home multimedia centre, it's not a great board, but it gets us by with the ATI video card we have in it. You can find the Foxconn specs at: http://www.foxconnchannel.com/product/Motherboards/detail_overview.aspx?ID=… Cheers, Charles p.s. Someone please tell me to stop if it's too much.

1 0

P2-BX (NOT ASUS)
by Charles M 20 Dec '09

20 Dec '09

The following motherboard is marked P2-BX but is NOT an ASUS motherboard despite a similar naming scheme. The board came into work with the paper motherboard manual (not at work at the moment). The manual is a very plain looking manual, not like Asus' typical documentation. Someone has incorrectly listed the P2-BX as an Asus motherboard on a couple of sites, but I can guarantee after looking closely at the board it's not. If I remember correctly it is a Slot 1 motherboard. Cheers, Charles

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Intel D845GEBV2
by Charles M 20 Dec '09

20 Dec '09

The Intel D845GEBV2 motherboard is one we see every once in a while. Intel currently maintains documentation on this board here: http://www.intel.com/support/motherboards/desktop/D845GEBV2/ Charles

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ASUSTEK CUSI-FX
by Charles M 20 Dec '09

20 Dec '09

We get quite a few ASUS motherboards, but the ASUSTEK CUSI-FX is one of the more interesting boards that we've come across lately. It's a Socket 370 motherboard (PIII). Asus has all motherboards available under the support section of their site. It's dynamically generated so you'll have to select MOTHERBOARDS > Socket 370 then CUSI-FX from: http://support.asus.com/download/download.aspx?SLanguage=en-us Regards, Charles

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Aopen MX36-LE-UN
by Charles M 20 Dec '09

20 Dec '09

Here is the start of the motherboard information uploads. I managed to capture four motherboards in the last half hour of work. I'm at home now and have to run, but here's one of the 4. I'll upload the other 3 later when I get back. Aopen MX36-LE-UN Motherboard Motherboard manual link (GERMANY): http://download.aopen.com.tw/Download.aspx?RecNo=3771&Model=238&Section=10&… Cheers, Charles McColm

2 1

Requested Information
by Corey Hamilton 18 Dec '09

18 Dec '09

Hello, Thanks for helping me get to the bottom of this issue. It's much appreciated! Here's the info you've requested: Motherboard: Asus M2NBP-VM CSM Official BIOS URL: ftp://ftp.asus.com/pub/ASUS/mb/socketAM2/M2NBP-VM_CSM/1101.zip Verbose outputs follow... thanks again! Corey Verbose outputs as requested: ---- ~# flashrom -V flashrom v0.9.1-r710 No coreboot table found. Found chipset "NVIDIA MCP51", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 632M loops per second, 100 myus = 196 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x00, id2 0xff Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x24, id2 0x4e Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x24, id2 0x4e Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x24, id2 0x4e Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x24, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x24, id2 0x2d Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x24, id2 0x4e Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x45, id2 0xa3 Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x45, id2 0xa3 Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x24, id2 0x4e Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x24, id2 0x4e Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x24, id2 0x4e Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x24, id2 0x2d Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x45, id2 0xa3 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x24, id2 0x4e Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified. ---- ---- lspci output ---- 00:00.0 RAM memory [0500]: nVidia Corporation C51 Host Bridge [10de:02f0] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 1: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 800MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 800MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping 00: de 10 f0 02 06 00 b0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 43 10 c0 81 08 e0 e0 01 22 00 11 11 22 20 11 00 50: 23 05 7f 80 03 05 7f 80 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 15 05 00 70: 44 44 41 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 1f 00 64 0c 03 00 00 00 7f 00 00 00 90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 61 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 10 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.1 RAM memory [0500]: nVidia Corporation C51 Memory Controller 0 [10de:02fa] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- 00: de 10 fa 02 00 01 20 40 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 10 00 21 21 14 00 11 11 00 00 03 00 00 00 60: 21 88 13 02 de 8f e1 1f 08 72 4e 10 02 3f 00 20 70: 10 32 54 0a 10 00 00 00 a0 00 00 00 10 00 01 01 80: 00 00 00 00 00 00 00 00 00 00 50 3f 90 3f 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 01 00 00 00 80 f9 fd 00 e0: 00 00 c9 fe 00 00 00 00 00 fc ff ff 00 00 00 00 f0: 00 00 00 00 c7 02 32 00 00 00 00 00 00 00 00 00 00:00.2 RAM memory [0500]: nVidia Corporation C51 Memory Controller 1 [10de:02fe] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: de 10 fe 02 00 00 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 43 10 c0 81 1f 20 1c 20 1f 20 c0 21 00 00 00 00 50: 36 00 38 c9 01 00 00 00 39 00 3b c9 02 1f 1c 80 60: 02 1f 1c 00 00 00 00 00 02 10 1c a0 02 0c 1c 90 70: 02 10 1c 90 02 14 1c 90 02 0c 1c 80 02 10 1c 80 80: 02 14 1c 80 02 18 1c 80 02 1c 1c 80 01 10 1c 80 90: 02 10 1c 80 11 00 11 00 32 01 00 00 00 00 00 00 a0: c2 00 40 21 10 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 41 23 05 08 c0: fd ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.3 RAM memory [0500]: nVidia Corporation C51 Memory Controller 5 [10de:02f8] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: de 10 f8 02 00 00 a0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 10 c0 81 00 00 00 00 02 10 1c 80 02 10 1c a0 50: 02 0c 1c 90 02 10 1c 90 02 14 1c 90 02 0c 1c 80 60: 02 10 1c 80 02 14 1c 80 02 18 1c 80 02 1c 1c 80 70: 01 10 1c 80 1f 20 c0 81 00 00 00 00 3e 30 40 c9 80: 01 00 00 00 45 30 47 c9 02 1f 1c 80 70 20 00 40 90: 89 da 01 09 00 00 00 00 11 00 10 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 08 00 00 00 e4 18 00 00 10 00 02 00 40 14 00 14 c0: 00 00 00 00 00 00 00 00 01 01 00 05 00 00 00 00 d0: 00 00 f0 03 00 04 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 60 ea 10 10 18 00 00 20 00 00 00 00 00 00 00 00 00:00.4 RAM memory [0500]: nVidia Corporation C51 Memory Controller 4 [10de:02f9] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: de 10 f9 02 06 00 a0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: ef dd 7b 2f f7 de 7b 2f f7 de 7b 2f f7 02 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 70: 0a 00 00 00 03 00 00 00 25 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 05 00 00 00 04 00 00 00 90: 03 04 00 00 01 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.5 RAM memory [0500]: nVidia Corporation C51 Host Bridge [10de:02ff] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] #00 [00fe] Capabilities: [fc] #00 [0000] 00: de 10 ff 02 06 00 b0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 17 00 00 00 00 fe fe 00 00 fe fe 00 00 fe fe 00 50: 00 fe fe 00 00 fe fe 00 00 fe fe 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.6 RAM memory [0500]: nVidia Corporation C51 Memory Controller 3 [10de:027f] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: de 10 7f 02 02 01 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 00 00 00 00 00 00 00 00 80 cb fe 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.7 RAM memory [0500]: nVidia Corporation C51 Memory Controller 2 [10de:027e] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: de 10 7e 02 00 00 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 43 10 c0 81 11 00 00 00 64 06 00 00 11 00 00 00 50: 63 06 00 00 40 00 70 00 70 60 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04 b0: ff ff 03 00 10 11 00 00 ac 10 20 00 30 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fc] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: fd800000-fd8fffff Prefetchable memory behind bridge: 00000000fd700000-00000000fd7fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0100c Data: 41a9 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 2 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x1 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 fc 02 07 04 10 00 a1 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 00 20: 80 fd 80 fd 71 fd 71 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 10 e0 fe 00 00 00 00 a9 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 11 3c 11 02 90: 00 00 11 10 00 00 00 00 c0 01 00 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fd] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00008000-00008fff Memory behind bridge: fde00000-fdefffff Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0100c Data: 41b1 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 1 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x1 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 fd 02 07 04 10 00 a1 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 81 81 00 00 20: e0 fd e0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 10 e0 fe 00 00 00 00 b1 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 11 3c 11 01 90: 00 00 11 10 00 00 00 00 c0 01 00 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fb] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fdc00000-fdcfffff Prefetchable memory behind bridge: 00000000fd900000-00000000fd9fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0100c Data: 41b9 Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s <512ns, L1 <4us Device: Errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x16, ASPM L0s L1, Port 0 Link: Latency L0s <512ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x16 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise- Slot: Number 0, PowerLimit 0.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Off, PwrInd On, Power- Root: Correctable- Non-Fatal- Fatal- PME- 00: de 10 fb 02 07 04 10 00 a1 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 b1 b1 00 00 20: c0 fd c0 fd 91 fd 91 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 10 e0 fe 00 00 00 00 b9 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 01 3d 11 00 90: 00 00 01 11 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 VGA compatible controller [0300]: nVidia Corporation C51 [Quadro NVS 210S/GeForce 6150LE] [10de:0245] (rev a2) (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81cd] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 20 Region 0: Memory at fc000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at fb000000 (64-bit, non-prefetchable) [size=16M] [virtual] Expansion ROM at 50000000 [disabled] [size=128K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 00: de 10 45 02 07 00 b0 00 a2 00 00 03 00 00 00 00 10: 00 00 00 fc 0c 00 00 d0 00 00 00 00 04 00 00 fb 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 cd 81 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 01 00 00 40: 43 10 cd 81 00 00 00 00 01 50 02 00 00 00 00 00 50: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 00 00 04 00 00 00 00 00 00 00 01 00 00 00 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: 00 00 7c 00 00 00 00 02 00 00 00 00 ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00:09.0 RAM memory [0500]: nVidia Corporation MCP51 Host Bridge [10de:0270] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=9 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 0: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 800MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping 00: de 10 70 02 06 00 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 43 10 c0 81 08 e0 e9 01 22 20 00 00 d0 00 00 00 50: 23 05 7f 80 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 15 05 00 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 55 00 80: 23 55 55 00 fa 00 64 0c 03 00 00 00 7f 00 00 00 90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 ISA bridge [0601]: nVidia Corporation MCP51 LPC Bridge [10de:0260] (rev a3) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: de 10 60 02 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 10 c0 81 00 f0 ff fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f9 ff 70: 10 00 ff ff c5 00 00 00 00 00 45 19 00 00 00 03 80: 09 10 00 81 02 2d 00 00 c0 00 00 01 00 00 00 00 90: 00 00 00 00 00 00 00 00 21 47 65 b7 ef cd 00 00 a0: 01 00 10 c1 00 00 00 00 00 00 00 00 00 00 00 00 b0: 90 02 ef 02 00 08 5f 08 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:0a.1 SMBus [0c05]: nVidia Corporation MCP51 SMBus [10de:0264] (rev a3) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 10 Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 64 02 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4c 00 00 41 4c 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 00 00 40: 43 10 c0 81 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 40 00 00 01 44 00 00 01 48 00 00 00 00 00 00 70: 01 00 00 00 00 00 c8 fe 00 00 fe fe 01 20 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 01 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 10 10 04 00 00 a0 00 00 80 30 00 00 41 44 44 11 f0: 5a ff 5f bf 00 00 00 c0 10 00 00 00 00 00 00 00 00:0a.2 RAM memory [0500]: nVidia Corporation MCP51 Memory Controller 0 [10de:0272] (rev a3) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: de 10 72 02 00 04 a0 00 a3 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10 50: 10 10 10 10 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 03 00 00 12 00 00 00 02 00 00 00 10 01 12 00 70: 32 33 00 00 03 00 00 00 00 00 00 00 12 01 00 00 80: 10 00 00 00 00 00 00 00 00 00 00 00 30 02 00 00 90: 00 00 00 00 01 20 00 00 01 00 00 00 00 09 00 00 a0: 01 02 00 00 00 10 00 00 05 00 00 00 01 00 00 00 b0: 00 10 00 80 01 00 00 80 00 00 00 00 02 00 00 00 c0: 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 USB Controller [0c03]: nVidia Corporation MCP51 USB Controller [10de:026d] (rev a3) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 17 Region 0: Memory at fe02f000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 6d 02 07 00 b0 00 a3 10 03 0c 00 00 80 00 10: 00 f0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01 40: 43 10 c0 81 01 00 02 fe 00 00 00 00 00 00 00 00 50: 03 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.1 USB Controller [0c03]: nVidia Corporation MCP51 USB Controller [10de:026e] (rev a3) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81c0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 16 Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 00: de 10 6e 02 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 02 03 01 40: 43 10 c0 81 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 0a 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 04 00 80: 01 00 02 fe 00 80 00 00 00 00 00 00 15 16 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 11 22 33 00 00 00 00 ff 00 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:0d.0 IDE interface [0101]: nVidia Corporation MCP51 IDE [10de:0265] (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: Unknown device [f043:81c0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at f400 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 65 02 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f4 00 00 00 00 00 00 00 00 00 00 43 f0 c0 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 43 f0 c0 81 01 00 02 00 00 00 00 00 00 00 00 00 50: 03 f0 01 00 00 00 00 00 99 99 99 99 aa 00 a8 a8 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:0e.0 IDE interface [0101]: nVidia Corporation MCP51 Serial ATA Controller [10de:0266] (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:9999] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at e000 [size=16] Region 5: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 66 02 07 00 b0 00 a1 85 01 01 00 00 00 00 10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00 20: 01 e0 00 00 00 d0 02 fe 00 00 00 00 43 10 99 99 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01 40: 43 10 99 99 01 b0 02 00 00 00 00 00 00 00 00 00 50: 03 00 00 00 00 00 00 00 a8 a8 a8 a8 aa 00 99 99 60: 00 00 00 00 51 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 00 01 00 11 08 00 00 d0 00 28 08 88 0c 90: 00 00 2d 1a 00 00 00 00 06 00 06 10 00 00 01 01 a0: 14 10 00 00 00 00 00 00 00 00 00 00 33 33 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 01 00 02 6b 42 00 00 00 00 00 00 00 0f 00 b0 07 e0: 01 00 02 6b 42 00 00 00 00 00 00 00 00 00 20 00 f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00:0f.0 IDE interface [0101]: nVidia Corporation MCP51 Serial ATA Controller [10de:0267] (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:9999] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 16 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at cc00 [size=16] Region 5: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 67 02 07 00 b0 00 a1 85 01 01 00 00 00 00 10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00 20: 01 cc 00 00 00 c0 02 fe 00 00 00 00 43 10 99 99 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01 40: 43 10 99 99 01 b0 02 00 00 00 00 00 00 00 00 00 50: 03 00 00 00 00 00 00 00 a8 a8 a8 a8 aa 00 99 99 60: 00 00 00 00 51 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 00 41 06 09 08 00 00 05 03 8b 81 a2 80 90: 00 00 e4 19 00 00 00 00 06 00 06 10 00 00 01 01 a0: 14 10 00 00 00 00 00 00 00 00 00 00 33 33 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 01 00 02 6b 42 00 00 00 00 00 00 00 00 00 f0 07 e0: 01 00 02 6b 42 00 00 00 00 00 00 00 00 00 30 00 f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00:10.0 PCI bridge [0604]: nVidia Corporation MCP51 PCI Bridge [10de:026f] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=128 I/O behind bridge: 00009000-00009fff Memory behind bridge: fdb00000-fdbfffff Prefetchable memory behind bridge: fda00000-fdafffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [b8] Subsystem: Gammagraphx, Inc. Unknown device [0000:0000] Capabilities: [8c] HyperTransport: MSI Mapping 00: de 10 6f 02 07 00 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 80 90 90 80 02 20: b0 fd b0 fd a0 fd a0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 ff 00 04 02 40: 00 00 03 00 01 00 02 00 07 00 00 00 00 00 4c 00 50: 00 00 fe 3f 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 00 00 00 00 c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:10.1 Audio device [0403]: nVidia Corporation MCP51 High Definition Audio [10de:026c] (rev a2) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:81b3] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (500ns min, 1250ns max) Interrupt: pin B routed to IRQ 17 Region 0: Memory at fe024000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping 00: de 10 6c 02 06 00 b0 00 a2 00 03 04 00 00 80 00 10: 00 40 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 02 05 40: 43 10 b3 81 01 50 02 c0 00 00 00 00 01 01 0f 00 50: 05 6c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 46 00 29 00 00 00 00 00 00 00:14.0 Bridge [0680]: nVidia Corporation MCP51 Ethernet Controller [10de:0269] (rev a3) Subsystem: ASUSTeK Computer Inc. Unknown device [1043:816a] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 18 Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at c800 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping 00: de 10 69 02 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 b0 02 fe 01 c8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 6a 81 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14 40: 43 10 6a 81 01 50 02 fe 00 01 00 00 0b 00 00 00 50: 05 6c 84 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 11 00 00 00 42 01 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 00 00 e4 00 00 00 0f cc 20 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 05 35 80 02 00 00 00 90: 69 01 61 01 00 00 04 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 3f 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 0a 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 90: 03 00 40 00 00 ff df 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 03 00 f0 00 00 02 fe 00 b0: 03 00 e0 00 80 4f e0 00 00 00 00 00 00 00 00 00 c0: 13 80 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 81 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 60 3f 38 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 80: 00 02 00 00 00 00 00 00 24 f2 7d 0c 20 13 02 04 90: 10 04 01 00 5b 80 10 77 24 00 00 80 20 25 2b 00 a0: ff 02 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 b0: 1b 9c 7f 93 80 00 00 00 36 1d 00 50 a2 06 c0 22 c0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 28 20 41 3e 89 00 05 21 1a d9 c1 24 00 90 90 b0 e0: 9a 40 e9 36 9f f1 82 17 85 10 98 38 2f 32 80 38 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 01 00 00 40 00 10 02 00 00 00 00 00 00 00 00 50: f8 40 b4 57 b7 00 00 00 00 00 00 00 40 79 8a 91 60: e7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 32 51 21 40 70 50 00 2a 00 08 18 21 00 00 80: 00 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 70 35 89 b7 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 01 a7 0d 00 00 00 80 08 26 26 26 00 e0: 00 00 00 00 36 d9 3f 00 01 05 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 0f 07 00 ---- ---- superiotool -deV output ---- superiotool r4931 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 01 01 00 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 09 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 00 00 0a 00 8a 00 3f def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 00 00 00 00 00 1f 00 00 08 00 00 00 00 00 00 38 00 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Environment controller (0x0295) Register dump: idx 00 04 05 06 07 08 09 0b 0c 10 11 12 13 14 15 16 17 1b 1c 1d 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 48 50 51 52 53 54 56 57 59 5c 5d 5e 5f 60 61 62 63 64 65 68 69 6a 6b 6c 6d 70 71 72 73 74 75 84 85 86 87 88 89 8c 8d 8e 8f 90 91 92 93 94 95 98 99 9a 9b 9c 9d val 11 00 00 00 00 00 80 09 07 d0 d0 ff 70 d7 80 81 82 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 2d ff 31 7f 7f 7f f5 00 00 60 00 00 00 00 19 7f 21 90 03 14 19 48 21 90 80 7f 7f 7f 00 00 03 ff ff ff ff 00 00 02 00 99 99 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f def 18 00 00 00 00 00 80 09 00 NA NA NA 07 50 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA RR 00 00 7f 7f 7f 00 00 00 00 00 00 00 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f NA NA NA NA 00 00 02 00 99 99 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

1 0

[PATCH] Add board enable for ECS K7S6A.
by Luc Verhaegen 18 Dec '09

18 Dec '09

Please use the recent svn, and apply http://patchwork.coreboot.org/patch/635/ first. When this works, please send: Acked-by: [realname here] <spirals(a)eircom.net> Luc Verhaegen.

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Re: [flashrom] [commit] r806 - trunk
by Luc Verhaegen 18 Dec '09

18 Dec '09

On Thu, Dec 17, 2009 at 04:20:02PM +0100, svn(a)flashrom.org wrote: > - Set board-specific max decode size for Elitegroup K7VTA3. > - Set board-specific max decode size for Shuttle AK38N. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > > Modified: trunk/board_enable.c > =================================================================== > --- trunk/board_enable.c 2009-12-17 04:22:40 UTC (rev 805) > +++ trunk/board_enable.c 2009-12-17 15:20:01 UTC (rev 806) > @@ -987,16 +987,24 @@ > } > > /** > - * Suited for: > - * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F > - * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F > + * Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F > */ > -static int it8705f_write_enable_2e(const char *name) > +static int elitegroup_k7vta3(const char *name) > { > + max_rom_decode.parallel = 256 * 1024; > return it8705f_write_enable(0x2e, name); > } > > /** > + * Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F > + */ > +static int shuttle_ak38n(const char *name) > +{ > + max_rom_decode.parallel = 256 * 1024; > + return it8705f_write_enable(0x2e, name); > +} > + > +/** What happened here, and why do we require two different entries here? Luc Verhaegen.

2 1

Re: [flashrom] cannot work on Intel ICH7/ICH7R & SST SST25VF016B (2048 KB, SPI)
by Carl-Daniel Hailfinger 18 Dec '09

18 Dec '09

Hi Water, I am working on a patch which will fix the problem you're seeing. Unfortunately the ICH SPI driver has a few bugs which need to be fixed first. My patch is almost ready. On 15.12.2009 03:25, Water Chen wrote: > Could you kindly check a patch for SST25VF016B? > Your patch was a great help for me because it pinpointed the problem exactly. However, it had a few unfortunate side effects which break flashing on other chips. I will keep you updated about my progress. Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 2

Re: [flashrom] flash erase failure
by Thao Hoang 18 Dec '09

18 Dec '09

Opps sorry... This time the files are attached! The output.txt has both the flashrom and lspci results. This is for the ibase motherboard. I'll send you the the set of files for the laptop in the next e-mail. :) Thao --- On Mon, 11/23/09, Adrian Glaubitz <adrian.glaubitz(a)googlemail.com> wrote: From: Adrian Glaubitz <adrian.glaubitz(a)googlemail.com> Subject: Re: [flashrom] flash erase failure To: "Thao Hoang" <thao_hoang(a)yahoo.com>, flashrom(a)flashrom.org Date: Monday, November 23, 2009, 5:57 PM Hi, On Mon, Nov 23, 2009 at 10:52 PM, Thao Hoang <thao_hoang(a)yahoo.com> wrote: > > Thanks Adrian! I appreciate the advice and insight. You're welcome, again. > I was not able to run superiotool because it wasn't install on my system, however I did run the other two. > See attachment. If you really need me to run superiotool, I can download it and run it. > Yes, please install it. It would be nice to have a full output of: lspci -nnvvvxx superiotool -dV flashrom -V By the way, I don't see your attachments, did you forget them (thats what I usually do :)). Please post the put of all three tools like I suggested to the mailing list (flashrom(a)flashrom.org), that will help us with your board. > Don't laugh... but I haven't used IRC chat before. Never had a reason to until now I guess. Is there a way to post the chats somewhere so that anyone with a similar problem can go there without taking up your time? hum... > Well, really, IRC is nothing magical or mystical. Just use any IRC-capable software to connect (like irssi, pidgin, xchat or mIRC). Set the server to irc.freenode.org and the channel to #flashrom. Then just start asking questions and many people will be happy to help you and answer all your questions. > Also, did I get the syntax correct to force a write <./flashrom -f -w (filename) -c (chipname)>. Yes, think so. Check the manpage. > I have a laptop also that doesn't seem to work off the bat. I was able to force the read and > find some chips that successfullly read the bios. (i.e.... forced read and compared the result > using the original binary which I extracted using a dos bios utility.) Mhh, okey. Don't hesitate to post all your results to the mailing list. Please post every laptop and mainboard and whatever your try to flash in a single mail to the mailing list. And seriously, join the IRC-channel. You'll learn alot of stuff there. Adrian

2 3

[commit] r808 - trunk
by svn＠flashrom.org 18 Dec '09

18 Dec '09

Author: libv Date: 2009-12-18 09:37:55 +0100 (Fri, 18 Dec 2009) New Revision: 808 Modified: trunk/board_enable.c Log: Boards: Add ECS K7S6A. The nulled second set of subsystem ids is correct, and this seems to be a unique match. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: spirals <spirals(a)eircom.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-17 16:20:26 UTC (rev 807) +++ trunk/board_enable.c 2009-12-18 08:37:55 UTC (rev 808) @@ -987,7 +987,9 @@ } /** - * Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F + * Suited for: + * - Elitegroup K7S6A: SiS745 + ITE IT8705F + * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F */ static int elitegroup_k7vta3(const char *name) { @@ -1241,6 +1243,7 @@ {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, + {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, "Elitegroup", "K7S6A", elitegroup_k7vta3}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", elitegroup_k7vta3}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise},

1 0

totally confused
by Blackfoot 18 Dec '09

18 Dec '09

I've clicked about every link and am still confused, I have a 945GCT-M/1333 Mainboard by ECS Elitegroup and can't figure out if you have this listed in your database. Also having trouble figuring out where to start, what to download once I find my board, and how to access links like this: svn://coreboot.org/coreboot/trunk I am a tech and understand basically what you are doing here, but I am just super lost on the site and a lot of links just take me to a page with the icon on it I clicked. Dave.

2 1

[PATCH] Debug excessive toggle bit delay
by Carl-Daniel Hailfinger 17 Dec '09

17 Dec '09

Today's systems are quite capable of running 2^32 reads in short time. Some chips may be slow enough to fall off the loop here. This patch is an attempt at debugging a problem we're seeing on the Winbond W39V040C where the standard toggle bit algorithm seems to fail for block erases. Note: This probably needs a few tweaks before it can be committed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-detect_excessive_toggle/jedec.c =================================================================== --- flashrom-detect_excessive_toggle/jedec.c (Revision 803) +++ flashrom-detect_excessive_toggle/jedec.c (Arbeitskopie) @@ -33,7 +33,7 @@ return (val ^ (val >> 1)) & 0x1; } -void toggle_ready_jedec(chipaddr dst) +void toggle_ready_jedec_common(chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; @@ -41,14 +41,31 @@ tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { + if (delay) + programmer_delay(delay); tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } tmp1 = tmp2; } + if (i > 0x10000) + printf_debug("%s: excessive toggle, i=0x%x\n", __func__, i); } +void toggle_ready_jedec(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 0); +} + +/* Some chips require a minimum delay between toggle bit reads. + * The Winbond W39V040C wants 50 ms between reads on sector erase toggle. + */ +void toggle_ready_jedec_slow(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 50 * 1000); +} + void data_polling_jedec(chipaddr dst, uint8_t data) { unsigned int i = 0; @@ -62,6 +79,8 @@ break; } } + if (i > 0x10000) + printf_debug("%s: excessive data poll, i=0x%x\n", __func__, i); } void start_program_jedec(chipaddr bios) -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

3 6

[commit] r807 - trunk
by svn＠flashrom.org 17 Dec '09

17 Dec '09

Author: hailfinger Date: 2009-12-17 17:20:26 +0100 (Thu, 17 Dec 2009) New Revision: 807 Modified: trunk/jedec.c Log: If the JEDEC Toggle Bit algorithm needs more than 2^20 loops, it is a good sign we should have used delays between toggle bit reads. Tell the user about this. 2^20 loops need roughly a second depending on flash bus speed. One reason for excessive loops can be a slow operation like erase. The Winbond W39V040C requires a 50 ms delay between toggle bit reads during erase according to the datasheet. Turns out a 2 ms delay is sufficient. Use a safety factor of 4 and default all erase operations to 8 ms delay between toggle reads. This is short enough not to have a substantial negative impact on erase times, and should improve reliability. This patch addresses the excessive toggle behaviour (observed on some non-Winbond chips) and the toggle delay requirement (Winbond W39V040C). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Javier Ortega Conde (aka Malkavian) <malkavian666(a)gmail.com> Acked-By: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-12-17 15:20:01 UTC (rev 806) +++ trunk/jedec.c 2009-12-17 16:20:26 UTC (rev 807) @@ -33,7 +33,7 @@ return (val ^ (val >> 1)) & 0x1; } -void toggle_ready_jedec(chipaddr dst) +void toggle_ready_jedec_common(chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; @@ -41,14 +41,35 @@ tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { + if (delay) + programmer_delay(delay); tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } tmp1 = tmp2; } + if (i > 0x100000) + printf_debug("%s: excessive loops, i=0x%x\n", __func__, i); } +void toggle_ready_jedec(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 0); +} + +/* Some chips require a minimum delay between toggle bit reads. + * The Winbond W39V040C wants 50 ms between reads on sector erase toggle, + * but experiments show that 2 ms are already enough. Pick a safety factor + * of 4 and use an 8 ms delay. + * Given that erase is slow on all chips, it is recommended to use + * toggle_ready_jedec_slow in erase functions. + */ +void toggle_ready_jedec_slow(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 8 * 1000); +} + void data_polling_jedec(chipaddr dst, uint8_t data) { unsigned int i = 0; @@ -62,6 +83,8 @@ break; } } + if (i > 0x100000) + printf_debug("%s: excessive loops, i=0x%x\n", __func__, i); } void start_program_jedec(chipaddr bios) @@ -184,7 +207,7 @@ programmer_delay(10); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec_slow(bios); if (check_erased_range(flash, page, pagesize)) { fprintf(stderr,"ERASE FAILED!\n"); @@ -213,7 +236,7 @@ programmer_delay(10); /* wait for Toggle bit ready */ - toggle_ready_jedec(bios); + toggle_ready_jedec_slow(bios); if (check_erased_range(flash, block, blocksize)) { fprintf(stderr,"ERASE FAILED!\n"); @@ -242,7 +265,7 @@ chip_writeb(0x10, bios + 0x5555); programmer_delay(10); - toggle_ready_jedec(bios); + toggle_ready_jedec_slow(bios); if (check_erased_range(flash, 0, total_size)) { fprintf(stderr,"ERASE FAILED!\n");

1 0

[PATCH 1/2] Error out when chipset/board doesn't decode full ROM
by Carl-Daniel Hailfinger 17 Dec '09

17 Dec '09

Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rom_decode_check_infrastructure/flash.h =================================================================== --- flashrom-rom_decode_check_infrastructure/flash.h (Revision 753) +++ flashrom-rom_decode_check_infrastructure/flash.h (Arbeitskopie) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Index: flashrom-rom_decode_check_infrastructure/chipset_enable.c =================================================================== --- flashrom-rom_decode_check_infrastructure/chipset_enable.c (Revision 753) +++ flashrom-rom_decode_check_infrastructure/chipset_enable.c (Arbeitskopie) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Index: flashrom-rom_decode_check_infrastructure/flashrom.c =================================================================== --- flashrom-rom_decode_check_infrastructure/flashrom.c (Revision 753) +++ flashrom-rom_decode_check_infrastructure/flashrom.c (Arbeitskopie) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,63 @@ return ret; } +int check_max_decode(enum chipbustype buses, unsigned int size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for Parallel interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.parallel); + } + if ((buses & CHIP_BUSTYPE_LPC) && + (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for LPC interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.lpc); + } + if ((buses & CHIP_BUSTYPE_FWH) && + (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for FWH interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.fwh); + } + if ((buses & CHIP_BUSTYPE_SPI) && + (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for SPI interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.spi); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + unsigned int size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +475,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +487,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -975,6 +1039,14 @@ verify_it = 1; size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "This chip is too big for this programmer. " + "Details are given in verbose mode. You can override " + "this check with --force."); + programmer_shutdown(); + return 1; + } buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) { -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 6

[commit] r806 - trunk
by svn＠flashrom.org 17 Dec '09

17 Dec '09

Author: hailfinger Date: 2009-12-17 16:20:01 +0100 (Thu, 17 Dec 2009) New Revision: 806 Modified: trunk/board_enable.c trunk/chipset_enable.c Log: Use the maximum decode size infrastructure. - Detect max FWH size for Intel 631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10. - Move IDSEL override before decode size checking for the chipsets listed above or flashrom will complain based on old values. - Adjust supported flash buses for the chipsets listed above (none of them supports LPC or Parallel). - Detect max parallel size for AMD/National Semiconductor CS5530. - Adjust supported flash buses for CS5530/CS5530A. - Set board-specific max decode size for Elitegroup K7VTA3. - Set board-specific max decode size for Shuttle AK38N. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-17 04:22:40 UTC (rev 805) +++ trunk/board_enable.c 2009-12-17 15:20:01 UTC (rev 806) @@ -987,16 +987,24 @@ } /** - * Suited for: - * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F - * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F + * Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F */ -static int it8705f_write_enable_2e(const char *name) +static int elitegroup_k7vta3(const char *name) { + max_rom_decode.parallel = 256 * 1024; return it8705f_write_enable(0x2e, name); } /** + * Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F + */ +static int shuttle_ak38n(const char *name) +{ + max_rom_decode.parallel = 256 * 1024; + return it8705f_write_enable(0x2e, name); +} + +/** * Find the runtime registers of an SMSC Super I/O, after verifying its * chip ID. * @@ -1233,7 +1241,7 @@ {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, - {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, + {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", elitegroup_k7vta3}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, @@ -1257,7 +1265,7 @@ {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, - {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, + {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-12-17 04:22:40 UTC (rev 805) +++ trunk/chipset_enable.c 2009-12-17 15:20:01 UTC (rev 806) @@ -4,6 +4,7 @@ * Copyright (C) 2000 Silicon Integrated System Corporation * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -301,48 +302,92 @@ uint32_t fwh_conf; int i; char *idsel = NULL; + int tmp; + int max_decode_fwh_idsel = 0; + int max_decode_fwh_decode = 0; + int contiguous = 1; - /* Ignore all legacy ranges below 1 MB. */ + if (programmer_param) + idsel = strstr(programmer_param, "fwh_idsel="); + + if (idsel) { + idsel += strlen("fwh_idsel="); + fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); + + /* FIXME: Need to undo this on shutdown. */ + printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); + pci_write_long(dev, 0xd0, fwh_conf); + pci_write_word(dev, 0xd4, fwh_conf); + /* FIXME: Decode settings are not changed. */ + } + + /* Ignore all legacy ranges below 1 MB. + * We currently only support flashing the chip which responds to + * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations + * have to be adjusted. + */ /* FWH_SEL1 */ fwh_conf = pci_read_long(dev, 0xd0); - for (i = 7; i >= 0; i--) + for (i = 7; i >= 0; i--) { + tmp = (fwh_conf >> (i * 4)) & 0xf; printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, - (fwh_conf >> (i * 4)) & 0xf); + tmp); + if ((tmp == 0) && contiguous) { + max_decode_fwh_idsel = (8 - i) * 0x80000; + } else { + contiguous = 0; + } + } /* FWH_SEL2 */ fwh_conf = pci_read_word(dev, 0xd4); - for (i = 3; i >= 0; i--) + for (i = 3; i >= 0; i--) { + tmp = (fwh_conf >> (i * 4)) & 0xf; printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, - (fwh_conf >> (i * 4)) & 0xf); + tmp); + if ((tmp == 0) && contiguous) { + max_decode_fwh_idsel = (8 - i) * 0x100000; + } else { + contiguous = 0; + } + } + contiguous = 1; /* FWH_DEC_EN1 */ fwh_conf = pci_read_word(dev, 0xd8); - for (i = 7; i >= 0; i--) + for (i = 7; i >= 0; i--) { + tmp = (fwh_conf >> (i + 0x8)) & 0x1; printf_debug("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, - (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis"); - for (i = 3; i >= 0; i--) + tmp ? "en" : "dis"); + if ((tmp == 0) && contiguous) { + max_decode_fwh_decode = (8 - i) * 0x80000; + } else { + contiguous = 0; + } + } + for (i = 3; i >= 0; i--) { + tmp = (fwh_conf >> i) & 0x1; printf_debug("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, - (fwh_conf >> i) & 0x1 ? "en" : "dis"); - - if (programmer_param) - idsel = strstr(programmer_param, "fwh_idsel="); - - if (idsel) { - idsel += strlen("fwh_idsel="); - fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); - - /* FIXME: Need to undo this on shutdown. */ - printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); - pci_write_long(dev, 0xd0, fwh_conf); - pci_write_word(dev, 0xd4, fwh_conf); + tmp ? "en" : "dis"); + if ((tmp == 0) && contiguous) { + max_decode_fwh_decode = (8 - i) * 0x100000; + } else { + contiguous = 0; + } } + max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); + printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + /* If we're called by enable_flash_ich_dc_spi, it will override + * buses_supported anyway. + */ + buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -355,6 +400,7 @@ { uint32_t mmio_base; + /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; printf_debug("MMIO base at = 0x%x\n", mmio_base); spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); @@ -409,8 +455,7 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { - /* Not sure if it speaks LPC as well. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + buses_supported = CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } @@ -422,16 +467,14 @@ spibar_offset = 0x3020; break; case 8: - /* Not sure if it speaks LPC as well. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - /* Not sure if it speaks LPC as well. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -612,14 +655,22 @@ #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ +#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */ +#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */ #define LOWER_ROM_ADDRESS_RANGE (1 << 0) #define ROM_WRITE_ENABLE (1 << 1) #define UPPER_ROM_ADDRESS_RANGE (1 << 2) #define BIOS_ROM_POSITIVE_DECODE (1 << 5) +#define CS5530_ISA_MASTER (1 << 7) +#define CS5530_ENABLE_SA2320 (1 << 2) +#define CS5530_ENABLE_SA20 (1 << 6) + buses_supported = CHIP_BUSTYPE_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. + * FIXME: Should we really touch the low mapping below 1 MB? Flashrom + * ignores that region completely. * Make the configured ROM areas writable. */ reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); @@ -633,6 +684,24 @@ reg8 |= BIOS_ROM_POSITIVE_DECODE; pci_write_byte(dev, DECODE_CONTROL_REG2, reg8); + reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); + if (reg8 & CS5530_ISA_MASTER) { + /* We have A0-A23 available. */ + max_rom_decode.parallel = 16 * 1024 * 1024; + } else { + reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); + if (reg8 & CS5530_ENABLE_SA2320) { + /* We have A0-19, A20-A23 available. */ + max_rom_decode.parallel = 16 * 1024 * 1024; + } else if (reg8 & CS5530_ENABLE_SA20) { + /* We have A0-19, A20 available. */ + max_rom_decode.parallel = 2 * 1024 * 1024; + } else { + /* A20 and above are not active. */ + max_rom_decode.parallel = 1024 * 1024; + } + } + return 0; }

1 0

[RFC] Coding style limits
by Carl-Daniel Hailfinger 17 Dec '09

17 Dec '09

We currently have a 80-column limit in almost all files (except database like stuff in flashchips.c etc.). In the last few months, we have added more debug messages and more verbose and thus better understandable messages. Especially at a deep nesting level, using printf_debug can mean you have less than 20 chars per line left for messages. This actively reduces code readability. I would like to move the column limit from 80 to some other agreed-upon value, but I don't know which one. - 100 - 120 - 132 What do YOU think? Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

5 9

Re: [flashrom] not supported motherboard
by Luc Verhaegen 17 Dec '09

17 Dec '09

On Wed, Dec 16, 2009 at 12:48:43PM +0100, Sz??gyényi Gábor wrote: > It's good I think. > > Szogyenyi Gabor AMI, but i cannot find a valid board enable. This is multimeter work now. Luc Verhaegen.

1 0

[PATCH] Make probe_jedec's delays conditional
by Sean Nelson 17 Dec '09

17 Dec '09

As Carl-Daniel's says: probe_jedec checks the delay value and issues programmer_delay based on the value. Except for delays between single chip_writeb. If a chip has zero probe_delay, delays between chip_writeb should be skipped. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 3

[commit] r805 - trunk
by svn＠flashrom.org 17 Dec '09

17 Dec '09

Author: hailfinger Date: 2009-12-17 05:22:40 +0100 (Thu, 17 Dec 2009) New Revision: 805 Modified: trunk/jedec.c Log: probe_jedec() checks the delay value and issues programmer_delay based on the value except for delays between single chip_writeb. If a chip has zero probe_delay, delays between chip_writeb should be skipped as well. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-12-17 04:21:12 UTC (rev 804) +++ trunk/jedec.c 2009-12-17 04:22:40 UTC (rev 805) @@ -96,11 +96,14 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - programmer_delay(10); + if (probe_timing_enter) + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - programmer_delay(10); + if (probe_timing_enter) + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - programmer_delay(probe_timing_enter); + if (probe_timing_enter) + programmer_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -122,11 +125,14 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - programmer_delay(10); + if (probe_timing_exit) + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - programmer_delay(10); + if (probe_timing_exit) + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - programmer_delay(probe_timing_exit); + if (probe_timing_exit) + programmer_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); if (!oddparity(id1))

1 0

[commit] r804 - trunk
by svn＠flashrom.org 17 Dec '09

17 Dec '09

Author: hailfinger Date: 2009-12-17 05:21:12 +0100 (Thu, 17 Dec 2009) New Revision: 804 Modified: trunk/chipdrivers.h Log: Remove nonexisting functions from chipdrivers.h Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipdrivers.h =================================================================== --- trunk/chipdrivers.h 2009-12-14 10:41:58 UTC (rev 803) +++ trunk/chipdrivers.h 2009-12-17 04:21:12 UTC (rev 804) @@ -97,8 +97,6 @@ int block_erase_m29f400bt(struct flashchip *flash, int start, int len); int write_m29f400bt(struct flashchip *flash, uint8_t *buf); int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf); -void toggle_ready_m29f400bt(chipaddr dst); -void data_polling_m29f400bt(chipaddr dst, uint8_t data); void protect_m29f400bt(chipaddr bios); void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size); @@ -117,8 +115,6 @@ int probe_lhf00l04(struct flashchip *flash); int erase_lhf00l04(struct flashchip *flash); int write_lhf00l04(struct flashchip *flash, uint8_t *buf); -void toggle_ready_lhf00l04(chipaddr dst); -void data_polling_lhf00l04(chipaddr dst, uint8_t data); void protect_lhf00l04(chipaddr bios); /* sst28sf040.c */

1 0

Verbose output of lspci, superiotool and flashrom - AsRock K7VT2
by Adrian Glaubitz 17 Dec '09

17 Dec '09

Attaching the output of: "flashrom -V", "lspci -nnvvvxxx", "superiotool -dV" for AsRock K7VT2 on flashrom r761. Adrian

2 2

Flash failed on ASUS P4C-800E Deluxe
by Adrian Glaubitz 16 Dec '09

16 Dec '09

Hi, I was just trying to flash the BIOS (version 1023) into an old ASUS P4C-800E Deluxe on ArchLinux (current updates as of 13-11-2009) and the latest version of flashrom from SVN. I get the following error: [root@bart flashrom]# flashrom -w Display all 101 possibilities? (y or n) [root@bart flashrom]# flashrom w P4CED23.ROM -bash: flashrom: command not found [root@bart flashrom]# ./flashrom -w P4CED23.ROM flashrom v0.9.1-r756 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x000038d0! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x0000ffff: 0xc648 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! [root@bart flashrom]# Any hints? Adrian

2 4

[PATCH] Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.
by Luc Verhaegen 16 Dec '09

16 Dec '09

Massive cleanup and more boards working out of the box. Luc Verhaegen.

1 1

[RFC] Add .reset to struct flashchip?
by Carl-Daniel Hailfinger 16 Dec '09

16 Dec '09

We have more than one chip which gets horribly confused by probe sequences for other chips. Sending a reset command to the detected chip (and sleeping a bit) before performing any read/write/erase action could fix a number of problems we're seeing right now. This could be achieved by adding a .reset function to struct flashchip. Thoughts? Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

4 5

Flash failed on ASUS A8V-E, flash still intact
by Adrian Glaubitz 15 Dec '09

15 Dec '09

Hi, tried flashing an ASUS A8V-E which didn't work. However, the flash rom is still intact and the machine still boots fine. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

2 1

not supported motherboard
by Szőgyényi Gábor 15 Dec '09

15 Dec '09

Hi! I have a P4-M266 AMPTRON motherboard. It's not supported by flashrom-0.9.1. It has SST(MPF)39SF020A. The board looks like this: http://www.motherboard.cz/mb/amptron/P4-M266A.htm The wiki page says, flashrom supports PM266 - Albatron. It looks like: http://www.motherboard.cz/mb/albatron/PM266A.htm I attached the "./flashrom" output, and an "lspi -v -v" output. I hope, this helps for You. I have another motherboards, which are not supported. Thanks for Your reply, Gabor Szogyenyi --------------------------Hirdetés----------------------------- Kötelező biztosítási díjak 2010 Számolja ki és váltson kedvezőbbre!

2 1

Verbose output of lspci, superiotool and flashrom - MSI MS-6590
by Adrian Glaubitz 15 Dec '09

15 Dec '09

Attaching the output of: "flashrom -V", "lspci -nnvvvxxx", "superiotool -dV" for MSI MS-MS6590 on flashrom r761 with ITE refactoring patch by Carl-Daniel. Adrian

2 1

[PATCH] Board: Add MSI K8N Neo4-F
by Luc Verhaegen 15 Dec '09

15 Dec '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index f8b1e10..e9e9d9e 100644 --- a/board_enable.c +++ b/board_enable.c @@ -435,6 +435,14 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) } /** + * Suited for MSI K8N Neo4: nVidia CK804. + */ +static int nvidia_mcp_gpio2_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x02, 1); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) @@ -1160,6 +1168,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --xXmbgvnjoT4axfJE--

1 0

erase failed on ASUS A8N-SLI Deluxe.
by Andreas Henriksson 15 Dec '09

15 Dec '09

Hello everybody! I've been unsuccessful in updating by BIOS on my ASUS A8N-SLI Deluxe motherboard using flashrom. To my novice eyes it looks like the first 768kB has been erased and the rest left as is.... I'll put some information below.... http://paste.debian.net/50883/plain/50883 =================================================== $ sudo flashrom -w 1805.BIN flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00060000! Expected=0xff, Read=0xd4, failed byte count from 0x00060000-0x0006ffff: 0xacde ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! http://paste.debian.net/50884/plain/50884 =================================================== $ sudo flashrom -w backup-bios-1002.bin flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00060000! Expected=0xff, Read=0xd4, fail ed byte count from 0x00060000-0x0006ffff: 0xacde ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! http://paste.debian.net/50885/plain/50885 =================================================== $ sudo flashrom -v backup-bios-1002.bin flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFY FAILED at 0x00000000! Expected=0x21, Read=0xff, failed byte count from 0x00000000-0x0007ffff: 0x3fac2 Quotes from IRC: =================================================== 14:42 < carldani> fatal^: AFAICS erase was partially successful. 14:47 < carldani> fatal^: the first 384k are erased. 14:48 < carldani> fatal^: ok, there are two things we can do. 14:49 < carldani> 1. we unlock the test of the chip and then rewrite in full 14:50 < carldani> 2. We only rewrite the erased part. 14:51 < carldani> fatal^: I'll tell you what we need to fix this. 14:53 < carldani> fatal^: Please send a mail with the exact board name (and board version, if your board exists in multiple versions), output of "lspci -nnvvvxxx" (as root), output of "flashrom -V" (as root), output of "superiotool -dV" (as root), and the output of "flashrom -EV" (as root) to flashrom(a)flashrom.org 14:54 < carldani> if you subscribe to that list before posting, your mail will be passed through immediately (otherwise it ends up in the moderator queue) 14:55 < carldani> and mention in the mail that erase partially fails. Requested information: =================================================== Exact board name: ASUS A8N-SLI Deluxe Versions: "Deluxe" is the "full" version, there are budget versions called "Premium" and maybe even more low-budget versions... lspci -nnvvvxxx: attached as "lspci-nnvvvxxx.txt" flashrom -V: attached as "flashrom-V.txt" superiotool -dV: attached as "superiotool-dV.txt" flashrom -EV: attached as "flashrom-EV.txt" Other files: ==================================================== Maybe to large to attach, so as long as I don't reboot you should be able to reach my computer at: http://fatal.se/tmp/bios/ "backup-bios-1002.bin" is what I got from "flashrom -r backup-bios-1002.bin" before I did anything else. "fucked-bios.bin" is what I currently get if I do "flashrom -r fucked-bios.bin" "1805.BIN" is the new bios I tried to update to. Thanks for your interest reading this far! :) -- Regards, Andreas Henriksson

3 2

[PATCH] Board: Add Asus A8N.
by Luc Verhaegen 15 Dec '09

15 Dec '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 19a77e9..f8b1e10 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1128,6 +1128,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, "ASUS", "A8N", board_shuttle_fn25}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, -- 1.6.0.2 --cWoXeonUoKmBZSoM--

1 0

#5: rKdcRzWWisJHafAk
by flashrom 15 Dec '09

15 Dec '09

#5: rKdcRzWWisJHafAk ---------------------------------+------------------------------------------ Reporter: soeqjvpr | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: flashrom 0.9.2 Component: flashrom | Version: pre-0.9.0 Keywords: XBQOtXfRZNxW | Dependencies: IpMeRHXaRGCyFwkuP Patchstatus: there is no patch | ---------------------------------+------------------------------------------ GADS9k <a href="http://ryonxwovdvli.com/">ryonxwovdvli</a>, [url=http://xfljdwyyyrvj.com/]xfljdwyyyrvj[/url], [link=http://jaagzzjtesui.com/]jaagzzjtesui[/link], http://gnbcygbbgttk.com/ -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/5> flashrom <http://www.flashrom.org/>

1 0

#4: rKdcRzWWisJHafAk
by flashrom 15 Dec '09

15 Dec '09

#4: rKdcRzWWisJHafAk ---------------------------------+------------------------------------------ Reporter: soeqjvpr | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: flashrom 0.9.2 Component: flashrom | Version: pre-0.9.0 Keywords: XBQOtXfRZNxW | Dependencies: IpMeRHXaRGCyFwkuP Patchstatus: there is no patch | ---------------------------------+------------------------------------------ GADS9k <a href="http://ryonxwovdvli.com/">ryonxwovdvli</a>, [url=http://xfljdwyyyrvj.com/]xfljdwyyyrvj[/url], [link=http://jaagzzjtesui.com/]jaagzzjtesui[/link], http://gnbcygbbgttk.com/ -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/4> flashrom <http://www.flashrom.org/>

1 0

[Patch] Board: Acorp 6A815EPD autodetectable (v2).
by Luc Verhaegen 14 Dec '09

14 Dec '09

Hi Jonathan, I've swapped both id blocks around, so it could actually work this time :) Luc Verhaegen.

3 3

[PATCH] Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.
by Luc Verhaegen 14 Dec '09

14 Dec '09

Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 205 ++++++++++++++---------------------------------------- chipset_enable.c | 7 ++ 2 files changed, 60 insertions(+), 152 deletions(-) diff --git a/board_enable.c b/board_enable.c index 35972ab..19a77e9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -162,26 +162,41 @@ static void w836xx_memw_enable(uint16_t port) } /** - * Common routine for several VT823x based boards. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. */ -static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev) +static int w836xx_memw_enable_2e(const char *name) { - uint8_t val; + w836xx_memw_enable(0x2E); - /* All memory cycles, not just ROM ones, go to LPC. */ - val = pci_read_byte(dev, 0x59); - val &= ~0x80; - pci_write_byte(dev, 0x59, val); + return 0; } + /** * VT823x: Set one of the GPIO pins. */ -static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) +static int via_vt823x_gpio_set(uint8_t gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t val, bit, offset; + dev = pci_dev_find_vendorclass(0x1106, 0x0601); + switch (dev->device_id) { + case 0x3177: /* VT8235 */ + case 0x3227: /* VT8237R */ + case 0x3337: /* VT8237A */ + break; + default: + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + return -1; + } + if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); @@ -199,7 +214,7 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) } else { fprintf(stderr, "\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); - return; + return -1; } /* We need the I/O Base Address for this board's flash enable. */ @@ -214,103 +229,53 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) else val &= ~bit; OUTB(val, base + offset); -} - -/** - * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. - * - * We don't need to do this when using coreboot, GPIO15 is never lowered there. - */ -static int board_via_epia_m(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - - /* GPIO15 is connected to write protect. */ - vt823x_gpio_set(dev, 15, 1); return 0; } /** - * Suited for: - * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. + * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F */ -static int board_asus_a7v8x_mx(const char *name) +static int via_vt823x_gpio5_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - w836xx_memw_enable(0x2E); - - return 0; + /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ + return via_vt823x_gpio_set(5, 1); } /** - * Suited for VIAs EPIA SP and EPIA CN. + * Suited for VIAs EPIA N & NL. */ -static int board_via_epia_sp(const char *name) +static int via_vt823x_gpio9_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return 0; + return via_vt823x_gpio_set(9, 1); } /** - * Suited for VIAs EPIA N & NL. + * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. + * + * We don't need to do this for EPIA M when using coreboot, GPIO15 is never + * lowered there. */ -static int board_via_epia_n(const char *name) +static int via_vt823x_gpio15_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - /* All memory cycles, not just ROM ones, go to LPC */ - vt823x_set_all_writes_to_lpc(dev); - - /* GPIO9 -> output */ - vt823x_gpio_set(dev, 9, 1); - - return 0; + return via_vt823x_gpio_set(15, 1); } /** + * Winbond W83697HF Super I/O + VIA VT8235 southbridge + * * Suited for: - * - EPoX EP-8K5A2: VIA KT333 + VT8235. - * - Albatron PM266A Pro: VIA P4M266A + VT8235. - * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ -static int w836xx_memw_enable_2e(const char *name) +static int board_msi_kt4v(const char *name) { + int ret; + + ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E); - return 0; + return ret; } /** @@ -880,6 +845,7 @@ static int board_kontron_986lcd_m(const char *name) * Suited for: * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 + * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. * * SIS950 superio probably requires the same flash write enable. */ @@ -903,49 +869,6 @@ static int it8705_rom_write_enable(const char *name) } /** - * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - */ -static int board_aopen_vkm400(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return it8705_rom_write_enable(name); -} - -/** - * Winbond W83697HF Super I/O + VIA VT8235 southbridge - * - * Suited for: - * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 - * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - */ -static int board_msi_kt4v(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - vt823x_gpio_set(dev, 12, 1); - w836xx_memw_enable(0x2E); - - return 0; -} - -/** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int board_soyo_sy_7vca(const char *name) @@ -1166,26 +1089,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F - */ -static int board_asus_m2v_mx(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3337); /* VT8237A ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237A ISA bridge not found.\n"); - return -1; - } - - /* GPO5 is connected to WP# and TBL#. */ - vt823x_gpio_set(dev, 5, 1); - - return 0; -} - - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1219,13 +1122,13 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", board_asus_m2v_mx}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, + {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, @@ -1260,11 +1163,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n}, - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ diff --git a/chipset_enable.c b/chipset_enable.c index 333d79d..4372872 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -603,6 +603,13 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return -1; } + if (dev->device_id == 0x3227) { /* VT8237 */ + /* All memory cycles, not just ROM ones, go to LPC. */ + val = pci_read_byte(dev, 0x59); + val &= ~0x80; + pci_write_byte(dev, 0x59, val); + } + return 0; } -- 1.6.0.2 --gBBFr7Ir9EOA20Yy--

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