- flashrom - mail.coreboot.org

[PATCH] flashrom 0.9.2
by Carl-Daniel Hailfinger 15 May '10

15 May '10

No, 0.9.2 is not yet out. This patch should be committed in r999 so that the 0.9.2 tag in svn will be r1000. Patches I absolutely want to get in before 0.9.2: AT49F002(N)(T) eraseblock fix (needs re-review due to datasheet contradictions) http://patchwork.coreboot.org/patch/833/ drkaiser: MEM BAR fixes (needs update to fix gfxnvidia MEM BAR as well) http://patchwork.coreboot.org/patch/1077/ msg_* conversions (two patches, preferably as one commit, needs review) http://patchwork.coreboot.org/patch/1167/ http://patchwork.coreboot.org/patch/1166/ Fix delay loop (needs review) http://patchwork.coreboot.org/patch/1172/ This means we can fit 5 additional patches in flashrom to reach the desired commit number. Candidates for such patches (desirable, but not absolutely must-have): flashrom dependencies (needs fixing) http://patchwork.coreboot.org/patch/1131/ Merge print/print_wiki tables (needs review) http://patchwork.coreboot.org/patch/1044/ Move Gigabyte it87spi boards to 'no enable' section (conflicts with 1044) http://patchwork.coreboot.org/patch/1151/ Fix Kontron 986lcd-m (needs cleanup and retesting) http://patchwork.coreboot.org/patch/871/ Add missing Intel/VIA chipset IDs (needs finishing, Idwer made some progress) http://patchwork.coreboot.org/patch/1169/ Suggestions for other patches? If I overlooked any of your patches, I'm sorry. Feel free to point me to them and/or push them for inclusion. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-0.9.2/Makefile =================================================================== --- flashrom-0.9.2/Makefile (Revision 989) +++ flashrom-0.9.2/Makefile (Arbeitskopie) @@ -73,7 +73,7 @@ # will not require subversion. The downloadable snapshots are already exported. SVNVERSION := $(shell LC_ALL=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . | grep ^Revision | sed "s/.*[[:blank:]]\+$[0-9]*$[^0-9]*/\1/" | grep "[0-9]" || echo unknown) -RELEASE := 0.9.1 +RELEASE := 0.9.2 VERSION := $(RELEASE)-r$(SVNVERSION) RELEASENAME ?= $(VERSION) -- http://www.hailfinger.org/

3 10

[commit] r998 - trunk
by repository service 15 May '10

15 May '10

Author: hailfinger Date: Sat May 15 17:04:37 2010 New Revision: 998 URL: http://flashrom.org/trac/coreboot/changeset/998 Log: Fix assorted documentation, frontend and printing bugs. Change the command line interface to make file names positional. Add more sanity checks to the command line parser. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/Makefile trunk/cli_classic.c trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/print.c trunk/print_wiki.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri May 7 22:09:04 2010 (r997) +++ trunk/Makefile Sat May 15 17:04:37 2010 (r998) @@ -71,7 +71,7 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . | grep ^Revision | sed "s/.*[[:blank:]]\+$[0-9]*$[^0-9]*/\1/" | grep "[0-9]" || echo unknown) +SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) RELEASE := 0.9.1 VERSION := $(RELEASE)-r$(SVNVERSION) Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Fri May 7 22:09:04 2010 (r997) +++ trunk/cli_classic.c Sat May 15 17:04:37 2010 (r998) @@ -37,33 +37,53 @@ int remaining = 0; enum programmer p; - printf("Usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname]\n" - " [-m [vendor:]part] [-l file] [-i image] [-p programmer]\n\n", name); - - printf("Please note that the command line interface for flashrom will " - "change before\nflashrom 1.0. Do not use flashrom in scripts " - "or other automated tools without\nchecking that your flashrom" - " version won't interpret options in a different way.\n\n"); - - printf - (" -r | --read: read flash and save into file\n" - " -w | --write: write file into flash\n" - " -v | --verify: verify flash against file\n" - " -n | --noverify: don't verify flash against file\n" - " -E | --erase: erase flash device\n" - " -V | --verbose: more verbose output\n" - " -c | --chip <chipname>: probe only for specified flash chip\n" + printf("Usage: %s [-n] [-V] [-f] [-h|-R|-L|" +#if PRINT_WIKI_SUPPORT == 1 + "-z|" +#endif + "-E|-r <file>|-w <file>|-v <file>]\n" + " [-c <chipname>] [-m [<vendor>:]<part>] [-l <file>]\n" + " [-i <image>] [-p <programmername>[:<parameters>]]\n", + name); + + printf("Please note that the command line interface for flashrom has " + "changed between\n" + "0.9.1 and 0.9.2 and will change again before flashrom 1.0.\n" + "Do not use flashrom in scripts or other automated tools " + "without checking\n" + "that your flashrom version won't interpret options in a " + "different way.\n\n"); + + printf(" -h | --help print this help text\n" + " -R | --version print version (release)\n" + " -r | --read <file> read flash and save to " + "<file>\n" + " -w | --write <file> write <file> to flash\n" + " -v | --verify <file> verify flash against " + "<file>\n" + " -E | --erase erase flash device\n" + " -V | --verbose more verbose output\n" + " -c | --chip <chipname> probe only for specified " + "flash chip\n" #if INTERNAL_SUPPORT == 1 - " -m | --mainboard <[vendor:]part>: override mainboard settings\n" + /* FIXME: --mainboard should be a programmer parameter */ + " -m | --mainboard <[vendor:]part> override mainboard " + "detection\n" #endif - " -f | --force: force write without checking image\n" - " -l | --layout <file.layout>: read ROM layout from file\n" - " -i | --image <name>: only flash image name from flash layout\n" - " -L | --list-supported: print supported devices\n" + " -f | --force force specific operations " + "(see man page)\n" + " -n | --noverify don't auto-verify\n" + " -l | --layout <file> read ROM layout from " + "<file>\n" + " -i | --image <name> only flash image <name> " + "from flash layout\n" + " -L | --list-supported print supported devices\n" #if PRINT_WIKI_SUPPORT == 1 - " -z | --list-supported-wiki: print supported devices in wiki syntax\n" + " -z | --list-supported-wiki print supported devices " + "in wiki syntax\n" #endif - " -p | --programmer <name>: specify the programmer device"); + " -p | --programmer <name>[:<param>] specify the programmer " + "device"); for (p = 0; p < PROGRAMMER_INVALID; p++) { pname = programmer_table[p].name; @@ -88,12 +108,19 @@ printf(")\n"); } } - - printf( - " -h | --help: print this help text\n" - " -R | --version: print the version (release)\n" - "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" - "specified, then all that happens is that flash info is dumped.\n\n"); + + printf("\nYou can specify one of -h, -R, -L, " +#if PRINT_WIKI_SUPPORT == 1 + "-z, " +#endif + "-E, -r, -w, -v or no operation.\n" + "If no operation is specified, flashrom will only probe for " + "flash chips.\n\n"); +} + +void cli_classic_abort_usage(const char *name) +{ + printf("Please run \"%s --help\" for usage info.\n", name); exit(1); } @@ -115,16 +142,12 @@ int operation_specified = 0; int i; -#if PRINT_WIKI_SUPPORT == 1 - const char *optstring = "rRwvnVEfc:m:l:i:p:Lzh"; -#else - const char *optstring = "rRwvnVEfc:m:l:i:p:Lh"; -#endif + const char *optstring = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; static struct option long_options[] = { - {"read", 0, 0, 'r'}, - {"write", 0, 0, 'w'}, + {"read", 1, 0, 'r'}, + {"write", 1, 0, 'w'}, {"erase", 0, 0, 'E'}, - {"verify", 0, 0, 'v'}, + {"verify", 1, 0, 'v'}, {"noverify", 0, 0, 'n'}, {"chip", 1, 0, 'c'}, {"mainboard", 1, 0, 'm'}, @@ -133,9 +156,7 @@ {"layout", 1, 0, 'l'}, {"image", 1, 0, 'i'}, {"list-supported", 0, 0, 'L'}, -#if PRINT_WIKI_SUPPORT == 1 {"list-supported-wiki", 0, 0, 'z'}, -#endif {"programmer", 1, 0, 'p'}, {"help", 0, 0, 'h'}, {"version", 0, 0, 'R'}, @@ -147,18 +168,15 @@ char *tempstr = NULL; print_version(); - - if (argc > 1) { - /* Yes, print them. */ - printf_debug("The arguments are:\n"); - for (i = 1; i < argc; ++i) - printf_debug("%s\n", argv[i]); - } + print_banner(); if (selfcheck()) exit(1); setbuf(stdout, NULL); + /* FIXME: Delay all operation_specified checks until after command + * line parsing to allow --help overriding everything else. + */ while ((opt = getopt_long(argc, argv, optstring, long_options, &option_index)) != EOF) { switch (opt) { @@ -166,16 +184,18 @@ if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } + filename = strdup(optarg); read_it = 1; break; case 'w': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } + filename = strdup(optarg); write_it = 1; break; case 'v': @@ -183,20 +203,21 @@ if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } if (dont_verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } + filename = strdup(optarg); verify_it = 1; break; case 'n': if (verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } dont_verify_it = 1; break; @@ -210,36 +231,55 @@ if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - exit(1); + cli_classic_abort_usage(argv[0]); } erase_it = 1; break; -#if INTERNAL_SUPPORT == 1 case 'm': +#if INTERNAL_SUPPORT == 1 tempstr = strdup(optarg); lb_vendor_dev_from_string(tempstr); - break; +#else + fprintf(stderr, "Error: Internal programmer support " + "was not compiled in and --mainboard only\n" + "applies to the internal programmer. Aborting.\n"); + cli_classic_abort_usage(argv[0]); #endif + break; case 'f': force = 1; break; case 'l': tempstr = strdup(optarg); if (read_romlayout(tempstr)) - exit(1); + cli_classic_abort_usage(argv[0]); break; case 'i': tempstr = strdup(optarg); find_romentry(tempstr); break; case 'L': + if (++operation_specified > 1) { + fprintf(stderr, "More than one operation " + "specified. Aborting.\n"); + cli_classic_abort_usage(argv[0]); + } list_supported = 1; break; -#if PRINT_WIKI_SUPPORT == 1 case 'z': +#if PRINT_WIKI_SUPPORT == 1 + if (++operation_specified > 1) { + fprintf(stderr, "More than one operation " + "specified. Aborting.\n"); + cli_classic_abort_usage(argv[0]); + } list_supported_wiki = 1; - break; +#else + fprintf(stderr, "Error: Wiki output was not compiled " + "in. Aborting.\n"); + cli_classic_abort_usage(argv[0]); #endif + break; case 'p': for (programmer = 0; programmer < PROGRAMMER_INVALID; programmer++) { name = programmer_table[programmer].name; @@ -267,21 +307,37 @@ } } if (programmer == PROGRAMMER_INVALID) { - printf("Error: Unknown programmer %s.\n", optarg); - exit(1); + fprintf(stderr, "Error: Unknown programmer " + "%s.\n", optarg); + cli_classic_abort_usage(argv[0]); } break; case 'R': /* print_version() is always called during startup. */ + if (++operation_specified > 1) { + fprintf(stderr, "More than one operation " + "specified. Aborting.\n"); + cli_classic_abort_usage(argv[0]); + } exit(0); break; case 'h': - default: + if (++operation_specified > 1) { + fprintf(stderr, "More than one operation " + "specified. Aborting.\n"); + cli_classic_abort_usage(argv[0]); + } cli_classic_usage(argv[0]); + exit(0); + break; + default: + cli_classic_abort_usage(argv[0]); break; } } + /* FIXME: Print the actions flashrom will take. */ + if (list_supported) { print_supported(); exit(0); @@ -294,18 +350,18 @@ } #endif - if (read_it && write_it) { - printf("Error: -r and -w are mutually exclusive.\n"); - cli_classic_usage(argv[0]); + if (optind < argc) { + fprintf(stderr, "Error: Extra parameter found.\n"); + cli_classic_abort_usage(argv[0]); } - if (optind < argc) - filename = argv[optind++]; - - if (optind < argc) { - printf("Error: Extra parameter found.\n"); - cli_classic_usage(argv[0]); +#if INTERNAL_SUPPORT == 1 + if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { + fprintf(stderr, "Error: --mainboard requires the internal " + "programmer. Aborting.\n"); + cli_classic_abort_usage(argv[0]); } +#endif if (chip_to_probe) { for (flash = flashchips; flash && flash->name; flash++) @@ -321,13 +377,15 @@ /* Clean up after the check. */ flash = NULL; } - + + msg_pdbg("Initializing %s programmer\n", + programmer_table[programmer].name); if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); exit(1); } - // FIXME: Delay calibration should happen in programmer code. + /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); for (i = 0; i < ARRAY_SIZE(flashes); i++) { @@ -383,7 +441,7 @@ printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! programmer_shutdown(); - exit(1); + exit(0); } if (!filename && !erase_it) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri May 7 22:09:04 2010 (r997) +++ trunk/flash.h Sat May 15 17:04:37 2010 (r998) @@ -548,6 +548,7 @@ int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); +void print_banner(void); int selfcheck(void); int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it); Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Fri May 7 22:09:04 2010 (r997) +++ trunk/flashrom.8 Sat May 15 17:04:37 2010 (r998) @@ -1,9 +1,13 @@ -.TH FLASHROM 8 "May 21, 2009" +.TH FLASHROM 8 "Apr 29, 2010" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS -.B flashrom \fR[\fB\-VfLzhRn\fR] [\fB\-E\fR|\fB\-r\fR file|\fB\-w\fR file|\fB\-v\fR file] [\fB\-c\fR chipname] - [\fB\-m\fR [vendor:]part] [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] +.B flashrom \fR[\fB\-n\fR] [\fB\-V\fR] [\fB\-f\fR] [\fB\-h\fR|\fB\-R\fR|\ +\fB\-L\fR|\fB\-z\fR|\fB\-E\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\ +\fB\-v\fR <file>] + [\fB\-c\fR <chipname>] [\fB\-m\fR [<vendor>:]<part>] \ +[\fB\-l\fR <file>] + [\fB\-i\fR <image>] [\fB\-p\fR <programmername>[:<parameters>]] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash @@ -20,9 +24,8 @@ flashrom 1.0. Do not use flashrom in scripts or other automated tools without checking that your flashrom version won't interpret options in a different way. .PP -You can specify one of \-E, \-r, \-w, \-v or no operation. -If no operation is specified, then all that happens -is that flash info is dumped and the flash chip is set to writable. It is +You can specify one of \-h, \-R, \-L, \-z, \-E, \-r, \-w, \-v or no operation. +If no operation is specified, flashrom will only probe for flash chips. It is recommended that if you try flashrom the first time on a system, you run it in probe only mode and check the output. Also you are advised to make a backup of your current ROM contents with \-r before you try to write a new @@ -33,19 +36,19 @@ .BR <file> . .TP .B "\-w, \-\-write <file>" -Write file into flash ROM. +Write +.B <file> +into flash ROM. .TP .B "\-n, \-\-noverify" -Do -.B not -verify the flash ROM contents after writing them to the chip. Using this +Skip the automatic verification of flash ROM contents after writing. Using this option is .B not -recommended, you should only use it if you know what you are doing and you +recommended, you should only use it if you know what you are doing and if you feel that the time for verification takes too long. .sp Typical usage is: -.B "flashrom -wn file" +.B "flashrom -n -w file" .sp This option is only useful in combination with .BR \-\-write . @@ -66,14 +69,14 @@ .B "flashrom \-L" without the vendor name. Please note that the chip name is case sensitive. .TP -.B "\-m, \-\-mainboard" <[vendor:]part> +.B "\-m, \-\-mainboard" [<vendor>:]<part> Override mainboard settings. .sp flashrom reads the coreboot table to determine the current mainboard. If no coreboot table could be read or if you want to override these values, you can specify \-m, e.g.: .sp -.B " flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom" +.B " flashrom --mainboard AGAMI:ARUMA -w agami_aruma.rom" .sp See the 'Supported mainboards' section in the output of 'flashrom \-L' for a list of boards which require the specification of the board name, if no @@ -108,19 +111,15 @@ All addresses are offsets within the file, not absolute addresses! If you only want to update the normal image in a ROM you can say: .sp -.B " flashrom -w --layout rom.layout --image normal agami_aruma.rom" +.B " flashrom --layout rom.layout --image normal -w agami_aruma.rom" .sp To update normal and fallback but leave the VGA BIOS alone, say: .sp -.B " flashrom -w -l rom.layout -i normal \" +.B " flashrom -l rom.layout -i normal \" .br -.B " -i fallback agami_aruma.rom" +.B " -i fallback -w agami_aruma.rom" .sp Currently overlapping sections are not supported. -.sp -ROM layouts should replace the \-s and \-e option since they are more -flexible and they should lead to a ROM update file format with the -ROM layout and the ROM image in one file (cpio, zip or something?). .TP .B "\-i, \-\-image <name>" Only flash image @@ -141,7 +140,8 @@ Same as .BR \-\-list\-supported , but outputs the supported hardware in MediaWiki syntax, so that it can be -easily pasted into the wiki page at http://www.flashrom.org/. +easily pasted into the wiki page at http://www.flashrom.org/. Please note +that MediaWiki output is not compiled in by default. .TP .B "\-p, \-\-programmer <name>[:parameter[,parameter[,parameter]]]" Specify the programmer device. Currently supported are: @@ -237,6 +237,7 @@ .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. You can use +.sp .B "flashrom -p internal:it87spiport=portnum" syntax as explained in the .B it87spi @@ -382,6 +383,8 @@ .br Markus Boas <ryven(a)ryven.de> .br +Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> +.br Nikolay Petukhov <nikolay.petukhov(a)gmail.com> .br Peter Stuge <peter(a)stuge.se> @@ -392,6 +395,8 @@ .br Ronald Hoogenboom <ronald(a)zonnet.nl> .br +Sean Nelson <audiohacked(a)gmail.com> +.br Stefan Reinauer <stepan(a)coresystems.de> .br Stefan Wildemann <stefan.wildemann(a)kontron.com> @@ -406,5 +411,6 @@ .br some others .PP -This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de>. +This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de> and Carl-Daniel +Hailfinger. It is licensed under the terms of the GNU GPL (version 2 or later). Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri May 7 22:09:04 2010 (r997) +++ trunk/flashrom.c Sat May 15 17:04:37 2010 (r998) @@ -1130,8 +1130,9 @@ { msg_gerr("Your flash chip is in an unknown state.\n" "Get help on IRC at irc.freenode.net (channel #flashrom) or\n" - "mail flashrom(a)flashrom.org!\n--------------------" - "-----------------------------------------------------------\n" + "mail flashrom(a)flashrom.org!\n" + "-------------------------------------------------------------" + "------------------\n" "DO NOT REBOOT OR POWEROFF!\n"); } @@ -1183,10 +1184,17 @@ void print_version(void) { - msg_ginfo("flashrom v%s\n", flashrom_version); + msg_ginfo("flashrom v%s", flashrom_version); print_sysinfo(); } +void print_banner(void) +{ + msg_ginfo("flashrom is free software, get the source code at " + "http://www.flashrom.org\n"); + msg_ginfo("\n"); +} + int selfcheck(void) { int ret = 0; @@ -1247,13 +1255,20 @@ msg_cinfo("\n"); } /* FIXME: This message is designed towards CLI users. */ - msg_cinfo("Please email a report to flashrom(a)flashrom.org if any " - "of the above operations\nwork correctly for you with " - "this flash part. Please include the flashrom\noutput " - "with the additional -V option for all operations you " - "tested (-V, -rV,\n-wV, -EV), and mention which " - "mainboard or programmer you tested.\nThanks for your " - "help!\n===\n"); + msg_cinfo("The test status of this chip may have been updated " + "in the latest development\n" + "version of flashrom. If you are running the latest " + "development version,\n" + "please email a report to flashrom(a)flashrom.org if " + "any of the above operations\n" + "work correctly for you with this flash part. Please " + "include the flashrom\n" + "output with the additional -V option for all " + "operations you tested (-V, -Vr,\n" + "-Vw, -VE), and mention which mainboard or " + "programmer you tested.\n" + "Thanks for your help!\n" + "===\n"); } } Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri May 7 22:09:04 2010 (r997) +++ trunk/print.c Sat May 15 17:04:37 2010 (r998) @@ -247,6 +247,9 @@ #if SATASII_SUPPORT == 1 print_supported_pcidevs(satas_sii); #endif +#if ATAHPT_SUPPORT == 1 + print_supported_pcidevs(ata_hpt); +#endif } Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri May 7 22:09:04 2010 (r997) +++ trunk/print_wiki.c Sat May 15 17:04:37 2010 (r998) @@ -25,6 +25,7 @@ #include "flash.h" #include "flashchips.h" +#if INTERNAL_SUPPORT == 1 struct board_info_url { const char *vendor; const char *name; @@ -36,6 +37,7 @@ const char *name; const char *note; }; +#endif const char *wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ @@ -44,6 +46,7 @@ generated by pasting '''flashrom -z''' output. \ '''Last update:''' %s(generated by flashrom %s)\n</div>\n"; +#if INTERNAL_SUPPORT == 1 const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ @@ -69,6 +72,7 @@ Mainboards which don't appear in the list may or may not work (we don't \ know, someone has to give it a try). Please report any further verified \ mainboards on the [[Mailinglist|mailing list]].\n"; +#endif const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ @@ -85,6 +89,7 @@ ! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ ! align=\"left\" | Status\n\n"; +#if INTERNAL_SUPPORT == 1 const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ In general, flashing laptops is more difficult because laptops\n\n\ * often use the flash chip for stuff besides the BIOS,\n\ @@ -505,6 +510,7 @@ wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); wiki_helper("Not supported (yet)", "No", 1, laptops_bad); } +#endif void print_supported_chips_wiki(void) { @@ -576,9 +582,11 @@ time_t t = time(NULL); printf(wiki_header, ctime(&t), flashrom_version); +#if INTERNAL_SUPPORT == 1 print_supported_chips_wiki(); print_supported_chipsets_wiki(); print_supported_boards_wiki(); +#endif printf("%s", programmer_section); #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com);

1 0

[patch] unhide the flash chip on QDI KD7G
by Idwer Vollering 15 May '10

15 May '10

Only works with "Flash Write Protect" set to "Disabled", in the BIOS menu. With the attached patch write/erase work without the need of extra code. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>

3 2

[PATCH] Don't ignore wait_82802ab() return value
by Stefan Reinauer 14 May '10

14 May '10

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 2

[Patch] RFC: Set status register option
by David Hendricks 14 May '10

14 May '10

Hello all, I'd like to know what people's thoughts are on setting the status register for SPI flash memories using Flashrom. It seems like a good fit for Flashrom and would go a long way in helping OEMs/ODMs migrate away from crappy DOS utilities to using Flashrom for mass production. I've attached a very lame patch that adds a command-line option (-s or --set-status) to do this for SPI chips. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

2 3

[PATCH] VIA: disable byte merging
by Michael Karcher 12 May '10

12 May '10

All mentioned north bridges have been checked against data sheet. That's all north bridges google found a datasheet for with "byte enable" included. Second revision. Should now run multiple chipset enables if the first one requests further enables to be run. VIA byte-merging logic tested: works. multiple chipset logic: completely untested Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 52 insertions(+), 7 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..547c35e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#define NOT_DONE_YET 1 + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -639,6 +641,32 @@ static int enable_flash_ich10(struct pci_dev *dev, const char *name) return enable_flash_ich_dc_spi(dev, name, 10); } +static void via_do_byte_merge(void * arg) +{ + struct pci_dev * dev = arg; + uint8_t val; + + printf_debug("Re-enabling byte merging\n"); + val = pci_read_byte(dev, 0x71); + val |= 0x40; + pci_write_byte(dev, 0x71, val); +} + +static int via_no_byte_merge(struct pci_dev *dev, const char *name) +{ + uint8_t val; + + val = pci_read_byte(dev, 0x71); + if (val & 0x40) + { + printf_debug("Disabling byte merging\n"); + val &= ~0x40; + pci_write_byte(dev, 0x71, val); + register_shutdown(via_do_byte_merge, dev); + } + return NOT_DONE_YET; /* need to find south bridge, too */ +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1405,6 +1433,14 @@ const struct penable chipset_enables[] = { {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, + /* VIA northbridges */ + {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, + {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, + {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, + {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */ + {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, + {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, + /* VIA southbridges */ {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, @@ -1431,22 +1467,31 @@ int chipset_flash_enable(void) for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { dev = pci_dev_find(chipset_enables[i].vendor_id, chipset_enables[i].device_id); - if (dev) - break; - } - - if (dev) { + if (!dev) + continue; + if (ret != -2) { + printf("WARNING: unexpected second chipset match: " + "\"%s %s\"\nignoring, please report lspci and " + "board URL to flashrom(a)flashrom.org!\n", + chipset_enables[i].vendor_name, + chipset_enables[i].device_name); + continue; + } printf("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); - if (ret) + if (ret == NOT_DONE_YET) { + ret = -2; + printf("OK - searching further chips.\n"); + } else if (ret < 0) printf("FAILED!\n"); - else + else if(ret == 0) printf("OK.\n"); } + printf("This chipset supports the following protocols: %s.\n", flashbuses_to_text(buses_supported)); -- 1.7.1

1 0

[PATCH] VIA: disable byte merging
by Michael Karcher 12 May '10

12 May '10

All mentioned north bridges have been checked against data sheet. That's all north bridges google found a datasheet for with "byte enable" included. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..6ef1f8d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -639,6 +639,32 @@ static int enable_flash_ich10(struct pci_dev *dev, const char *name) return enable_flash_ich_dc_spi(dev, name, 10); } +static void via_do_byte_merge(void * arg) +{ + struct pci_dev * dev = arg; + uint8_t val; + + printf_debug("Re-enabling byte merging\n"); + val = pci_read_byte(dev, 0x71); + val |= 0x40; + pci_write_byte(dev, 0x71, val); +} + +static int via_no_byte_merge(struct pci_dev *dev, const char *name) +{ + uint8_t val; + + val = pci_read_byte(dev, 0x71); + if (val & 0x40) + { + printf_debug("Disabling byte merging\n"); + val &= ~0x40; + pci_write_byte(dev, 0x71, val); + register_shutdown(via_do_byte_merge, dev); + } + return 0; +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1405,6 +1431,14 @@ const struct penable chipset_enables[] = { {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, + /* VIA northbridges */ + {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, + {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, + {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, + {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */ + {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, + {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, + /* VIA southbridges */ {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, -- 1.7.1

1 0

Re: [flashrom] flashing BIOS using flashrom on ASUS M2N-SLI DELUXE
by adrian.glaubitz＠googlemail.com 11 May '10

11 May '10

On Tue, May 11, 2010 at 03:59:46PM +0200, Kasper M. Nielsen wrote: > hi Adrian > > I don't know if the Ethernet MAC address has changed since the BIOS > flash, as I don't know what it was before. Does this look like the MAC > your Ethernet got after the flash? > > MAC: 04:4B:80:80:80:03 Ok, then it is always set to the same hardware address obviously. Mine reads the same: glaubitz@z6:~> /sbin/ifconfig |grep HWaddr br0 Link encap:Ethernet HWaddr 04:4b:80:80:80:03 eth0 Link encap:Ethernet HWaddr 04:4b:80:80:80:03 glaubitz@z6:~> Obviously not a good thing :/. At least we should know where the address can be found in the ROM image to correct it afterwards. Btw, there is supposed to be an AWARD flash utility from the mainboard vendor which allows to re-set the mac address. Have you tried this one? I think AWDFLASH.EXE can be used with a special option for that. > > but I can confirm that the board/computer wouldn't boot before a > reset-to-factory-defaults was done. I figured that it was standart > procedure after a BIOS flash, since it had to been done with my laptop > as well. Well, I didn't know that so I started to panic a bit since my machine wouldn't come up again. It didn't boot until I reset the CMOS. But good to know that my board still works well ;). Hilse fra Oslo, Adrian

1 0

About my motherboard.
by Buğra Gökalp Okçu 10 May '10

10 May '10

Hi, I have a laptop with sis chipset and i decided to give you some information about it if it would help. Below are the outputs from lspci, flashrom and superiotool. It seem it hasn't any significant information (except being unsupported). I hope this helps. Regards, Bugra lspci -nnvvvxxx 00:00.0 Host bridge [0600]: Silicon Integrated Systems [SiS] 671MX [1039:0671] Subsystem: Fujitsu Siemens Computers Device [1734:1125] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 32 Region 0: Memory at d0000000 (32-bit, non-prefetchable) [size=64M] Capabilities: <access denied> Kernel driver in use: agpgart-sis 00: 39 10 71 06 07 00 10 22 00 00 00 06 00 20 00 00 10: 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 34 17 25 11 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: Silicon Integrated Systems [SiS] SiS AGP Port (virtual PCI-to-PCI bridge) [1039:0003] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 16 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: d4000000-d40fffff Prefetchable memory behind bridge: c0000000-cfffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: 39 10 03 00 07 00 20 00 00 00 04 06 04 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 90 90 20 20 20: 00 d4 00 d4 00 c0 f0 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 0c 00 00:02.0 ISA bridge [0601]: Silicon Integrated Systems [SiS] SiS968 [MuTIOL Media IO] [1039:0968] (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 39 10 68 09 0f 00 00 02 01 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.5 IDE interface [0101]: Silicon Integrated Systems [SiS] 5513 [IDE] [1039:5513] (rev 01) (prog-if 80 [Master]) Subsystem: Silicon Integrated Systems [SiS] SiS5513 EIDE Controller (A,B step) [1039:5513] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 128 Interrupt: pin ? routed to IRQ 16 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at 1000 [size=16] Capabilities: <access denied> Kernel driver in use: pata_sis Kernel modules: pata_sis 00: 39 10 13 55 05 00 10 02 01 80 01 01 00 80 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 10 00 00 00 00 00 00 00 00 00 00 39 10 13 55 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00:03.0 USB Controller [0c03]: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] (rev 0f) (prog-if 10 [OHCI]) Subsystem: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at d4204000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 39 10 01 70 17 00 80 02 0f 10 03 0c 00 20 80 00 10: 00 40 20 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 50 00:03.1 USB Controller [0c03]: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] (rev 0f) (prog-if 10 [OHCI]) Subsystem: Silicon Integrated Systems [SiS] USB 1.1 Controller [1039:7001] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at d4205000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 39 10 01 70 17 00 80 02 0f 10 03 0c 00 20 00 00 10: 00 50 20 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 50 00:03.3 USB Controller [0c03]: Silicon Integrated Systems [SiS] USB 2.0 Controller [1039:7002] (prog-if 20 [EHCI]) Subsystem: Fujitsu Siemens Computers Device [1734:1125] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max), Cache Line Size: 32 bytes Interrupt: pin C routed to IRQ 22 Region 0: Memory at d4206000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: ehci_hcd 00: 39 10 02 70 06 00 90 02 00 20 03 0c 08 20 00 00 10: 00 60 20 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 34 17 25 11 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 03 00 50 00:04.0 Ethernet controller [0200]: Silicon Integrated Systems [SiS] 191 Gigabit Ethernet Adapter [1039:0191] (rev 02) Subsystem: Fujitsu Siemens Computers Device [1734:1125] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 19 Region 0: Memory at d4407000 (32-bit, non-prefetchable) [size=128] Region 1: I/O ports at 1080 [size=128] Capabilities: <access denied> Kernel driver in use: sis190 Kernel modules: sis190 00: 39 10 91 01 07 00 10 02 02 00 00 02 00 00 00 00 10: 00 70 40 d4 81 10 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 34 17 25 11 30: 00 00 00 00 40 00 00 00 00 00 00 00 03 01 00 00 00:05.0 IDE interface [0101]: Silicon Integrated Systems [SiS] SATA Controller / IDE mode [1039:1183] (rev 03) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: Silicon Integrated Systems [SiS] SATA Controller / IDE mode [1039:1183] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 17 Region 0: I/O ports at 1058 [size=8] Region 1: I/O ports at 104c [size=4] Region 2: I/O ports at 1050 [size=8] Region 3: I/O ports at 1048 [size=4] Region 4: I/O ports at 1020 [size=16] Capabilities: <access denied> Kernel driver in use: sata_sis Kernel modules: sata_sis 00: 39 10 83 11 05 00 10 02 03 8f 01 01 00 20 00 00 10: 59 10 00 00 4d 10 00 00 51 10 00 00 49 10 00 00 20: 21 10 00 00 00 00 00 00 00 00 00 00 39 10 83 11 30: 00 00 00 00 58 00 00 00 00 00 00 00 05 01 00 00 00:06.0 PCI bridge [0604]: Silicon Integrated Systems [SiS] PCI-to-PCI bridge [1039:000a] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 16 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: d4100000-d41fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: 39 10 0a 00 07 00 10 00 00 00 04 06 04 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 20 20: 10 d4 10 d4 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b0 00 00 00 00 00 00 00 09 01 04 00 00:07.0 PCI bridge [0604]: Silicon Integrated Systems [SiS] PCI-to-PCI bridge [1039:000a] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 16 bytes Bus: primary=00, secondary=4d, subordinate=4e, sec-latency=0 I/O behind bridge: 00003000-00004fff Memory behind bridge: dc000000-dfffffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: 39 10 0a 00 07 00 10 00 00 00 04 06 04 00 01 00 10: 00 00 00 00 00 00 00 00 00 4d 4e 00 31 41 00 00 20: 00 dc f0 df f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b0 00 00 00 00 00 00 00 09 01 04 00 00:0f.0 Audio device [0403]: Silicon Integrated Systems [SiS] Azalia Audio Controller [1039:7502] Subsystem: Fujitsu Siemens Computers Device [1734:1125] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (13000ns min, 2750ns max) Interrupt: pin A routed to IRQ 18 Region 0: Memory at d4200000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: 39 10 02 75 06 00 10 02 00 00 03 04 00 00 00 00 10: 00 00 20 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 34 17 25 11 30: 00 00 00 00 50 00 00 00 00 00 00 00 04 01 34 0b 00:1f.0 PCI bridge [0604]: Silicon Integrated Systems [SiS] PCI-to-PCI bridge [1039:0004] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 16 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel modules: shpchp 00: 39 10 04 00 07 00 10 00 00 00 04 06 04 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 20 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 d0 00 00 00 00 00 00 00 ff 00 04 00 01:00.0 VGA compatible controller [0300]: Silicon Integrated Systems [SiS] 771/671 PCIE VGA Display Adapter [1039:6351] (rev 10) (prog-if 00 [VGA controller]) Subsystem: Fujitsu Siemens Computers Device [1734:1125] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 16 BIST result: 00 Region 0: Memory at c0000000 (32-bit, prefetchable) [size=256M] Region 1: Memory at d4000000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at 9000 [size=128] Expansion ROM at <unassigned> [disabled] Capabilities: <access denied> 00: 39 10 51 63 03 00 30 02 10 00 00 03 00 00 00 80 10: 08 00 00 c0 00 00 00 d4 01 90 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 34 17 25 11 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 01 00 00 02:00.0 Ethernet controller [0200]: Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter [168c:001c] (rev 01) Subsystem: Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter (rev 01) [168c:3067] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 16 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at d4100000 (64-bit, non-prefetchable) [size=64K] Capabilities: <access denied> Kernel driver in use: ath_pci Kernel modules: ath_pci, ath5k 00: 8c 16 1c 00 07 00 10 00 01 00 00 02 04 00 00 00 10: 04 00 10 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 01 50 00 00 8c 16 67 30 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 01 00 00 -------------------------------------------------------------- flashrom -V flashrom v0.9.1-r710 No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... 491M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x02, id2 0x00 Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xee, id2 0xba, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xee, id2 0xba, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x02, id2 0x00 Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0x4e, id2 0x41 Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0xff, id2 0xff Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0xff, id2 0xff Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x02, id2 0x00 Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x4e, id2 0x41 Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xee, id2 0xba, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x4e, id2 0x41 Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x02, id2 0x00 Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0x02, id2 0x00 Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0x02, id2 0x00 Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x02, id2 0x00 Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x4e, id2 0x41, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0x2, id2 0x0 Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0x4e, id2 0x41 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. -------------------------- superiotool -deV superiotool r5537 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. No Super I/O found

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Asus M4N78 PRO
by Kimmo Vuorinen 09 May '10

09 May '10

flashrom v0.9.1-r995 on Linux 2.6.32.11-99.fc12.x86_64 (x86_64), built with libpci 3.1.6, GCC 4.4.3 20100127 (Red Hat 4.4.3-4) No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4N78 PRO" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8720 Found chipset "NVIDIA MCP78S", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xf7f80000, after clearing low bits BAR is at 0xf7f80000 Mapping MCP67 SPI at 0xf7f80000, unaligned size 0x544. SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. No IT87* serial flash segment enabled. Calibrating delay loop... 993M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1033 us, 10000 myus = 10105 us, OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found.

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flashrom -V and others
by Benjamin Henrion 09 May '10

09 May '10

See attached. The machine is a Acer EL1200 desktop computer. -- Benjamin Henrion <bhenrion(a)ffii.org> FFII Brussels - +32-484-566109 - +32-2-4148403

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Erase+Write Success on VIA Epia-M
by Mark Morschhäuser 08 May '10

08 May '10

I successfully copied the Bios to a new, identical, hotswapped flash chip, see attached log. Greetings, Mark

1 0

PMC Pm49FL004 probe and read results
by Anders Jenbo 08 May '10

08 May '10

Hi hope this is helpfull ---- Msg sent via @Mail - http://atmail.com/

1 0

further ideas for future development of flashrom
by Matthias Olescher 08 May '10

08 May '10

Hello, after a short mail discussion with Carl-Daniel I want to present some new ideas and questions to everybody. Is there any solution to get the ft2232h or even the 1232h-development board to put it on an breadboard, similar to tiny boards with ft232 or ft245, for a moderate price? Farnell is very expensive and for digikey is it too less for shipping and sometimes the customs do not believe in free shipping and raise VAT on an fictive amount of 50-70 € for shipping. V-USB is not a solution because it is too slow. Carl-Daniel has mentioned the project Serprog of Urja Rannikko, can you send me please detailed information about how to build it and the source-code for the AVR? You can link it directly to an ft232 and so you can spare an max232 on both sides. Another solution for classical flashes was the IDE-Flasher of www.loet.de modified (but not tested yet, because of an lost example board) in http://www-user.tu-chemnitz.de/~heha/bastelecke/Rund%20um%20den%20PC/Progra… Unfortunatly the software is closed source, abandoned and doesn't mention newer development in the flash market. Another solution is a new MSP430 series with USB-Interface. http://focus.ti.com/docs/prod/folders/print/msp430f5529.html It is clocked up to 25 MHz, has from 32 kB up to 128 kB flash and 4+2 up to 8+2 kB Ram. It is aviable in 64VQFN 80LQFP and 80BGA. TI sends free samples to companies and research institutes e.g. universities. These MSP have not only SPI in Hardware a full speed USB but also enough gpio-pins for parallel flashes. The MSP430 is optimized for C programming, based on an instruction set of the DEC PDP. Another hint: it is not good to save screenshots and shematics in .jpg until they have been made with a digital camera or a scanner. .png with an reduced color depth is the optimal solution. If you want to answer me directly you can also do it in german. Thank you for every good answer. Matthias -- Das war's. Werbung bitte nicht beachten: GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

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[PATCH 2/2] convert general print messages to msg_g*
by Sean Nelson 07 May '10

07 May '10

--- cli_classic.c | 76 +++++++++++++++--------------- flash.h | 1 - flashrom.c | 144 ++++++++++++++++++++++++++++---------------------------- layout.c | 30 ++++++------ print.c | 74 +++++++++++++++--------------- print_wiki.c | 52 ++++++++++---------- 6 files changed, 188 insertions(+), 189 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index 6cb0578..e99fa7c 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -27,79 +27,79 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> #include "flash.h" #include "flashchips.h" void cli_classic_usage(const char *name) { const char *pname; int pnamelen; int remaining = 0; enum programmer p; - printf("Usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname]\n" + msg_ginfo("Usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname]\n" " [-m [vendor:]part] [-l file] [-i image] [-p programmer]\n\n", name); - printf("Please note that the command line interface for flashrom will " + msg_ginfo("Please note that the command line interface for flashrom will " "change before\nflashrom 1.0. Do not use flashrom in scripts " "or other automated tools without\nchecking that your flashrom" " version won't interpret options in a different way.\n\n"); - printf + msg_ginfo (" -r | --read: read flash and save into file\n" " -w | --write: write file into flash\n" " -v | --verify: verify flash against file\n" " -n | --noverify: don't verify flash against file\n" " -E | --erase: erase flash device\n" " -V | --verbose: more verbose output\n" " -c | --chip <chipname>: probe only for specified flash chip\n" #if INTERNAL_SUPPORT == 1 " -m | --mainboard <[vendor:]part>: override mainboard settings\n" #endif " -f | --force: force write without checking image\n" " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" " -L | --list-supported: print supported devices\n" #if PRINT_WIKI_SUPPORT == 1 " -z | --list-supported-wiki: print supported devices in wiki syntax\n" #endif " -p | --programmer <name>: specify the programmer device"); for (p = 0; p < PROGRAMMER_INVALID; p++) { pname = programmer_table[p].name; pnamelen = strlen(pname); if (remaining - pnamelen - 2 < 0) { - printf("\n "); + msg_ginfo("\n "); remaining = 43; } else { - printf(" "); + msg_ginfo(" "); remaining--; } if (p == 0) { - printf("("); + msg_ginfo("("); remaining--; } - printf("%s", pname); + msg_ginfo("%s", pname); remaining -= pnamelen; if (p < PROGRAMMER_INVALID - 1) { - printf(","); + msg_ginfo(","); remaining--; } else { - printf(")\n"); + msg_ginfo(")\n"); } } - printf( + msg_ginfo( " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" "specified, then all that happens is that flash info is dumped.\n\n"); exit(1); } int cli_classic(int argc, char *argv[]) { unsigned long size; /* Probe for up to three flash chips. */ struct flashchip *flash, *flashes[3]; const char *name; @@ -140,85 +140,85 @@ int cli_classic(int argc, char *argv[]) {"help", 0, 0, 'h'}, {"version", 0, 0, 'R'}, {0, 0, 0, 0} }; char *filename = NULL; char *tempstr = NULL; print_version(); if (argc > 1) { /* Yes, print them. */ - printf_debug("The arguments are:\n"); + msg_gdbg("The arguments are:\n"); for (i = 1; i < argc; ++i) - printf_debug("%s\n", argv[i]); + msg_gdbg("%s\n", argv[i]); } if (selfcheck()) exit(1); setbuf(stdout, NULL); while ((opt = getopt_long(argc, argv, optstring, long_options, &option_index)) != EOF) { switch (opt) { case 'r': if (++operation_specified > 1) { - fprintf(stderr, "More than one operation " + msg_ginfo("More than one operation " "specified. Aborting.\n"); exit(1); } read_it = 1; break; case 'w': if (++operation_specified > 1) { - fprintf(stderr, "More than one operation " + msg_ginfo("More than one operation " "specified. Aborting.\n"); exit(1); } write_it = 1; break; case 'v': //FIXME: gracefully handle superfluous -v if (++operation_specified > 1) { - fprintf(stderr, "More than one operation " + msg_ginfo("More than one operation " "specified. Aborting.\n"); exit(1); } if (dont_verify_it) { - fprintf(stderr, "--verify and --noverify are" + msg_ginfo("--verify and --noverify are" "mutually exclusive. Aborting.\n"); exit(1); } verify_it = 1; break; case 'n': if (verify_it) { - fprintf(stderr, "--verify and --noverify are" + msg_ginfo("--verify and --noverify are" "mutually exclusive. Aborting.\n"); exit(1); } dont_verify_it = 1; break; case 'c': chip_to_probe = strdup(optarg); break; case 'V': verbose++; break; case 'E': if (++operation_specified > 1) { - fprintf(stderr, "More than one operation " + msg_ginfo("More than one operation " "specified. Aborting.\n"); exit(1); } erase_it = 1; break; #if INTERNAL_SUPPORT == 1 case 'm': tempstr = strdup(optarg); lb_vendor_dev_from_string(tempstr); break; #endif case 'f': force = 1; @@ -253,27 +253,27 @@ int cli_classic(int argc, char *argv[]) break; default: /* The continue refers to the * for loop. It is here to be * able to differentiate between * foo and foobar. */ continue; } break; } } if (programmer == PROGRAMMER_INVALID) { - printf("Error: Unknown programmer %s.\n", optarg); + msg_ginfo("Error: Unknown programmer %s.\n", optarg); exit(1); } break; case 'R': /* print_version() is always called during startup. */ exit(0); break; case 'h': default: cli_classic_usage(argv[0]); break; } } @@ -281,106 +281,106 @@ int cli_classic(int argc, char *argv[]) if (list_supported) { print_supported(); exit(0); } #if PRINT_WIKI_SUPPORT == 1 if (list_supported_wiki) { print_supported_wiki(); exit(0); } #endif if (read_it && write_it) { - printf("Error: -r and -w are mutually exclusive.\n"); + msg_ginfo("Error: -r and -w are mutually exclusive.\n"); cli_classic_usage(argv[0]); } if (optind < argc) filename = argv[optind++]; if (optind < argc) { - printf("Error: Extra parameter found.\n"); + msg_ginfo("Error: Extra parameter found.\n"); cli_classic_usage(argv[0]); } if (programmer_init()) { - fprintf(stderr, "Error: Programmer initialization failed.\n"); + msg_ginfo("Error: Programmer initialization failed.\n"); exit(1); } // FIXME: Delay calibration should happen in programmer code. myusec_calibrate_delay(); for (i = 0; i < ARRAY_SIZE(flashes); i++) { flashes[i] = probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); if (!flashes[i]) for (i++; i < ARRAY_SIZE(flashes); i++) flashes[i] = NULL; } if (flashes[1]) { - printf("Multiple flash chips were detected:"); + msg_ginfo("Multiple flash chips were detected:"); for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); - printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); + msg_ginfo(" %s", flashes[i]->name); + msg_ginfo("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); } else if (!flashes[0]) { - printf("No EEPROM/flash device found.\n"); + msg_ginfo("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { - printf("If you know which flash chip you have, and if this version of flashrom\n"); - printf("supports a similar flash chip, you can try to force read your chip. Run:\n"); - printf("flashrom -f -r -c similar_supported_flash_chip filename\n"); - printf("\n"); - printf("Note: flashrom can never write when the flash chip isn't found automatically.\n"); + msg_ginfo("If you know which flash chip you have, and if this version of flashrom\n"); + msg_ginfo("supports a similar flash chip, you can try to force read your chip. Run:\n"); + msg_ginfo("flashrom -f -r -c similar_supported_flash_chip filename\n"); + msg_ginfo("\n"); + msg_ginfo("Note: flashrom can never write when the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { - printf("Force read (-f -r -c) requested, forcing chip probe success:\n"); + msg_ginfo("Force read (-f -r -c) requested, forcing chip probe success:\n"); flashes[0] = probe_flash(flashchips, 1); if (!flashes[0]) { - printf("flashrom does not support a flash chip named '%s'.\n", chip_to_probe); - printf("Run flashrom -L to view the hardware supported in this flashrom version.\n"); + msg_ginfo("flashrom does not support a flash chip named '%s'.\n", chip_to_probe); + msg_ginfo("Run flashrom -L to view the hardware supported in this flashrom version.\n"); exit(1); } - printf("Please note that forced reads most likely contain garbage.\n"); + msg_ginfo("Please note that forced reads most likely contain garbage.\n"); return read_flash(flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } flash = flashes[0]; check_chip_supported(flash); size = flash->total_size * 1024; if (check_max_decode((buses_supported & flash->bustype), size) && (!force)) { - fprintf(stderr, "Chip is too big for this programmer " + msg_ginfo("Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); programmer_shutdown(); return 1; } if (!(read_it | write_it | verify_it | erase_it)) { - printf("No operations were specified.\n"); + msg_ginfo("No operations were specified.\n"); // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } if (!filename && !erase_it) { - printf("Error: No filename specified.\n"); + msg_ginfo("Error: No filename specified.\n"); // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } /* Always verify write operations unless -n is used. */ if (write_it && !dont_verify_it) verify_it = 1; return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); } diff --git a/flash.h b/flash.h index aee95a3..3d0d114 100644 --- a/flash.h +++ b/flash.h @@ -521,27 +521,26 @@ enum write_granularity { extern enum chipbustype buses_supported; struct decode_sizes { uint32_t parallel; uint32_t lpc; uint32_t fwh; uint32_t spi; }; extern struct decode_sizes max_rom_decode; extern char *programmer_param; extern unsigned long flashbase; extern int verbose; extern const char *flashrom_version; extern char *chip_to_probe; -#define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); int read_flash(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); int max(int a, int b); char *extract_param(char **haystack, char *needle, char *delim); int check_erased_range(struct flashchip *flash, int start, int len); int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); diff --git a/flashrom.c b/flashrom.c index 2450dee..eb52661 100644 --- a/flashrom.c +++ b/flashrom.c @@ -341,27 +341,27 @@ struct shutdown_func_data { } shutdown_fn[SHUTDOWN_MAXFN]; /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will * be used as parameter to the registered function upon programmer shutdown. * This pointer can point to arbitrary data used by said function, e.g. undo * information for GPIO settings etc. If unneeded, set data=NULL. * Please note that the first (void *data) belongs to the function signature of * the function passed as first parameter. */ int register_shutdown(void (*function) (void *data), void *data) { if (shutdown_fn_count >= SHUTDOWN_MAXFN) { - msg_perr("Tried to register more than %n shutdown functions.\n", + msg_gerr("Tried to register more than %n shutdown functions.\n", SHUTDOWN_MAXFN); return 1; } shutdown_fn[shutdown_fn_count].func = function; shutdown_fn[shutdown_fn_count].data = data; shutdown_fn_count++; return 0; } int programmer_init(void) { return programmer_table[programmer].init(); @@ -500,56 +500,56 @@ char *extract_param(char **haystack, char *needle, char *delim) if (strchr(delim, *(param_pos - 1))) break; /* Continue searching. */ param_pos++; param_pos = strstr(param_pos, needle); } while (1); if (param_pos) { param_pos += strlen(needle); devlen = strcspn(param_pos, delim); if (devlen) { dev = malloc(devlen + 1); if (!dev) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } strncpy(dev, param_pos, devlen); dev[devlen] = '\0'; } rest = param_pos + devlen; rest += strspn(rest, delim); param_pos -= strlen(needle); memmove(param_pos, rest, strlen(rest) + 1); tmp = realloc(*haystack, strlen(*haystack) + 1); if (!tmp) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } *haystack = tmp; } return dev; } /* start is an offset to the base address of the flash chip */ int check_erased_range(struct flashchip *flash, int start, int len) { int ret; uint8_t *cmpbuf = malloc(len); if (!cmpbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } memset(cmpbuf, 0xff, len); ret = verify_range(flash, cmpbuf, start, len, "ERASE"); free(cmpbuf); return ret; } /** * @cmpbuf buffer to compare against, cmpbuf[0] is expected to match the flash content at location start * @start offset to the base address of the flash chip * @len length of the verified area @@ -557,36 +557,36 @@ int check_erased_range(struct flashchip *flash, int start, int len) * @return 0 for success, -1 for failure */ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message) { int i, j, starthere, lenhere, ret = 0; int page_size = flash->page_size; uint8_t *readbuf = malloc(page_size); int failcount = 0; if (!len) goto out_free; if (!flash->read) { - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_gerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } if (!readbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } if (start + len > flash->total_size * 1024) { - fprintf(stderr, "Error: %s called with start 0x%x + len 0x%x >" + msg_gerr("Error: %s called with start 0x%x + len 0x%x >" " total_size 0x%x\n", __func__, start, len, flash->total_size * 1024); ret = -1; goto out_free; } if (!message) message = "VERIFY"; /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that * division rounds down. The highest page number we want is the page * where the last byte of the range lives. That last byte has the @@ -594,36 +594,36 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, c * (start + len - 1) / page_size. Since we want to include that last * page as well, the loop condition uses <=. */ for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { /* Byte position of the first byte in the range in this page. */ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; flash->read(flash, readbuf, starthere, lenhere); for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ if (!failcount++) - fprintf(stderr, "%s FAILED at 0x%08x! " + msg_gerr("%s FAILED at 0x%08x! " "Expected=0x%02x, Read=0x%02x,", message, starthere + j, cmpbuf[starthere - start + j], readbuf[j]); } } } if (failcount) { - fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + msg_gerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", start, start + len - 1, failcount); ret = -1; } out_free: free(readbuf); return ret; } /** * Check if the buffer @have can be programmed to the content of @want without * erasing. This is only possible if all chunks of size @gran are either kept * as-is or changed from an all-ones state to any other state. @@ -728,27 +728,27 @@ int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gra * Patterns 10-11 are special purpose for detecting subblock aliasing with * block sizes >256 bytes (some Dataflash chips etc.) * AND Pattern 8/9 == Pattern 12 * AND Pattern 10/11 == Pattern 12 * Pattern 13 is the completely erased state. * None of the patterns can detect aliasing at boundaries which are a multiple * of 16 MBytes (but such chips do not exist anyway for Parallel/LPC/FWH/SPI). */ int generate_testpattern(uint8_t *buf, uint32_t size, int variant) { int i; if (!buf) { - fprintf(stderr, "Invalid buffer!\n"); + msg_gerr("Invalid buffer!\n"); return 1; } switch (variant) { case 0: for (i = 0; i < size; i++) buf[i] = (i & 0xf) << 4 | 0x5; break; case 1: for (i = 0; i < size; i++) buf[i] = (i & 0xf) << 4 | 0xa; break; case 2: @@ -816,64 +816,64 @@ int generate_testpattern(uint8_t *buf, uint32_t size, int variant) buf[i * 256 + 255] = i & 0xff; } } return 0; } int check_max_decode(enum chipbustype buses, uint32_t size) { int limitexceeded = 0; if ((buses & CHIP_BUSTYPE_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_gdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.parallel / 1024, "Parallel"); } if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_gdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.lpc / 1024, "LPC"); } if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_gdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.fwh / 1024, "FWH"); } if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_gdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.spi / 1024, "SPI"); } if (!limitexceeded) return 0; /* Sometimes chip and programmer have more than one bus in common, * and the limit is not exceeded on all buses. Tell the user. */ if (bitcount(buses) > limitexceeded) /* FIXME: This message is designed towards CLI users. */ - printf_debug("There is at least one common chip/programmer " + msg_gdbg("There is at least one common chip/programmer " "interface which can support a chip of this size. " "You can try --force at your own risk.\n"); return 1; } struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; unsigned long base = 0; uint32_t size; enum chipbustype buses_common; char *tmp; @@ -914,78 +914,78 @@ struct flashchip *probe_flash(struct flashchip *first_flash, int force) goto notfound; if (first_flash == flashchips || flash->model_id != GENERIC_DEVICE_ID) break; notfound: programmer_unmap_flash_region((void *)flash->virtual_memory, size); } if (!flash || !flash->name) return NULL; - printf("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + msg_ginfo("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); if (flash->printlock) flash->printlock(flash); return flash; } int verify_flash(struct flashchip *flash, uint8_t *buf) { int ret; int total_size = flash->total_size * 1024; - printf("Verifying flash... "); + msg_ginfo("Verifying flash... "); ret = verify_range(flash, buf, 0, total_size, NULL); if (!ret) - printf("VERIFIED. \n"); + msg_ginfo("VERIFIED. \n"); return ret; } int read_flash(struct flashchip *flash, char *filename) { unsigned long numbytes; FILE *image; unsigned long size = flash->total_size * 1024; unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - printf("Error: No filename specified.\n"); + msg_ginfo("Error: No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); exit(1); } - printf("Reading flash... "); + msg_ginfo("Reading flash... "); if (!flash->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_ginfo("FAILED!\n"); + msg_gerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } else flash->read(flash, buf, 0, size); numbytes = fwrite(buf, 1, size, image); fclose(image); free(buf); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); + msg_ginfo("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1; return 0; } /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ int selfcheck_eraseblocks(struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1007,27 +1007,27 @@ int selfcheck_eraseblocks(struct flashchip *flash) if (!eraser.eraseblocks[i].count && eraser.eraseblocks[i].size) { msg_gerr("ERROR: Flash chip %s erase function " "%i region %i has count 0. Please report" " a bug at flashrom(a)flashrom.org\n", flash->name, k, i); ret = 1; } done += eraser.eraseblocks[i].count * eraser.eraseblocks[i].size; } /* Empty eraseblock definition with erase function. */ if (!done && eraser.block_erase) - msg_pspew("Strange: Empty eraseblock definition with " + msg_gspew("Strange: Empty eraseblock definition with " "non-empty erase function. Not an error.\n"); if (!done) continue; if (done != flash->total_size * 1024) { msg_gerr("ERROR: Flash chip %s erase function %i " "region walking resulted in 0x%06x bytes total," " expected 0x%06x bytes. Please report a bug at" " flashrom(a)flashrom.org\n", flash->name, k, done, flash->total_size * 1024); ret = 1; } if (!eraser.block_erase) continue; @@ -1044,106 +1044,106 @@ int selfcheck_eraseblocks(struct flashchip *flash) flash->name, k, j); ret = 1; } } } return ret; } int erase_flash(struct flashchip *flash) { int i, j, k, ret = 0, found = 0; unsigned int start, len; - printf("Erasing flash chip... "); + msg_ginfo("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; - printf_debug("Looking at blockwise erase function %i... ", k); + msg_gdbg("Looking at blockwise erase function %i... ", k); if (!eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("not defined. " + msg_gdbg("not defined. " "Looking for another erase function.\n"); continue; } if (!eraser.block_erase && eraser.eraseblocks[0].count) { - printf_debug("eraseblock layout is known, but no " + msg_gdbg("eraseblock layout is known, but no " "matching block erase function found. " "Looking for another erase function.\n"); continue; } if (eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("block erase function found, but " + msg_gdbg("block erase function found, but " "eraseblock layout is unknown. " "Looking for another erase function.\n"); continue; } found = 1; - printf_debug("trying... "); + msg_gdbg("trying... "); for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ for (j = 0; j < eraser.eraseblocks[i].count; j++) { start = done + eraser.eraseblocks[i].size * j; len = eraser.eraseblocks[i].size; - printf_debug("0x%06x-0x%06x, ", start, + msg_gdbg("0x%06x-0x%06x, ", start, start + len - 1); ret = eraser.block_erase(flash, start, len); if (ret) break; } if (ret) break; done += eraser.eraseblocks[i].count * eraser.eraseblocks[i].size; } - printf_debug("\n"); + msg_gdbg("\n"); /* If everything is OK, don't try another erase function. */ if (!ret) break; } if (!found) { - fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); + msg_gerr("ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_gerr("FAILED!\n"); } else { - printf("SUCCESS.\n"); + msg_ginfo("SUCCESS.\n"); } return ret; } void emergency_help_message(void) { - fprintf(stderr, "Your flash chip is in an unknown state.\n" + msg_gerr("Your flash chip is in an unknown state.\n" "Get help on IRC at irc.freenode.net (channel #flashrom) or\n" "mail flashrom(a)flashrom.org!\n--------------------" "-----------------------------------------------------------\n" "DO NOT REBOOT OR POWEROFF!\n"); } /* The way to go if you want a delimited list of programmers*/ void list_programmers(char *delim) { enum programmer p; for (p = 0; p < PROGRAMMER_INVALID; p++) { - printf("%s", programmer_table[p].name); + msg_ginfo("%s", programmer_table[p].name); if (p < PROGRAMMER_INVALID - 1) - printf("%s", delim); + msg_ginfo("%s", delim); } - printf("\n"); + msg_ginfo("\n"); } void print_sysinfo(void) { #if HAVE_UTSNAME == 1 struct utsname osinfo; uname(&osinfo); msg_ginfo(" on %s %s (%s)", osinfo.sysname, osinfo.release, osinfo.machine); #else msg_ginfo(" on unknown machine"); #endif @@ -1162,91 +1162,91 @@ void print_sysinfo(void) #ifdef __VERSION__ msg_ginfo(" %s", __VERSION__); #else msg_ginfo(" unknown version"); #endif #else msg_ginfo(" unknown compiler"); #endif msg_ginfo("\n"); } void print_version(void) { - printf("flashrom v%s", flashrom_version); + msg_ginfo("flashrom v%s\n", flashrom_version); print_sysinfo(); } int selfcheck(void) { int ret = 0; struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. */ if (ARRAY_SIZE(programmer_table) - 1 != PROGRAMMER_INVALID) { - fprintf(stderr, "Programmer table miscompilation!\n"); + msg_gerr("Programmer table miscompilation!\n"); ret = 1; } if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - fprintf(stderr, "SPI programmer table miscompilation!\n"); + msg_gerr("SPI programmer table miscompilation!\n"); ret = 1; } #if BITBANG_SPI_SUPPORT == 1 if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { - fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); + msg_gerr("Bitbanging SPI master table miscompilation!\n"); ret = 1; } #endif for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; return ret; } void check_chip_supported(struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { - printf("===\n"); + msg_ginfo("===\n"); if (flash->tested & TEST_BAD_MASK) { - printf("This flash part has status NOT WORKING for operations:"); + msg_ginfo("This flash part has status NOT WORKING for operations:"); if (flash->tested & TEST_BAD_PROBE) - printf(" PROBE"); + msg_ginfo(" PROBE"); if (flash->tested & TEST_BAD_READ) - printf(" READ"); + msg_ginfo(" READ"); if (flash->tested & TEST_BAD_ERASE) - printf(" ERASE"); + msg_ginfo(" ERASE"); if (flash->tested & TEST_BAD_WRITE) - printf(" WRITE"); - printf("\n"); + msg_ginfo(" WRITE"); + msg_ginfo("\n"); } if ((!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) || (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) || (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) || (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE))) { - printf("This flash part has status UNTESTED for operations:"); + msg_ginfo("This flash part has status UNTESTED for operations:"); if (!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) - printf(" PROBE"); + msg_ginfo(" PROBE"); if (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) - printf(" READ"); + msg_ginfo(" READ"); if (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) - printf(" ERASE"); + msg_ginfo(" ERASE"); if (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE)) - printf(" WRITE"); - printf("\n"); + msg_ginfo(" WRITE"); + msg_ginfo("\n"); } /* FIXME: This message is designed towards CLI users. */ - printf("Please email a report to flashrom(a)flashrom.org if any " + msg_ginfo("Please email a report to flashrom(a)flashrom.org if any " "of the above operations\nwork correctly for you with " "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " "tested (-V, -rV,\n-wV, -EV), and mention which " "mainboard or programmer you tested.\nThanks for your " "help!\n===\n"); } } int main(int argc, char *argv[]) { return cli_classic(argc, argv); } @@ -1257,127 +1257,127 @@ int main(int argc, char *argv[]) int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) { uint8_t *buf; unsigned long numbytes; FILE *image; int ret = 0; unsigned long size; size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip. "); + msg_gerr("Erase is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_gerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_gerr("Continuing anyway.\n"); } } if (flash->unlock) flash->unlock(flash); if (erase_flash(flash)) { emergency_help_message(); programmer_shutdown(); return 1; } } else if (read_it) { if (flash->unlock) flash->unlock(flash); if (read_flash(flash, filename)) { programmer_shutdown(); return 1; } } else { struct stat image_stat; if (flash->unlock) flash->unlock(flash); if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip " + msg_gerr("Erase is not working on this chip " "and erase is needed for write. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_gerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_gerr("Continuing anyway.\n"); } } if (flash->tested & TEST_BAD_WRITE) { - fprintf(stderr, "Write is not working on this chip. "); + msg_gerr("Write is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_gerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_gerr("Continuing anyway.\n"); } } if ((image = fopen(filename, "rb")) == NULL) { perror(filename); programmer_shutdown(); exit(1); } if (fstat(fileno(image), &image_stat) != 0) { perror(filename); programmer_shutdown(); exit(1); } if (image_stat.st_size != flash->total_size * 1024) { - fprintf(stderr, "Error: Image size doesn't match\n"); + msg_gerr("Error: Image size doesn't match\n"); programmer_shutdown(); exit(1); } numbytes = fread(buf, 1, size, image); #if INTERNAL_SUPPORT == 1 show_id(buf, size, force); #endif fclose(image); if (numbytes != size) { - fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); + msg_gerr("Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); programmer_shutdown(); return 1; } } // This should be moved into each flash part's code to do it // cleanly. This does the job. handle_romentries(buf, flash); // //////////////////////////////////////////////////////////// if (write_it) { - printf("Writing flash chip... "); + msg_ginfo("Writing flash chip... "); if (!flash->write) { - fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n"); + msg_gerr("Error: flashrom has no write function for this flash chip.\n"); programmer_shutdown(); return 1; } ret = flash->write(flash, buf); if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_gerr("FAILED!\n"); emergency_help_message(); programmer_shutdown(); return 1; } else { - printf("COMPLETE.\n"); + msg_ginfo("COMPLETE.\n"); } } if (verify_it) { /* Work around chips which need some time to calm down. */ if (write_it) programmer_delay(1000*1000); ret = verify_flash(flash, buf); /* If we tried to write, and verification now fails, we * might have an emergency situation. */ if (ret && write_it) emergency_help_message(); diff --git a/layout.c b/layout.c index 26b7c6a..e9760d5 100644 --- a/layout.c +++ b/layout.c @@ -63,149 +63,149 @@ int show_id(uint8_t *bios, int size, int force) walk--; } /* * Check if coreboot last image size is 0 or not a multiple of 1k or * bigger than the chip or if the pointers to vendor ID or mainboard ID * are outside the image of if the start of ID strings are nonsensical * (nonprintable and not \0). */ mb_part_offset = *(walk - 1); mb_vendor_offset = *(walk - 2); if ((*walk) == 0 || ((*walk) & 0x3ff) != 0 || (*walk) > size || mb_part_offset > size || mb_vendor_offset > size) { - printf("Flash image seems to be a legacy BIOS. Disabling checks.\n"); + msg_ginfo("Flash image seems to be a legacy BIOS. Disabling checks.\n"); return 0; } mb_part = (char *)(bios + size - mb_part_offset); mb_vendor = (char *)(bios + size - mb_vendor_offset); if (!isprint((unsigned char)*mb_part) || !isprint((unsigned char)*mb_vendor)) { - printf("Flash image seems to have garbage in the ID location." + msg_ginfo("Flash image seems to have garbage in the ID location." " Disabling checks.\n"); return 0; } - printf_debug("coreboot last image size " + msg_gdbg("coreboot last image size " "(not ROM size) is %d bytes.\n", *walk); mainboard_part = strdup(mb_part); mainboard_vendor = strdup(mb_vendor); - printf_debug("Manufacturer: %s\n", mainboard_vendor); - printf_debug("Mainboard ID: %s\n", mainboard_part); + msg_gdbg("Manufacturer: %s\n", mainboard_vendor); + msg_gdbg("Mainboard ID: %s\n", mainboard_part); /* * If lb_vendor is not set, the coreboot table was * not found. Nor was -m VENDOR:PART specified. */ if (!lb_vendor || !lb_part) { - printf("Note: If the following flash access fails, " + msg_ginfo("Note: If the following flash access fails, " "try -m <vendor>:<mainboard>.\n"); return 0; } /* These comparisons are case insensitive to make things * a little less user^Werror prone. */ if (!strcasecmp(mainboard_vendor, lb_vendor) && !strcasecmp(mainboard_part, lb_part)) { - printf_debug("This firmware image matches this mainboard.\n"); + msg_ginfo("This firmware image matches this mainboard.\n"); } else { if (force) { - printf("WARNING: This firmware image does not " + msg_ginfo("WARNING: This firmware image does not " "seem to fit to this machine - forcing it.\n"); } else { - printf("ERROR: Your firmware image (%s:%s) does not " + msg_ginfo("ERROR: Your firmware image (%s:%s) does not " "appear to\n be correct for the detected " "mainboard (%s:%s)\n\nOverride with --force if you " "are absolutely sure that you\nare using a correct " "image for this mainboard or override\nthe detected " "values with --mainboard <vendor>:<mainboard>.\n\n", mainboard_vendor, mainboard_part, lb_vendor, lb_part); exit(1); } } return 0; } #endif int read_romlayout(char *name) { FILE *romlayout; char tempstr[256]; int i; romlayout = fopen(name, "r"); if (!romlayout) { - fprintf(stderr, "ERROR: Could not open ROM layout (%s).\n", + msg_gerr("ERROR: Could not open ROM layout (%s).\n", name); return -1; } while (!feof(romlayout)) { char *tstr1, *tstr2; if (2 != fscanf(romlayout, "%s %s\n", tempstr, rom_entries[romimages].name)) continue; #if 0 // fscanf does not like arbitrary comments like that :( later if (tempstr[0] == '#') { continue; } #endif tstr1 = strtok(tempstr, ":"); tstr2 = strtok(NULL, ":"); if (!tstr1 || !tstr2) { - fprintf(stderr, "Error parsing layout file.\n"); + msg_gerr("Error parsing layout file.\n"); fclose(romlayout); return 1; } rom_entries[romimages].start = strtol(tstr1, (char **)NULL, 16); rom_entries[romimages].end = strtol(tstr2, (char **)NULL, 16); rom_entries[romimages].included = 0; romimages++; } for (i = 0; i < romimages; i++) { - printf_debug("romlayout %08x - %08x named %s\n", + msg_gdbg("romlayout %08x - %08x named %s\n", rom_entries[i].start, rom_entries[i].end, rom_entries[i].name); } fclose(romlayout); return 0; } int find_romentry(char *name) { int i; if (!romimages) return -1; - printf("Looking for \"%s\"... ", name); + msg_ginfo("Looking for \"%s\"... ", name); for (i = 0; i < romimages; i++) { if (!strcmp(rom_entries[i].name, name)) { rom_entries[i].included = 1; - printf("found.\n"); + msg_ginfo("found.\n"); return i; } } - printf("not found.\n"); // Not found. Error. + msg_ginfo("not found.\n"); // Not found. Error. return -1; } int handle_romentries(uint8_t *buffer, struct flashchip *flash) { int i; // This function does not save flash write cycles. // // Also it does not cope with overlapping rom layout // sections. // example: diff --git a/print.c b/print.c index 2a2c81b..e7ff27e 100644 --- a/print.c +++ b/print.c @@ -47,27 +47,27 @@ char *flashbuses_to_text(enum chipbustype bustype) if (bustype & CHIP_BUSTYPE_FWH) ret = strcat_realloc(ret, "FWH,"); if (bustype & CHIP_BUSTYPE_SPI) ret = strcat_realloc(ret, "SPI,"); if (bustype == CHIP_BUSTYPE_NONE) ret = strcat_realloc(ret, "None,"); } /* Kill last comma. */ ret[strlen(ret) - 1] = '\0'; ret = realloc(ret, strlen(ret) + 1); return ret; } -#define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0) +#define POS_PRINT(x) do { pos += strlen(x); msg_ginfo(x); } while (0) static int digits(int n) { int i; if (!n) return 1; for (i = 0; n; ++i) n /= 10; return i; } @@ -77,172 +77,172 @@ void print_supported_chips(void) int okcol = 0, pos = 0, i, chipcount = 0; struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { if (GENERIC_DEVICE_ID == f->model_id) continue; okcol = max(okcol, strlen(f->vendor) + 1 + strlen(f->name)); } okcol = (okcol + 7) & ~7; for (f = flashchips; f->name != NULL; f++) chipcount++; - printf("\nSupported flash chips (total: %d):\n\n", chipcount); + msg_ginfo("\nSupported flash chips (total: %d):\n\n", chipcount); POS_PRINT("Vendor: Device:"); while (pos < okcol) { - printf("\t"); + msg_ginfo("\t"); pos += 8 - (pos % 8); } - printf("Tested OK:\tKnown BAD: Size/KB: Type:\n\n"); - printf("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); + msg_ginfo("Tested OK:\tKnown BAD: Size/KB: Type:\n\n"); + msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); for (f = flashchips; f->name != NULL; f++) { /* Don't print "unknown XXXX SPI chip" entries. */ if (!strncmp(f->name, "unknown", 7)) continue; - printf("%s", f->vendor); + msg_ginfo("%s", f->vendor); for (i = 0; i < 10 - strlen(f->vendor); i++) - printf(" "); - printf("%s", f->name); + msg_ginfo(" "); + msg_ginfo("%s", f->name); pos = 10 + strlen(f->name); while (pos < okcol) { - printf("\t"); + msg_ginfo("\t"); pos += 8 - (pos % 8); } if ((f->tested & TEST_OK_MASK)) { if ((f->tested & TEST_OK_PROBE)) POS_PRINT("P "); if ((f->tested & TEST_OK_READ)) POS_PRINT("R "); if ((f->tested & TEST_OK_ERASE)) POS_PRINT("E "); if ((f->tested & TEST_OK_WRITE)) POS_PRINT("W "); } while (pos < okcol + 9) { - printf("\t"); + msg_ginfo("\t"); pos += 8 - (pos % 8); } if ((f->tested & TEST_BAD_MASK)) { if ((f->tested & TEST_BAD_PROBE)) - printf("P "); + msg_ginfo("P "); if ((f->tested & TEST_BAD_READ)) - printf("R "); + msg_ginfo("R "); if ((f->tested & TEST_BAD_ERASE)) - printf("E "); + msg_ginfo("E "); if ((f->tested & TEST_BAD_WRITE)) - printf("W "); + msg_ginfo("W "); } - printf("\t %d", f->total_size); + msg_ginfo("\t %d", f->total_size); for (i = 0; i < 10 - digits(f->total_size); i++) - printf(" "); - printf("%s\n", flashbuses_to_text(f->bustype)); + msg_ginfo(" "); + msg_ginfo("%s\n", flashbuses_to_text(f->bustype)); } } #if INTERNAL_SUPPORT == 1 void print_supported_chipsets(void) { int i, j, chipsetcount = 0; const struct penable *c = chipset_enables; for (i = 0; c[i].vendor_name != NULL; i++) chipsetcount++; - printf("\nSupported chipsets (total: %d):\n\nVendor: " + msg_ginfo("\nSupported chipsets (total: %d):\n\nVendor: " "Chipset: PCI IDs:\n\n", chipsetcount); for (i = 0; c[i].vendor_name != NULL; i++) { - printf("%s", c[i].vendor_name); + msg_ginfo("%s", c[i].vendor_name); for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) - printf(" "); - printf("%s", c[i].device_name); + msg_ginfo(" "); + msg_ginfo("%s", c[i].device_name); for (j = 0; j < 25 - strlen(c[i].device_name); j++) - printf(" "); - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, + msg_ginfo(" "); + msg_ginfo("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, (c[i].status == OK) ? "" : " (untested)"); } } void print_supported_boards_helper(const struct board_info *b, const char *msg) { int i, j, boardcount = 0; for (i = 0; b[i].vendor != NULL; i++) boardcount++; - printf("\n%s (total: %d):\n\n", msg, boardcount); + msg_ginfo("\n%s (total: %d):\n\n", msg, boardcount); for (i = 0; b[i].vendor != NULL; i++) { - printf("%s", b[i].vendor); + msg_ginfo("%s", b[i].vendor); for (j = 0; j < 25 - strlen(b[i].vendor); j++) - printf(" "); - printf("%s", b[i].name); + msg_ginfo(" "); + msg_ginfo("%s", b[i].name); for (j = 0; j < 28 - strlen(b[i].name); j++) - printf(" "); - printf("\n"); + msg_ginfo(" "); + msg_ginfo("\n"); } } void print_supported_boards(void) { int i, j, boardcount = 0; struct board_pciid_enable *b = board_pciid_enables; for (i = 0; b[i].vendor_name != NULL; i++) boardcount++; - printf("\nSupported boards which need write-enable code (total: %d):" + msg_ginfo("\nSupported boards which need write-enable code (total: %d):" "\n\nVendor: Board: " "Required option:\n\n", boardcount); for (i = 0; b[i].vendor_name != NULL; i++) { - printf("%s", b[i].vendor_name); + msg_ginfo("%s", b[i].vendor_name); for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) - printf(" "); - printf("%s", b[i].board_name); + msg_ginfo(" "); + msg_ginfo("%s", b[i].board_name); for (j = 0; j < 30 - strlen(b[i].board_name); j++) - printf(" "); + msg_ginfo(" "); if (b[i].lb_vendor != NULL) - printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); + msg_ginfo("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); else - printf("(none, board is autodetected)\n"); + msg_ginfo("(none, board is autodetected)\n"); } print_supported_boards_helper(boards_ok, "Supported boards which don't need write-enable code"); print_supported_boards_helper(boards_bad, "Boards which have been verified to NOT work yet"); print_supported_boards_helper(laptops_ok, "Laptops which have been verified to work"); print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } #endif void print_supported(void) { print_supported_chips(); #if INTERNAL_SUPPORT == 1 print_supported_chipsets(); print_supported_boards(); #endif #if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) - printf("\nSupported PCI devices flashrom can use " + msg_ginfo("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #endif #if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); #endif #if GFXNVIDIA_SUPPORT == 1 print_supported_pcidevs(gfx_nvidia); #endif #if DRKAISER_SUPPORT == 1 print_supported_pcidevs(drkaiser_pcidev); #endif #if SATASII_SUPPORT == 1 print_supported_pcidevs(satas_sii); diff --git a/print_wiki.c b/print_wiki.c index 9c0143c..e5eb521 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -363,237 +363,237 @@ static int note(const char *vendor, const char *board) } return -1; } void print_supported_chipsets_wiki(void) { int i, j, enablescount = 0, color = 1; const struct penable *e; for (e = chipset_enables; e->vendor_name != NULL; e++) enablescount++; - printf("\n== Supported chipsets ==\n\nTotal amount of supported " + msg_ginfo("\n== Supported chipsets ==\n\nTotal amount of supported " "chipsets: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n| " "valign=\"top\"|\n\n%s", enablescount, chipset_th); e = chipset_enables; for (i = 0, j = 0; e[i].vendor_name != NULL; i++, j++) { /* Alternate colors if the vendor changes. */ if (i > 0 && strcmp(e[i].vendor_name, e[i - 1].vendor_name)) color = !color; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " + msg_ginfo("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " "|| %04x:%04x || %s\n", (color) ? "eeeeee" : "dddddd", e[i].vendor_name, e[i].device_name, e[i].vendor_id, e[i].device_id, (e[i].status == OK) ? "{{OK}}" : "?"); /* Split table in three columns. */ if (j >= (enablescount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); + msg_ginfo("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); j = 0; } } - printf("\n|}\n\n|}\n"); + msg_ginfo("\n|}\n\n|}\n"); } static void wiki_helper(const char *heading, const char *status, int cols, const struct board_info boards[]) { int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; const struct board_info *b; const struct board_info_url *u = boards_url; char *notes = calloc(1, 1); char tmp[900 + 1]; for (b = boards; b->vendor != NULL; b++) boardcount++; - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" + msg_ginfo("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", heading, boardcount, board_th); for (i = 0, j = 0, b = boards; b[i].vendor != NULL; i++, j++) { /* Alternate colors if the vendor changes. */ if (i > 0 && strcmp(b[i].vendor, b[i - 1].vendor)) color = !color; k = url(b[i].vendor, b[i].name); c = note(b[i].vendor, b[i].name); - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" + msg_ginfo("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, (k != -1 && u[k].url) ? "[" : "", (k != -1 && u[k].url) ? u[k].url : "", b[i].name, (k != -1 && u[k].url) ? "]" : "", status); if (c != -1) { - printf("%d\n", num_notes + 1); - snprintf((char *)&tmp, 900, "%d %s \n", + msg_ginfo("%d\n", num_notes + 1); + snmsg_ginfo((char *)&tmp, 900, "%d %s \n", 1 + num_notes++, boards_notes[c].note); notes = strcat_realloc(notes, (char *)&tmp); } else { - printf("\n"); + msg_ginfo("\n"); } /* Split table in 'cols' columns. */ if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th); + msg_ginfo("\n|}\n\n| valign=\"top\"|\n\n%s", board_th); j = 0; } } - printf("\n|}\n\n|}\n"); + msg_ginfo("\n|}\n\n|}\n"); if (num_notes > 0) - printf("\n\n%s\n", notes); + msg_ginfo("\n\n%s\n", notes); free(notes); } static void wiki_helper2(const char *heading, int cols) { int i, j, k, boardcount = 0, color = 1; struct board_pciid_enable *b; const struct board_info_url *u = boards_url; for (b = board_pciid_enables; b->vendor_name != NULL; b++) boardcount++; - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" + msg_ginfo("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", heading, boardcount, board_th2); b = board_pciid_enables; for (i = 0, j = 0; b[i].vendor_name != NULL; i++, j++) { /* Alternate colors if the vendor changes. */ if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) color = !color; k = url(b[i].vendor_name, b[i].board_name); - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " + msg_ginfo("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, (k != -1 && u[k].url) ? "]" : "", (b[i].lb_vendor) ? "-m " : "—", (b[i].lb_vendor) ? b[i].lb_vendor : "", (b[i].lb_vendor) ? ":" : "", (b[i].lb_vendor) ? b[i].lb_part : ""); /* Split table in three columns. */ if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); + msg_ginfo("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); j = 0; } } - printf("\n|}\n\n|}\n"); + msg_ginfo("\n|}\n\n|}\n"); } void print_supported_boards_wiki(void) { - printf("%s", board_intro); + msg_ginfo("%s", board_intro); wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); wiki_helper2("Known good (with write-enable code in flashrom)", 3); wiki_helper("Not supported (yet)", "No", 3, boards_bad); - printf("%s", laptop_intro); + msg_ginfo("%s", laptop_intro); wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); wiki_helper("Not supported (yet)", "No", 1, laptops_bad); } void print_supported_chips_wiki(void) { int i = 0, c = 1, chipcount = 0; struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) chipcount++; - printf("\n== Supported chips ==\n\nTotal amount of supported " + msg_ginfo("\n== Supported chips ==\n\nTotal amount of supported " "chips: '''%d'''\n\n{| border=\"0\" valign=\"top\"\n" "| valign=\"top\"|\n\n%s", chipcount, chip_th); for (f = flashchips; f->name != NULL; f++, i++) { /* Don't print "unknown XXXX SPI chip" entries. */ if (!strncmp(f->name, "unknown", 7)) continue; /* Alternate colors if the vendor changes. */ if (old != NULL && strcmp(old->vendor, f->vendor)) c = !c; t = f->tested; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " + msg_ginfo("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, f->total_size, flashbuses_to_text(f->bustype), (t & TEST_OK_PROBE) ? "OK" : (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), (t & TEST_OK_READ) ? "OK" : (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), (t & TEST_OK_ERASE) ? "OK" : (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), (t & TEST_OK_WRITE) ? "OK" : (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); /* Split table into three columns. */ if (i >= (chipcount / 3 + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); + msg_ginfo("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); i = 0; } old = f; } - printf("\n|}\n\n|}\n"); + msg_ginfo("\n|}\n\n|}\n"); } void print_supported_pcidevs_wiki(struct pcidev_status *devs) { int i = 0; static int c = 0; /* Alternate colors if the vendor changes. */ c = !c; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " + msg_ginfo("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, (devs[i].status == NT) ? (c) ? "?2" : "?" : "OK"); } } void print_supported_wiki(void) { time_t t = time(NULL); - printf(wiki_header, ctime(&t), flashrom_version); + msg_ginfo(wiki_header, ctime(&t), flashrom_version); print_supported_chips_wiki(); print_supported_chipsets_wiki(); print_supported_boards_wiki(); - printf("%s", programmer_section); + msg_ginfo("%s", programmer_section); #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); #endif #if GFXNVIDIA_SUPPORT == 1 print_supported_pcidevs_wiki(gfx_nvidia); #endif #if DRKAISER_SUPPORT == 1 print_supported_pcidevs_wiki(drkaiser_pcidev); #endif #if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii); #endif #if ATAHPT_SUPPORT == 1 print_supported_pcidevs_wiki(ata_hpt); #endif - printf("\n|}\n"); + msg_ginfo("\n|}\n"); } -- 1.6.6

2 6

[PATCH 1/2] convert programmer print messages to msg_p*
by Sean Nelson 07 May '10

07 May '10

--- board_enable.c | 93 +++++++++++------------ cbtable.c | 26 +++--- chipset_enable.c | 216 +++++++++++++++++++++++++++--------------------------- dmi.c | 12 ++-- hwaccess.c | 2 +- ichspi.c | 77 ++++++++----------- internal.c | 4 +- pcidev.c | 12 ++-- physmap.c | 34 ++++---- spi.c | 8 +- 10 files changed, 235 insertions(+), 249 deletions(-) diff --git a/board_enable.c b/board_enable.c index 9b05f76..9112011 100644 --- a/board_enable.c +++ b/board_enable.c @@ -77,48 +77,48 @@ static int enable_flash_decode_superio(void) case SUPERIO_VENDOR_NONE: ret = -1; break; case SUPERIO_VENDOR_ITE: enter_conf_mode_ite(superio.port); /* Enable flash mapping. Works for most old ITE style Super I/O. */ tmp = sio_read(superio.port, 0x24); tmp |= 0xfc; sio_write(superio.port, 0x24, tmp); exit_conf_mode_ite(superio.port); ret = 0; break; default: - printf_debug("Unhandled Super I/O type!\n"); + msg_perr("Unhandled Super I/O type!\n"); ret = -1; break; } return ret; } #endif /** * Winbond W83627HF: Raise GPIO24. * * Suited for: * - Agami Aruma * - IWILL DK8-HTX */ static int w83627hf_gpio24_raise(uint16_t port, const char *name) { w836xx_ext_enter(port); /* Is this the W83627HF? */ if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; } /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ sio_mask(port, 0x2B, 0x10, 0x10); /* Select logical device 8: GPIO port 2 */ sio_write(port, 0x07, 0x08); sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ @@ -138,27 +138,27 @@ static int w83627hf_gpio24_raise_2e(const char *name) /** * Winbond W83627THF: GPIO 4, bit 4 * * Suited for: * - MSI K8T Neo2-F * - MSI K8N-NEO3 */ static int w83627thf_gpio4_4_raise(uint16_t port, const char *name) { w836xx_ext_enter(port); /* Is this the W83627THF? */ if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; } /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ @@ -243,40 +243,40 @@ static int it8705f_write_enable_2e(const char *name) { return it8705f_write_enable(0x2e, name); } static int pc87360_gpio_set(uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; int gpio_pin = gpio % 8; uint16_t baseport; uint8_t id, val; if (gpio_bank > 4) { - fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC87360: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); if (id != 0xE1) { - fprintf(stderr, "PC87360: unexpected ID %02x\n", id); + msg_perr("PC87360: unexpected ID %02x\n", id); return -1; } sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */ baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { - fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", + msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); return -1; } sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */ sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */ val = INB(baseport + bankbase[gpio_bank]); if (raise) val |= 1 << gpio_pin; else val &= ~(1 << gpio_pin); OUTB(val, baseport + bankbase[gpio_bank]); @@ -290,46 +290,46 @@ static int pc87360_gpio_set(uint8_t gpio, int raise) static int via_vt823x_gpio_set(uint8_t gpio, int raise) { struct pci_dev *dev; uint16_t base; uint8_t val, bit, offset; dev = pci_dev_find_vendorclass(0x1106, 0x0601); switch (dev->device_id) { case 0x3177: /* VT8235 */ case 0x3227: /* VT8237R */ case 0x3337: /* VT8237A */ break; default: - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + msg_perr("\nERROR: VT823x ISA bridge not found.\n"); return -1; } if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); val |= 0x10; pci_write_byte(dev, 0xE4, val); } else if (gpio == 9) { /* GPIO9 -> Output */ val = pci_read_byte(dev, 0xE4); val |= 0x20; pci_write_byte(dev, 0xE4, val); } else if (gpio == 5) { val = pci_read_byte(dev, 0xE4); val |= 0x01; pci_write_byte(dev, 0xE4, val); } else { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); return -1; } /* We need the I/O Base Address for this board's flash enable. */ base = pci_read_word(dev, 0x88) & 0xff80; offset = 0x4C + gpio / 8; bit = 0x01 << (gpio % 8); val = INB(base + offset); if (raise) val |= bit; @@ -401,70 +401,70 @@ static int board_asus_p5a(const char *name) OUTB(0x00, 0xE807); OUTB(0xEF, 0xE803); OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { OUTB(0xE1, 0xFF); if (INB(0xE800) & 0x04) break; } if (i == ASUSP5A_LOOP) { - printf("%s: Unable to contact device.\n", name); + msg_perr("%s: Unable to contact device.\n", name); return -1; } OUTB(0x20, 0xE801); OUTB(0x20, 0xE1); OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = INB(0xE800); if (tmp & 0x70) break; } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to read device.\n", name); + msg_perr("%s: failed to read device.\n", name); return -1; } tmp = INB(0xE804); tmp &= ~0x02; OUTB(0x00, 0xE807); OUTB(0xEE, 0xE803); OUTB(tmp, 0xE804); OUTB(0xFF, 0xE800); OUTB(0xE1, 0xFF); OUTB(0x20, 0xE801); OUTB(0x20, 0xE1); OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = INB(0xE800); if (tmp & 0x70) break; } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to write to device.\n", name); + msg_perr("%s: failed to write to device.\n", name); return -1; } return 0; } /* * Set GPIO lines in the Broadcom HT-1000 southbridge. * * It's not a Super I/O but it uses the same index/data port method. */ static int board_hp_dl145_g3_enable(const char *name) { @@ -482,67 +482,65 @@ static int board_ibm_x3455(const char *name) return 0; } /** * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4). */ static int board_shuttle_fn25(const char *name) { struct pci_dev *dev; dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { - fprintf(stderr, - "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; } /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ pci_write_byte(dev, 0x92, 0); return 0; } /** * Very similar to AMD 8111 IO Hub. */ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { - fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } /* First, check the ISA Bridge */ dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: /* Newer MCPs use the SMBus Controller */ dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); switch (dev->device_id) { case 0x0264: /* MCP51 */ break; default: - fprintf(stderr, - "\nERROR: no NVIDIA LPC/SMBus controller found.\n"); + msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; } break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ base += 0xC0; tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) tmp |= 0x01; @@ -643,40 +641,40 @@ static int board_artecgroup_dbe6x(const char *name) } /** * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) { unsigned int gpo_byte, gpo_bit; struct pci_dev *dev; uint32_t tmp, base; dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; } /* sanity check */ if (gpo > 30) { - fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); return -1; } /* these are dual function pins which are most likely in use already */ if (((gpo >= 1) && (gpo <= 7)) || ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); return -1; } /* dual function that need special enable. */ if ((gpo >= 22) && (gpo <= 26)) { tmp = pci_read_long(dev, 0xB0); /* GENCFG */ switch (gpo) { case 22: /* XBUS: XDIR#/GPO22 */ case 23: /* XBUS: XOE#/GPO23 */ tmp |= 1 << 28; break; case 24: /* RTCSS#/GPO24 */ tmp |= 1 << 29; @@ -685,27 +683,27 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise) tmp |= 1 << 30; break; case 26: /* KBCSS#/GPO26 */ tmp |= 1 << 31; break; } pci_write_long(dev, 0xB0, tmp); } /* GPO {0,8,27,28,30} are always available. */ dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; } /* PM IO base */ base = pci_read_long(dev, 0x40) & 0x0000FFC0; gpo_byte = gpo >> 3; gpo_bit = gpo & 7; tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ if (raise) tmp |= 0x01 << gpo_bit; else tmp &= ~(0x01 << gpo_bit); @@ -787,69 +785,69 @@ static int intel_ich_gpio_set(int gpio, int raise) if ((dev->vendor_id == 0x8086) && (dev->device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id) break; if (intel_ich_gpio_table[i].id) break; } } if (!dev) { - fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1 strapped to zero. From some mobile ICH9 version on, this becomes 6:1. The mask below catches all. */ base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; /* check whether the line is allowed */ if (gpio < 32) allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; else if (gpio < 64) allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; else allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + msg_perr("\nERROR: This Intel LPC Bridge does not allow" " setting GPIO%02d\n", gpio); return -1; } - printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { /* Set line to GPIO */ tmp = INL(base); /* ICH/ICH0 multiplexes 27/28 on the line set. */ if ((gpio == 28) && ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) tmp |= 1 << 27; else tmp |= 1 << gpio; OUTL(tmp, base); /* As soon as we are talking to ICH8 and above, this register decides whether we can set the gpio or not. */ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; } } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x04); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x04); /* Raise GPIO line */ tmp = INL(base + 0x0C); @@ -861,27 +859,27 @@ static int intel_ich_gpio_set(int gpio, int raise) } else if (gpio < 64) { gpio -= 32; /* Set line to GPIO */ tmp = INL(base + 0x30); tmp |= 1 << gpio; OUTL(tmp, base + 0x30); /* As soon as we are talking to ICH8 and above, this register decides whether we can set the gpio or not. */ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; } } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x34); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x34); /* Raise GPIO line */ tmp = INL(base + 0x38); @@ -890,27 +888,27 @@ static int intel_ich_gpio_set(int gpio, int raise) else tmp &= ~(1 << gpio); OUTL(tmp, base + 0x38); } else { gpio -= 64; /* Set line to GPIO */ tmp = INL(base + 0x40); tmp |= 1 << gpio; OUTL(tmp, base + 0x40); tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x44); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x44); /* Raise GPIO line */ tmp = INL(base + 0x48); if (raise) tmp |= 1 << gpio; @@ -1033,31 +1031,31 @@ static int board_kontron_986lcd_m(const char *name) /** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int via_apollo_gpo_set(int gpio, int raise) { struct pci_dev *dev; uint32_t base; uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); if (!dev) { - fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); + msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; } - printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); switch(gpio) { case 0: tmp &= ~0x03; break; case 1: tmp |= 0x04; break; case 2: @@ -1100,27 +1098,27 @@ static int via_apollo_gpo0_lower(const char *name) } /** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ static int board_msi_651ml(const char *name) { struct pci_dev *dev; uint16_t base, temp; dev = pci_dev_find(0x1039, 0x0962); if (!dev) { - fprintf(stderr, "Expected south bridge not found\n"); + msg_perr("Expected south bridge not found\n"); return 1; } /* Registers 68 and 64 seem like bitmaps */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ OUTW(temp, base + 0x68); temp = INW(base + 0x64); temp |= (1 << 0); /* Raise output? */ OUTW(temp, base + 0x64); @@ -1133,59 +1131,59 @@ static int board_msi_651ml(const char *name) * Find the runtime registers of an SMSC Super I/O, after verifying its * chip ID. * * Returns the base port of the runtime register block, or 0 on error. */ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, uint8_t logical_device) { uint16_t rt_port = 0; /* Verify the chip ID. */ OUTB(0x55, sio_port); /* Enable configuration. */ if (sio_read(sio_port, 0x20) != chip_id) { - fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n"); + msg_perr("\nERROR: SMSC Super I/O not found.\n"); goto out; } /* If the runtime block is active, get its address. */ sio_write(sio_port, 0x07, logical_device); if (sio_read(sio_port, 0x30) & 1) { rt_port = (sio_read(sio_port, 0x60) << 8) | sio_read(sio_port, 0x61); } if (rt_port == 0) { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "Super I/O runtime interface not available.\n"); } out: OUTB(0xaa, sio_port); /* Disable configuration. */ return rt_port; } /** * Disable write protection on the Mitac 6513WU. WP# on the FWH is * connected to GP30 on the Super I/O, and TBL# is always high. */ static int board_mitac_6513wu(const char *name) { struct pci_dev *dev; uint16_t rt_port; uint8_t val; dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n"); + msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; } rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); if (rt_port == 0) return -1; /* Configure the GPIO pin. */ val = INB(rt_port + 0x33); /* GP30 config */ val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33); /* Disable write protection. */ @@ -1200,38 +1198,38 @@ static int board_mitac_6513wu(const char *name) * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) { uint16_t id, base; uint8_t tmp; /* find the IT8703F */ w836xx_ext_enter(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); w836xx_ext_leave(0x2E); if (id != 0x8701) { - fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n"); + msg_perr("\nERROR: IT8703F Super I/O not found.\n"); return -1; } /* Get the GP567 IO base */ w836xx_ext_enter(0x2E); sio_write(0x2E, 0x07, 0x0C); base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); w836xx_ext_leave(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO" " Base.\n"); return -1; } /* Raise GP51. */ tmp = INB(base); tmp |= 0x02; OUTB(tmp, base); return 0; } /* @@ -1241,49 +1239,48 @@ static int board_asus_a7v8x(const char *name) static int it8712f_gpio_set(unsigned int line, int raise) { unsigned int port; uint16_t id, base; uint8_t tmp; port = line / 10; port--; line %= 10; /* Check line */ if ((port > 4) || /* also catches unsigned -1 */ ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - fprintf(stderr, - "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); + msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); return -1; } /* find the IT8712F */ enter_conf_mode_ite(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); exit_conf_mode_ite(0x2E); if (id != 0x8712) { - fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n"); + msg_perr("\nERROR: IT8712F Super I/O not found.\n"); return -1; } /* Get the GPIO base */ enter_conf_mode_ite(0x2E); sio_write(0x2E, 0x07, 0x07); base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63); exit_conf_mode_ite(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" " Base.\n"); return -1; } /* set GPIO. */ tmp = INB(base + port); if (raise) tmp |= 1 << line; else tmp &= ~(1 << line); OUTB(tmp, base + port); return 0; @@ -1431,44 +1428,44 @@ static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, if (!pci_dev_find(board->first_vendor, board->first_device)) continue; if (board->second_vendor && !pci_dev_find(board->second_vendor, board->second_device)) continue; if (vendor) return board; if (partmatch) { /* a second entry has a matching part name */ - printf("AMBIGUOUS BOARD NAME: %s\n", part); - printf("At least vendors '%s' and '%s' match.\n", + msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part); + msg_pinfo("At least vendors '%s' and '%s' match.\n", partmatch->lb_vendor, board->lb_vendor); - printf("Please use the full -m vendor:part syntax.\n"); + msg_pinfo("Please use the full -m vendor:part syntax.\n"); return NULL; } partmatch = board; } if (partmatch) return partmatch; if (!partvendor_from_cbtable) { /* Only warn if the mainboard type was not gathered from the * coreboot table. If it was, the coreboot implementor is * expected to fix flashrom, too. */ - printf("\nUnknown vendor:board from -m option: %s:%s\n\n", + msg_pinfo("\nUnknown vendor:board from -m option: %s:%s\n\n", vendor, part); } return NULL; } /** * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ static struct board_pciid_enable *board_match_pci_card_ids(void) { struct board_pciid_enable *board = board_pciid_enables; @@ -1488,27 +1485,27 @@ static struct board_pciid_enable *board_match_pci_card_ids(void) board->second_device, board->second_card_vendor, board->second_card_device)) continue; } else { if (!pci_dev_find(board->second_vendor, board->second_device)) continue; } } if (board->dmi_pattern) { if (!has_dmi_support) { - fprintf(stderr, "WARNING: Can't autodetect %s %s," + msg_perr("WARNING: Can't autodetect %s %s," " DMI info unavailable.\n", board->vendor_name, board->board_name); continue; } else { if (!dmi_match(board->dmi_pattern)) continue; } } return board; } return NULL; @@ -1517,47 +1514,47 @@ static struct board_pciid_enable *board_match_pci_card_ids(void) int board_flash_enable(const char *vendor, const char *part) { struct board_pciid_enable *board = NULL; int ret = 0; if (part) board = board_match_coreboot_name(vendor, part); if (!board) board = board_match_pci_card_ids(); if (board && board->status == NT) { if (!force_boardenable) { - printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" "code has not been tested, and thus will not not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" "\"internal programmer\") for details.\n", board->vendor_name, board->board_name); board = NULL; } else { - printf("NOTE: Running an untested board enable procedure.\n" + msg_pinfo("NOTE: Running an untested board enable procedure.\n" "Please report success/failure to flashrom(a)flashrom.org.\n"); } } if (board) { if (board->max_rom_decode_parallel) max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; if (board->enable != NULL) { - printf("Disabling flash write protection for " + msg_pinfo("Disabling flash write protection for " "board \"%s %s\"... ", board->vendor_name, board->board_name); ret = board->enable(board->vendor_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } } return ret; } diff --git a/cbtable.c b/cbtable.c index c12354c..ce74381 100644 --- a/cbtable.c +++ b/cbtable.c @@ -102,76 +102,76 @@ static int count_lb_records(struct lb_header *head) static struct lb_header *find_lb_table(void *base, unsigned long start, unsigned long end) { unsigned long addr; /* For now be stupid.... */ for (addr = start; addr < end; addr += 16) { struct lb_header *head = (struct lb_header *)(((char *)base) + addr); struct lb_record *recs = (struct lb_record *)(((char *)base) + addr + sizeof(*head)); if (memcmp(head->signature, "LBIO", 4) != 0) continue; - printf_debug("Found candidate at: %08lx-%08lx\n", + msg_pdbg("Found candidate at: %08lx-%08lx\n", addr, addr + head->table_bytes); if (head->header_bytes != sizeof(*head)) { - fprintf(stderr, "Header bytes of %d are incorrect.\n", + msg_pdbg("Header bytes of %d are incorrect.\n", head->header_bytes); continue; } if (count_lb_records(head) != head->table_entries) { - fprintf(stderr, "Bad record count: %d.\n", + msg_pdbg("Bad record count: %d.\n", head->table_entries); continue; } if (compute_checksum((uint8_t *) head, sizeof(*head)) != 0) { - fprintf(stderr, "Bad header checksum.\n"); + msg_pdbg("Bad header checksum.\n"); continue; } if (compute_checksum(recs, head->table_bytes) != head->table_checksum) { - fprintf(stderr, "Bad table checksum: %04x.\n", + msg_pdbg("Bad table checksum: %04x.\n", head->table_checksum); continue; } - printf_debug("Found coreboot table at 0x%08lx.\n", addr); + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; }; return 0; } static void find_mainboard(struct lb_record *ptr, unsigned long addr) { struct lb_mainboard *rec; int max_size; char vendor[256], part[256]; rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); - printf("Vendor ID: %.*s, part ID: %.*s\n", + msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx, max_size - rec->part_number_idx, rec->strings + rec->part_number_idx); snprintf(vendor, 255, "%.*s", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx); snprintf(part, 255, "%.*s", max_size - rec->part_number_idx, rec->strings + rec->part_number_idx); if (lb_part) { - printf("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); + msg_pdbg("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); } else { partvendor_from_cbtable = 1; lb_part = strdup(part); lb_vendor = strdup(vendor); } } static struct lb_record *next_record(struct lb_record *rec) { return (struct lb_record *)(((char *)rec) + rec->size); } static void search_lb_records(struct lb_record *rec, struct lb_record *last, @@ -200,55 +200,55 @@ int coreboot_init(void) struct lb_header *lb_table; struct lb_record *rec, *last; #ifdef __DARWIN__ /* This is a hack. DirectIO fails to map physical address 0x00000000. * Why? */ start = 0x400; #else start = 0x0; #endif table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); if (!table_area) { - msg_perr("Failed getting access to coreboot low tables.\n"); + msg_pdbg("Failed getting access to coreboot low tables.\n"); return -1; } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); if (!table_area) { - msg_perr("Failed getting access to coreboot " + msg_pdbg("Failed getting access to coreboot " "high tables.\n"); return -1; } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } if (!lb_table) { - printf("No coreboot table found.\n"); + msg_pinfo("No coreboot table found.\n"); return -1; } addr = ((char *)lb_table) - ((char *)table_area) + start; - fprintf(stdout, "coreboot table found at 0x%lx.\n", + msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); - printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", + msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); search_lb_records(rec, last, addr + lb_table->header_bytes); return 0; } diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..f447685 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -64,46 +64,46 @@ static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) { uint8_t new, newer; /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ new = pci_read_byte(dev, 0x40); new &= (~0x04); /* No idea why we clear bit 2. */ new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ pci_write_byte(dev, 0x40, new); newer = pci_read_byte(dev, 0x40); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); return -1; } return 0; } static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) { struct pci_dev *sbdev; sbdev = pci_dev_find_vendorclass(vendor, 0x0601); if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0680); if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0000); if (!sbdev) - fprintf(stderr, "No southbridge found for %s!\n", name); + msg_perr("No southbridge found for %s!\n", name); if (sbdev) - printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n", + msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", sbdev->vendor_id, sbdev->device_id, sbdev->bus, sbdev->dev, sbdev->func); return sbdev; } static int enable_flash_sis501(struct pci_dev *dev, const char *name) { uint8_t tmp; int ret = 0; struct pci_dev *sbdev; sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) @@ -152,54 +152,54 @@ static int enable_flash_sis530(struct pci_dev *dev, const char *name) sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) return -1; ret = enable_flash_sis_mapping(sbdev, name); new = pci_read_byte(sbdev, 0x45); new &= (~0x20); new |= 0x4; pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); ret = -1; } return ret; } static int enable_flash_sis540(struct pci_dev *dev, const char *name) { uint8_t new, newer; int ret = 0; struct pci_dev *sbdev; sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) return -1; ret = enable_flash_sis_mapping(sbdev, name); new = pci_read_byte(sbdev, 0x45); new &= (~0x80); new |= 0x40; pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); ret = -1; } return ret; } /* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ static int enable_flash_piix4(struct pci_dev *dev, const char *name) @@ -225,63 +225,63 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) */ if (dev->device_id == 0x122e || dev->device_id == 0x7000 || dev->device_id == 0x1234) new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ else new = old | 0x02c4; if (new == old) return 0; pci_write_word(dev, xbcs, new); if (pci_read_word(dev, xbcs) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); return -1; } return 0; } /* * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) { uint8_t old, new; /* * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but * just treating it as 8 bit wide seems to work fine in practice. */ old = pci_read_byte(dev, bios_cntl); - printf_debug("\nBIOS Lock Enable: %sabled, ", + msg_pdbg("\nBIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); - printf_debug("BIOS Write Enable: %sabled, ", + msg_pdbg("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); - printf_debug("BIOS_CNTL is 0x%x\n", old); + msg_pdbg("BIOS_CNTL is 0x%x\n", old); new = old | 1; if (new == old) return 0; pci_write_byte(dev, bios_cntl, new); if (pci_read_byte(dev, bios_cntl) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); return -1; } return 0; } static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { /* * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ @@ -296,137 +296,137 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) int tmp; int max_decode_fwh_idsel = 0; int max_decode_fwh_decode = 0; int contiguous = 1; if (programmer_param) idsel = strstr(programmer_param, "fwh_idsel="); if (idsel) { idsel += strlen("fwh_idsel="); fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); /* FIXME: Need to undo this on shutdown. */ - printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); + msg_pdbg("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); pci_write_long(dev, 0xd0, fwh_conf); pci_write_word(dev, 0xd4, fwh_conf); /* FIXME: Decode settings are not changed. */ } /* Ignore all legacy ranges below 1 MB. * We currently only support flashing the chip which responds to * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations * have to be adjusted. */ /* FWH_SEL1 */ fwh_conf = pci_read_long(dev, 0xd0); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); if ((tmp == 0) && contiguous) { max_decode_fwh_idsel = (8 - i) * 0x80000; } else { contiguous = 0; } } /* FWH_SEL2 */ fwh_conf = pci_read_word(dev, 0xd4); for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); if ((tmp == 0) && contiguous) { max_decode_fwh_idsel = (8 - i) * 0x100000; } else { contiguous = 0; } } contiguous = 1; /* FWH_DEC_EN1 */ fwh_conf = pci_read_word(dev, 0xd8); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i + 0x8)) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); if ((tmp == 1) && contiguous) { max_decode_fwh_decode = (8 - i) * 0x80000; } else { contiguous = 0; } } for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> i) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); if ((tmp == 1) && contiguous) { max_decode_fwh_decode = (8 - i) * 0x100000; } else { contiguous = 0; } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override * buses_supported anyway. */ buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0xdc); } static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) { uint16_t old, new; int err; if ((err = enable_flash_ich(dev, name, 0xd8)) != 0) return err; old = pci_read_byte(dev, 0xd9); - printf_debug("BIOS Prefetch Enable: %sabled, ", + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); new = old & ~1; if (new != old) pci_write_byte(dev, 0xd9, new); return 0; } #define ICH_STRAP_RSVD 0x00 #define ICH_STRAP_SPI 0x01 #define ICH_STRAP_PCI 0x02 #define ICH_STRAP_LPC 0x03 static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { uint32_t mmio_base; /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; - printf_debug("MMIO base at = 0x%x\n", mmio_base); + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); return 0; } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { @@ -434,40 +434,40 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, uint8_t old, new, bbs, buc; uint16_t spibar_offset, tmp2; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); + msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); gcs = mmio_readl(rcrb + 0x3410); - printf_debug("GCS = 0x%x: ", gcs); - printf_debug("BIOS Interface Lock-Down: %sabled, ", + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); - printf_debug("Top Swap : %s\n", + msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); /* It seems the ICH7 does not support SPI and LPC chips at the same * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { buses_supported = CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } @@ -482,147 +482,147 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; } /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: - printf_debug("0x00: 0x%04x (SPIS)\n", + msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0)); - printf_debug("0x02: 0x%04x (SPIC)\n", + msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2)); - printf_debug("0x04: 0x%08x (SPIA)\n", + msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); - printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(spibar + offs), i); - printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } - printf_debug("0x50: 0x%08x (BBAR)\n", + msg_pdbg("0x50: 0x%08x (BBAR)\n", mmio_readl(spibar + 0x50)); - printf_debug("0x54: 0x%04x (PREOP)\n", + msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); - printf_debug("0x56: 0x%04x (OPTYPE)\n", + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56)); - printf_debug("0x58: 0x%08x (OPMENU)\n", + msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5c: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); - printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(spibar + offs), i); } - printf_debug("\n"); + msg_pdbg("\n"); if (mmio_readw(spibar) & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(spibar + 4); - printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); - printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - printf_debug("FDV %i, ", (tmp2 >> 14) & 1); - printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); - printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); - printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); - printf_debug("AEL %i, ", (tmp2 >> 2) & 1); - printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); - printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); tmp = mmio_readl(spibar + 0x50); - printf_debug("0x50: 0x%08x (FRAP)\n", tmp); - printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); - printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); - printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); - printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); + msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); + msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); + msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - printf_debug("0x54: 0x%08x (FREG0)\n", + msg_pdbg("0x54: 0x%08x (FREG0)\n", mmio_readl(spibar + 0x54)); - printf_debug("0x58: 0x%08x (FREG1)\n", + msg_pdbg("0x58: 0x%08x (FREG1)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5C: 0x%08x (FREG2)\n", + msg_pdbg("0x5C: 0x%08x (FREG2)\n", mmio_readl(spibar + 0x5C)); - printf_debug("0x60: 0x%08x (FREG3)\n", + msg_pdbg("0x60: 0x%08x (FREG3)\n", mmio_readl(spibar + 0x60)); - printf_debug("0x64: 0x%08x (FREG4)\n", + msg_pdbg("0x64: 0x%08x (FREG4)\n", mmio_readl(spibar + 0x64)); - printf_debug("0x74: 0x%08x (PR0)\n", + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); - printf_debug("0x78: 0x%08x (PR1)\n", + msg_pdbg("0x78: 0x%08x (PR1)\n", mmio_readl(spibar + 0x78)); - printf_debug("0x7C: 0x%08x (PR2)\n", + msg_pdbg("0x7C: 0x%08x (PR2)\n", mmio_readl(spibar + 0x7C)); - printf_debug("0x80: 0x%08x (PR3)\n", + msg_pdbg("0x80: 0x%08x (PR3)\n", mmio_readl(spibar + 0x80)); - printf_debug("0x84: 0x%08x (PR4)\n", + msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", mmio_readl(spibar + 0x90)); - printf_debug("0x94: 0x%04x (PREOP)\n", + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); - printf_debug("0x96: 0x%04x (OPTYPE)\n", + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x96)); - printf_debug("0x98: 0x%08x (OPMENU)\n", + msg_pdbg("0x98: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x98)); - printf_debug("0x9C: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); - printf_debug("0xA0: 0x%08x (BBAR)\n", + msg_pdbg("0xA0: 0x%08x (BBAR)\n", mmio_readl(spibar + 0xA0)); - printf_debug("0xB0: 0x%08x (FDOC)\n", + msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; default: /* Nothing */ break; } old = pci_read_byte(dev, 0xdc); - printf_debug("SPI Read Configuration: "); + msg_pdbg("SPI Read Configuration: "); new = (old >> 2) & 0x3; switch (new) { case 0: case 1: case 2: - printf_debug("prefetching %sabled, caching %sabled, ", + msg_pdbg("prefetching %sabled, caching %sabled, ", (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); break; default: - printf_debug("invalid prefetching/caching settings, "); + msg_pdbg("invalid prefetching/caching settings, "); break; } return ret; } static int enable_flash_ich7(struct pci_dev *dev, const char *name) { return enable_flash_ich_dc_spi(dev, name, 7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { @@ -642,27 +642,27 @@ static int enable_flash_ich10(struct pci_dev *dev, const char *name) static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */ pci_write_byte(dev, 0x41, 0x7f); /* ROM write enable */ val = pci_read_byte(dev, 0x40); val |= 0x10; pci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - printf("\nWARNING: Failed to enable flash write on \"%s\"\n", + msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } if (dev->device_id == 0x3227) { /* VT8237R */ /* All memory cycles, not just ROM ones, go to LPC. */ val = pci_read_byte(dev, 0x59); val &= ~0x80; pci_write_byte(dev, 0x59, val); } return 0; } @@ -759,189 +759,189 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) #undef MSR_NORF_CTL return 0; } static int enable_flash_sc1100(struct pci_dev *dev, const char *name) { uint8_t new; pci_write_byte(dev, 0x52, 0xee); new = pci_read_byte(dev, 0x52); if (new != 0xee) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); return -1; } return 0; } /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { uint8_t old, new; /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, 0x43); new = old | 0xC0; if (new != old) { pci_write_byte(dev, 0x43, new); if (pci_read_byte(dev, 0x43) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); } } /* Enable 'ROM write' bit. */ old = pci_read_byte(dev, 0x40); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x40, new); if (pci_read_byte(dev, 0x40) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); return -1; } return 0; } static int enable_flash_sb600(struct pci_dev *dev, const char *name) { uint32_t tmp, prot; uint8_t reg; struct pci_dev *smbus_dev; int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { prot = pci_read_long(dev, reg); /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - printf_debug("SB600 %s%sprotected from %u to %u\n", + msg_pdbg("SB600 %s%sprotected from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); prot &= 0xfffffffc; pci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); if (prot & 0x3) - printf("SB600 %s%sunprotect failed from %u to %u\n", + msg_pinfo("SB600 %s%sunprotect failed from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - printf_debug("SPI base address is at 0x%x\n", tmp); + msg_pdbg("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) has_spi = 0; if (has_spi) { /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); /* The low bits of the SPI base address are used as offset into * the mapped page. */ sb600_spibar += tmp & 0xfff; tmp = pci_read_long(dev, 0xa0); - printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); tmp = pci_read_byte(dev, 0xbb); - printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", tmp & 0x1, (tmp & 0x20) >> 5); tmp = mmio_readl(sb600_spibar); - printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); } /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (has_spi && !smbus_dev) { - fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; } if (has_spi) { /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); reg &= 0xC0; - printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); if (reg != 0x00) has_spi = 0; /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ reg = pci_read_byte(smbus_dev, 0x83); reg &= 0xC0; - printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); /* SPI_HOLD is not used on all boards, filter it out. */ if ((reg & 0x80) != 0x00) has_spi = 0; /* GPIO47/SPI_CLK status */ reg = pci_read_byte(smbus_dev, 0xA7); reg &= 0x40; - printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); if (reg != 0x00) has_spi = 0; } buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; if (has_spi) { buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); reg = INB(0xcd7); reg &= 0x0e; - printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); + msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); if (reg & 0x02) { switch ((reg & 0x0c) >> 2) { case 0x00: - printf_debug(": LPC"); + msg_pdbg(": LPC"); break; case 0x01: - printf_debug(": PCI"); + msg_pdbg(": PCI"); break; case 0x02: - printf_debug(": FWH"); + msg_pdbg(": FWH"); break; case 0x03: - printf_debug(": SPI"); + msg_pdbg(": SPI"); break; } } - printf_debug("\n"); + msg_pdbg("\n"); /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have * to trade off. We only access LPC ROM if we boot via LPC ROM. And * only SPI ROM if we boot via SPI ROM. If you want to access SPI on * boards with LPC straps, you have to use the code below. */ /* OUTB(0x8f, 0xcd6); OUTB(0x0e, 0xcd7); */ @@ -960,55 +960,55 @@ static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) return 0; } static int enable_flash_ck804(struct pci_dev *dev, const char *name) { uint8_t old, new; old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { pci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); } } old = pci_read_byte(dev, 0x6d); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } return 0; } /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ static int enable_flash_sb400(struct pci_dev *dev, const char *name) { uint8_t tmp; struct pci_dev *smbusdev; /* Look for the SMBus device. */ smbusdev = pci_dev_find(0x1002, 0x4372); if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); + msg_perr("ERROR: SMBus device not found. Aborting.\n"); exit(1); } /* Enable some SMBus stuff. */ tmp = pci_read_byte(smbusdev, 0x79); tmp |= 0x01; pci_write_byte(smbusdev, 0x79, tmp); /* Change southbridge. */ tmp = pci_read_byte(dev, 0x48); tmp |= 0x21; pci_write_byte(dev, 0x48, tmp); @@ -1037,27 +1037,27 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) val |= 0xff; /* 1M */ pci_write_byte(dev, 0x8c, val); wordval = pci_read_word(dev, 0x90); wordval |= 0x7fff; /* 16M */ pci_write_word(dev, 0x90, wordval); old = pci_read_byte(dev, 0x6d); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } return 0; } /* This is a shot in the dark. Even if the code is totally bogus for some * chipsets, users will at least start to send in reports. */ static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name) { int ret = 0; uint8_t val; @@ -1267,27 +1267,27 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0] * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0] */ if (bootcs_found) { if (parx & (1 << 25)) { parx &= (1 << 14) - 1; /* Mask [13:0] */ flashbase = parx << 16; } else { parx &= (1 << 18) - 1; /* Mask [17:0] */ flashbase = parx << 12; } } else { - printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); } /* 4. Clean up */ physunmap(mmcr, getpagesize()); return 0; } /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, @@ -1426,29 +1426,29 @@ int chipset_flash_enable(void) struct pci_dev *dev = 0; int ret = -2; /* Nothing! */ int i; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { dev = pci_dev_find(chipset_enables[i].vendor_id, chipset_enables[i].device_id); if (dev) break; } if (dev) { - printf("Found chipset \"%s %s\", enabling flash write... ", + msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } - printf("This chipset supports the following protocols: %s.\n", + msg_pinfo("This chipset supports the following protocols: %s.\n", flashbuses_to_text(buses_supported)); return ret; } diff --git a/dmi.c b/dmi.c index d9f307f..a907a18 100644 --- a/dmi.c +++ b/dmi.c @@ -43,99 +43,99 @@ char *dmistrings[ARRAY_SIZE(dmidecode_names)]; #define DMI_MAX_ANSWER_LEN 4096 static char *get_dmi_string(const char *string_name) { FILE *dmidecode_pipe; char *result; char answerbuf[DMI_MAX_ANSWER_LEN]; char commandline[DMI_COMMAND_LEN_MAX + 40]; snprintf(commandline, sizeof(commandline), "%s -s %s", dmidecode_command, string_name); dmidecode_pipe = popen(commandline, "r"); if (!dmidecode_pipe) { - printf_debug("DMI pipe open error\n"); + msg_pdbg("DMI pipe open error\n"); return NULL; } if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { if(ferror(dmidecode_pipe)) { - printf_debug("DMI pipe read error\n"); + msg_pdbg("DMI pipe read error\n"); pclose(dmidecode_pipe); return NULL; } else { answerbuf[0] = 0; /* Hit EOF */ } } /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent deadlock on pclose. */ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - printf_debug("DMI pipe close error\n"); + msg_pdbg("DMI pipe close error\n"); return NULL; } /* Chomp trailing newline. */ if (answerbuf[0] != 0 && answerbuf[strlen(answerbuf) - 1] == '\n') answerbuf[strlen(answerbuf) - 1] = 0; - printf_debug("DMI string %s: \"%s\"\n", string_name, answerbuf); + msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf); result = strdup(answerbuf); if (!result) puts("WARNING: Out of memory - DMI support fails"); return result; } void dmi_init(void) { int i; char *chassis_type; has_dmi_support = 1; for (i = 0; i < ARRAY_SIZE(dmidecode_names); i++) { dmistrings[i] = get_dmi_string(dmidecode_names[i]); if (!dmistrings[i]) { has_dmi_support = 0; return; } } chassis_type = get_dmi_string("chassis-type"); if (chassis_type && !strcmp(chassis_type, "Notebook")) { - printf_debug("Laptop detected via DMI\n"); + msg_pdbg("Laptop detected via DMI\n"); is_laptop = 1; } free(chassis_type); } /** * Does an substring/prefix/postfix/whole-string match. * * The pattern is matched as-is. The only metacharacters supported are '^' * at the beginning and '$' at the end. So you can look for "^prefix", * "suffix$", "substring" or "^complete string$". * * @param value The string to check. * @param pattern The pattern. * @return Nonzero if pattern matches. */ static int dmi_compare(const char *value, const char *pattern) { int anchored = 0; int patternlen; - printf_debug("matching %s against %s\n", value, pattern); + msg_pdbg("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ if (pattern[0] == 0) return 1; if (pattern[0] == '^') { anchored = 1; pattern++; } patternlen = strlen(pattern); if (pattern[patternlen - 1] == '$') { int valuelen = strlen(value); patternlen--; diff --git a/hwaccess.c b/hwaccess.c index 10e67bd..0e889bb 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -31,27 +31,27 @@ int io_fd; #endif void get_io_perms(void) { #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #elif __DJGPP__ if (0) { #else if (iopl(3) != 0) { #endif - fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" + msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); exit(1); } } void release_io_perms(void) { #if defined(__FreeBSD__) || defined(__DragonFly__) close(io_fd); #endif } #ifdef __DJGPP__ diff --git a/ichspi.c b/ichspi.c index 35b9dbd..587fbcb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -28,37 +28,26 @@ * ST M25P80 * ST M25P16 * ST M25P32 already tested * ST M25P64 * AT 25DF321 already tested * */ #include <string.h> #include "flash.h" #include "chipdrivers.h" #include "spi.h" -/* Change this to #define if you want lowlevel debugging of commands - * sent to the ICH/VIA SPI controller. - */ -#undef COMM_DEBUG - -#ifdef COMM_DEBUG -#define msg_comm_debug printf_debug -#else -#define msg_comm_debug(...) do {} while (0) -#endif - /* ICH9 controller register definition */ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 #define SSFC_ACS 0x00000400 @@ -227,46 +216,46 @@ static int find_preop(OPCODES *op, uint8_t preop) } return -1; } /* Create a struct OPCODES based on what we find in the locked down chipset. */ static int generate_opcodes(OPCODES * op) { int a; uint16_t preop, optype; uint32_t opmenu[2]; if (op == NULL) { - printf_debug("\n%s: null OPCODES pointer!\n", __func__); + msg_pdbg("\n%s: null OPCODES pointer!\n", __func__); return -1; } switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: preop = REGREAD16(ICH9_REG_PREOP); optype = REGREAD16(ICH9_REG_OPTYPE); opmenu[0] = REGREAD32(ICH9_REG_OPMENU); opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); return -1; } op->preop[0] = (uint8_t) preop; op->preop[1] = (uint8_t) (preop >> 8); for (a = 0; a < 8; a++) { op->opcode[a].spi_type = (uint8_t) (optype & 0x3); optype >>= 2; } for (a = 0; a < 4; a++) { op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); @@ -305,79 +294,79 @@ int program_opcodes(OPCODES * op) /* Program Allowable Opcodes 0 - 3 */ opmenu[0] = 0; for (a = 0; a < 4; a++) { opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); } /*Program Allowable Opcodes 4 - 7 */ opmenu[1] = 0; for (a = 4; a < 8; a++) { opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } - printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); + msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: REGWRITE16(ICH7_REG_PREOP, preop); REGWRITE16(ICH7_REG_OPTYPE, optype); REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); break; case SPI_CONTROLLER_ICH9: REGWRITE16(ICH9_REG_PREOP, preop); REGWRITE16(ICH9_REG_OPTYPE, optype); REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); return -1; } return 0; } /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * * It should be called before ICH sends any spi command. */ int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; if (curopcodes) return 0; if (ichspi_lock) { - printf_debug("Generating OPCODES... "); + msg_pdbg("Generating OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { - printf_debug("Programming OPCODES... "); + msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); } if (rc) { curopcodes = NULL; - printf_debug("failed\n"); + msg_pdbg("failed\n"); return 1; } else { curopcodes = curopcodes_done; - printf_debug("done\n"); + msg_pdbg("done\n"); return 0; } } static int ich7_run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data, int maxdata) { int write_cmd = 0; int timeout; uint32_t temp32 = 0; uint16_t temp16; uint32_t a; uint64_t opmenu; @@ -429,27 +418,27 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, } /* Select opcode */ opmenu = REGREAD32(ICH7_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; for (opcode_index = 0; opcode_index < 8; opcode_index++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; /* Handle Atomic */ switch (op.atomic) { case 2: /* Select second preop. */ temp16 |= SPIC_SPOP; /* And fall through. */ case 1: /* Atomic command (preop+op) */ temp16 |= SPIC_ACS; @@ -458,31 +447,31 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* Start */ temp16 |= SPIC_SCGO; /* write it */ REGWRITE16(ICH7_REG_SPIC, temp16); /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_pdbg("timeout\n"); } if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } if ((!write_cmd) && (datalength != 0)) { for (a = 0; a < datalength; a++) { if ((a % 4) == 0) { temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); } data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >> ((a % 4) * 8); } @@ -547,27 +536,27 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } /* Select opcode */ opmenu = REGREAD32(ICH9_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; for (opcode_index = 0; opcode_index < 8; opcode_index++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); /* Handle Atomic */ switch (op.atomic) { case 2: /* Select second preop. */ temp32 |= SSFC_SPOP; /* And fall through. */ case 1: /* Atomic command (preop+op) */ temp32 |= SSFC_ACS; @@ -576,100 +565,100 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Start */ temp32 |= SSFC_SCGO; /* write it */ REGWRITE32(ICH9_REG_SSFS, temp32); /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_pdbg("timeout\n"); } if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } if ((!write_cmd) && (datalength != 0)) { for (a = 0; a < datalength; a++) { if ((a % 4) == 0) { temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); } data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >> ((a % 4) * 8); } } return 0; } static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { switch (spi_controller) { case SPI_CONTROLLER_VIA: if (datalength > 16) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich9_run_opcode(op, offset, datalength, data); default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); } /* If we ever get here, something really weird happened */ return -1; } static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { int page_size = flash->page_size; uint32_t remaining = page_size; int towrite; - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", + msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", offset, page_size, bytes); for (; remaining > 0; remaining -= towrite) { towrite = min(remaining, maxdata); if (spi_nbyte_program(offset + (page_size - remaining), &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); + msg_pdbg("Error writing"); return 1; } } return 0; } int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; @@ -677,169 +666,169 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) return spi_read_chunked(flash, buf, start, len, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { int i, j, rc = 0; int total_size = flash->total_size * 1024; int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; spi_disable_blockprotect(); /* Erase first */ - printf("Erasing flash before programming... "); + msg_pinfo("Erasing flash before programming... "); if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); + msg_perr("ERASE FAILED!\n"); return -1; } - printf("done.\n"); + msg_pinfo("done.\n"); - printf("Programming page: \n"); + msg_pinfo("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; for (j = 0; j < erase_size / page_size; j++) { ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)), (i * erase_size) + (j * page_size), maxdata); } } - printf("\n"); + msg_pinfo("\n"); return rc; } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; int opcode_index = -1; const unsigned char cmd = *writearr; OPCODE *opcode; uint32_t addr = 0; uint8_t *data; int count; /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { /* FIXME: Reprogram opcodes if possible. Autodetect type of * opcode by checking readcnt/writecnt. */ - printf_debug("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); return SPI_INVALID_OPCODE; } opcode = &(curopcodes->opcode[opcode_index]); /* The following valid writecnt/readcnt combinations exist: * writecnt = 4, readcnt >= 0 * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && (writecnt != 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && (writecnt != 1)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && (writecnt < 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && (readcnt)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, readcnt); return SPI_INVALID_LENGTH; } /* if opcode-type requires an address */ if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); } /* translate read/write array/count */ if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { data = (uint8_t *) (writearr + 1); count = writecnt - 1; } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { data = (uint8_t *) (writearr + 4); count = writecnt - 4; } else { data = (uint8_t *) readarr; count = readcnt; } result = run_opcode(*opcode, addr, count, data); if (result) { - printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); } return result; } int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; int oppos, preoppos; for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { /* Next command is valid. */ preoppos = find_preop(curopcodes, cmds->writearr[0]); oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); if ((oppos == -1) && (preoppos != -1)) { /* Current command is listed as preopcode in * ICH struct OPCODES, but next command is not * listed as opcode in that struct. * Check for command sanity, then * try to reprogram the ICH opcode list. */ if (find_preop(curopcodes, (cmds + 1)->writearr[0]) != -1) { - fprintf(stderr, "%s: Two subsequent " + msg_pdbg("%s: Two subsequent " "preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", __func__, cmds->writearr[0], (cmds + 1)->writearr[0]); continue; } /* If the chipset is locked down, we'll fail * during execution of the next command anyway. * No need to bother with fixups. */ if (!ichspi_lock) { - printf_debug("%s: FIXME: Add on-the-fly" + msg_pdbg("%s: FIXME: Add on-the-fly" " reprogramming of the " "chipset opcode list.\n", __func__); /* FIXME: Reprogram opcode menu. * Find a less-useful opcode, replace it * with the wanted opcode, detect optype * and reprogram the opcode menu. * Update oppos so the next if-statement * can do something useful. */ //curopcodes.opcode[lessusefulindex] = (cmds + 1)->writearr[0]); //update_optypes(curopcodes); //program_opcodes(curopcodes); diff --git a/internal.c b/internal.c index 39edd10..672b41f 100644 --- a/internal.c +++ b/internal.c @@ -146,40 +146,40 @@ int internal_init(void) pci_scan_bus(pacc); /* We want to get the list of devices */ /* We look at the lbtable first to see if we need a * mainboard specific flash enable sequence. */ coreboot_init(); dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); /* Warn if a laptop is detected. */ if (is_laptop) - printf("========================================================================\n" + msg_pinfo("========================================================================\n" "WARNING! You seem to be running flashrom on a laptop.\n" "Laptops, notebooks and netbooks are difficult to support and we recommend\n" "to use the vendor flashing utility. The embedded controller (EC) in these\n" "machines often interacts badly with flashing.\n" "See http://www.flashrom.org/Laptops for details.\n" "========================================================================\n"); /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ ret = chipset_flash_enable(); if (ret == -2) { - printf("WARNING: No chipset found. Flash detection " + msg_pinfo("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); } /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); board_flash_enable(lb_vendor, lb_part); /* Even if chipset init returns an error code, we don't want to abort. * The error code might have been a warning only. * Besides that, we don't check the board enable return code either. */ return 0; diff --git a/pcidev.c b/pcidev.c index 818819a..add1fce 100644 --- a/pcidev.c +++ b/pcidev.c @@ -35,48 +35,48 @@ uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, /* FIXME: 64 bit memory BARs need a 64 bit addr. */ uint32_t addr; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); if (addr & 0x1) { /* Mask off IO space indicator and reserved bit. */ msg_pdbg("\n"); addr &= ~0x3; } else { msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); /* Mask off Mem space indicator, 32/64bit type indicator * and Prefetchable indicator. */ addr &= ~0xf; } if (devs[i].status == NT) { - printf("===\nThis PCI device is UNTESTED. Please " + msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " "for you. Thank you for your help!\n===\n"); } return addr; } return 0; } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf) @@ -85,54 +85,54 @@ uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, char *msg = NULL; int found = 0; uint32_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); /* Filter by vendor and also bb:dd.f (if supplied by the user). */ filter.vendor = vendor_id; if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { - fprintf(stderr, "Error: %s\n", msg); + msg_perr("Error: %s\n", msg); exit(1); } } for (dev = pacc->devices; dev; dev = dev->next) { if (pci_filter_match(&filter, dev)) { if ((addr = pcidev_validate(dev, bar, devs)) != 0) { curaddr = addr; pcidev_dev = dev; found++; } } } /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { - fprintf(stderr, "Error: No supported PCI device found.\n"); + msg_perr("Error: No supported PCI device found.\n"); exit(1); } else if (found > 1) { - fprintf(stderr, "Error: Multiple supported PCI devices found. " + msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1); } return curaddr; } void print_supported_pcidevs(struct pcidev_status *devs) { int i; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, + msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, (devs[i].status == NT) ? " (untested)" : ""); } } diff --git a/physmap.c b/physmap.c index 38a395c..efd641c 100644 --- a/physmap.c +++ b/physmap.c @@ -160,76 +160,76 @@ void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) perror("Critical error: open(" MEM_DEV ")"); exit(2); } } virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, fd_mem_cached, (off_t)phys_addr); return MAP_FAILED == virt_addr ? NULL : virt_addr; } void physunmap(void *virt_addr, size_t len) { if (len == 0) { - printf_debug("Not unmapping zero size at %p\n", virt_addr); + msg_pdbg("Not unmapping zero size at %p\n", virt_addr); return; } munmap(virt_addr, len); } #endif #define PHYSMAP_NOFAIL 0 #define PHYSMAP_MAYFAIL 1 #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; if (len == 0) { - printf_debug("Not mapping %s, zero size at 0x%08lx.\n", + msg_pdbg("Not mapping %s, zero size at 0x%08lx.\n", descr, phys_addr); return NULL; } if ((getpagesize() - 1) & len) { - fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", + msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", descr, phys_addr, (unsigned long)len); } if ((getpagesize() - 1) & phys_addr) { - fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", + msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", descr, (unsigned long)len, phys_addr); } if (readonly) { virt_addr = sys_physmap_ro_cached(phys_addr, len); } else { virt_addr = sys_physmap_rw_uncached(phys_addr, len); } if (NULL == virt_addr) { if (NULL == descr) descr = "memory"; - fprintf(stderr, "Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); perror(MEM_DEV " mmap failed"); if (EINVAL == errno) { - fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); - fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); - fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n"); - fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); - fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); + msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); + msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); + msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n"); + msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); + msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } if (!mayfail) exit(3); } return virt_addr; } void *physmap(const char *descr, unsigned long phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); } @@ -295,45 +295,45 @@ int wrmsr(int addr, msr_t msr) if (errno == EIO) return -1; return 0; } int setup_cpu_msr(int cpu) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } fd_msr = open(msrfilename, O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); + msg_pinfo("Did you run 'modprobe msr'?\n"); return -1; } return 0; } void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } close(fd_msr); /* Clear MSR file descriptor */ fd_msr = -1; } #else #if defined(__FreeBSD__) || defined(__DragonFly__) #include <sys/ioctl.h> typedef struct { @@ -378,45 +378,45 @@ int wrmsr(int addr, msr_t msr) exit(1); } return 0; } int setup_cpu_msr(int cpu) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu%d", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } fd_msr = open(msrfilename, O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu0"); - printf("Did you install ports/sysutils/devcpu?\n"); + msg_pinfo("Did you install ports/sysutils/devcpu?\n"); return -1; } return 0; } void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } close(fd_msr); /* Clear MSR file descriptor */ fd_msr = -1; } #else #ifdef __DARWIN__ int setup_cpu_msr(int cpu) @@ -434,25 +434,25 @@ msr_t rdmsr(int addr) { msr_t ret = { 0xffffffff, 0xffffffff }; return ret; } int wrmsr(int addr, msr_t msr) { return -1; } int setup_cpu_msr(int cpu) { - printf("No MSR support for your OS yet.\n"); + msg_pinfo("No MSR support for your OS yet.\n"); return -1; } void cleanup_cpu_msr(void) { // Nothing, yet. } #endif #endif #endif diff --git a/spi.c b/spi.c index 8bbbe6e..9bb4687 100644 --- a/spi.c +++ b/spi.c @@ -120,39 +120,39 @@ const struct spi_programmer spi_programmer[] = { .write_256 = spi_chip_write_1, }, #endif {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; const int spi_programmer_count = ARRAY_SIZE(spi_programmer); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (!spi_programmer[spi_controller].command) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct spi_command cmd[] = { { .writecnt = writecnt, @@ -172,41 +172,41 @@ int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, int default_spi_send_multicommand(struct spi_command *cmds) { int result = 0; for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { result = spi_send_command(cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); } return result; } int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - fprintf(stderr, "%s called, but SPI read is unsupported on this" + msg_perr("%s called, but SPI read is unsupported on this" " hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].read(flash, buf, start, len); } /* * Program chip using page (256 bytes) programming. * Some SPI masters can't do this, they use single byte programming instead. */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - fprintf(stderr, "%s called, but SPI page write is unsupported " + msg_perr("%s called, but SPI page write is unsupported " " on this hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].write_256(flash, buf); } uint32_t spi_get_valid_read_addr(void) { /* Need to return BBAR for ICH chipsets. */ return 0; } -- 1.6.6

3 7

[commit] r997 - trunk
by repository service 07 May '10

07 May '10

Author: snelson Date: Fri May 7 22:09:04 2010 New Revision: 997 URL: http://flashrom.org/trac/coreboot/changeset/997 Log: convert programmer print messages to msg_p* convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/cbtable.c trunk/chipset_enable.c trunk/dmi.c trunk/flashrom.c trunk/hwaccess.c trunk/ichspi.c trunk/pcidev.c trunk/physmap.c trunk/spi.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/board_enable.c Fri May 7 22:09:04 2010 (r997) @@ -87,7 +87,7 @@ ret = 0; break; default: - printf_debug("Unhandled Super I/O type!\n"); + msg_pdbg("Unhandled Super I/O type!\n"); ret = -1; break; } @@ -108,7 +108,7 @@ /* Is this the W83627HF? */ if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; @@ -148,7 +148,7 @@ /* Is this the W83627THF? */ if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; @@ -253,20 +253,20 @@ uint8_t id, val; if (gpio_bank > 4) { - fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC87360: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); if (id != 0xE1) { - fprintf(stderr, "PC87360: unexpected ID %02x\n", id); + msg_perr("PC87360: unexpected ID %02x\n", id); return -1; } sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */ baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { - fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", + msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); return -1; } @@ -300,7 +300,7 @@ case 0x3337: /* VT8237A */ break; default: - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + msg_perr("\nERROR: VT823x ISA bridge not found.\n"); return -1; } @@ -319,7 +319,7 @@ val |= 0x01; pci_write_byte(dev, 0xE4, val); } else { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); return -1; } @@ -411,7 +411,7 @@ } if (i == ASUSP5A_LOOP) { - printf("%s: Unable to contact device.\n", name); + msg_perr("%s: Unable to contact device.\n", name); return -1; } @@ -427,7 +427,7 @@ } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to read device.\n", name); + msg_perr("%s: failed to read device.\n", name); return -1; } @@ -454,7 +454,7 @@ } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to write to device.\n", name); + msg_perr("%s: failed to write to device.\n", name); return -1; } @@ -492,8 +492,7 @@ dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { - fprintf(stderr, - "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; } @@ -513,7 +512,7 @@ uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { - fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } @@ -531,8 +530,7 @@ case 0x0264: /* MCP51 */ break; default: - fprintf(stderr, - "\nERROR: no NVIDIA LPC/SMBus controller found.\n"); + msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; } break; @@ -661,20 +659,20 @@ dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; } /* sanity check */ if (gpo > 30) { - fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); return -1; } /* these are dual function pins which are most likely in use already */ if (((gpo >= 1) && (gpo <= 7)) || ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); return -1; } @@ -703,7 +701,7 @@ dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; } @@ -805,7 +803,7 @@ } if (!dev) { - fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } @@ -823,12 +821,12 @@ allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + msg_perr("\nERROR: This Intel LPC Bridge does not allow" " setting GPIO%02d\n", gpio); return -1; } - printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { @@ -847,7 +845,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; @@ -879,7 +877,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; @@ -908,7 +906,7 @@ tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } @@ -1051,11 +1049,11 @@ /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); if (!dev) { - fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); + msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; } - printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); /* select GPO function on multiplexed pins */ @@ -1118,7 +1116,7 @@ dev = pci_dev_find(0x1039, 0x0962); if (!dev) { - fprintf(stderr, "Expected south bridge not found\n"); + msg_perr("Expected south bridge not found\n"); return 1; } @@ -1151,7 +1149,7 @@ /* Verify the chip ID. */ OUTB(0x55, sio_port); /* Enable configuration. */ if (sio_read(sio_port, 0x20) != chip_id) { - fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n"); + msg_perr("\nERROR: SMSC Super I/O not found.\n"); goto out; } @@ -1163,7 +1161,7 @@ } if (rt_port == 0) { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "Super I/O runtime interface not available.\n"); } out: @@ -1183,7 +1181,7 @@ dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n"); + msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; } @@ -1218,7 +1216,7 @@ w836xx_ext_leave(0x2E); if (id != 0x8701) { - fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n"); + msg_perr("\nERROR: IT8703F Super I/O not found.\n"); return -1; } @@ -1229,7 +1227,7 @@ w836xx_ext_leave(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO" " Base.\n"); return -1; } @@ -1259,8 +1257,7 @@ /* Check line */ if ((port > 4) || /* also catches unsigned -1 */ ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - fprintf(stderr, - "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); + msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); return -1; } @@ -1270,7 +1267,7 @@ exit_conf_mode_ite(0x2E); if (id != 0x8712) { - fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n"); + msg_perr("\nERROR: IT8712F Super I/O not found.\n"); return -1; } @@ -1281,7 +1278,7 @@ exit_conf_mode_ite(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" " Base.\n"); return -1; } @@ -1450,10 +1447,10 @@ if (partmatch) { /* a second entry has a matching part name */ - printf("AMBIGUOUS BOARD NAME: %s\n", part); - printf("At least vendors '%s' and '%s' match.\n", + msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part); + msg_pinfo("At least vendors '%s' and '%s' match.\n", partmatch->lb_vendor, board->lb_vendor); - printf("Please use the full -m vendor:part syntax.\n"); + msg_perr("Please use the full -m vendor:part syntax.\n"); return NULL; } partmatch = board; @@ -1467,7 +1464,7 @@ * coreboot table. If it was, the coreboot implementor is * expected to fix flashrom, too. */ - printf("\nUnknown vendor:board from -m option: %s:%s\n\n", + msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n", vendor, part); } return NULL; @@ -1507,7 +1504,7 @@ if (board->dmi_pattern) { if (!has_dmi_support) { - fprintf(stderr, "WARNING: Can't autodetect %s %s," + msg_perr("WARNING: Can't autodetect %s %s," " DMI info unavailable.\n", board->vendor_name, board->board_name); continue; @@ -1536,7 +1533,7 @@ if (board && board->status == NT) { if (!force_boardenable) { - printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" "code has not been tested, and thus will not not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" @@ -1545,7 +1542,7 @@ board->vendor_name, board->board_name); board = NULL; } else { - printf("NOTE: Running an untested board enable procedure.\n" + msg_pinfo("NOTE: Running an untested board enable procedure.\n" "Please report success/failure to flashrom(a)flashrom.org.\n"); } } @@ -1556,15 +1553,15 @@ board->max_rom_decode_parallel * 1024; if (board->enable != NULL) { - printf("Disabling flash write protection for " + msg_pinfo("Disabling flash write protection for " "board \"%s %s\"... ", board->vendor_name, board->board_name); ret = board->enable(board->vendor_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } } Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/cbtable.c Fri May 7 22:09:04 2010 (r997) @@ -112,29 +112,29 @@ (struct lb_record *)(((char *)base) + addr + sizeof(*head)); if (memcmp(head->signature, "LBIO", 4) != 0) continue; - printf_debug("Found candidate at: %08lx-%08lx\n", + msg_pdbg("Found candidate at: %08lx-%08lx\n", addr, addr + head->table_bytes); if (head->header_bytes != sizeof(*head)) { - fprintf(stderr, "Header bytes of %d are incorrect.\n", + msg_perr("Header bytes of %d are incorrect.\n", head->header_bytes); continue; } if (count_lb_records(head) != head->table_entries) { - fprintf(stderr, "Bad record count: %d.\n", + msg_perr("Bad record count: %d.\n", head->table_entries); continue; } if (compute_checksum((uint8_t *) head, sizeof(*head)) != 0) { - fprintf(stderr, "Bad header checksum.\n"); + msg_perr("Bad header checksum.\n"); continue; } if (compute_checksum(recs, head->table_bytes) != head->table_checksum) { - fprintf(stderr, "Bad table checksum: %04x.\n", + msg_perr("Bad table checksum: %04x.\n", head->table_checksum); continue; } - printf_debug("Found coreboot table at 0x%08lx.\n", addr); + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; }; @@ -150,7 +150,7 @@ rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); - printf("Vendor ID: %.*s, part ID: %.*s\n", + msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx, max_size - rec->part_number_idx, @@ -161,7 +161,7 @@ rec->strings + rec->part_number_idx); if (lb_part) { - printf("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); + msg_pdbg("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); } else { partvendor_from_cbtable = 1; lb_part = strdup(part); @@ -235,16 +235,16 @@ } if (!lb_table) { - printf("No coreboot table found.\n"); + msg_pinfo("No coreboot table found.\n"); return -1; } addr = ((char *)lb_table) - ((char *)table_area) + start; - fprintf(stdout, "coreboot table found at 0x%lx.\n", + msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); - printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", + msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/chipset_enable.c Fri May 7 22:09:04 2010 (r997) @@ -74,8 +74,8 @@ pci_write_byte(dev, 0x40, new); newer = pci_read_byte(dev, 0x40); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); return -1; } return 0; @@ -91,9 +91,9 @@ if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0000); if (!sbdev) - fprintf(stderr, "No southbridge found for %s!\n", name); + msg_perr("No southbridge found for %s!\n", name); if (sbdev) - printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n", + msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", sbdev->vendor_id, sbdev->device_id, sbdev->bus, sbdev->dev, sbdev->func); return sbdev; @@ -162,8 +162,8 @@ pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); ret = -1; } @@ -188,8 +188,8 @@ pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); ret = -1; } @@ -235,7 +235,7 @@ pci_write_word(dev, xbcs, new); if (pci_read_word(dev, xbcs) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); return -1; } @@ -257,11 +257,11 @@ */ old = pci_read_byte(dev, bios_cntl); - printf_debug("\nBIOS Lock Enable: %sabled, ", + msg_pdbg("\nBIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); - printf_debug("BIOS Write Enable: %sabled, ", + msg_pdbg("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); - printf_debug("BIOS_CNTL is 0x%x\n", old); + msg_pdbg("BIOS_CNTL is 0x%x\n", old); new = old | 1; @@ -271,7 +271,7 @@ pci_write_byte(dev, bios_cntl, new); if (pci_read_byte(dev, bios_cntl) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); return -1; } @@ -306,7 +306,7 @@ fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); /* FIXME: Need to undo this on shutdown. */ - printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); + msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); pci_write_long(dev, 0xd0, fwh_conf); pci_write_word(dev, 0xd4, fwh_conf); /* FIXME: Decode settings are not changed. */ @@ -321,7 +321,7 @@ fwh_conf = pci_read_long(dev, 0xd0); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); @@ -335,7 +335,7 @@ fwh_conf = pci_read_word(dev, 0xd4); for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); @@ -350,7 +350,7 @@ fwh_conf = pci_read_word(dev, 0xd8); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i + 0x8)) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); @@ -362,7 +362,7 @@ } for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> i) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); @@ -373,7 +373,7 @@ } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override * buses_supported anyway. @@ -391,7 +391,7 @@ return err; old = pci_read_byte(dev, 0xd9); - printf_debug("BIOS Prefetch Enable: %sabled, ", + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); new = old & ~1; @@ -413,10 +413,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; - printf_debug("MMIO base at = 0x%x\n", mmio_base); + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ @@ -444,20 +444,20 @@ /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); + msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); gcs = mmio_readl(rcrb + 0x3410); - printf_debug("GCS = 0x%x: ", gcs); - printf_debug("BIOS Interface Lock-Down: %sabled, ", + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); - printf_debug("Top Swap : %s\n", + msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); /* It seems the ICH7 does not support SPI and LPC chips at the same @@ -492,105 +492,105 @@ } /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: - printf_debug("0x00: 0x%04x (SPIS)\n", + msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0)); - printf_debug("0x02: 0x%04x (SPIC)\n", + msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2)); - printf_debug("0x04: 0x%08x (SPIA)\n", + msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); - printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(spibar + offs), i); - printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } - printf_debug("0x50: 0x%08x (BBAR)\n", + msg_pdbg("0x50: 0x%08x (BBAR)\n", mmio_readl(spibar + 0x50)); - printf_debug("0x54: 0x%04x (PREOP)\n", + msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); - printf_debug("0x56: 0x%04x (OPTYPE)\n", + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56)); - printf_debug("0x58: 0x%08x (OPMENU)\n", + msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5c: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); - printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(spibar + offs), i); } - printf_debug("\n"); + msg_pdbg("\n"); if (mmio_readw(spibar) & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(spibar + 4); - printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); - printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - printf_debug("FDV %i, ", (tmp2 >> 14) & 1); - printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); - printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); - printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); - printf_debug("AEL %i, ", (tmp2 >> 2) & 1); - printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); - printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); tmp = mmio_readl(spibar + 0x50); - printf_debug("0x50: 0x%08x (FRAP)\n", tmp); - printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); - printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); - printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); - printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); + msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); + msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); + msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - printf_debug("0x54: 0x%08x (FREG0)\n", + msg_pdbg("0x54: 0x%08x (FREG0)\n", mmio_readl(spibar + 0x54)); - printf_debug("0x58: 0x%08x (FREG1)\n", + msg_pdbg("0x58: 0x%08x (FREG1)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5C: 0x%08x (FREG2)\n", + msg_pdbg("0x5C: 0x%08x (FREG2)\n", mmio_readl(spibar + 0x5C)); - printf_debug("0x60: 0x%08x (FREG3)\n", + msg_pdbg("0x60: 0x%08x (FREG3)\n", mmio_readl(spibar + 0x60)); - printf_debug("0x64: 0x%08x (FREG4)\n", + msg_pdbg("0x64: 0x%08x (FREG4)\n", mmio_readl(spibar + 0x64)); - printf_debug("0x74: 0x%08x (PR0)\n", + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); - printf_debug("0x78: 0x%08x (PR1)\n", + msg_pdbg("0x78: 0x%08x (PR1)\n", mmio_readl(spibar + 0x78)); - printf_debug("0x7C: 0x%08x (PR2)\n", + msg_pdbg("0x7C: 0x%08x (PR2)\n", mmio_readl(spibar + 0x7C)); - printf_debug("0x80: 0x%08x (PR3)\n", + msg_pdbg("0x80: 0x%08x (PR3)\n", mmio_readl(spibar + 0x80)); - printf_debug("0x84: 0x%08x (PR4)\n", + msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", mmio_readl(spibar + 0x90)); - printf_debug("0x94: 0x%04x (PREOP)\n", + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); - printf_debug("0x96: 0x%04x (OPTYPE)\n", + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x96)); - printf_debug("0x98: 0x%08x (OPMENU)\n", + msg_pdbg("0x98: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x98)); - printf_debug("0x9C: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); - printf_debug("0xA0: 0x%08x (BBAR)\n", + msg_pdbg("0xA0: 0x%08x (BBAR)\n", mmio_readl(spibar + 0xA0)); - printf_debug("0xB0: 0x%08x (FDOC)\n", + msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); @@ -601,18 +601,18 @@ } old = pci_read_byte(dev, 0xdc); - printf_debug("SPI Read Configuration: "); + msg_pdbg("SPI Read Configuration: "); new = (old >> 2) & 0x3; switch (new) { case 0: case 1: case 2: - printf_debug("prefetching %sabled, caching %sabled, ", + msg_pdbg("prefetching %sabled, caching %sabled, ", (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); break; default: - printf_debug("invalid prefetching/caching settings, "); + msg_pdbg("invalid prefetching/caching settings, "); break; } @@ -652,7 +652,7 @@ pci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - printf("\nWARNING: Failed to enable flash write on \"%s\"\n", + msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } @@ -769,7 +769,7 @@ new = pci_read_byte(dev, 0x52); if (new != 0xee) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); return -1; } @@ -787,7 +787,7 @@ if (new != old) { pci_write_byte(dev, 0x43, new); if (pci_read_byte(dev, 0x43) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); } } @@ -799,7 +799,7 @@ pci_write_byte(dev, 0x40, new); if (pci_read_byte(dev, 0x40) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); return -1; } @@ -819,7 +819,7 @@ /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - printf_debug("SB600 %s%sprotected from %u to %u\n", + msg_pinfo("SB600 %s%sprotected from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), @@ -828,7 +828,7 @@ pci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); if (prot & 0x3) - printf("SB600 %s%sunprotect failed from %u to %u\n", + msg_perr("SB600 %s%sunprotect failed from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), @@ -838,7 +838,7 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - printf_debug("SPI base address is at 0x%x\n", tmp); + msg_pdbg("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) @@ -854,17 +854,17 @@ sb600_spibar += tmp & 0xfff; tmp = pci_read_long(dev, 0xa0); - printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); tmp = pci_read_byte(dev, 0xbb); - printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", tmp & 0x1, (tmp & 0x20) >> 5); tmp = mmio_readl(sb600_spibar); - printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, @@ -876,7 +876,7 @@ smbus_dev = pci_dev_find(0x1002, 0x4385); if (has_spi && !smbus_dev) { - fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; } if (has_spi) { @@ -884,22 +884,22 @@ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); reg &= 0xC0; - printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); if (reg != 0x00) has_spi = 0; /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ reg = pci_read_byte(smbus_dev, 0x83); reg &= 0xC0; - printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); /* SPI_HOLD is not used on all boards, filter it out. */ if ((reg & 0x80) != 0x00) has_spi = 0; /* GPIO47/SPI_CLK status */ reg = pci_read_byte(smbus_dev, 0xA7); reg &= 0x40; - printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); if (reg != 0x00) has_spi = 0; } @@ -914,24 +914,24 @@ OUTB(0x8f, 0xcd6); reg = INB(0xcd7); reg &= 0x0e; - printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); + msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); if (reg & 0x02) { switch ((reg & 0x0c) >> 2) { case 0x00: - printf_debug(": LPC"); + msg_pdbg(": LPC"); break; case 0x01: - printf_debug(": PCI"); + msg_pdbg(": PCI"); break; case 0x02: - printf_debug(": FWH"); + msg_pdbg(": FWH"); break; case 0x03: - printf_debug(": SPI"); + msg_pdbg(": SPI"); break; } } - printf_debug("\n"); + msg_pdbg("\n"); /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. @@ -970,7 +970,7 @@ if (new != old) { pci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); } } @@ -981,7 +981,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } @@ -998,7 +998,7 @@ smbusdev = pci_dev_find(0x1002, 0x4372); if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); + msg_perr("ERROR: SMBus device not found. Aborting.\n"); exit(1); } @@ -1047,7 +1047,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } @@ -1277,7 +1277,7 @@ flashbase = parx << 12; } } else { - printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); } /* 4. Clean up */ @@ -1436,18 +1436,18 @@ } if (dev) { - printf("Found chipset \"%s %s\", enabling flash write... ", + msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } - printf("This chipset supports the following protocols: %s.\n", + msg_pinfo("This chipset supports the following protocols: %s.\n", flashbuses_to_text(buses_supported)); return ret; Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/dmi.c Fri May 7 22:09:04 2010 (r997) @@ -53,12 +53,12 @@ "%s -s %s", dmidecode_command, string_name); dmidecode_pipe = popen(commandline, "r"); if (!dmidecode_pipe) { - printf_debug("DMI pipe open error\n"); + msg_perr("DMI pipe open error\n"); return NULL; } if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { if(ferror(dmidecode_pipe)) { - printf_debug("DMI pipe read error\n"); + msg_perr("DMI pipe read error\n"); pclose(dmidecode_pipe); return NULL; } else { @@ -70,7 +70,8 @@ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - printf_debug("DMI pipe close error\n"); + msg_pinfo("dmidecode execution unsucessfull - continuing " + "without DMI info\n"); return NULL; } @@ -78,7 +79,7 @@ if (answerbuf[0] != 0 && answerbuf[strlen(answerbuf) - 1] == '\n') answerbuf[strlen(answerbuf) - 1] = 0; - printf_debug("DMI string %s: \"%s\"\n", string_name, answerbuf); + msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf); result = strdup(answerbuf); if (!result) @@ -104,7 +105,7 @@ chassis_type = get_dmi_string("chassis-type"); if (chassis_type && (!strcmp(chassis_type, "Notebook") || !strcmp(chassis_type, "Portable"))) { - printf_debug("Laptop detected via DMI\n"); + msg_pdbg("Laptop detected via DMI\n"); is_laptop = 1; } free(chassis_type); @@ -126,7 +127,7 @@ int anchored = 0; int patternlen; - printf_debug("matching %s against %s\n", value, pattern); + msg_pspew("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ if (pattern[0] == 0) return 1; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/flashrom.c Fri May 7 22:09:04 2010 (r997) @@ -520,7 +520,7 @@ if (devlen) { dev = malloc(devlen + 1); if (!dev) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } strncpy(dev, param_pos, devlen); @@ -532,7 +532,7 @@ memmove(param_pos, rest, strlen(rest) + 1); tmp = realloc(*haystack, strlen(*haystack) + 1); if (!tmp) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } *haystack = tmp; @@ -549,7 +549,7 @@ uint8_t *cmpbuf = malloc(len); if (!cmpbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } memset(cmpbuf, 0xff, len); @@ -577,16 +577,16 @@ goto out_free; if (!flash->read) { - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } if (!readbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } if (start + len > flash->total_size * 1024) { - fprintf(stderr, "Error: %s called with start 0x%x + len 0x%x >" + msg_gerr("Error: %s called with start 0x%x + len 0x%x >" " total_size 0x%x\n", __func__, start, len, flash->total_size * 1024); ret = -1; @@ -614,7 +614,7 @@ if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ if (!failcount++) - fprintf(stderr, "%s FAILED at 0x%08x! " + msg_cerr("%s FAILED at 0x%08x! " "Expected=0x%02x, Read=0x%02x,", message, starthere + j, cmpbuf[starthere - start + j], @@ -623,7 +623,7 @@ } } if (failcount) { - fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", start, start + len - 1, failcount); ret = -1; } @@ -748,7 +748,7 @@ int i; if (!buf) { - fprintf(stderr, "Invalid buffer!\n"); + msg_gerr("Invalid buffer!\n"); return 1; } @@ -836,7 +836,7 @@ if ((buses & CHIP_BUSTYPE_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -844,7 +844,7 @@ } if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -852,7 +852,7 @@ } if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -860,7 +860,7 @@ } if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -873,7 +873,7 @@ */ if (bitcount(buses) > limitexceeded) /* FIXME: This message is designed towards CLI users. */ - printf_debug("There is at least one common chip/programmer " + msg_pdbg("There is at least one common chip/programmer " "interface which can support a chip of this size. " "You can try --force at your own risk.\n"); return 1; @@ -934,7 +934,7 @@ if (!flash || !flash->name) return NULL; - printf("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", force ? "Assuming" : "Found", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); @@ -950,12 +950,12 @@ int ret; int total_size = flash->total_size * 1024; - printf("Verifying flash... "); + msg_cinfo("Verifying flash... "); ret = verify_range(flash, buf, 0, total_size, NULL); if (!ret) - printf("VERIFIED. \n"); + msg_cinfo("VERIFIED. \n"); return ret; } @@ -968,17 +968,17 @@ unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - printf("Error: No filename specified.\n"); + msg_gerr("Error: No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); exit(1); } - printf("Reading flash... "); + msg_cinfo("Reading flash... "); if (!flash->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_cinfo("FAILED!\n"); + msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } else flash->read(flash, buf, 0, size); @@ -986,7 +986,7 @@ numbytes = fwrite(buf, 1, size, image); fclose(image); free(buf); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); + msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1; return 0; @@ -1028,7 +1028,7 @@ } /* Empty eraseblock definition with erase function. */ if (!done && eraser.block_erase) - msg_pspew("Strange: Empty eraseblock definition with " + msg_gspew("Strange: Empty eraseblock definition with " "non-empty erase function. Not an error.\n"); if (!done) continue; @@ -1065,31 +1065,31 @@ int i, j, k, ret = 0, found = 0; unsigned int start, len; - printf("Erasing flash chip... "); + msg_cinfo("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; - printf_debug("Looking at blockwise erase function %i... ", k); + msg_cdbg("Looking at blockwise erase function %i... ", k); if (!eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("not defined. " + msg_cdbg("not defined. " "Looking for another erase function.\n"); continue; } if (!eraser.block_erase && eraser.eraseblocks[0].count) { - printf_debug("eraseblock layout is known, but no " + msg_cdbg("eraseblock layout is known, but no " "matching block erase function found. " "Looking for another erase function.\n"); continue; } if (eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("block erase function found, but " + msg_cdbg("block erase function found, but " "eraseblock layout is unknown. " "Looking for another erase function.\n"); continue; } found = 1; - printf_debug("trying... "); + msg_cdbg("trying... "); for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. @@ -1097,7 +1097,7 @@ for (j = 0; j < eraser.eraseblocks[i].count; j++) { start = done + eraser.eraseblocks[i].size * j; len = eraser.eraseblocks[i].size; - printf_debug("0x%06x-0x%06x, ", start, + msg_cdbg("0x%06x-0x%06x, ", start, start + len - 1); ret = eraser.block_erase(flash, start, len); if (ret) @@ -1108,27 +1108,27 @@ done += eraser.eraseblocks[i].count * eraser.eraseblocks[i].size; } - printf_debug("\n"); + msg_cdbg("\n"); /* If everything is OK, don't try another erase function. */ if (!ret) break; } if (!found) { - fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); + msg_cerr("ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_cerr("FAILED!\n"); } else { - printf("SUCCESS.\n"); + msg_cinfo("SUCCESS.\n"); } return ret; } void emergency_help_message(void) { - fprintf(stderr, "Your flash chip is in an unknown state.\n" + msg_gerr("Your flash chip is in an unknown state.\n" "Get help on IRC at irc.freenode.net (channel #flashrom) or\n" "mail flashrom(a)flashrom.org!\n--------------------" "-----------------------------------------------------------\n" @@ -1140,11 +1140,11 @@ { enum programmer p; for (p = 0; p < PROGRAMMER_INVALID; p++) { - printf("%s", programmer_table[p].name); + msg_ginfo("%s", programmer_table[p].name); if (p < PROGRAMMER_INVALID - 1) - printf("%s", delim); + msg_ginfo("%s", delim); } - printf("\n"); + msg_ginfo("\n"); } void print_sysinfo(void) @@ -1183,7 +1183,7 @@ void print_version(void) { - printf("flashrom v%s", flashrom_version); + msg_ginfo("flashrom v%s\n", flashrom_version); print_sysinfo(); } @@ -1196,16 +1196,16 @@ * if more errors exist. */ if (ARRAY_SIZE(programmer_table) - 1 != PROGRAMMER_INVALID) { - fprintf(stderr, "Programmer table miscompilation!\n"); + msg_gerr("Programmer table miscompilation!\n"); ret = 1; } if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - fprintf(stderr, "SPI programmer table miscompilation!\n"); + msg_gerr("SPI programmer table miscompilation!\n"); ret = 1; } #if BITBANG_SPI_SUPPORT == 1 if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { - fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); + msg_gerr("Bitbanging SPI master table miscompilation!\n"); ret = 1; } #endif @@ -1218,36 +1218,36 @@ void check_chip_supported(struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { - printf("===\n"); + msg_cinfo("===\n"); if (flash->tested & TEST_BAD_MASK) { - printf("This flash part has status NOT WORKING for operations:"); + msg_cinfo("This flash part has status NOT WORKING for operations:"); if (flash->tested & TEST_BAD_PROBE) - printf(" PROBE"); + msg_cinfo(" PROBE"); if (flash->tested & TEST_BAD_READ) - printf(" READ"); + msg_cinfo(" READ"); if (flash->tested & TEST_BAD_ERASE) - printf(" ERASE"); + msg_cinfo(" ERASE"); if (flash->tested & TEST_BAD_WRITE) - printf(" WRITE"); - printf("\n"); + msg_cinfo(" WRITE"); + msg_cinfo("\n"); } if ((!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) || (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) || (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) || (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE))) { - printf("This flash part has status UNTESTED for operations:"); + msg_cinfo("This flash part has status UNTESTED for operations:"); if (!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) - printf(" PROBE"); + msg_cinfo(" PROBE"); if (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) - printf(" READ"); + msg_cinfo(" READ"); if (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) - printf(" ERASE"); + msg_cinfo(" ERASE"); if (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE)) - printf(" WRITE"); - printf("\n"); + msg_cinfo(" WRITE"); + msg_cinfo("\n"); } /* FIXME: This message is designed towards CLI users. */ - printf("Please email a report to flashrom(a)flashrom.org if any " + msg_cinfo("Please email a report to flashrom(a)flashrom.org if any " "of the above operations\nwork correctly for you with " "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " @@ -1278,13 +1278,13 @@ if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip. "); + msg_cerr("Erase is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if (flash->unlock) @@ -1310,24 +1310,24 @@ flash->unlock(flash); if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip " + msg_cerr("Erase is not working on this chip " "and erase is needed for write. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if (flash->tested & TEST_BAD_WRITE) { - fprintf(stderr, "Write is not working on this chip. "); + msg_cerr("Write is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if ((image = fopen(filename, "rb")) == NULL) { @@ -1341,7 +1341,7 @@ exit(1); } if (image_stat.st_size != flash->total_size * 1024) { - fprintf(stderr, "Error: Image size doesn't match\n"); + msg_gerr("Error: Image size doesn't match\n"); programmer_shutdown(); exit(1); } @@ -1352,7 +1352,7 @@ #endif fclose(image); if (numbytes != size) { - fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); + msg_gerr("Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); programmer_shutdown(); return 1; } @@ -1365,20 +1365,20 @@ // //////////////////////////////////////////////////////////// if (write_it) { - printf("Writing flash chip... "); + msg_cinfo("Writing flash chip... "); if (!flash->write) { - fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n"); + msg_cerr("Error: flashrom has no write function for this flash chip.\n"); programmer_shutdown(); return 1; } ret = flash->write(flash, buf); if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_cerr("FAILED!\n"); emergency_help_message(); programmer_shutdown(); return 1; } else { - printf("COMPLETE.\n"); + msg_cinfo("COMPLETE.\n"); } } Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/hwaccess.c Fri May 7 22:09:04 2010 (r997) @@ -41,7 +41,7 @@ #else if (iopl(3) != 0) { #endif - fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" + msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); exit(1); } Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/ichspi.c Fri May 7 22:09:04 2010 (r997) @@ -38,17 +38,6 @@ #include "chipdrivers.h" #include "spi.h" -/* Change this to #define if you want lowlevel debugging of commands - * sent to the ICH/VIA SPI controller. - */ -#undef COMM_DEBUG - -#ifdef COMM_DEBUG -#define msg_comm_debug printf_debug -#else -#define msg_comm_debug(...) do {} while (0) -#endif - /* ICH9 controller register definition */ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -237,7 +226,7 @@ uint32_t opmenu[2]; if (op == NULL) { - printf_debug("\n%s: null OPCODES pointer!\n", __func__); + msg_perr("\n%s: null OPCODES pointer!\n", __func__); return -1; } @@ -256,7 +245,7 @@ opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -315,7 +304,7 @@ opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } - printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); + msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: @@ -331,7 +320,7 @@ REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -352,22 +341,22 @@ return 0; if (ichspi_lock) { - printf_debug("Generating OPCODES... "); + msg_pdbg("Generating OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { - printf_debug("Programming OPCODES... "); + msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); } if (rc) { curopcodes = NULL; - printf_debug("failed\n"); + msg_perr("failed\n"); return 1; } else { curopcodes = curopcodes_done; - printf_debug("done\n"); + msg_pdbg("done\n"); return 0; } } @@ -439,7 +428,7 @@ opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; @@ -468,11 +457,12 @@ programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_perr("timeout\n"); } + /* FIXME: make sure we do not needlessly cause transaction errors. */ if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } @@ -557,7 +547,7 @@ opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); @@ -586,11 +576,12 @@ programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_perr("timeout\n"); } + /* FIXME make sure we do not needlessly cause transaction errors. */ if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } @@ -615,7 +606,7 @@ switch (spi_controller) { case SPI_CONTROLLER_VIA: if (datalength > 16) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; @@ -623,7 +614,7 @@ return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; @@ -631,14 +622,14 @@ return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich9_run_opcode(op, offset, datalength, data); default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); } /* If we ever get here, something really weird happened */ @@ -652,14 +643,14 @@ uint32_t remaining = page_size; int towrite; - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", + msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", offset, page_size, bytes); for (; remaining > 0; remaining -= towrite) { towrite = min(remaining, maxdata); if (spi_nbyte_program(offset + (page_size - remaining), &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); + msg_perr("Error writing"); return 1; } } @@ -687,14 +678,14 @@ spi_disable_blockprotect(); /* Erase first */ - printf("Erasing flash before programming... "); + msg_pinfo("Erasing flash before programming... "); if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); + msg_perr("ERASE FAILED!\n"); return -1; } - printf("done.\n"); + msg_pinfo("done.\n"); - printf("Programming page: \n"); + msg_pinfo("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; @@ -706,7 +697,7 @@ } } - printf("\n"); + msg_pinfo("\n"); return rc; } @@ -728,7 +719,7 @@ /* FIXME: Reprogram opcodes if possible. Autodetect type of * opcode by checking readcnt/writecnt. */ - printf_debug("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); return SPI_INVALID_OPCODE; } @@ -743,21 +734,21 @@ */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && (writecnt != 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && (writecnt != 1)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && (writecnt < 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; @@ -765,7 +756,7 @@ if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && (readcnt)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, readcnt); return SPI_INVALID_LENGTH; @@ -792,7 +783,7 @@ result = run_opcode(*opcode, addr, count, data); if (result) { - printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); } return result; @@ -817,7 +808,7 @@ */ if (find_preop(curopcodes, (cmds + 1)->writearr[0]) != -1) { - fprintf(stderr, "%s: Two subsequent " + msg_perr("%s: Two subsequent " "preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", __func__, cmds->writearr[0], @@ -829,7 +820,7 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - printf_debug("%s: FIXME: Add on-the-fly" + msg_pdbg("%s: FIXME: Add on-the-fly" " reprogramming of the " "chipset opcode list.\n", __func__); Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/pcidev.c Fri May 7 22:09:04 2010 (r997) @@ -45,7 +45,7 @@ */ addr = pci_read_long(dev, bar); - printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); @@ -66,7 +66,7 @@ } if (devs[i].status == NT) { - printf("===\nThis PCI device is UNTESTED. Please " + msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " "for you. Thank you for your help!\n===\n"); @@ -95,7 +95,7 @@ filter.vendor = vendor_id; if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { - fprintf(stderr, "Error: %s\n", msg); + msg_perr("Error: %s\n", msg); exit(1); } } @@ -112,10 +112,10 @@ /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { - fprintf(stderr, "Error: No supported PCI device found.\n"); + msg_perr("Error: No supported PCI device found.\n"); exit(1); } else if (found > 1) { - fprintf(stderr, "Error: Multiple supported PCI devices found. " + msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); @@ -130,7 +130,7 @@ int i; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, + msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, (devs[i].status == NT) ? " (untested)" : ""); Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/physmap.c Fri May 7 22:09:04 2010 (r997) @@ -158,7 +158,7 @@ if (-1 == fd_mem_cached) { /* Open the memory device CACHED. */ if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - perror("Critical error: open(" MEM_DEV ")"); + msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno)); exit(2); } } @@ -171,7 +171,7 @@ void physunmap(void *virt_addr, size_t len) { if (len == 0) { - printf_debug("Not unmapping zero size at %p\n", virt_addr); + msg_pspew("Not unmapping zero size at %p\n", virt_addr); return; } @@ -189,18 +189,18 @@ void *virt_addr; if (len == 0) { - printf_debug("Not mapping %s, zero size at 0x%08lx.\n", + msg_pspew("Not mapping %s, zero size at 0x%08lx.\n", descr, phys_addr); return NULL; } if ((getpagesize() - 1) & len) { - fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", + msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", descr, phys_addr, (unsigned long)len); } if ((getpagesize() - 1) & phys_addr) { - fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", + msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", descr, (unsigned long)len, phys_addr); } @@ -213,15 +213,17 @@ if (NULL == virt_addr) { if (NULL == descr) descr = "memory"; - fprintf(stderr, "Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); perror(MEM_DEV " mmap failed"); +#ifdef __linux__ if (EINVAL == errno) { - fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); - fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); - fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n"); - fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); - fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); + msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); + msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); + msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n"); + msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); + msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#endif if (!mayfail) exit(3); } @@ -306,7 +308,7 @@ sprintf(msrfilename, "/dev/cpu/%d/msr", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } @@ -314,7 +316,7 @@ if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); + msg_pinfo("Did you run 'modprobe msr'?\n"); return -1; } @@ -324,7 +326,7 @@ void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } @@ -389,7 +391,7 @@ sprintf(msrfilename, "/dev/cpu%d", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } @@ -397,7 +399,7 @@ if (fd_msr < 0) { perror("Error while opening /dev/cpu0"); - printf("Did you install ports/sysutils/devcpu?\n"); + msg_pinfo("Did you install ports/sysutils/devcpu?\n"); return -1; } @@ -407,7 +409,7 @@ void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } @@ -445,7 +447,7 @@ int setup_cpu_msr(int cpu) { - printf("No MSR support for your OS yet.\n"); + msg_pinfo("No MSR support for your OS yet.\n"); return -1; } Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/spi.c Fri May 7 22:09:04 2010 (r997) @@ -130,7 +130,7 @@ const unsigned char *writearr, unsigned char *readarr) { if (!spi_programmer[spi_controller].command) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } @@ -142,7 +142,7 @@ int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } @@ -182,7 +182,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - fprintf(stderr, "%s called, but SPI read is unsupported on this" + msg_perr("%s called, but SPI read is unsupported on this" " hardware. Please report a bug.\n", __func__); return 1; } @@ -197,7 +197,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - fprintf(stderr, "%s called, but SPI page write is unsupported " + msg_perr("%s called, but SPI page write is unsupported " " on this hardware. Please report a bug.\n", __func__); return 1; }

1 0

(no subject)
by Steve Herber 06 May '10

06 May '10

Hello: I ran flashrom on an asus P4P800-VM motherboard and got this error: tux tmp # flashrom -w P4PVM1018.rom flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00007810! Expected=0xff, Read=0x3c, failed byte count from 0x00000000-0x0000ffff: 0x8732 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! Any suggestions? Thanks, -- Steve Herber herber(a)thing.com work: 206-221-7262 Software Engineer, UW Medicine, IT Services home: 425-454-2399

3 3

ERASE works on with a Macronix MX25L8005 (ASUS M3A-H/HDMI)
by Emil Gruno 05 May '10

05 May '10

flashrom v0.9.1-r946 No coreboot table found. Found ITE Super I/O, id 8716 Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. done. Programming flash done. COMPLETE. Verifying flash... VERIFIED. BR, Emil Gruno

1 0

SREC Files
by KC2WNG 04 May '10

04 May '10

Hi Guys I Was wondering if you guys have ever worked on editing SREC files, and figuring out the checksum mechanism

2 1

flashrom external programming with different usb high speed converter
by Matthias Olescher 04 May '10

04 May '10

Hello, as I can see are you using one port of an FT2232H for the SPI programming. Unfortunatly for germans, the chip and the converter board is only aviable from Digikey. Is it also possible to only use full speed with FT232 or even low Speed and V-USB? If high speed is necessary, can the program be changed that it works with http://www-user.tu-chemnitz.de/~heha/bastelecke/Rund%20um%20den%20PC/USB2LP… ? Thank you in advance. Matthias -- Das war's. Werbung bitte nicht beachten: GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

2 1

on chip status table
by FENG Yu Ning 02 May '10

02 May '10

A successful flash chip operation is closely related to a few factors other than the flash chip - southbridge, embedded controller, special enabling operation of a particular board and the flashrom revision. Shall we include other related information in the chip status table? Let us put aside how to store the table first.

1 0

How do you calculate CRC/Checksum for Intel ICH8M-E ?
by Bill Flanders (wtflanders) 01 May '10

01 May '10

Hi, Any idea of what algorithm and bytes to use to update the CRC/Checksum in the flash image? The mac address is stored in the image. I have written a script to update the mac address and know where the CRC/Checksum is. I have tried various algorithms (those supported by Hex Workshop- Checksum-8 and -16, CRC-8 and -16, etc. w/1's and 2's complements) but am unable to duplicate a known checksum. Hardware is a Kontron ETX Express module, flashrom reports: 'Found Chipset "Intel ICH8M-E" ...', 'Found chip "SST SST25VF016B" ...' Thanks in advance, Bill Flanders

2 1

Re: [flashrom] Flashrom - DOS version report
by Carl-Daniel Hailfinger 01 May '10

01 May '10

Hi, [fullquote for flashrom(a)flashrom.org] On 23.03.2010 22:58, RayeR wrote: > >That is very strange. Do you have a log? > >SB600 should work fine. Maybe the SPI chip is not > >attached to the SB600 but instead to the SuperI/O. > >Can you try > >flashrom -p it87spi > > Yes here's it: > > C:\F>flashrom.exe -p it87spi > flashrom v0.9.1-r933 > Error: Programmer initialization failed. OK, so it is not ITE IT87. > C:\F>flashrom.exe -V -r > flashrom v0.9.1-r933 > No coreboot table found. > DMI string system-manufacturer: "Dell Inc. " > DMI string system-product-name: "OptiPlex 320 " > DMI string system-version: "Not Specified" > DMI string baseboard-manufacturer: "Dell Inc. " > DMI string baseboard-product-name: "0CU395" > DMI string baseboard-version: " " > DMI string chassis-type: "Tower" > Found chipset "AMD SB600", enabling flash write... SPI base address is > at 0xd8000 > Error accessing SB600 SPI registers, 0x1000 bytes at 0x000d8000 > dpmi mmap failed: No such file or directory (ENOENT) Ah yes. That's a limitation of the DOS port of flashrom. Usually the SB600 SPI base address is near the top of the address space (4 GB). On your board it is below 1 MB, and AFAIK Rudolf said that we can't map any region below 1 MB as uncached due to CWSDPMI/DJGPP limitations. If anyone has an idea how to overcome these limitations, we can fix flashrom for this special case. > See PCI device listing attached. > > >The W25x40 supports multiple erase commands, > >and your chipset does not allow flashrom to use > >the spi_block_erase_20 command. Flashrom notices > >that this command failed and tries another erase command which works. > > OK > > >Yes, strange. Maybe that happens as side effect from DJGPP compilation? > > I don't know... > > >It should try only 2 times. If it tries more often, > >we have to check the code (bug?). I think Rudolf(?) said that there > >are problems if we try to run a CWSDPMI app (dmidecode) from another > >CWSDPMI app (flashrom). > >Does it work if dmidecode.exe is in the PATH? > >Hm. DMIDECODE.EXE is a name with 9+3 letters. That can't work on old > DOS. > > Yes it works with dmidecode in path but nobody told me that I need it. > On my home PC I already have dmidecode for DOS in my utilities > directory. The file name is not problem because of DJGPP is smart > and do some file name translation. If there's no LFN support it > tries to look for "dmidecod.exe" and when run on LFN enabled OS > it will use "dmidecode.exe". But it's different LFN truncating > mode than windows use ("dmidec~1.exe"). I don't know why but e.g. > DJGPP PKUNZIP tool use filename truncate this way without ~. > But it would be better to check if both version of name exist and > display non-confusing error message when nothing found. Michael? Is there a good way to handle this? Regards, Carl-Daniel -- http://www.hailfinger.org/

4 12

flashrom in a Toshiba notebook
by Luciano Diamand 30 Apr '10

30 Apr '10

Hi, I have a Toshiba Satellite A100 notebook and when I run flashrom with the following command line: sudo flashrom I get the verbose of the chipset and bios found, but a second later it shuts down When I use the following command line: sudo flashrom -f -r a100.bin -c SST39VF080 it prints the message but in this case it does not power off. flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH6-M", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Found chip "SST SST39VF080" (1024 KB, Parallel) at physical address 0xfff00000. Please note that forced reads most likely contain garbage. Reading flash... done. I would like to report that the bios file read with flashrom was the same that I write with the program provided by Toshiba. Thank you. Regards, Luciano Diamand

1 0

GA-6BXE works with out a hitch
by Anders Jenbo 29 Apr '10

29 Apr '10

http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI… -Anders

1 0

[RFC] Kill --force
by Carl-Daniel Hailfinger 28 Apr '10

28 Apr '10

--force may have been a good idea back when only developers were using flashrom, but over the last few months I've seen too many people who incorrectly believed that --force would solve anything. One of the problems is that --force has multiple meanings: - Force chip read by faking probe success. - Force writing even if cbtable tells us that this is the wrong image for this board. - Force chip access even if the chip is bigger than max decode size for the flash bus. - Force erase even if erase is known bad. - Force write even if write is known bad. We should kill --force and replace it with explicit --force-erase or --force-cbtable-mismatch or similar stuff, maybe -p internal:ignore_cbtable. First step: - Remove any suggestions to use --force for probe/read from flashrom output. - Don't talk about "success" or "Found chip" if the chip is forced. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-forced_stupid/cli_classic.c =================================================================== --- flashrom-forced_stupid/cli_classic.c (Revision 992) +++ flashrom-forced_stupid/cli_classic.c (Arbeitskopie) @@ -303,6 +303,18 @@ cli_classic_usage(argv[0]); } + if (chip_to_probe) { + for (flash = flashchips; flash && flash->name; flash++) + if (!strcmp(flash->name, chip_to_probe)) + break; + if (!flash || !flash->name) { + fprintf(stderr, "Error: Unknown chip specified.\n"); + exit(1); + } + /* Clean up after the check. */ + flash = NULL; + } + if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); exit(1); @@ -329,14 +341,10 @@ } else if (!flashes[0]) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { - printf("If you know which flash chip you have, and if this version of flashrom\n"); - printf("supports a similar flash chip, you can try to force read your chip. Run:\n"); - printf("flashrom -f -r -c similar_supported_flash_chip filename\n"); - printf("\n"); - printf("Note: flashrom can never write when the flash chip isn't found automatically.\n"); + printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { - printf("Force read (-f -r -c) requested, forcing chip probe success:\n"); + printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); flashes[0] = probe_flash(flashchips, 1); if (!flashes[0]) { printf("flashrom does not support a flash chip named '%s'.\n", chip_to_probe); Index: flashrom-forced_stupid/flashrom.c =================================================================== --- flashrom-forced_stupid/flashrom.c (Revision 992) +++ flashrom-forced_stupid/flashrom.c (Arbeitskopie) @@ -924,7 +924,8 @@ if (!flash || !flash->name) return NULL; - printf("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + printf("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + force ? "Assuming" : "Found", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); -- http://www.hailfinger.org/

3 10

[commit] r996 - trunk
by repository service 28 Apr '10

28 Apr '10

Author: hailfinger Date: Wed Apr 28 17:22:14 2010 New Revision: 996 URL: http://flashrom.org/trac/coreboot/changeset/996 Log: --force may have been a good idea back when only developers were using flashrom, but over the last few months we've seen too many people who incorrectly believed that --force would solve anything. One of the problems is that --force had multiple meanings: - Force chip read by faking probe success. - Force chip access even if the chip is bigger than max decode size for the flash bus. - Force erase even if erase is known bad. - Force write even if write is known bad. - Force writing even if cbtable tells us that this is the wrong image for this board. This patch cleans up --force usage: - Remove any suggestions to use --force for probe/read from flashrom output. - Don't talk about "success" or "Found chip" if the chip is forced. - Add a new internal programmer parameter boardmismatch=force. This overrides any mismatch detection from cbtable/image comparisons. - Add a new internal programmer parameter laptop=force_I_want_a_brick. - Adjust the documentation for --force. - Clean up the man page a bit whereever it talks about --force or laptops. Additional changes in this patch: - Add warnings about laptops to the documentation. - Abort if a laptop is detected. Can be overridden with the programmer parameter mentioned above. - Add "Portable" to the list of DMI strings indicating laptops. - Check if a chip specified with -c is known to flashrom. - Programmer parameter reliability and consistency fixes. - More paranoid self-checks. - Improve documentation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/README trunk/cli_classic.c trunk/dmi.c trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/internal.c trunk/layout.c Modified: trunk/README ============================================================================== --- trunk/README Mon Apr 26 00:47:50 2010 (r995) +++ trunk/README Wed Apr 28 17:22:14 2010 (r996) @@ -11,6 +11,12 @@ It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash, or SPI. +Do not use flashrom on laptops! The embedded controller (EC) present in many +laptops interacts badly with any flash attempts and can brick your laptop +permanently. + +Please make a backup of your flash chip before writing to it. + Please see the flashrom(8) manpage. Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Mon Apr 26 00:47:50 2010 (r995) +++ trunk/cli_classic.c Wed Apr 28 17:22:14 2010 (r996) @@ -248,6 +248,10 @@ switch (optarg[namelen]) { case ':': programmer_param = strdup(optarg + namelen + 1); + if (!strlen(programmer_param)) { + free(programmer_param); + programmer_param = NULL; + } break; case '\0': break; @@ -303,6 +307,21 @@ cli_classic_usage(argv[0]); } + if (chip_to_probe) { + for (flash = flashchips; flash && flash->name; flash++) + if (!strcmp(flash->name, chip_to_probe)) + break; + if (!flash || !flash->name) { + fprintf(stderr, "Error: Unknown chip '%s' specified.\n", + chip_to_probe); + printf("Run flashrom -L to view the hardware supported " + "in this flashrom version.\n"); + exit(1); + } + /* Clean up after the check. */ + flash = NULL; + } + if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); exit(1); @@ -329,18 +348,14 @@ } else if (!flashes[0]) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { - printf("If you know which flash chip you have, and if this version of flashrom\n"); - printf("supports a similar flash chip, you can try to force read your chip. Run:\n"); - printf("flashrom -f -r -c similar_supported_flash_chip filename\n"); - printf("\n"); - printf("Note: flashrom can never write when the flash chip isn't found automatically.\n"); + printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { - printf("Force read (-f -r -c) requested, forcing chip probe success:\n"); + printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); flashes[0] = probe_flash(flashchips, 1); if (!flashes[0]) { - printf("flashrom does not support a flash chip named '%s'.\n", chip_to_probe); - printf("Run flashrom -L to view the hardware supported in this flashrom version.\n"); + printf("Probing for flash chip '%s' failed.\n", chip_to_probe); + programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Mon Apr 26 00:47:50 2010 (r995) +++ trunk/dmi.c Wed Apr 28 17:22:14 2010 (r996) @@ -102,7 +102,8 @@ } chassis_type = get_dmi_string("chassis-type"); - if (chassis_type && !strcmp(chassis_type, "Notebook")) { + if (chassis_type && (!strcmp(chassis_type, "Notebook") || + !strcmp(chassis_type, "Portable"))) { printf_debug("Laptop detected via DMI\n"); is_laptop = 1; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Mon Apr 26 00:47:50 2010 (r995) +++ trunk/flash.h Wed Apr 28 17:22:14 2010 (r996) @@ -385,6 +385,7 @@ #if INTERNAL_SUPPORT == 1 extern int is_laptop; extern int force_boardenable; +extern int force_boardmismatch; void probe_superio(void); int internal_init(void); int internal_shutdown(void); Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon Apr 26 00:47:50 2010 (r995) +++ trunk/flashrom.8 Wed Apr 28 17:22:14 2010 (r996) @@ -61,7 +61,10 @@ More verbose output. .TP .B "\-c, \-\-chip" <chipname> -Probe only for specified flash ROM chip. +Probe only for specified flash ROM chip. This option takes the chip name as +printed by +.B "flashrom \-L" +without the vendor name. Please note that the chip name is case sensitive. .TP .B "\-m, \-\-mainboard" <[vendor:]part> Override mainboard settings. @@ -77,11 +80,16 @@ coreboot table is found. .TP .B "\-f, \-\-force" -Force write without checking whether the ROM image file is really meant -to be used on this board. +Force one or more of the following actions: .sp -Note: This check only works while coreboot is running, and only for those -boards where the coreboot code supports it. +* Force chip read and pretend the chip is there. +.sp +* Force chip access even if the chip is bigger than max decode size for\ + the flash bus. +.sp +* Force erase even if erase is known bad. +.sp +* Force write even if write is known bad. .TP .B "\-l, \-\-layout <file>" Read ROM layout from @@ -135,7 +143,7 @@ but outputs the supported hardware in MediaWiki syntax, so that it can be easily pasted into the wiki page at http://www.flashrom.org/. .TP -.B "\-p, \-\-programmer <name>[:parameters]" +.B "\-p, \-\-programmer <name>[:parameter[,parameter[,parameter]]]" Specify the programmer device. Currently supported are: .sp .BR "* internal" " (default, for in-system flashing in the mainboard)" @@ -220,6 +228,13 @@ enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +On systems running coreboot, flashrom checks whether the desired image matches +your mainboard. This needs some special board ID to be present in the image. +If flashrom detects that the image you want to write and the current board +do not match, it will refuse to write the image unless you specify +.sp +.B "flashrom -p internal:boardmismatch=force" +.sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. You can use .B "flashrom -p internal:it87spiport=portnum" @@ -228,6 +243,24 @@ programmer section to use a non-default port for controlling the IT87 series Super I/O. In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, you can try to force recognition by using the it87spi programmer. +.sp +Using flashrom on laptops is dangerous and may easily make your hardware +unusable (see also the BUGS section). The embedded controller (EC) in these +machines often interacts badly with flashing. http://www.flashrom.org/Laptops +has more information. If flash is shared with the EC, erase is guaranteed to +brick your laptop and write is very likely to brick your laptop. +Chip read and probe may irritate your EC and cause fan failure, backlight +failure, sudden poweroff, and other nasty effects. +flashrom will attempt to detect laptops and abort immediately for safety +reasons. +If you want to proceed anyway at your own risk, use +.sp +.B "flashrom -p internal:laptop=force_I_want_a_brick" +.sp +You have been warned. +.sp +We will not help you if you force flashing on a laptop because this is a really +dumb idea. .TP .BR "dummy " programmer An optional parameter specifies the bus types it @@ -315,8 +348,14 @@ .SH BUGS Please report any bugs at .BR http://www.flashrom.org/trac/flashrom/newticket "," -or on the flashrom mailing list -.RB "(" http://www.flashrom.org/mailman/listinfo/flashrom ")." +or on the flashrom mailing list at +.BR http://www.flashrom.org/mailman/listinfo/flashrom "." +.sp +Using flashrom on laptops is dangerous and may easily make your hardware +unusable unless you can desolder the flash chip and have a full flash chip +backup. This is caused by the embedded controller (EC) present in many laptops, +which interacts badly with any flash attempts. This is a hardware limitation +and flashrom will attempt to detect it and abort immediately for safety reasons. .SH LICENCE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Mon Apr 26 00:47:50 2010 (r995) +++ trunk/flashrom.c Wed Apr 28 17:22:14 2010 (r996) @@ -488,7 +488,17 @@ char *param_pos, *rest, *tmp; char *dev = NULL; int devlen; + int needlelen; + needlelen = strlen(needle); + if (!needlelen) { + msg_gerr("%s: empty needle! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return NULL; + } + /* No programmer parameters given. */ + if (*haystack == NULL) + return NULL; param_pos = strstr(*haystack, needle); do { if (!param_pos) @@ -924,7 +934,8 @@ if (!flash || !flash->name) return NULL; - printf("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + printf("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + force ? "Assuming" : "Found", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Mon Apr 26 00:47:50 2010 (r995) +++ trunk/internal.c Wed Apr 28 17:22:14 2010 (r996) @@ -101,6 +101,7 @@ #if INTERNAL_SUPPORT == 1 struct superio superio = {}; int force_boardenable = 0; +int force_boardmismatch = 0; void probe_superio(void) { @@ -117,26 +118,42 @@ int internal_init(void) { int ret = 0; + int force_laptop = 0; + char *arg; - if (programmer_param && !strlen(programmer_param)) { - free(programmer_param); - programmer_param = NULL; + arg = extract_param(&programmer_param, "boardenable=", ",:"); + if (arg && !strcmp(arg,"force")) { + force_boardenable = 1; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for boardenable.\n"); + } else if (arg) { + msg_perr("Unknown argument for boardenable: %s\n", arg); + exit(1); } - if (programmer_param) { - char *arg; - arg = extract_param(&programmer_param, "boardenable=", ",:"); - if (arg && !strcmp(arg,"force")) - force_boardenable = 1; - else if (arg) - msg_perr("Unknown argument for boardenable: %s\n", arg); - free(arg); - - if (strlen(programmer_param)) - msg_perr("Unhandled programmer parameters: %s\n", - programmer_param); - free(programmer_param); - programmer_param = NULL; + free(arg); + + arg = extract_param(&programmer_param, "boardmismatch=", ",:"); + if (arg && !strcmp(arg,"force")) { + force_boardmismatch = 1; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for boardmismatch.\n"); + } else if (arg) { + msg_perr("Unknown argument for boardmismatch: %s\n", arg); + exit(1); + } + free(arg); + + arg = extract_param(&programmer_param, "laptop=", ",:"); + if (arg && !strcmp(arg,"force_I_want_a_brick")) { + force_laptop = 1; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for laptop.\n"); + } else if (arg) { + msg_perr("Unknown argument for laptop: %s\n", arg); + exit(1); } + free(arg); + get_io_perms(); /* Initialize PCI access for flash enables */ @@ -155,22 +172,35 @@ probe_superio(); /* Warn if a laptop is detected. */ - if (is_laptop) - printf("========================================================================\n" - "WARNING! You seem to be running flashrom on a laptop.\n" - "Laptops, notebooks and netbooks are difficult to support and we recommend\n" - "to use the vendor flashing utility. The embedded controller (EC) in these\n" - "machines often interacts badly with flashing.\n" - "See http://www.flashrom.org/Laptops for details.\n" - "========================================================================\n"); + if (is_laptop) { + msg_perr("========================================================================\n" + "WARNING! You seem to be running flashrom on a laptop.\n" + "Laptops, notebooks and netbooks are difficult to support and we recommend\n" + "to use the vendor flashing utility. The embedded controller (EC) in these\n" + "machines often interacts badly with flashing.\n" + "See http://www.flashrom.org/Laptops for details.\n\n" + "If flash is shared with the EC, erase is guaranteed to brick your laptop\n" + "and write may brick your laptop.\n" + "Read and probe may irritate your EC and cause fan failure, backlight\n" + "failure and sudden poweroff.\n" + "You have been warned.\n" + "========================================================================\n"); + if (force_laptop) { + msg_perr("Proceeding anyway because user specified " + "laptop=force_I_want_a_brick\n"); + } else { + msg_perr("Aborting.\n"); + exit(1); + } + } /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ ret = chipset_flash_enable(); if (ret == -2) { - printf("WARNING: No chipset found. Flash detection " - "will most likely fail.\n"); + msg_perr("WARNING: No chipset found. Flash detection " + "will most likely fail.\n"); } /* Probe for IT87* LPC->SPI translation unconditionally. */ @@ -182,7 +212,7 @@ * The error code might have been a warning only. * Besides that, we don't check the board enable return code either. */ - return 0; + return 0; } int internal_shutdown(void) Modified: trunk/layout.c ============================================================================== --- trunk/layout.c Mon Apr 26 00:47:50 2010 (r995) +++ trunk/layout.c Wed Apr 28 17:22:14 2010 (r996) @@ -111,14 +111,15 @@ !strcasecmp(mainboard_part, lb_part)) { printf_debug("This firmware image matches this mainboard.\n"); } else { - if (force) { + if (force_boardmismatch) { printf("WARNING: This firmware image does not " "seem to fit to this machine - forcing it.\n"); } else { printf("ERROR: Your firmware image (%s:%s) does not " "appear to\n be correct for the detected " - "mainboard (%s:%s)\n\nOverride with --force if you " - "are absolutely sure that you\nare using a correct " + "mainboard (%s:%s)\n\nOverride with -p internal:" + "boardmismatch=force if you are absolutely sure " + "that\nyou are using a correct " "image for this mainboard or override\nthe detected " "values with --mainboard <vendor>:<mainboard>.\n\n", mainboard_vendor, mainboard_part, lb_vendor,

1 0

[feature-request] skip the unwanted sections in ROM layout
by Water Chen 27 Apr '10

27 Apr '10

Hi flashrom designers, >From the handle_romentries() function, I know the current design for "--layout" and "--image" is to read the unwanted sections from the flashchip to a buffer and then write the whole buffer back to the flashchip. For some reasons, I don't want to touch the unwanted sections in the flashchip. Can flashrom just skip them? My platform is "Intel ICH10R" and "Atmel AT25DF321". Thank you. Water

2 2

board enable for Sun Fire v40z
by Mark Morschhäuser 27 Apr '10

27 Apr '10

Hi, as we found out in IRC yesterday, flashrom needs boardenable code to function for the Sun Fire v40z mainboard. I attached the output of # flashrom -V &> flashrom.txt # superiotool -deV &> superiotool.txt # lspci -nnvvvxxx &> lspci.tx flashrom and superiotool were checked out from svn. The official Bios download is a bit tricky as you need a Sun Premium account to access it :-/ Anyway, here is the link: http://www.sun.com/servers/entry/v40z/downloads.jsp If you don't have such an account and need the Bios, send me a note. Documentation however is freely available under [1] (the "Sun Fire v40z Server Architectural Whitepaper" may be of interest) and [2] (see "Full Components List" and "Related Documentation"). If you need more information or help, just ask me. Greetings, Mark [1] http://www.sun.com/servers/entry/v40z/specs.xml [2] http://sunsolve.sun.com/handbook_pub/validateUser.do?target=Systems/SunFire…

1 0

MCP SPI Gigabyte GA-M56S-S3 (MCP65)
by Mark Morschhäuser 27 Apr '10

27 Apr '10

Hello, I am using a Gigabyte GA-M56S-S3 mainboard, read your random notes about MCP SPI support and want to help you with flashrom/lspci/superiotool output I made (with recend svn versions). I attached the output of # flashrom -V &> flashrom.txt # superiotool -deV &> superiotool.txt # lspci -nnvvvxxx &> lspci.txt Link to official BIOS Download: http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=2563&v… Greetings, Mark

1 0

[commit] r995 - trunk
by repository service 26 Apr '10

26 Apr '10

Author: ruik Date: Mon Apr 26 00:47:50 2010 New Revision: 995 URL: http://flashrom.org/trac/coreboot/changeset/995 Log: Fix the DOS port. Now the DS selector limit is set to 4GB and all mmio accesses goes through DS, the 1:1 mapping is fixed so the _DS base is taken onto account. Plus is that the hwaccess.c needs no change and memcpy etc can be used on mmaped space. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/hwaccess.c trunk/physmap.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Apr 20 21:34:31 2010 (r994) +++ trunk/Makefile Mon Apr 26 00:47:50 2010 (r995) @@ -202,12 +202,8 @@ endif ifeq ($(NEED_PCI), yes) -ifneq ($(OS_ARCH), DOS) -# FIXME This workaround is needed until libpci detection can handle -# cross-compiling for DOS. CHECK_LIBPCI = yes endif -endif ifeq ($(NEED_PCI), yes) FEATURE_CFLAGS += -D'NEED_PCI=1' Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Tue Apr 20 21:34:31 2010 (r994) +++ trunk/hwaccess.c Mon Apr 26 00:47:50 2010 (r995) @@ -54,44 +54,6 @@ #endif } -#ifdef __DJGPP__ - -extern unsigned short segFS; - -#include <sys/farptr.h> - -void mmio_writeb(uint8_t val, void *addr) -{ - _farpokeb(segFS, (unsigned long) addr, val); -} - -void mmio_writew(uint16_t val, void *addr) -{ - _farpokew(segFS, (unsigned long) addr, val); -} - -void mmio_writel(uint32_t val, void *addr) -{ - _farpokel(segFS, (unsigned long) addr, val); -} - -uint8_t mmio_readb(void *addr) -{ - return _farpeekb(segFS, (unsigned long) addr); -} - -uint16_t mmio_readw(void *addr) -{ - return _farpeekw(segFS, (unsigned long) addr); -} - -uint32_t mmio_readl(void *addr) -{ - return _farpeekl(segFS, (unsigned long) addr); -} - -#else - void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; @@ -121,4 +83,3 @@ { return *(volatile uint32_t *) addr; } -#endif Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Tue Apr 20 21:34:31 2010 (r994) +++ trunk/physmap.c Mon Apr 26 00:47:50 2010 (r995) @@ -30,66 +30,67 @@ #ifdef __DJGPP__ #include <dpmi.h> +#include <sys/nearptr.h> #define MEM_DEV "dpmi" -unsigned short segFS = 0; +static void *realmem_map; -void *sys_physmap(unsigned long phys_addr, size_t len) +static void *map_first_meg(unsigned long phys_addr, size_t len) { - int ret; - __dpmi_meminfo mi; - if (segFS == 0) { - segFS = __dpmi_allocate_ldt_descriptors (1); - __dpmi_set_segment_base_address (segFS, 0x0); - __dpmi_set_segment_limit (segFS, 0xffffffff); + if (realmem_map) { + return realmem_map + phys_addr; } - mi.address = phys_addr; - mi.size = len; - ret = __dpmi_physical_address_mapping (&mi); + realmem_map = valloc(1024 * 1024); - if (ret != 0) { + if (!realmem_map) { return NULL; } - return (void *) mi.address; -} - -#define sys_physmap_rw_uncached sys_physmap - -#include <sys/movedata.h> -#include <sys/segments.h> -#include <go32.h> + if (__djgpp_map_physical_memory(realmem_map, (1024 * 1024), 0)) { + return NULL; + } -static void *realmem_cpy; + return realmem_map + phys_addr; +} -void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +void *sys_physmap(unsigned long phys_addr, size_t len) { - /* no support for not a 1MB of mem */ - if ((phys_addr + len) > 1024*1024) + int ret; + __dpmi_meminfo mi; + + /* enable 4GB limit on DS descriptor */ + if (!__djgpp_nearptr_enable()) { return NULL; + } - if (realmem_cpy) - return realmem_cpy + phys_addr; + if ((phys_addr + len - 1) < (1024 * 1024)) { + /* we need to use another method to map first 1MB */ + return map_first_meg(phys_addr, len); + } - realmem_cpy = valloc(1024*1024); + mi.address = phys_addr; + mi.size = len; + ret = __dpmi_physical_address_mapping (&mi); - if (!realmem_cpy) + if (ret != 0) { return NULL; + } - movedata(_dos_ds, 0, _my_ds(), (unsigned long) realmem_cpy, 1024*1024); - return realmem_cpy + phys_addr; + return (void *) mi.address + __djgpp_conventional_base; } +#define sys_physmap_rw_uncached sys_physmap +#define sys_physmap_ro_cached sys_physmap void physunmap(void *virt_addr, size_t len) { __dpmi_meminfo mi; - /* we ignore unmaps for our cheat 1MB copy */ - if ((virt_addr >= realmem_cpy) && ((virt_addr + len) <= (realmem_cpy + 1024*1024))) { + /* we ignore unmaps for our first 1MB */ + if ((virt_addr >= realmem_map) && ((virt_addr + len) <= (realmem_map + (1024 * 1024)))) { return; }

1 0

help - flash chip unknown state - attached output files
by csh tmp 24 Apr '10

24 Apr '10

Hello, First, I want to thank Flashrom developers and maintainers and all the helpers who help make this wonderful utility. Please help urgent problem - flashrom erase failed, flash chip in unknown state now. PLEASE help - what do I do now ? THANK YOU. Attached diagnostic output plain-text files. Thanks again. My system: HP Pavilion a445w, P4SD-LA Motherboard (Stingray), XUbuntu 9.10 Karmic uname -a gives Linux 2.6.31-20-generic #58-Ubuntu SMP Fri Mar 12 05:23:09 UTC 2010 i686 GNU/Linux Extracted Windows exe "sp26381.exe" from HP software and downloads site at ftp://ftp.hp.com/pub/softpaq/sp26001-26500/sp26381.exe - it contains "328.rom" (524288 bytes) - new BIOS version 3.28 Current existing BIOS version 3.19 Using flashrom v0.9.1-r706, I first earlier saved current BIOS image to "current_bios_amibios3.19.img" (524288 bytes) - got the following output: flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Reading flash... done. I stupidly made a typo in testing by first trying to re-write current bios back to the chip, to test. I typed the following cmd (missed giving the '-' char to -v option) $ sudo flashrom -w current_bios_amibios3.19.img v current_bios_amibios3.19.img flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x000061f0! Expected=0xff, Read=0x3c, failed byte count from 0x00000000-0x0007ffff: 0x6a379 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF!

4 4

NVIDIA MCP65 ("flashrom -V" for unsupported chipset)
by Melchior FRANZ 24 Apr '10

24 Apr '10

> Please send the output of "flashrom -V" to flashrom(a)flashrom.org to > help us finish support for your chipset. Thanks. OK. :-) m.

1 0

please help - urgent - flash chip in unknown state
by csh tmp 24 Apr '10

24 Apr '10

Hello, First, I want to thank Flashrom developers and maintainers and all the helpers who help make this wonderful utility. Please help urgent problem - flashrom erase failed, flash chip in unknown state now. PLEASE help - what do I do now ? THANK YOU. My system: HP Pavilion a445w, XUbuntu 9.10 Karmic, uname -a gives Linux 2.6.31-20-generic #58-Ubuntu SMP Fri Mar 12 05:23:09 UTC 2010 i686 GNU/Linux Using flashrom v0.9.1-r706, I first earlier saved current BIOS image to "current_bios_amibios3.19.img" flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Reading flash... done. I stupidly made a typo in testing by first trying to re-write current bios back to the chip, I typed the following cmd (missed giving the '-' char to -v option) $ sudo flashrom -w current_bios_amibios3.19.img v current_bios_amibios3.19.img flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x000061f0! Expected=0xff, Read=0x3c, failed byte count from 0x00000000-0x0007ffff: 0x6a379 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF!

1 0

DOS flashrom - partial success on Dell Optiplex 320
by rayer 24 Apr '10

24 Apr '10

Hi, I tried the latest build and didn't get a crash - well mmap() emulation seems to be finally working ;) but when I tried to dump flash with -V -r it hanged after probing chip: AE49F2008, skipped I wait a minute but it didn't probed other chips, so I pressed CTRL+C... It also seems to have some problems with delay loop calibration. Maybe you can use DJGPP functions udelay() and uclock() with ~1us granularity. So I opened the case and lookoed for the flash chip - PMC Pm49FL004T and passed - c Pm49FL004 option. Then the chip was probed OK and flash content dumped, well done. http://rayer.ic.cz/350d/flashrom.jpg Here's the dumped BIOS image http://rayer.ic.cz/350d/dell320.bin Martin

3 3

[PATCH] Add Winbond W25Qxx
by Rudolf Marek 22 Apr '10

22 Apr '10

Hello, Using a DOS version of flashrom, I added following Winbond chips: W25Q80, W25Q16 and W25Q32. I tested read/write/probe with W25Q80. Dont know how should I test all erase opcodes? Attaching patch and some info, currently marking all untested. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> http://www.winbond-usa.com/products/Nexflash/pdfs/datasheets/W25Q80_16_32c.… Rudolf flashrom v0.9.1-r990 on FreeDOS 7 (i786), built with libpci 3.1.5, GCC 4.3.2 No coreboot table found. DMI string system-manufacturer: "" DMI string system-product-name: "" DMI string system-version: "" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "" Found chipset "AMD SB700/SB710/SB750", enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 795M loops per second, delay more than 100o short, recalculating... 906M loops per second, delay more than 100o short, recalculating... 901M loops per second, delay more than 100o short, recalculating... 892M loops per second, delay more than 100o short, recalculating... 912M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Chip status register is 00 Found chip "Winbond W25Q80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rems: id1 0xef, id2 0x13 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. flashrom v0.9.1-r990 on FreeDOS 7 (i786), built with libpci 3.1.5, GCC 4.3.2 No coreboot table found. DMI string system-manufacturer: "" DMI string system-product-name: "" DMI string system-version: "" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "" Found chipset "AMD SB700/SB710/SB750", enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 937M loops per second, delay more than 100o short, recalculating... 878M loops per second, delay more than 100o short, recalculating... 904M loops per second, delay more than 100o short, recalculating... 910M loops per second, delay more than 100o short, recalculating... 903M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x58, id2 0x56, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Chip status register is 00 Found chip "Winbond W25Q80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x08, id2 0x31, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rems: id1 0xef, id2 0x13 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... done. flashrom v0.9.1-r990 on FreeDOS 7 (i786), built with libpci 3.1.5, GCC 4.3.2 No coreboot table found. DMI string system-manufacturer: "" DMI string system-product-name: "" DMI string system-version: "" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "" Found chipset "AMD SB700/SB710/SB750", enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 795M loops per second, delay more than 100o short, recalculating... 906M loops per second, delay more than 100o short, recalculating... 901M loops per second, delay more than 100o short, recalculating... 892M loops per second, delay more than 100o short, recalculating... 912M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Chip status register is 00 Found chip "Winbond W25Q80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. probe_spi_rems: id1 0xef, id2 0x13 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. done. Programming flash done. COMPLETE. Verifying flash... VERIFIED.

3 7

Warning and failure messages from flashrom
by Alan Mast 22 Apr '10

22 Apr '10

Received the following WARNING and FAILED messages: [root@rhlab2 ~]# flashrom flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH9DO", enabling flash write... WARNING: SPI Configuration Lockdown activated. FAILED! This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address 0xffc00000. No operations were specified. How do I turn off the "Configuration Lockdown"? Thanks, Alan This document may contain unclassified technical data whose export, transfer and/or disclosure is restricted by United States law. Dissemination to non-US persons, whether in the United States or abroad may require an export license or other authorization. The information contained herein, including any attached documents or files, is confidential, may be legally privileged and is solely for the intended recipient(s). If you received this information in error, please destroy it and notify us immediately by reply e-mail, letter, fax or phone. Any unauthorized use, dissemination, disclosure, copying or printing is strictly prohibited.

1 0

How to identify a BIOS file
by 890gx＠hushmail.com 22 Apr '10

22 Apr '10

I downloaded the following BIOS update for the MSI 890GXM-G65 (http://www.msi.com/index.php?func=prodmbspec&maincat_no=1&cat2_no=& cat3_no=&prod_no=2012). http://download1.msi.com/files/downloads/bos_exe/7642v12.zip The zip file contains the following files: 4.0K 7642v12/7642v1x.txt 2.1M 7642v12/A7642AMS.120 148K 7642v12/AFUD4310.EXE 56K 7642v12/How to flash the BIOS.DOC Am I right to assume that the largest file "A7642AMS.120" (2.1 MB) is the BIOS file? Here's the edited result of the "file" command on the files within the directory: 7642v12/7642v1x.txt: ISO-8859 English text [...] 7642v12/A7642AMS.120: data 7642v12/AFUD4310.EXE: MS-DOS executable 7642v12/How to flash the BIOS.DOC: CDF V2 Document, [...] The file "A7642AMS.120" is identified only as generic "data".

3 2

Arima HDAMA REV G
by Robert 22 Apr '10

22 Apr '10

flashrom v0.9.1-r994 on Linux 2.6.31.5-127.fc12.i686.PAE (i686), built with libpci 3.1.6, GCC 4.4.3 20100127 (Red Hat 4.4.3-4) No coreboot table found. DMI string system-manufacturer: "# SMBIOS implementations newer than version 2.6 are not" DMI string system-product-name: "# SMBIOS implementations newer than version 2.6 are not" DMI string system-version: "# SMBIOS implementations newer than version 2.6 are not" DMI string baseboard-manufacturer: "# SMBIOS implementations newer than version 2.6 are not" DMI string baseboard-product-name: "# SMBIOS implementations newer than version 2.6 are not" DMI string baseboard-version: "# SMBIOS implementations newer than version 2.6 are not" DMI string chassis-type: "# SMBIOS implementations newer than version 2.6 are not" Found chipset "AMD AMD8111", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 1194M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1002 us, 10000 myus = 10003 us, OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-T, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-B, 512 KB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-T, 512 KB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Lock status for 0x000000 (size 0x010000) is 01, write locked Lock status for 0x010000 (size 0x010000) is 01, write locked Lock status for 0x020000 (size 0x010000) is 01, write locked Lock status for 0x030000 (size 0x010000) is 01, write locked Lock status for 0x040000 (size 0x010000) is 01, write locked Lock status for 0x050000 (size 0x010000) is 01, write locked Lock status for 0x060000 (size 0x010000) is 01, write locked Lock status for 0x070000 (size 0x010000) is 01, write locked Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xbf, id2 0xdf, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xbe, id2 0xad, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xbf, id2 0x60, id1 is normal flash content Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x60 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No operations were specified. 00:06.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8111 PCI [1022:7460] (rev 07) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 115 Bus: primary=00, secondary=01, subordinate=01, sec-latency=36 I/O behind bridge: 00002000-00002fff Memory behind bridge: fc100000-fdffffff Prefetchable memory behind bridge: 80000000-800fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [c0] HyperTransport: Slave or Primary Interface Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.02 Link Frequency 0: 200MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration 00: 22 10 60 74 17 00 30 02 07 00 04 06 00 73 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 24 20 20 00 22 20: 10 fc f0 fd 00 80 00 80 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0e 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 0d 00 00 00 10 00 00 00 18 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 ISA bridge [0601]: Advanced Micro Devices [AMD] AMD-8111 LPC [1022:7468] (rev 05) Subsystem: Rioworks Device [161f:3016] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 1f 16 16 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 30 07 f1 01 00 00 80 0b 71 00 01 00 00 00 c0 50: 00 00 00 00 8d 71 00 00 43 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 1f 16 16 30 00 11 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.1 IDE interface [0101]: Advanced Micro Devices [AMD] AMD-8111 IDE [1022:7469] (rev 03) (prog-if 8a [Master SecP PriP]) Subsystem: Rioworks Device [161f:3016] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at 1020 [size=16] Kernel driver in use: pata_amd Kernel modules: pata_amd 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 21 10 00 00 00 00 00 00 00 00 00 00 1f 16 16 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 03 f0 00 00 00 00 00 00 99 99 99 99 aa 00 a8 a8 50: 03 03 03 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 1f 16 16 30 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.3 Bridge [0680]: Advanced Micro Devices [AMD] AMD-8111 ACPI [1022:746b] (rev 05) Subsystem: Rioworks Device [161f:3016] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: amd756_smbus Kernel modules: i2c-amd756, amd-rng 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 1f 16 16 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 80 b1 09 47 00 00 00 00 20 04 40 00 00 00 00 00 50: 01 81 00 00 0f 00 00 00 01 80 00 00 00 00 00 00 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 1f 16 16 30 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: ec b6 4e 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 33 Bus: primary=00, secondary=02, subordinate=02, sec-latency=32 I/O behind bridge: 00003000-00003fff Memory behind bridge: fe000000-fe0fffff Prefetchable memory behind bridge: 0000000080100000-00000000801fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=conv Status: Dev=00:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream: Capacity=14 CommitmentLimit=65535 Downstream: Capacity=2 CommitmentLimit=65535 Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration Capabilities: [c0] HyperTransport: Slave or Primary Interface Command: BaseUnitID=10 UnitCnt=2 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.02 Link Frequency 0: 600MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 00: 22 10 50 74 17 00 30 02 12 00 04 06 00 21 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 20 31 31 20 02 20: 00 fe 00 fe 11 80 11 80 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 04 00 40: 06 00 1f 00 01 00 00 00 02 0d 00 00 01 2c 00 00 50: 00 00 03 00 00 00 04 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 50 00 03 00 0e 00 ff ff 02 00 ff ff b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 c0: 08 00 4a 00 20 00 11 11 20 00 00 00 22 04 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 0e 00 00 00 0e 00 00 00 19 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.1 PIC [0800]: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] (rev 01) (prog-if 10 [IO-APIC]) Subsystem: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at fc000000 (64-bit, non-prefetchable) [size=4K] 00: 22 10 51 74 06 00 00 02 01 10 00 08 00 00 00 00 10: 04 00 00 fc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 51 74 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 00 00 fc 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 33 Bus: primary=00, secondary=03, subordinate=03, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=00:0b.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream: Capacity=14 CommitmentLimit=65535 Downstream: Capacity=2 CommitmentLimit=65535 Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration 00: 22 10 50 74 17 00 30 02 12 00 04 06 00 21 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 20 f1 01 20 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 04 00 40: 04 00 0b 00 00 00 00 00 00 00 00 00 01 2c 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 c3 00 58 00 03 00 0e 00 ff ff 02 00 ff ff b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.1 PIC [0800]: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] (rev 01) (prog-if 10 [IO-APIC]) Subsystem: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at fc001000 (64-bit, non-prefetchable) [size=4K] 00: 22 10 51 74 06 00 00 02 01 10 00 08 00 00 00 00 10: 04 10 00 fc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 51 74 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 10 00 fc 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 600MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [a0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 800MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [c0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c8 0e 0f 1c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 74 04 01 02 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 3f 00 03 00 40 00 01 00 7f 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 fc 00 80 2f fe 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 03 c0 fe 00 00 c0 fe 00 03 0a 00 00 00 0b 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 33 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 01 00 00 00 01 10 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 ee e0 03 00 ee e0 03 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 70 00 00 00 00 00 00 00 25 31 62 03 20 09 10 00 90: 00 8c 2a 08 09 0c 2b 0a 00 00 00 00 09 04 40 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 1c 0b 58 dd a8 00 00 00 9d 3f 00 10 c1 06 f4 7b c0: 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 2f 00 23 10 8d 4c 41 36 ea 85 11 64 0c 5b 1c e0: 00 7e a0 89 f3 c0 00 81 f0 59 d2 98 53 44 3b cb f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: k8temp Kernel modules: k8temp 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 40 02 00 00 00 00 00 00 00 00 50: 48 48 8e 88 90 00 00 00 10 00 00 00 81 a2 20 02 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 40 02 aa 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 16 00 00 40 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 a7 e2 04 10 27 40 20 25 25 25 00 e0: 00 00 00 00 24 07 00 09 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [a0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 800MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [c0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c8 0e 0f 14 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 96 51 53 07 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: ac 02 50 01 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 3f 00 03 00 40 00 01 00 7f 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 fc 00 80 2f fe 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 03 c0 fe 00 00 c0 fe 00 03 0a 00 00 00 0b 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 33 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 fe e0 03 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 90 00 00 00 00 00 00 00 25 31 62 03 20 09 10 00 90: 00 8c 2a 08 09 0c 2b 0a 00 00 00 00 09 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 2c 47 a6 85 a8 00 00 00 03 24 ac 24 f0 50 73 70 c0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: ba a2 97 49 62 98 b5 3e d1 28 5f 41 40 03 7a 73 e0: 24 66 8f 2a 5e 5a 82 bf ea 64 b6 71 00 72 85 f1 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: k8temp Kernel modules: k8temp 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 40 02 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 10 00 00 00 c1 d9 2d 42 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 79 d6 ad 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 00 40 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 a7 e2 04 10 27 40 20 25 25 25 00 e0: 00 00 00 00 24 00 00 0a 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 USB Controller [0c03]: Advanced Micro Devices [AMD] AMD-8111 USB [1022:7464] (rev 0b) (prog-if 10 [OHCI]) Subsystem: Rioworks Device [161f:3016] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max) Interrupt: pin D routed to IRQ 19 Region 0: Memory at fc100000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 22 10 64 74 17 00 80 02 0b 10 03 0c 00 20 80 00 10: 00 00 10 fc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 1f 16 16 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 1f 16 16 30 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.1 USB Controller [0c03]: Advanced Micro Devices [AMD] AMD-8111 USB [1022:7464] (rev 0b) (prog-if 10 [OHCI]) Subsystem: Rioworks Device [161f:3016] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (20000ns max) Interrupt: pin D routed to IRQ 19 Region 0: Memory at fc101000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 22 10 64 74 17 00 80 02 0b 10 03 0c 00 20 00 00 10: 00 10 10 fc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 1f 16 16 30 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 1f 16 16 30 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:06.0 VGA compatible controller [0300]: ATI Technologies Inc Rage XL [1002:4752] (rev 27) (prog-if 00 [VGA controller]) Subsystem: ATI Technologies Inc Rage XL [1002:8008] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 66 (2000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M] Region 1: I/O ports at 2000 [size=256] Region 2: Memory at fc102000 (32-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at 80000000 [disabled] [size=128K] Capabilities: [5c] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel modules: atyfb 00: 02 10 52 47 87 00 90 02 27 00 00 03 10 42 00 00 10: 00 00 00 fd 01 20 00 00 00 20 10 fc 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 08 80 30: 00 00 00 00 5c 00 00 00 00 00 00 00 0a 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:03.0 Ethernet controller [0200]: Broadcom Corporation NetXtreme BCM5702X Gigabit Ethernet [14e4:16a6] (rev 02) Subsystem: Broadcom Corporation BCM5702 1000Base-T [14e4:000c] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (16000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 27 Region 0: Memory at fe000000 (64-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at 80180000 [disabled] [size=64K] Capabilities: [40] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=ff:1f.1 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Broadcom NetXtreme Gigabit Ethernet Controller Read-only fields: [PN] Part number: BCM95702A20 [EC] Engineering changes: 106679-15 [SN] Serial number: 0123456789 [MN] Manufacture ID: 31 34 65 34 [RV] Reserved: checksum bad, 25 byte(s) reserved Read/write fields: [YA] Asset tag: XYZ01234567 [RW] Read-write area: 107 byte(s) free End Capabilities: [58] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000100000000 Data: ffff Kernel driver in use: tg3 Kernel modules: tg3 00: e4 14 a6 16 06 00 b0 02 02 00 00 02 10 40 00 00 10: 04 00 00 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 fc 80 00 00 00 78 05 00 86 00 00 00 00 00 60: 01 00 00 00 ff ff 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 98 d6 bf 6a 34 00 13 04 82 10 08 00 90: 09 92 00 01 64 00 00 00 00 00 00 00 f6 01 00 00 a0: 00 00 00 00 2e 01 00 00 00 00 00 00 64 00 00 00 b0: 00 00 00 00 00 00 00 78 00 00 00 00 00 00 00 78 c0: 00 00 00 00 00 00 00 78 00 00 00 00 00 00 00 78 d0: 00 00 00 00 00 00 00 78 00 00 00 00 00 00 00 78 e0: 00 00 00 00 00 00 00 78 00 00 00 00 00 00 00 78 f0: 00 00 00 00 00 00 00 78 00 00 00 00 00 00 00 78 02:04.0 Ethernet controller [0200]: Broadcom Corporation NetXtreme BCM5702X Gigabit Ethernet [14e4:16a6] (rev 02) Subsystem: Broadcom Corporation BCM5702 1000Base-T [14e4:000c] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (16000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 27 Region 0: Memory at fe010000 (64-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at 80190000 [disabled] [size=64K] Capabilities: [40] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=ff:1f.1 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Broadcom NetXtreme Gigabit Ethernet Controller Read-only fields: [PN] Part number: BCM95702A20 [EC] Engineering changes: 106679-15 [SN] Serial number: 0123456789 [MN] Manufacture ID: 31 34 65 34 [RV] Reserved: checksum bad, 25 byte(s) reserved Read/write fields: [YA] Asset tag: XYZ01234567 [RW] Read-write area: 107 byte(s) free End Capabilities: [58] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000100000000 Data: ffff Kernel driver in use: tg3 Kernel modules: tg3 00: e4 14 a6 16 06 00 b0 02 02 00 00 02 10 40 00 00 10: 04 00 01 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 fc 80 00 00 00 78 05 00 86 00 00 00 00 00 60: 01 00 00 00 ff ff 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 bf 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 c3 ec eb a6 34 00 13 04 82 10 08 00 90: 09 92 00 01 00 00 00 37 00 00 00 00 f8 00 00 00 a0: 00 00 00 00 30 00 00 00 00 00 00 00 06 00 00 00 b0: 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 37 c0: 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 37 d0: 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 37 e0: 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 37 f0: 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 37 02:05.0 RAID bus controller [0104]: Silicon Image, Inc. SiI 3114 [SATALink/SATARaid] Serial ATA Controller [1095:3114] (rev 02) Subsystem: Silicon Image, Inc. SiI 3114 SATARaid Controller [1095:6114] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 25 Region 0: I/O ports at 3020 [size=8] Region 1: I/O ports at 3014 [size=4] Region 2: I/O ports at 3018 [size=8] Region 3: I/O ports at 3010 [size=4] Region 4: I/O ports at 3000 [size=16] Region 5: Memory at fe020000 (32-bit, non-prefetchable) [size=1K] [virtual] Expansion ROM at 80100000 [disabled] [size=512K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- Kernel driver in use: sata_sil Kernel modules: sata_sil 00: 95 10 14 31 07 00 b0 02 02 00 04 01 10 20 00 00 10: 21 30 00 00 15 30 00 00 19 30 00 00 11 30 00 00 20: 01 30 00 00 00 00 02 fe 00 00 00 00 95 10 14 61 30: 00 00 00 00 60 00 00 00 00 00 00 00 05 01 00 00 40: 02 00 00 00 00 02 08 09 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 22 06 00 40 00 64 00 00 00 00 00 00 00 00 70: 00 00 60 00 00 00 a5 36 00 00 60 00 00 00 00 00 80: 03 00 00 00 22 00 00 00 00 00 01 00 7f 70 fb fb 90: 00 00 00 09 ff ff 00 00 00 00 00 19 00 00 00 00 a0: 01 21 15 65 dd 62 dd 62 92 43 92 43 09 40 09 40 b0: 01 21 15 65 dd 62 dd 62 92 43 92 43 09 40 09 40 c0: 84 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 superiotool r4931 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xc0c0, rev=0xc0 Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0503, id=0x11e1 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 2a 2b 2c 2d 2e val e1 11 00 03 05 00 00 0f 00 00 10 00 18 00 def e1 11 00 03 00 00 00 NA 00 MM 00 00 00 RR LDN 0x00 (Floppy) idx 30 60 61 70 71 74 75 f0 f1 val 01 03 f0 06 03 02 04 20 00 def 00 03 f2 06 03 02 04 24 00 LDN 0x01 (Parallel port) idx 30 60 61 70 71 74 75 f0 val 01 03 78 07 02 04 04 f2 def 00 02 78 07 02 04 04 f2 LDN 0x02 (COM2) idx 30 60 61 70 71 74 75 f0 val 01 02 f8 03 03 04 04 02 def 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 def 00 03 f8 04 03 04 04 02 LDN 0x04 (System wake-up control (SWC)) idx 30 60 61 70 71 74 75 val 00 00 00 00 03 04 04 def 00 00 00 00 03 04 04 LDN 0x05 (Mouse) idx 30 70 71 74 75 val 01 0c 03 04 04 def 00 0c 02 04 04 LDN 0x06 (Keyboard) idx 30 60 61 62 63 70 71 74 75 f0 val 01 00 60 00 64 01 03 04 04 40 def 01 00 60 00 64 01 02 04 04 40 LDN 0x07 (GPIO) idx 30 60 61 70 71 74 75 f0 f1 f2 val 00 00 00 00 03 04 04 00 44 01 def 00 00 00 00 03 04 04 00 00 00 LDN 0x08 (ACCESS.bus (ACB)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x09 (Fan speed control and monitor (FSCM)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x0a (Watchdog timer) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 02 def 00 00 00 00 03 04 04 02 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xe1, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xc0, rev=0xc0 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xc0, rev=0xc0 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xc0/0x00, rev=0xc0 Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xc0/0x00, rev=0xc0 Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xc0/0x00, rev=0xc0 Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xc0/0x00, rev=0xc0 Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

1 0

[PATCH] Board-enable for MS-7025 (K8N Neo2 Platinum)
by Michael Karcher 21 Apr '10

21 Apr '10

now includes the PCI ID of the nForce3 MCP. AND THE RIGHT PATCH! Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ chipset_enable.c | 1 + print_wiki.c | 1 + 3 files changed, 12 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index f1f7953..5e7a774 100644 --- a/board_enable.c +++ b/board_enable.c @@ -523,6 +523,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ + case 0x00E0: /* nForce3 MCP */ break; default: /* Newer MCPs use the SMBus Controller */ @@ -586,6 +587,14 @@ static int nvidia_mcp_gpio8_raise(const char *name) } /** + * Suited for MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + MCP04. + */ +static int nvidia_mcp_gpio0c_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x0c, 1); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) @@ -1403,6 +1412,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..bbfcdaa 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1347,6 +1347,7 @@ const struct penable chipset_enables[] = { {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, + {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, diff --git a/print_wiki.c b/print_wiki.c index 87adf4d..720f387 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -263,6 +263,7 @@ const struct board_info_url boards_url[] = { { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=505" }, { "MSI", "MS-7005 (651M-L)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=559" }, { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, + { "MSI", "MS-7025 (K8N Neo2)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=587" }, { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=170" }, { "Shuttle", "AK31", "http://www.motherboard.cz/mb/shuttle/AK31.htm" }, { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, -- 1.7.0

1 0

[PATCH] Board-enable for MS-7025 (K8N Neo2 Platinum)
by Michael Karcher 21 Apr '10

21 Apr '10

now includes the PCI ID of the nForce3 MCP. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 9 +++++++++ chipset_enable.c | 1 + print_wiki.c | 1 + 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index f1f7953..15ddf2a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -586,6 +586,14 @@ static int nvidia_mcp_gpio8_raise(const char *name) } /** + * Suited for MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + MCP04. + */ +static int nvidia_mcp_gpio0c_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x0c, 1); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) @@ -1403,6 +1411,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..bbfcdaa 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1347,6 +1347,7 @@ const struct penable chipset_enables[] = { {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, + {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, diff --git a/print_wiki.c b/print_wiki.c index 87adf4d..720f387 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -263,6 +263,7 @@ const struct board_info_url boards_url[] = { { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=505" }, { "MSI", "MS-7005 (651M-L)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=559" }, { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, + { "MSI", "MS-7025 (K8N Neo2)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=587" }, { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=170" }, { "Shuttle", "AK31", "http://www.motherboard.cz/mb/shuttle/AK31.htm" }, { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, -- 1.7.0

1 0

MSI K8N Neo2 (Platinum) support
by rider 21 Apr '10

21 Apr '10

Here is the diagnostic information on MSI K8N Neo2 Platinum board.

2 1

[commit] r994 - trunk
by repository service 20 Apr '10

20 Apr '10

Author: ruik Date: Tue Apr 20 21:34:31 2010 New Revision: 994 URL: http://flashrom.org/trac/coreboot/changeset/994 Log: I added following Winbond chips: W25Q80, W25Q16 and W25Q32. I tested read/write/probe with W25Q80. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Apr 11 23:01:06 2010 (r993) +++ trunk/flashchips.c Tue Apr 20 21:34:31 2010 (r994) @@ -5593,6 +5593,108 @@ { .vendor = "Winbond", + .name = "W25Q80", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25Q80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", + .name = "W25Q16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25Q16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", + .name = "W25Q32", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25Q32, + .total_size = 4096, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W25x10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Apr 11 23:01:06 2010 (r993) +++ trunk/flashchips.h Tue Apr 20 21:34:31 2010 (r994) @@ -506,6 +506,9 @@ #define W_25X16 0x3015 #define W_25X32 0x3016 #define W_25X64 0x3017 +#define W_25Q80 0x4014 +#define W_25Q16 0x4015 +#define W_25Q32 0x4016 #define W_29C011 0xC1 #define W_29C020C 0x45 /* Same as W29C020 and ASD AE29F2008 */ #define W_29C040P 0x46 /* Same as W29C040 */

1 0

Successful flash of Asus Rampage II Extreme motherboard
by Stephen Pape 20 Apr '10

20 Apr '10

I was able to successfully write a new firmware image from Asus for a Rampage II Extreme using flashrom v0.9.1-r710 . It asked me to send the verbose log, as it was formerly untested, so it is attached. Thanks!

1 0

Re: [flashrom] ASUS A8N-VM CSM results (write/erase failed) / ASUS P2B-LS status?
by Keith Hui 19 Apr '10

19 Apr '10

> One note about the board testing Wiki page you may want to clarify: > > "To check if you can read the existing BIOS image from the chip, run flashrom > -r backup.bin. Make sure that backup.bin contains a useful BIOS image. (Some > chipsets will return 0xff for large areas of flash without any error > messages.)" > > For a BIOS newbie like me, the remark in parenthesis doesn't tell much - is it > a good or a bad sign if a chipset returns 0xff for large areas of flash > without any error messages? (Bad, I guess ;)) While booted with factory BIOS, make note of the BIOS version you currently have. Compare the backup image with a copy downloaded from ASUS. If they are mostly the same with only configuration store areas differing, you should be fine. --- By the way, what is the status of ASUS P2B-LS support? I reported here earlier that the same support mechanisms for P2B-F also work for the LS. And I have successfully flashed multiple times on a SST 39SF020 chip. Thanks Keith

1 0

SST25VF016B flash chip is not respondin in INTEL EP80579 PROCESSOR using Flashrom utility
by sougata barik 15 Apr '10

15 Apr '10

Hi, I am unable to use flashrom utility in my system. I am using EP80579 processor by Intel ans having one flashchip SST25VF061B which is connected to the processor by SPI interface. > [root@localhost flashrom-0.9.0]# ./flashrom -V > Calibrating delay loop... 339M loops per second, 100 myus = 198 us. OK. > No coreboot table found. > Found chipset "Intel EP80579", enabling flash write... > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0xd70260: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x0 (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3020 > 0x00: 0x800c (SPIS) > 0x02: 0x4140 (SPIC) > 0x04: 0x00000000 (SPIA) > 0x08: 0x0000411c (SPID0) > 0x0c: 0x00000000 (SPID0+4) > 0x10: 0x00000000 (SPID1) > 0x14: 0x00000000 (SPID1+4) > 0x18: 0x00000000 (SPID2) > 0x1c: 0x00000000 (SPID2+4) > 0x20: 0x00000000 (SPID3) > 0x24: 0x00000000 (SPID3+4) > 0x28: 0x00000000 (SPID4) > 0x2c: 0x00000000 (SPID4+4) > 0x30: 0x00000000 (SPID5) > 0x34: 0x00000000 (SPID5+4) > 0x38: 0x00000000 (SPID6) > 0x3c: 0x00000000 (SPID6+4) > 0x40: 0x00000000 (SPID7) > 0x44: 0x00000000 (SPID7+4) > 0x50: 0x00e00000 (BBAR) > 0x54: 0x5006 (PREOP) > 0x56: 0x163b (OPTYPE) > 0x58: 0x05200302 (OPMENU) > 0x5c: 0x00016090 (OPMENU+4) > 0x60: 0x00000000 (PBR0) > 0x64: 0x00000000 (PBR1) > 0x68: 0x00000000 (PBR2) > 0x6c: 0x00000000 (PBR3) > > WARNING: SPI Configuration Lockdown activated. > Generating OPCODES... done > SPI Read Configuration: prefetching disabled, caching enabled, OK. > Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0x00, id2 0x00 > Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for AMD Am29F080B, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Atmel AT25DF021, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF041A, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF081, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF161, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF321, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF321A, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25DF641, 8192 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25F512B, 64 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25FS010, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT25FS040, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT26DF041, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT26DF081A, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT26DF161, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT26DF161A, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT26F004, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Atmel AT45CS1282, 16896 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB011D, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB021D, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB041D, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB081D, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB161D, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB321C, 4224 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB321D, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT45DB642D, 8192 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for AMIC A25L40P, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x00, id2 0x00 > Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x00, id2 0x00 > Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff > Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff > Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff > Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff > Probing for Macronix MX25L512, 64 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L1005, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L2005, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L4005, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L8005, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L1605, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L1635D, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L3205, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L3235D, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L6405, 8192 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX25L12805, 16384 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x00, id2 0x00 > Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x00, id2 0x00 > Probing for Macronix MX29LV040C, 512 KB: probe_29f002: id1 0xff, id2 0xff > Probing for Numonyx M25PE10, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Numonyx M25PE20, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Numonyx M25PE40, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Numonyx M25PE80, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Numonyx M25PE16, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV010, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV016B, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV020, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV040, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV080B, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm25LV512, 64 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff > Probing for Spansion S25FL016A, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF016B, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF032B, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF040B, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF040.REMS, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF040B.REMS, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST25VF080B, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff > Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x0b, id2 0x72 > Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff > Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff > Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0x00, id2 0x00 > Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0x00, id2 0x00 > Probing for ST M25P05-A, 64 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P10-A, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P20, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P40, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P40-old, 512 KB: Transaction error! > run OPCODE 0x90 failed > Invalid OPCODE 0xab > Probing for ST M25P80, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P16, 2048 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P32, 4096 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P64, 8192 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M25P128, 16384 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff > Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff > Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff > Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff > Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff > Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x00, id2 0x00 > Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0x00, id2 0x00 > Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff > Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff > Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W25x10, 128 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Winbond W25x20, 256 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Winbond W25x40, 512 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Winbond W25x80, 1024 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xea, id2 0xd0 > Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W29EE011, 128 KB: > === > Probing disabled for Winbond W29EE011 because the probing sequence puts the > AMIC A49LF040A in a funky state. > Use 'flashrom -c W29EE011' if you have a board with this chip. > === > Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation > Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff > Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xff, did 0xff > Probing for Atmel unknown Atmel SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > Probing for EON unknown EON SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > Probing for Macronix unknown Macronix SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > Probing for PMC unknown PMC SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > Probing for SST unknown SST SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > Probing for ST unknown ST SPI chip, 0 KB: Transaction error! > run OPCODE 0x90 failed > No EEPROM/flash device found. > If you know which flash chip you have, and if this version of flashrom > supports a similar flash chip, you can try to force read your chip. Run: > flashrom -f -r -c similar_supported_flash_chip filename > > Note: flashrom can never write when the flash chip isn't found automatically. > [root@localhost flashrom-0.9.0]# > > [root@localhost flashrom-0.9.0]# ./flashrom > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel EP80579", enabling flash write... WARNING: SPI Configuration Lockdown activated. > OK. > No EEPROM/flash device found. > If you know which flash chip you have, and if this version of flashrom > supports a similar flash chip, you can try to force read your chip. Run: > flashrom -f -r -c similar_supported_flash_chip filename > > Note: flashrom can never write when the flash chip isn't found automatically. > [root@localhost flashrom-0.9.0]# please tell me what should I change to work this utility. Regards Sougata Please do not print this email unless it is absolutely necessary. The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com

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Board enable needed for MS-6309 Lite
by Milan Prvulovic 14 Apr '10

14 Apr '10

Exact name of my board is MSI MS-6309 Lite PCB revision 2.0 overview page - http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&p… BIOS download page - http://www.msi.com/index.php?func=downloaddetail&type=bios&maincat_no=1&pro…

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Re: [flashrom] [PATCH] Board enable (EC sleep) for Acer Ferrari 3400
by Michael Karcher 12 Apr '10

12 Apr '10

Am Montag, den 12.04.2010, 02:35 +0200 schrieb Magnus Alm: > OK, I got a problem now, tested "flashrom -EV", bad idea it seems, now > I cant write the BACKUP.ROM back. Oh, this looks like you *really* have a problem now. I'm sorry I didn't think of this case beforehand, but I seriously doubt that it is possible to fix the situation from within the running system. The problem on your system (which carldani correctly recognized) is the following. The data flow to the ROM chip is like Processor --HT--> Southbridge --LPC/FWH--> Embedded Controller --FWH--> Flash chip The embedded controller uses parts of the flash contents as instructions. There is one magic instruction (or two in your case) that make the EC spin in an idle loop that doesn't access the flash chip. In this configuration, the processor can access the flash chip as it likes to. But this idle loop drops all EC functionality like keyboard, mouse, fan control, brightness control, temperature monitoring and so on, so you should only use it for limited amounts of time. When the processor is finished with updating the flash chip, it sends a magic "exit the idle loop" instruction to the EC. Now, after you used flashrom -E on your flash chip, the EC program crashes when it tries to resume. On your system, it seemed to have the EC crashed so hard, that it doesn't pass the flash commands from the south bridge to the flash chip. As fan control is done by EC code in some systems, your situation might even cause overheating of the whole system until thermal breakdown. If your system is not damaged by heat, it is now in a configuration it is directly after manufacturing the board - so there definitely *is* a way to rewrite the flash chip in system, as vendors usually don't pre-program the flash chips before assembling the board. But this way might include special vendor tools in hardware (like test pins contacting the board on special position) or software (like a special protocal over JEDEC pins) we don't have. As your system is bricked anyway now, you could open it up and try to find the EC (a bigger chip, but not the northbridge, southbridge, graphics chip, LAN chip or audio chip) and check whether there is a usable datasheet for it. > Note: flashrom can never write when the flash chip isn't found automatically. And that is for a reason. If the flash chip is not found automatically, it means we didn't get the probe command to the chip. In times before we had these SPI firewalling chipsets (you don't have one), this was a clear indication that we also can't get erase or write commands to the chip. So erasing/writing if detection of a known chip fails is generally futile. I am sorry that I didn't think about the danger beforehands. I will definitely think about a protection mechanism that prevents this happening again before the patch goes into main flashrom. Regards, Michael Karcher

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Acer Ferrari 3400 doesn't work with Flashrom
by Magnus Alm 12 Apr '10

12 Apr '10

When running "sudo flashrom" I gett the following output: flashrom v0.9.1-r946 No coreboot table found. ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "VIA VT8235", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST39SF040" (512 KB, Parallel) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. After this the keyboard and touchpad stops working. Also one of the thermal sensors stops working too. Plugging in a usb mouse allows me to shut down the laptop nicely tho. >From syslog after: Apr 11 10:13:33 Ferry kernel: [ 488.402186] __ratelimit: 21 callbacks suppressed Apr 11 10:13:33 Ferry kernel: [ 488.402190] atkbd.c: Spurious ACK on isa0060/serio0. Some program might be trying access hardware directly. Apr 11 10:13:36 Ferry kernel: [ 490.588044] ACPI Exception: AE_TIME, Returned by Handler for [EmbeddedControl] (20090903/evregion-424) Apr 11 10:13:36 Ferry kernel: [ 490.588076] ACPI Error (psparse-0537): Method parse/execution failed [\_TZ_.THRM._TMP] (Node f7010a50), AE_TIME Apr 11 10:13:36 Ferry kernel: [ 491.272032] ACPI: EC: input buffer is not empty, aborting transaction Apr 11 10:13:36 Ferry kernel: [ 491.272048] ACPI Exception: AE_TIME, Returned by Handler for [EmbeddedControl] (20090903/evregion-424) Apr 11 10:13:36 Ferry kernel: [ 491.272076] ACPI Error (psparse-0537): Method parse/execution failed [\_TZ_.THRM._TMP] (Node f7010a50), AE_TIME Apr 11 10:13:38 Ferry kernel: [ 492.588031] ACPI: EC: input buffer is not empty, aborting transaction Running "sudo flashrom" once more after reboot will cause the laptop to reboot immediately. Shutting down and removing power cable and battery resets the condition so "sudo flashrom" just disables keyboard/touchpad. Running "sudo flashrom -r backup.rom" will cause the laptop to shut down immediately. I read some abut making support for a laptop but it seemed a bit complicated for me. /Magnus

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