- flashrom - mail.coreboot.org

[PATCH] Kill globals, initialize programmer-related variables explicitly
by Carl-Daniel Hailfinger 03 Jul '10

03 Jul '10

Kill global variables, constants and functions if local scope suffices. Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Kill some dead code. Rename global variables with namespace-polluting names. This is needed for libflashrom. Some of the const pointer to const changes may be excessive. Comments welcome. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-explicit_init/flash.h =================================================================== --- flashrom-explicit_init/flash.h (Revision 1066) +++ flashrom-explicit_init/flash.h (Arbeitskopie) @@ -300,7 +300,7 @@ int (*enable) (void); }; -extern struct board_pciid_enable board_pciid_enables[]; +extern const struct board_pciid_enable board_pciid_enables[]; struct board_info { const char *vendor; @@ -335,15 +335,15 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs, char *pcidev_bdf); #endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(struct pcidev_status *devs); +void print_supported_pcidevs(const struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -463,7 +463,7 @@ int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_3com[]; +extern const struct pcidev_status nics_3com[]; #endif /* gfxnvidia.c */ @@ -472,7 +472,7 @@ int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern struct pcidev_status gfx_nvidia[]; +extern const struct pcidev_status gfx_nvidia[]; #endif /* drkaiser.c */ @@ -481,7 +481,7 @@ int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); -extern struct pcidev_status drkaiser_pcidev[]; +extern const struct pcidev_status drkaiser_pcidev[]; #endif /* nicrealtek.c */ @@ -491,8 +491,8 @@ int nicrealtek_shutdown(void); void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_realtek[]; -extern struct pcidev_status nics_realteksmc1211[]; +extern const struct pcidev_status nics_realtek[]; +extern const struct pcidev_status nics_realteksmc1211[]; #endif /* nicnatsemi.c */ @@ -501,7 +501,7 @@ int nicnatsemi_shutdown(void); void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_natsemi[]; +extern const struct pcidev_status nics_natsemi[]; #endif /* satasii.c */ @@ -510,7 +510,7 @@ int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); -extern struct pcidev_status satas_sii[]; +extern const struct pcidev_status satas_sii[]; #endif /* atahpt.c */ @@ -519,7 +519,7 @@ int atahpt_shutdown(void); void atahpt_chip_writeb(uint8_t val, chipaddr addr); uint8_t atahpt_chip_readb(const chipaddr addr); -extern struct pcidev_status ata_hpt[]; +extern const struct pcidev_status ata_hpt[]; #endif /* ft2232_spi.c */ @@ -572,7 +572,7 @@ extern char *programmer_param; extern unsigned long flashbase; extern int verbose; -extern const char *flashrom_version; +extern const char * const flashrom_version; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -671,7 +671,6 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -extern void *spibar; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -683,6 +682,7 @@ /* ichspi.c */ extern int ichspi_lock; extern uint32_t ichspi_bbar; +extern void *ich_spibar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Index: flashrom-explicit_init/drkaiser.c =================================================================== --- flashrom-explicit_init/drkaiser.c (Revision 1066) +++ flashrom-explicit_init/drkaiser.c (Arbeitskopie) @@ -26,12 +26,12 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971 -struct pcidev_status drkaiser_pcidev[] = { +const struct pcidev_status drkaiser_pcidev[] = { {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; -uint8_t *drkaiser_bar; +static uint8_t *drkaiser_bar; int drkaiser_init(void) { Index: flashrom-explicit_init/it87spi.c =================================================================== --- flashrom-explicit_init/it87spi.c (Revision 1066) +++ flashrom-explicit_init/it87spi.c (Arbeitskopie) @@ -36,7 +36,7 @@ uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -int fast_spi = 1; +static int fast_spi = 1; /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 Index: flashrom-explicit_init/pcidev.c =================================================================== --- flashrom-explicit_init/pcidev.c (Revision 1066) +++ flashrom-explicit_init/pcidev.c (Arbeitskopie) @@ -25,11 +25,11 @@ uint32_t io_base_addr; struct pci_access *pacc; -struct pci_filter filter; +static struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, - struct pcidev_status *devs) + const struct pcidev_status *devs) { int i; /* FIXME: 64 bit memory BARs need a 64 bit addr. */ @@ -79,7 +79,7 @@ } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, - struct pcidev_status *devs, char *pcidev_bdf) + const struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; char *msg = NULL; @@ -125,7 +125,7 @@ return curaddr; } -void print_supported_pcidevs(struct pcidev_status *devs) +void print_supported_pcidevs(const struct pcidev_status *devs) { int i; Index: flashrom-explicit_init/gfxnvidia.c =================================================================== --- flashrom-explicit_init/gfxnvidia.c (Revision 1066) +++ flashrom-explicit_init/gfxnvidia.c (Arbeitskopie) @@ -27,7 +27,7 @@ uint8_t *nvidia_bar; -struct pcidev_status gfx_nvidia[] = { +const struct pcidev_status gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, Index: flashrom-explicit_init/nicrealtek.c =================================================================== --- flashrom-explicit_init/nicrealtek.c (Revision 1066) +++ flashrom-explicit_init/nicrealtek.c (Arbeitskopie) @@ -29,12 +29,12 @@ #define BIOS_ROM_ADDR 0xD4 #define BIOS_ROM_DATA 0xD7 -struct pcidev_status nics_realtek[] = { +const struct pcidev_status nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {}, }; -struct pcidev_status nics_realteksmc1211[] = { +const struct pcidev_status nics_realteksmc1211[] = { {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ {}, }; Index: flashrom-explicit_init/nic3com.c =================================================================== --- flashrom-explicit_init/nic3com.c (Revision 1066) +++ flashrom-explicit_init/nic3com.c (Arbeitskopie) @@ -31,10 +31,10 @@ #define PCI_VENDOR_ID_3COM 0x10b7 -uint32_t internal_conf; -uint16_t id; +static uint32_t internal_conf; +static uint16_t id; -struct pcidev_status nics_3com[] = { +const struct pcidev_status nics_3com[] = { /* 3C90xB */ {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, Index: flashrom-explicit_init/spi.c =================================================================== --- flashrom-explicit_init/spi.c (Revision 1066) +++ flashrom-explicit_init/spi.c (Arbeitskopie) @@ -28,7 +28,6 @@ #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; -void *spibar = NULL; void spi_prettyprint_status_register(struct flashchip *flash); Index: flashrom-explicit_init/satasii.c =================================================================== --- flashrom-explicit_init/satasii.c (Revision 1066) +++ flashrom-explicit_init/satasii.c (Arbeitskopie) @@ -28,7 +28,7 @@ uint8_t *sii_bar; uint16_t id; -struct pcidev_status satas_sii[] = { +const struct pcidev_status satas_sii[] = { {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, Index: flashrom-explicit_init/ft2232_spi.c =================================================================== --- flashrom-explicit_init/ft2232_spi.c (Revision 1066) +++ flashrom-explicit_init/ft2232_spi.c (Arbeitskopie) @@ -47,7 +47,7 @@ static struct ftdi_context ftdic_context; -int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); @@ -59,7 +59,7 @@ return 0; } -int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_read_data(ftdic, (unsigned char *) buf, size); Index: flashrom-explicit_init/chipset_enable.c =================================================================== --- flashrom-explicit_init/chipset_enable.c (Revision 1066) +++ flashrom-explicit_init/chipset_enable.c (Arbeitskopie) @@ -417,10 +417,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(spibar + 0x6c)); + mmio_readw(ich_spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; @@ -450,7 +450,7 @@ int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | ((ICH_BRRA(frap) & (1 << i)) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]); @@ -536,50 +536,50 @@ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ - spibar = rcrb + spibar_offset; + ich_spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(spibar + 0)); + mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(spibar + 2)); + mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(spibar + 4)); + mmio_readl(ich_spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(spibar + offs + 4), i); + mmio_readl(ich_spibar + offs + 4), i); } - ichspi_bbar = mmio_readl(spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x54)); + mmio_readw(ich_spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x56)); + mmio_readw(ich_spibar + 0x56)); msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x58)); + mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x5c)); + mmio_readl(ich_spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); } msg_pdbg("\n"); - if (mmio_readw(spibar) & (1 << 15)) { + if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(spibar + 4); + tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); @@ -590,7 +590,7 @@ msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = mmio_readl(spibar + 0x50); + tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -602,30 +602,30 @@ do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(spibar + 0x74)); + mmio_readl(ich_spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(spibar + 0x78)); + mmio_readl(ich_spibar + 0x78)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(spibar + 0x7C)); + mmio_readl(ich_spibar + 0x7C)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(spibar + 0x80)); + mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(spibar + 0x84)); + mmio_readl(ich_spibar + 0x84)); msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + mmio_readl(ich_spibar + 0x90)); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x94)); + mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x96)); + mmio_readw(ich_spibar + 0x96)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x98)); + mmio_readl(ich_spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x9C)); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(spibar + 0xB0)); + mmio_readl(ich_spibar + 0xB0)); if (tmp2 & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; Index: flashrom-explicit_init/flashrom.c =================================================================== --- flashrom-explicit_init/flashrom.c (Revision 1066) +++ flashrom-explicit_init/flashrom.c (Arbeitskopie) @@ -34,7 +34,7 @@ #include "flash.h" #include "flashchips.h" -const char *flashrom_version = FLASHROM_VERSION; +const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; @@ -89,26 +89,23 @@ ; #endif +/* programmer_param is programmer-specific, but it MUST NOT be initialized in + * programmer_init() because it is initialized in the command line parser. + */ char *programmer_param = NULL; -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/* Supported buses for the current programmer. */ +enum chipbustype buses_supported; /** * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; +struct decode_sizes max_rom_decode; +/* If nonzero, used as the start address of bottom-aligned flash. */ +unsigned long flashbase; + const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 { @@ -428,6 +425,21 @@ int programmer_init(void) { + /* Initialize all programmer specific data. */ + /* Default to unlimited decode sizes. */ + max_rom_decode = (const struct decode_sizes) { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff + }; + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Default to top aligned flash at 4 GB. */ + flashbase = 0; + return programmer_table[programmer].init(); } @@ -437,6 +449,7 @@ for (i = shutdown_fn_count - 1; i >= 0; i--) shutdown_fn[i].func(shutdown_fn[i].data); + /* FIXME: Clear the shutdown function array on shutdown or startup? */ return programmer_table[programmer].shutdown(); } @@ -512,8 +525,6 @@ return 0; } -unsigned long flashbase = 0; - int min(int a, int b) { return (a < b) ? a : b; Index: flashrom-explicit_init/layout.c =================================================================== --- flashrom-explicit_init/layout.c (Revision 1066) +++ flashrom-explicit_init/layout.c (Arbeitskopie) @@ -28,7 +28,7 @@ char *mainboard_vendor = NULL; char *mainboard_part = NULL; #endif -int romimages = 0; +static int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -39,7 +39,7 @@ char name[256]; } romlayout_t; -romlayout_t rom_entries[MAX_ROMLAYOUT]; +static romlayout_t rom_entries[MAX_ROMLAYOUT]; #if CONFIG_INTERNAL == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; Index: flashrom-explicit_init/ichspi.c =================================================================== --- flashrom-explicit_init/ichspi.c (Revision 1066) +++ flashrom-explicit_init/ichspi.c (Arbeitskopie) @@ -105,6 +105,8 @@ uint32_t ichspi_bbar = 0; +void *ich_spibar = NULL; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -134,17 +136,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - return mmio_readl(spibar + X); + return mmio_readl(ich_spibar + X); } static uint16_t REGREAD16(int X) { - return mmio_readw(spibar + X); + return mmio_readw(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) +#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -161,7 +163,7 @@ }; /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ -struct preop_opcode_pair pops[] = { +const struct preop_opcode_pair pops[] = { {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, {JEDEC_WREN, JEDEC_SE}, /* sector erase */ {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ @@ -177,7 +179,7 @@ /* Reasonable default configuration. Needs ad-hoc modifications if we * encounter unlisted opcodes. Fun. */ -OPCODES O_ST_M25P = { +static OPCODES O_ST_M25P = { { JEDEC_WREN, JEDEC_EWSR, @@ -194,7 +196,7 @@ } }; -OPCODES O_EXISTING = {}; +static OPCODES O_EXISTING = {}; static int find_opcode(OPCODES *op, uint8_t opcode) { @@ -337,15 +339,15 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, spibar + 0x50); - ichspi_bbar = mmio_readl(spibar + 0x50); + mmio_writel(minaddr, ich_spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, spibar + 0xA0); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_writel(minaddr, ich_spibar + 0xA0); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); Index: flashrom-explicit_init/print_wiki.c =================================================================== --- flashrom-explicit_init/print_wiki.c (Revision 1066) +++ flashrom-explicit_init/print_wiki.c (Arbeitskopie) @@ -26,7 +26,7 @@ #include "flash.h" #include "flashchips.h" -const char *wiki_header = "= Supported devices =\n\n\ +static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ @@ -34,16 +34,16 @@ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; #if CONFIG_INTERNAL == 1 -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ +static const char * const chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ ! align=\"left\" | Status\n\n"; -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const board_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; -const char *board_intro = "\ +static const char * const board_intro = "\ \n== Supported mainboards ==\n\n\ In general, it is very likely that flashrom works out of the box even if your \ mainboard is not listed below.\n\nThis is a list of mainboards where we have \ @@ -56,14 +56,14 @@ mainboards on the [[Mailinglist|mailing list]].\n"; #endif -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ ! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ | Probe\n| Read\n| Erase\n| Write\n\n"; -const char *programmer_section = "\ +static const char * const programmer_section = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ @@ -72,7 +72,7 @@ ! align=\"left\" | Status\n\n"; #if CONFIG_INTERNAL == 1 -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ +static const char * const laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ In general, flashing laptops is more difficult because laptops\n\n\ * often use the flash chip for stuff besides the BIOS,\n\ * often have special protection stuff which has to be handled by flashrom,\n\ @@ -124,7 +124,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) @@ -245,7 +245,7 @@ printf("\n|}\n\n|}\n"); } -static void print_supported_pcidevs_wiki(struct pcidev_status *devs) +static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; static int c = 0; Index: flashrom-explicit_init/udelay.c =================================================================== --- flashrom-explicit_init/udelay.c (Revision 1066) +++ flashrom-explicit_init/udelay.c (Arbeitskopie) @@ -26,7 +26,7 @@ #include "flash.h" /* loops per microsecond */ -unsigned long micro = 1; +static unsigned long micro = 1; __attribute__ ((noinline)) void myusec_delay(int usecs) { Index: flashrom-explicit_init/nicnatsemi.c =================================================================== --- flashrom-explicit_init/nicnatsemi.c (Revision 1066) +++ flashrom-explicit_init/nicnatsemi.c (Arbeitskopie) @@ -28,7 +28,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 -struct pcidev_status nics_natsemi[] = { +const struct pcidev_status nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, {}, Index: flashrom-explicit_init/print.c =================================================================== --- flashrom-explicit_init/print.c (Revision 1066) +++ flashrom-explicit_init/print.c (Arbeitskopie) @@ -173,7 +173,7 @@ const char *devicetype) { int i, j, boardcount_good = 0, boardcount_bad = 0; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Index: flashrom-explicit_init/dediprog.c =================================================================== --- flashrom-explicit_init/dediprog.c (Revision 1066) +++ flashrom-explicit_init/dediprog.c (Arbeitskopie) @@ -24,19 +24,21 @@ #include "spi.h" #define DEFAULT_TIMEOUT 3000 -usb_dev_handle *dediprog_handle; +static usb_dev_handle *dediprog_handle; -int dediprog_do_stuff(void); - -void print_hex(void *buf, size_t len) +#if 0 +/* Might be useful for other pieces of code as well. */ +static void print_hex(void *buf, size_t len) { size_t i; for (i = 0; i < len; i++) msg_pdbg(" %02x", ((uint8_t *)buf)[i]); } +#endif -struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) +/* Might be useful for other USB devices as well. static for now. */ +static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) { struct usb_bus *bus; struct usb_device *dev; @@ -323,10 +325,11 @@ return 0; } +#if 0 /* Leftovers from reverse engineering. Keep for documentation purposes until * completely understood. */ -int dediprog_do_stuff(void) +static int dediprog_do_stuff(void) { char buf[0x4]; /* SPI command processing starts here. */ @@ -341,7 +344,6 @@ return 1; msg_pdbg("Receiving response: "); print_hex(buf, JEDEC_RDID_INSIZE); -#if 0 /* URB 14-27 are more SPI commands. */ /* URB 28. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(0x0)) @@ -369,12 +371,10 @@ /* Command I is probably Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ /* Command J is probably Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ /* Bulk transfer sizes for Command I/J are always 512 bytes, rest is filled with 0xff. */ -#endif - msg_pinfo("All probes will fail because this driver is not hooked up " - "to the SPI infrastructure yet."); return 0; } +#endif int dediprog_shutdown(void) { Index: flashrom-explicit_init/board_enable.c =================================================================== --- flashrom-explicit_init/board_enable.c (Revision 1066) +++ flashrom-explicit_init/board_enable.c (Arbeitskopie) @@ -1577,7 +1577,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -struct board_pciid_enable board_pciid_enables[] = { +const struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -1661,11 +1661,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part) { - struct board_pciid_enable *board = board_pciid_enables; - struct board_pciid_enable *partmatch = NULL; + const struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -1714,9 +1714,9 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(void) { - struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *board = board_pciid_enables; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -1762,7 +1762,7 @@ int board_flash_enable(const char *vendor, const char *part) { - struct board_pciid_enable *board = NULL; + const struct board_pciid_enable *board = NULL; int ret = 0; if (part) -- http://www.hailfinger.org/

2 6

[commit] r1068 - trunk
by repository service 03 Jul '10

03 Jul '10

Author: hailfinger Date: Sat Jul 3 13:02:10 2010 New Revision: 1068 URL: http://flashrom.org/trac/coreboot/changeset/1068 Log: Kill global variables, constants and functions if local scope suffices. Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c trunk/buspirate_spi.c trunk/chipset_enable.c trunk/cli_classic.c trunk/dediprog.c trunk/dmi.c trunk/drkaiser.c trunk/flash.h trunk/flashrom.c trunk/ft2232_spi.c trunk/gfxnvidia.c trunk/ichspi.c trunk/it87spi.c trunk/jedec.c trunk/layout.c trunk/nic3com.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/pcidev.c trunk/physmap.c trunk/pm49fl00x.c trunk/print.c trunk/print_wiki.c trunk/satasii.c trunk/spi.c trunk/sst28sf040.c trunk/sst49lfxxxc.c trunk/sst_fwhub.c trunk/stm50flw0x0x.c trunk/udelay.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/board_enable.c Sat Jul 3 13:02:10 2010 (r1068) @@ -1577,7 +1577,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -struct board_pciid_enable board_pciid_enables[] = { +const struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -1661,11 +1661,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part) { - struct board_pciid_enable *board = board_pciid_enables; - struct board_pciid_enable *partmatch = NULL; + const struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -1714,9 +1714,9 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(void) { - struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *board = board_pciid_enables; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -1762,7 +1762,7 @@ int board_flash_enable(const char *vendor, const char *part) { - struct board_pciid_enable *board = NULL; + const struct board_pciid_enable *board = NULL; int ret = 0; if (part) Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/buspirate_spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -30,7 +30,7 @@ #undef FAKE_COMMUNICATION #ifndef FAKE_COMMUNICATION -int buspirate_serialport_setup(char *dev) +static int buspirate_serialport_setup(char *dev) { /* 115200bps, 8 databits, no parity, 1 stopbit */ sp_fd = sp_openserport(dev, 115200); @@ -44,7 +44,7 @@ #define sp_flush_incoming(...) 0 #endif -int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) +static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/chipset_enable.c Sat Jul 3 13:02:10 2010 (r1068) @@ -417,10 +417,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(spibar + 0x6c)); + mmio_readw(ich_spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; @@ -450,7 +450,7 @@ int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | ((ICH_BRRA(frap) & (1 << i)) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]); @@ -536,50 +536,50 @@ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ - spibar = rcrb + spibar_offset; + ich_spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(spibar + 0)); + mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(spibar + 2)); + mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(spibar + 4)); + mmio_readl(ich_spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(spibar + offs + 4), i); + mmio_readl(ich_spibar + offs + 4), i); } - ichspi_bbar = mmio_readl(spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x54)); + mmio_readw(ich_spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x56)); + mmio_readw(ich_spibar + 0x56)); msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x58)); + mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x5c)); + mmio_readl(ich_spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); } msg_pdbg("\n"); - if (mmio_readw(spibar) & (1 << 15)) { + if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(spibar + 4); + tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); @@ -590,7 +590,7 @@ msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = mmio_readl(spibar + 0x50); + tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -602,30 +602,30 @@ do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(spibar + 0x74)); + mmio_readl(ich_spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(spibar + 0x78)); + mmio_readl(ich_spibar + 0x78)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(spibar + 0x7C)); + mmio_readl(ich_spibar + 0x7C)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(spibar + 0x80)); + mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(spibar + 0x84)); + mmio_readl(ich_spibar + 0x84)); msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + mmio_readl(ich_spibar + 0x90)); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x94)); + mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x96)); + mmio_readw(ich_spibar + 0x96)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x98)); + mmio_readl(ich_spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x9C)); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(spibar + 0xB0)); + mmio_readl(ich_spibar + 0xB0)); if (tmp2 & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/cli_classic.c Sat Jul 3 13:02:10 2010 (r1068) @@ -31,7 +31,7 @@ #include "flash.h" #include "flashchips.h" -void cli_classic_usage(const char *name) +static void cli_classic_usage(const char *name) { const char *pname; int pnamelen; @@ -118,7 +118,7 @@ "flash chips.\n\n"); } -void cli_classic_abort_usage(void) +static void cli_classic_abort_usage(void) { printf("Please run \"flashrom --help\" for usage info.\n"); exit(1); @@ -166,6 +166,7 @@ char *filename = NULL; char *tempstr = NULL; + char *pparam = NULL; print_version(); print_banner(); @@ -287,10 +288,10 @@ if (strncmp(optarg, name, namelen) == 0) { switch (optarg[namelen]) { case ':': - programmer_param = strdup(optarg + namelen + 1); - if (!strlen(programmer_param)) { - free(programmer_param); - programmer_param = NULL; + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; } break; case '\0': @@ -381,9 +382,7 @@ /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); - msg_pdbg("Initializing %s programmer\n", - programmer_table[programmer].name); - if (programmer_init()) { + if (programmer_init(pparam)) { fprintf(stderr, "Error: Programmer initialization failed.\n"); exit(1); } Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/dediprog.c Sat Jul 3 13:02:10 2010 (r1068) @@ -24,19 +24,21 @@ #include "spi.h" #define DEFAULT_TIMEOUT 3000 -usb_dev_handle *dediprog_handle; +static usb_dev_handle *dediprog_handle; -int dediprog_do_stuff(void); - -void print_hex(void *buf, size_t len) +#if 0 +/* Might be useful for other pieces of code as well. */ +static void print_hex(void *buf, size_t len) { size_t i; for (i = 0; i < len; i++) msg_pdbg(" %02x", ((uint8_t *)buf)[i]); } +#endif -struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) +/* Might be useful for other USB devices as well. static for now. */ +static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) { struct usb_bus *bus; struct usb_device *dev; @@ -52,7 +54,7 @@ //int usb_control_msg(usb_dev_handle *dev, int requesttype, int request, int value, int index, char *bytes, int size, int timeout); -int dediprog_set_spi_voltage(uint16_t voltage) +static int dediprog_set_spi_voltage(uint16_t voltage) { int ret; unsigned int mv; @@ -85,6 +87,7 @@ return 0; } +#if 0 /* After dediprog_set_spi_speed, the original app always calls * dediprog_set_spi_voltage(0) and then * dediprog_check_devicestring() four times in a row. @@ -92,7 +95,7 @@ * This looks suspiciously like the microprocessor in the SF100 has to be * restarted/reinitialized in case the speed changes. */ -int dediprog_set_spi_speed(uint16_t speed) +static int dediprog_set_spi_speed(uint16_t speed) { int ret; unsigned int khz; @@ -140,6 +143,7 @@ } return 0; } +#endif int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -183,7 +187,7 @@ return 0; } -int dediprog_check_devicestring(void) +static int dediprog_check_devicestring(void) { int ret; char buf[0x11]; @@ -223,7 +227,7 @@ * dediprog_check_devicestring (often) or Command A (often) or * Command F (once). */ -int dediprog_command_a(void) +static int dediprog_command_a(void) { int ret; char buf[0x1]; @@ -242,7 +246,7 @@ * dediprog_command_a(); dediprog_check_devicestring() sequence in each session. * I'm tempted to call this one start_SPI_engine or finish_init. */ -int dediprog_command_c(void) +static int dediprog_command_c(void) { int ret; @@ -254,11 +258,12 @@ return 0; } +#if 0 /* Very strange. Seems to be a programmer keepalive or somesuch. * Wait unsuccessfully for timeout ms to read one byte. * Is usually called after setting voltage to 0. */ -int dediprog_command_f(int timeout) +static int dediprog_command_f(int timeout) { int ret; char buf[0x1]; @@ -271,6 +276,7 @@ } return 0; } +#endif /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) @@ -323,10 +329,11 @@ return 0; } +#if 0 /* Leftovers from reverse engineering. Keep for documentation purposes until * completely understood. */ -int dediprog_do_stuff(void) +static int dediprog_do_stuff(void) { char buf[0x4]; /* SPI command processing starts here. */ @@ -341,7 +348,6 @@ return 1; msg_pdbg("Receiving response: "); print_hex(buf, JEDEC_RDID_INSIZE); -#if 0 /* URB 14-27 are more SPI commands. */ /* URB 28. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(0x0)) @@ -369,12 +375,10 @@ /* Command I is probably Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ /* Command J is probably Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ /* Bulk transfer sizes for Command I/J are always 512 bytes, rest is filled with 0xff. */ -#endif - msg_pinfo("All probes will fail because this driver is not hooked up " - "to the SPI infrastructure yet."); return 0; } +#endif int dediprog_shutdown(void) { Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/dmi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -44,7 +44,7 @@ #else /* STANDALONE */ -const char *dmidecode_names[] = { +static const char *dmidecode_names[] = { "system-manufacturer", "system-product-name", "system-version", @@ -54,9 +54,9 @@ }; #define DMI_COMMAND_LEN_MAX 260 -const char *dmidecode_command = "dmidecode"; +static const char *dmidecode_command = "dmidecode"; -char *dmistrings[ARRAY_SIZE(dmidecode_names)]; +static char *dmistrings[ARRAY_SIZE(dmidecode_names)]; /* Strings longer than 4096 in DMI are just insane. */ #define DMI_MAX_ANSWER_LEN 4096 Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/drkaiser.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,12 +26,12 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971 -struct pcidev_status drkaiser_pcidev[] = { +const struct pcidev_status drkaiser_pcidev[] = { {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; -uint8_t *drkaiser_bar; +static uint8_t *drkaiser_bar; int drkaiser_init(void) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/flash.h Sat Jul 3 13:02:10 2010 (r1068) @@ -112,7 +112,7 @@ int register_shutdown(void (*function) (void *data), void *data); -int programmer_init(void); +int programmer_init(char *param); int programmer_shutdown(void); void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); @@ -300,7 +300,7 @@ int (*enable) (void); }; -extern struct board_pciid_enable board_pciid_enables[]; +extern const struct board_pciid_enable board_pciid_enables[]; struct board_info { const char *vendor; @@ -335,15 +335,15 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs, char *pcidev_bdf); #endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(struct pcidev_status *devs); +void print_supported_pcidevs(const struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -463,7 +463,7 @@ int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_3com[]; +extern const struct pcidev_status nics_3com[]; #endif /* gfxnvidia.c */ @@ -472,7 +472,7 @@ int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern struct pcidev_status gfx_nvidia[]; +extern const struct pcidev_status gfx_nvidia[]; #endif /* drkaiser.c */ @@ -481,7 +481,7 @@ int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); -extern struct pcidev_status drkaiser_pcidev[]; +extern const struct pcidev_status drkaiser_pcidev[]; #endif /* nicrealtek.c */ @@ -491,8 +491,8 @@ int nicrealtek_shutdown(void); void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_realtek[]; -extern struct pcidev_status nics_realteksmc1211[]; +extern const struct pcidev_status nics_realtek[]; +extern const struct pcidev_status nics_realteksmc1211[]; #endif /* nicnatsemi.c */ @@ -501,7 +501,7 @@ int nicnatsemi_shutdown(void); void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_natsemi[]; +extern const struct pcidev_status nics_natsemi[]; #endif /* satasii.c */ @@ -510,7 +510,7 @@ int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); -extern struct pcidev_status satas_sii[]; +extern const struct pcidev_status satas_sii[]; #endif /* atahpt.c */ @@ -519,7 +519,7 @@ int atahpt_shutdown(void); void atahpt_chip_writeb(uint8_t val, chipaddr addr); uint8_t atahpt_chip_readb(const chipaddr addr); -extern struct pcidev_status ata_hpt[]; +extern const struct pcidev_status ata_hpt[]; #endif /* ft2232_spi.c */ @@ -572,7 +572,7 @@ extern char *programmer_param; extern unsigned long flashbase; extern int verbose; -extern const char *flashrom_version; +extern const char * const flashrom_version; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -671,7 +671,6 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -extern void *spibar; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -683,6 +682,7 @@ /* ichspi.c */ extern int ichspi_lock; extern uint32_t ichspi_bbar; +extern void *ich_spibar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/flashrom.c Sat Jul 3 13:02:10 2010 (r1068) @@ -34,7 +34,7 @@ #include "flash.h" #include "flashchips.h" -const char *flashrom_version = FLASHROM_VERSION; +const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; @@ -91,23 +91,17 @@ char *programmer_param = NULL; -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/* Supported buses for the current programmer. */ +enum chipbustype buses_supported; /** * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; +struct decode_sizes max_rom_decode; + +/* If nonzero, used as the start address of bottom-aligned flash. */ +unsigned long flashbase; const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 @@ -402,7 +396,11 @@ struct shutdown_func_data { void (*func) (void *data); void *data; -} shutdown_fn[SHUTDOWN_MAXFN]; +} static shutdown_fn[SHUTDOWN_MAXFN]; +/* Initialize to 0 to make sure nobody registers a shutdown function before + * programmer init. + */ +static int may_register_shutdown = 0; /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will @@ -419,6 +417,11 @@ SHUTDOWN_MAXFN); return 1; } + if (!may_register_shutdown) { + msg_perr("Tried to register a shutdown function before " + "programmer init.\n"); + return 1; + } shutdown_fn[shutdown_fn_count].func = function; shutdown_fn[shutdown_fn_count].data = data; shutdown_fn_count++; @@ -426,17 +429,39 @@ return 0; } -int programmer_init(void) +int programmer_init(char *param) { + /* Initialize all programmer specific data. */ + /* Default to unlimited decode sizes. */ + max_rom_decode = (const struct decode_sizes) { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff + }; + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Default to top aligned flash at 4 GB. */ + flashbase = 0; + /* Registering shutdown functions is now allowed. */ + may_register_shutdown = 1; + + programmer_param = param; + msg_pdbg("Initializing %s programmer\n", + programmer_table[programmer].name); return programmer_table[programmer].init(); } int programmer_shutdown(void) { - int i; - - for (i = shutdown_fn_count - 1; i >= 0; i--) + /* Registering shutdown functions is no longer allowed. */ + may_register_shutdown = 0; + while (shutdown_fn_count > 0) { + int i = --shutdown_fn_count; shutdown_fn[i].func(shutdown_fn[i].data); + } return programmer_table[programmer].shutdown(); } @@ -512,8 +537,6 @@ return 0; } -unsigned long flashbase = 0; - int min(int a, int b) { return (a < b) ? a : b; @@ -1059,7 +1082,7 @@ /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ -int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(struct flashchip *flash) { int i, j, k; int ret = 0; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/ft2232_spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -47,7 +47,7 @@ static struct ftdi_context ftdic_context; -int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); @@ -59,7 +59,7 @@ return 0; } -int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_read_data(ftdic, (unsigned char *) buf, size); Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/gfxnvidia.c Sat Jul 3 13:02:10 2010 (r1068) @@ -27,7 +27,7 @@ uint8_t *nvidia_bar; -struct pcidev_status gfx_nvidia[] = { +const struct pcidev_status gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/ichspi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -105,6 +105,8 @@ uint32_t ichspi_bbar = 0; +void *ich_spibar = NULL; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -134,17 +136,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - return mmio_readl(spibar + X); + return mmio_readl(ich_spibar + X); } static uint16_t REGREAD16(int X) { - return mmio_readw(spibar + X); + return mmio_readw(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) +#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -161,7 +163,7 @@ }; /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ -struct preop_opcode_pair pops[] = { +const struct preop_opcode_pair pops[] = { {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, {JEDEC_WREN, JEDEC_SE}, /* sector erase */ {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ @@ -177,7 +179,7 @@ /* Reasonable default configuration. Needs ad-hoc modifications if we * encounter unlisted opcodes. Fun. */ -OPCODES O_ST_M25P = { +static OPCODES O_ST_M25P = { { JEDEC_WREN, JEDEC_EWSR, @@ -194,7 +196,7 @@ } }; -OPCODES O_EXISTING = {}; +static OPCODES O_EXISTING = {}; static int find_opcode(OPCODES *op, uint8_t opcode) { @@ -337,15 +339,15 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, spibar + 0x50); - ichspi_bbar = mmio_readl(spibar + 0x50); + mmio_writel(minaddr, ich_spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, spibar + 0xA0); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_writel(minaddr, ich_spibar + 0xA0); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/it87spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -36,7 +36,7 @@ uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -int fast_spi = 1; +static int fast_spi = 1; /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/jedec.c Sat Jul 3 13:02:10 2010 (r1068) @@ -38,7 +38,7 @@ return (val ^ (val >> 1)) & 0x1; } -void toggle_ready_jedec_common(chipaddr dst, int delay) +static void toggle_ready_jedec_common(chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; @@ -70,7 +70,7 @@ * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ -void toggle_ready_jedec_slow(chipaddr dst) +static void toggle_ready_jedec_slow(chipaddr dst) { toggle_ready_jedec_common(dst, 8 * 1000); } @@ -92,7 +92,7 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -void start_program_jedec_common(struct flashchip *flash, unsigned int mask) +static void start_program_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; chip_writeb(0xAA, bios + (0x5555 & mask)); @@ -100,7 +100,7 @@ chip_writeb(0xA0, bios + (0x5555 & mask)); } -int probe_jedec_common(struct flashchip *flash, unsigned int mask) +static int probe_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2; @@ -199,7 +199,7 @@ return 1; } -int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, +static int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, unsigned int pagesize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -229,7 +229,7 @@ return 0; } -int erase_block_jedec_common(struct flashchip *flash, unsigned int block, +static int erase_block_jedec_common(struct flashchip *flash, unsigned int block, unsigned int blocksize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -259,7 +259,7 @@ return 0; } -int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) +static int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) { int total_size = flash->total_size * 1024; chipaddr bios = flash->virtual_memory; @@ -288,7 +288,7 @@ return 0; } -int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, +static int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, chipaddr dst, unsigned int mask) { int tried = 0, failed = 0; @@ -335,7 +335,7 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, +static int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size, unsigned int mask) { int i, tried = 0, failed; @@ -374,7 +374,7 @@ return failed; } -int getaddrmask(struct flashchip *flash) +static int getaddrmask(struct flashchip *flash) { switch (flash->feature_bits & FEATURE_ADDR_MASK) { case FEATURE_ADDR_FULL: Modified: trunk/layout.c ============================================================================== --- trunk/layout.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/layout.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,7 @@ char *mainboard_vendor = NULL; char *mainboard_part = NULL; #endif -int romimages = 0; +static int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -39,7 +39,7 @@ char name[256]; } romlayout_t; -romlayout_t rom_entries[MAX_ROMLAYOUT]; +static romlayout_t rom_entries[MAX_ROMLAYOUT]; #if CONFIG_INTERNAL == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nic3com.c Sat Jul 3 13:02:10 2010 (r1068) @@ -31,10 +31,10 @@ #define PCI_VENDOR_ID_3COM 0x10b7 -uint32_t internal_conf; -uint16_t id; +static uint32_t internal_conf; +static uint16_t id; -struct pcidev_status nics_3com[] = { +const struct pcidev_status nics_3com[] = { /* 3C90xB */ {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nicnatsemi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 -struct pcidev_status nics_natsemi[] = { +const struct pcidev_status nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, {}, Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nicrealtek.c Sat Jul 3 13:02:10 2010 (r1068) @@ -29,12 +29,12 @@ #define BIOS_ROM_ADDR 0xD4 #define BIOS_ROM_DATA 0xD7 -struct pcidev_status nics_realtek[] = { +const struct pcidev_status nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {}, }; -struct pcidev_status nics_realteksmc1211[] = { +const struct pcidev_status nics_realteksmc1211[] = { {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ {}, }; Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/pcidev.c Sat Jul 3 13:02:10 2010 (r1068) @@ -25,11 +25,10 @@ uint32_t io_base_addr; struct pci_access *pacc; -struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, - struct pcidev_status *devs) + const struct pcidev_status *devs) { int i; /* FIXME: 64 bit memory BARs need a 64 bit addr. */ @@ -79,9 +78,10 @@ } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, - struct pcidev_status *devs, char *pcidev_bdf) + const struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; + struct pci_filter filter; char *msg = NULL; int found = 0; uint32_t addr = 0, curaddr = 0; @@ -125,7 +125,7 @@ return curaddr; } -void print_supported_pcidevs(struct pcidev_status *devs) +void print_supported_pcidevs(const struct pcidev_status *devs) { int i; Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/physmap.c Sat Jul 3 13:02:10 2010 (r1068) @@ -62,7 +62,7 @@ return realmem_map + phys_addr; } -void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(unsigned long phys_addr, size_t len) { int ret; __dpmi_meminfo mi; @@ -110,7 +110,7 @@ #define MEM_DEV "DirectIO" -void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(unsigned long phys_addr, size_t len) { return map_physical(phys_addr, len); } @@ -137,7 +137,7 @@ static int fd_mem_cached = -1; /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ -void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) +static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -157,7 +157,7 @@ /* For reading DMI/coreboot/whatever tables. We should never write, and we * do not care about caching. */ -void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -190,7 +190,7 @@ #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 -void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) +static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; Modified: trunk/pm49fl00x.c ============================================================================== --- trunk/pm49fl00x.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/pm49fl00x.c Sat Jul 3 13:02:10 2010 (r1068) @@ -23,7 +23,7 @@ #include "flash.h" #include "chipdrivers.h" -void write_lockbits_49fl00x(chipaddr bios, int size, +static void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) { int i, left = size; Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/print.c Sat Jul 3 13:02:10 2010 (r1068) @@ -73,7 +73,7 @@ return i; } -void print_supported_chips(void) +static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; struct flashchip *f; @@ -146,7 +146,7 @@ } #if CONFIG_INTERNAL == 1 -void print_supported_chipsets(void) +static void print_supported_chipsets(void) { int i, j, chipsetcount = 0; const struct penable *c = chipset_enables; @@ -169,11 +169,11 @@ } } -void print_supported_boards_helper(const struct board_info *boards, +static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { int i, j, boardcount_good = 0, boardcount_bad = 0; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/print_wiki.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,7 +26,7 @@ #include "flash.h" #include "flashchips.h" -const char *wiki_header = "= Supported devices =\n\n\ +static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ @@ -34,16 +34,16 @@ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; #if CONFIG_INTERNAL == 1 -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ +static const char * const chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ ! align=\"left\" | Status\n\n"; -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const board_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; -const char *board_intro = "\ +static const char * const board_intro = "\ \n== Supported mainboards ==\n\n\ In general, it is very likely that flashrom works out of the box even if your \ mainboard is not listed below.\n\nThis is a list of mainboards where we have \ @@ -56,14 +56,14 @@ mainboards on the [[Mailinglist|mailing list]].\n"; #endif -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ ! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ | Probe\n| Read\n| Erase\n| Write\n\n"; -const char *programmer_section = "\ +static const char * const programmer_section = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ @@ -72,7 +72,7 @@ ! align=\"left\" | Status\n\n"; #if CONFIG_INTERNAL == 1 -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ +static const char * const laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ In general, flashing laptops is more difficult because laptops\n\n\ * often use the flash chip for stuff besides the BIOS,\n\ * often have special protection stuff which has to be handled by flashrom,\n\ @@ -124,7 +124,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) @@ -245,7 +245,7 @@ printf("\n|}\n\n|}\n"); } -static void print_supported_pcidevs_wiki(struct pcidev_status *devs) +static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; static int c = 0; Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/satasii.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,9 +26,9 @@ #define PCI_VENDOR_ID_SII 0x1095 uint8_t *sii_bar; -uint16_t id; +static uint16_t id; -struct pcidev_status satas_sii[] = { +const struct pcidev_status satas_sii[] = { {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,6 @@ #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; -void *spibar = NULL; void spi_prettyprint_status_register(struct flashchip *flash); Modified: trunk/sst28sf040.c ============================================================================== --- trunk/sst28sf040.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst28sf040.c Sat Jul 3 13:02:10 2010 (r1068) @@ -69,7 +69,7 @@ return 0; } -int write_sector_28sf040(chipaddr bios, uint8_t *src, chipaddr dst, +static int write_sector_28sf040(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size) { int i; @@ -92,7 +92,7 @@ return 0; } -int erase_28sf040(struct flashchip *flash) +static int erase_28sf040(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; Modified: trunk/sst49lfxxxc.c ============================================================================== --- trunk/sst49lfxxxc.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst49lfxxxc.c Sat Jul 3 13:02:10 2010 (r1068) @@ -23,7 +23,7 @@ #include "flash.h" #include "chipdrivers.h" -int unlock_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) +static int write_lockbits_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) { unsigned long lock = flash->virtual_registers + address + 2; msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(lock)); @@ -40,31 +40,16 @@ msg_cdbg("\nbios=0x%08lx\n", registers); for (i = 0; left > 65536; i++, left -= 65536) { - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + (i * 65536) + 2, - chip_readb(registers + (i * 65536) + 2)); - chip_writeb(bits, registers + (i * 65536) + 2); + write_lockbits_block_49lfxxxc(flash, i * 65536, bits); } address = i * 65536; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 32768; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 8192; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 8192; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); return 0; } Modified: trunk/sst_fwhub.c ============================================================================== --- trunk/sst_fwhub.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst_fwhub.c Sat Jul 3 13:02:10 2010 (r1068) @@ -25,7 +25,7 @@ #include "flash.h" #include "chipdrivers.h" -int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -51,7 +51,7 @@ return blockstatus & 0x1; } -int clear_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int clear_sst_fwhub_block_lock(struct flashchip *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; Modified: trunk/stm50flw0x0x.c ============================================================================== --- trunk/stm50flw0x0x.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/stm50flw0x0x.c Sat Jul 3 13:02:10 2010 (r1068) @@ -36,7 +36,7 @@ * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, * before you can erase them or write to them. */ -int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) +static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + 2; const uint8_t unlock_sector = 0x00; Modified: trunk/udelay.c ============================================================================== --- trunk/udelay.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/udelay.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,7 +26,7 @@ #include "flash.h" /* loops per microsecond */ -unsigned long micro = 1; +static unsigned long micro = 1; __attribute__ ((noinline)) void myusec_delay(int usecs) { @@ -37,7 +37,7 @@ } } -unsigned long measure_os_delay_resolution(void) +static unsigned long measure_os_delay_resolution(void) { unsigned long timeusec; struct timeval start, end; @@ -61,7 +61,7 @@ return timeusec; } -unsigned long measure_delay(int usecs) +static unsigned long measure_delay(int usecs) { unsigned long timeusec; struct timeval start, end;

1 0

ASUS M3N78 PRO
by Brad Rogers 03 Jul '10

03 Jul '10

flashrom v0.9.2-r1028 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1032M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10024 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M3N78 PRO" DMI string baseboard-version: "1.XX" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8716 Found chipset "NVIDIA MCP78S", enabling flash write... chipset PCI ID is 10de:075c, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xfdf80000, after clearing low bits BAR is at 0xfdf80000 SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. 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Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. -- Regards _ / ) "The blindingly obvious is / _)rad never immediately apparent" I ain't got no time for intellectual music, e.g. Hergest Ridge Alberto y Lost Trios Paranoias

1 0

ASUSTeK Computer INC. M4N78-VM
by Rainer Stumbaum 03 Jul '10

03 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4N78-VM" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8712 Found chipset "NVIDIA MCP78S", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xf5f80000, after clearing low bits BAR is at 0xf5f80000 Mapping MCP67 SPI at 0xf5f80000, unaligned size 0x544. SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 607M loops per second, 100 myus = 173 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

Re: [flashrom] Porting flashrom to OpenBSD
by Carl-Daniel Hailfinger 02 Jul '10

02 Jul '10

On 28.06.2010 22:01, Stuart Henderson wrote: > On 2010/06/29 00:06, Ian McWilliam wrote: > >> On 28/06/2010, at 6:41 PM, Matthieu Herrb wrote: >> >> >>> On Sun, Jun 27, 2010 at 10:38:30PM +0200, Carl-Daniel Hailfinger wrote: >>> >>>> Could I ask you to write one or two short sentences which will be >>>> printed if flashrom detects insufficient permisions on OpenBSD? Maybe >>>> something like this (feel free to change it completely): >>>> >>>> "Error: Insufficient permissions to access hardware. Please set >>>> securelevel=-1 in /etc/rc.securelevel and reboot, or reboot into single >>>> user mode." >>>> >>> This message looks good to me. You could add "See the securelevel(7) >>> and init(8) manual pages for details". >>> >>> Thanks for your work on this port. >>> -- >>> Matthieu Herrb >>> > > I agree with both points :) > Thanks. >> I think in the port we could probably add a README.OpenBSD file where >> we could explain the situation in more detail like we do for many other ports >> stored in the share/doc/flashrom directory as well. >> > > We could, but I think it's even better to have proper instructions > for OpenBSD in the main distribution. > I added the message to strategic places in the code and the man page. Add OpenBSD support. Add a requirements section to the man page which lists the needed access permissions for each programmer. This patch needs the libpci 8/16-bit write patch I sent earlier. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-openbsd/flashrom.8 =================================================================== --- flashrom-openbsd/flashrom.8 (revision 1063) +++ flashrom-openbsd/flashrom.8 (working copy) @@ -306,7 +306,7 @@ Example: .B "flashrom \-p dummy:lpc,fwh" .TP -.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii\ +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii \ " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -391,6 +391,51 @@ .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +.SH REQUIREMENTS +flashrom needs different access permissions for different programmers. +.sp +.B internal +needs raw memory access, PCI configuration space access, raw I/O port +access (x86) and MSR access (x86). +.sp +.B it87spi +needs raw I/O port access (x86). +.sp +.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " +need PCI configuration space read access and raw I/O port access. +.sp +.B atahpt +needs PCI configuration space access and raw I/O port access. +.sp +.BR gfxnvidia " and " drkaiser +need PCI configuration space access and raw memory access. +.sp +.B satasii +needs PCI configuration space read access and raw memory access. +.sp +.B serprog +needs TCP access to the network or userspace access to a serial port. +.sp +.B buspirate_spi +needs userspace access to a serial port. +.sp +.BR dediprog " and " ft2232_spi +need access to the USB device via libusb. +.sp +.B dummy +needs no access permissions at all. +.sp +.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " +.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +have to be run as superuser/root, and need additional raw access permission. +.sp +.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +can be run as normal user on most operating systems if appropriate device +permissions are set. +.sp +On OpenBSD, you can obtain raw access permission by setting +securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single +user mode. .SH BUGS Please report any bugs at .sp Index: flashrom-openbsd/hwaccess.c =================================================================== --- flashrom-openbsd/hwaccess.c (revision 1063) +++ flashrom-openbsd/hwaccess.c (working copy) @@ -57,6 +57,11 @@ #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); +#if defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); +#endif exit(1); } #endif Index: flashrom-openbsd/hwaccess.h =================================================================== --- flashrom-openbsd/hwaccess.h (revision 1063) +++ flashrom-openbsd/hwaccess.h (working copy) @@ -228,17 +228,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Index: flashrom-openbsd/physmap.c =================================================================== --- flashrom-openbsd/physmap.c (revision 1063) +++ flashrom-openbsd/physmap.c (working copy) @@ -229,6 +229,10 @@ msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#elif defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); #endif if (!mayfail) exit(3); Index: flashrom-openbsd/Makefile =================================================================== --- flashrom-openbsd/Makefile (revision 1063) +++ flashrom-openbsd/Makefile (working copy) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,9 +263,13 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) endif endif endif +endif ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' Index: flashrom-openbsd/README =================================================================== --- flashrom-openbsd/README (revision 1063) +++ flashrom-openbsd/README (working copy) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. -- http://www.hailfinger.org/

2 3

[commit] r1067 - trunk
by repository service 02 Jul '10

02 Jul '10

Author: hailfinger Date: Fri Jul 2 19:12:50 2010 New Revision: 1067 URL: http://flashrom.org/trac/coreboot/changeset/1067 Log: Add OpenBSD support. Add a requirements section to the man page which lists the needed access permissions for each programmer. This feature needs my pciutils/libpci 8/16-bit write emulation patch at http://marc.info/?l=openbsd-ports&m=127780030728045 titled [PATCH] Fix pciutils non-32bit PCI write on OpenBSD Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stuart Henderson <sthen(a)openbsd.org> Modified: trunk/Makefile trunk/README trunk/flashrom.8 trunk/hwaccess.c trunk/hwaccess.h trunk/physmap.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/Makefile Fri Jul 2 19:12:50 2010 (r1067) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,6 +263,10 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) +endif endif endif endif Modified: trunk/README ============================================================================== --- trunk/README Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/README Fri Jul 2 19:12:50 2010 (r1067) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/flashrom.8 Fri Jul 2 19:12:50 2010 (r1067) @@ -306,7 +306,7 @@ Example: .B "flashrom \-p dummy:lpc,fwh" .TP -.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii\ +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii \ " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -391,6 +391,51 @@ .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +.SH REQUIREMENTS +flashrom needs different access permissions for different programmers. +.sp +.B internal +needs raw memory access, PCI configuration space access, raw I/O port +access (x86) and MSR access (x86). +.sp +.B it87spi +needs raw I/O port access (x86). +.sp +.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " +need PCI configuration space read access and raw I/O port access. +.sp +.B atahpt +needs PCI configuration space access and raw I/O port access. +.sp +.BR gfxnvidia " and " drkaiser +need PCI configuration space access and raw memory access. +.sp +.B satasii +needs PCI configuration space read access and raw memory access. +.sp +.B serprog +needs TCP access to the network or userspace access to a serial port. +.sp +.B buspirate_spi +needs userspace access to a serial port. +.sp +.BR dediprog " and " ft2232_spi +need access to the USB device via libusb. +.sp +.B dummy +needs no access permissions at all. +.sp +.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " +.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +have to be run as superuser/root, and need additional raw access permission. +.sp +.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +can be run as normal user on most operating systems if appropriate device +permissions are set. +.sp +On OpenBSD, you can obtain raw access permission by setting +securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single +user mode. .SH BUGS Please report any bugs at .sp Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.c Fri Jul 2 19:12:50 2010 (r1067) @@ -57,6 +57,11 @@ #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); +#if defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); +#endif exit(1); } #endif Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.h Fri Jul 2 19:12:50 2010 (r1067) @@ -228,17 +228,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/physmap.c Fri Jul 2 19:12:50 2010 (r1067) @@ -229,6 +229,10 @@ msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#elif defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); #endif if (!mayfail) exit(3);

1 0

(no subject)
by Benjamin 02 Jul '10

02 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Studio XPS 1340" DMI string system-version: "A11" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: " " DMI string baseboard-version: "A11" DMI string chassis-type: "Portable" Found chipset "NVIDIA MCP79", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xf0600000, after clearing low bits BAR is at 0xf0600000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. LPC on this chipset is not supported yet. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 671M loops per second, 100 myus = 197 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

[PATCH] ICH9/10: display FRAP/FREGx access controls
by Joshua Roys 01 Jul '10

01 Jul '10

Hello, Attached is a patch to display the FRAP access controls on the FREGx regions of the flash chip. Also attached is the output from `flashrom -Vr foo.bin' on an ICH10 machine. Thanks, Josh

2 7

[commit] r1066 - trunk
by repository service 01 Jul '10

01 Jul '10

Author: hailfinger Date: Thu Jul 1 19:45:54 2010 New Revision: 1066 URL: http://flashrom.org/trac/coreboot/changeset/1066 Log: ICH9/10: display FRAP/FREGx access controls Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 1 13:16:28 2010 (r1065) +++ trunk/chipset_enable.c Thu Jul 1 19:45:54 2010 (r1066) @@ -430,6 +430,44 @@ return 0; } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | + ((ICH_BRRA(frap) & (1 << i)) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(spibar + offset), base, limit; + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { @@ -554,21 +592,15 @@ tmp = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); - msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); - msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); - msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - - msg_pdbg("0x54: 0x%08x (FREG0)\n", - mmio_readl(spibar + 0x54)); - msg_pdbg("0x58: 0x%08x (FREG1)\n", - mmio_readl(spibar + 0x58)); - msg_pdbg("0x5C: 0x%08x (FREG2)\n", - mmio_readl(spibar + 0x5C)); - msg_pdbg("0x60: 0x%08x (FREG3)\n", - mmio_readl(spibar + 0x60)); - msg_pdbg("0x64: 0x%08x (FREG4)\n", - mmio_readl(spibar + 0x64)); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n",

1 0

[PATCH] Support for HP DL165 G6
by Arne Georg Gleditsch 01 Jul '10

01 Jul '10

Hi, Attached is a patch to board_enable.c for the HP DL165 board. Apparently, the PCI signature of the DL165 is identical to the DL145, but the enable pins are placed differently... :/ I'm not sure what the best way to handle that is. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

3 9

[commit] r1065 - trunk
by repository service 01 Jul '10

01 Jul '10

Author: hailfinger Date: Thu Jul 1 13:16:28 2010 New Revision: 1065 URL: http://flashrom.org/trac/coreboot/changeset/1065 Log: Add support for the HP DL165 G6. Change the match for the HP DL145 G3 to avoid matching on the DL165 G6. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Jun 29 16:44:40 2010 (r1064) +++ trunk/board_enable.c Thu Jul 1 13:16:28 2010 (r1065) @@ -648,6 +648,20 @@ return 0; } +/* + * Set GPIO lines in the Broadcom HT-1000 southbridge. + * + * It's not a Super I/O but it uses the same index/data port method. + */ +static int board_hp_dl165_g6_enable(void) +{ + /* Variant of DL145, with slightly different pin placement. */ + sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */ + sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */ + + return 0; +} + static int board_ibm_x3455(void) { /* raise gpio13 */ @@ -1607,7 +1621,8 @@ {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},

1 0

Re: [flashrom] [coreboot] [PATCH] superiotool: libsuperiodetect
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

On 30.06.2010 14:51, Stefan Reinauer wrote: > On 6/30/10 2:35 PM, Carl-Daniel Hailfinger wrote: > >> Using the superiotool code to detect SuperI/O chips can be really useful >> even for applications besides superiotool, e.g. flashrom. >> The biggest hurdle right now is the excessive size of the superiotool >> binary (>2.2 MB) which is still ~15 kB after lzma compression. That's >> simply unacceptable for a library. >> >> > Why? There is no size constraints on libraries in Unix like systems. > Yes, but if I proposed to increase the size of the flashrom binary by over 2 MBytes, various people would ask if I'm crazy. > Assuming we're talking about a static library > >From my system: > > 20M /usr/lib64/libbfd.a > 20M /usr/lib64/libc.a > 11M /usr/lib64/libcrypto.a > 19M /usr/lib64/libdb-4.5.a > 3.9M /usr/lib64/libfreetype.a > 5.1M /usr/lib64/libgio-2.0.a > 3.6M /usr/lib64/libglib-2.0.a > 3.3M /usr/lib64/libgmp.a > 2.8M /usr/lib64/libm.a > 2.8M /usr/lib64/libncurses.a > 3.2M /usr/lib64/libncursesw.a > 4.9M /usr/lib64/libopcodes.a > 4.2M /usr/lib64/libruby-static.a > 3.0M /usr/lib64/libssl.a > 6.9M /usr/lib64/libxml2.a > > Also, keep in mind that the size of the library in the filesystem is not > the size increase when linking it. > However, if all objects in the library are used, the size increase of the binary is correlated closely to the linked static library size. > 15kb lzma compressed is nothing. > 8 kB more or less in a recovery payload of a coreboot image are not negligible IMHO. In normal OS environments people don't use compressed binaries, and there a 2 MB size increase for flashrom (98% of it for dead code which can't be optimized away by the compiler/linker) is definitely something people will object to. >> This minimally invasive patch makes all dumping code optional and >> reduces binary size for the probe-only case (libsuperiodetect) a lot. >> Binary sizes: >> 2268258 (before) >> 31600 (after) 98.6% reduction >> LZMA compressed and stripped binary sizes: >> 14778 (before) >> 6709 (after) 54.6% reduction >> >> > Not worth the additional unreadability of the code in my opinion > > >> To test compilation of superiotool with probe-only functionality, run >> make CONFIG_LIB=yes >> >> This patch is the first step towards libsuperiodetect, and more will >> have to follow. >> >> > I think the idea for libsuperio is great. > > I'll gladly ack this without the very intrusive "we save 6700 bytes" > part of the patch. > The patch is a pure size reduction. If I remove the size reduction part, the patch will be empty. I can reduce the number of #ifdefs, but that won't make the patch prettier. Will send the patch with less #ifdefs in a separate mail. >> IMHO the {EOT} markers should be killed in libsuperiodetect, at least >> for the LDNs. Such an operation would have increased the size of the >> patch and would have reduced readability as well. Due to that, I skipped >> it, but I plan to do that in a later operation. >> >> > What would you use instead? The array members all have different sizes > as far as I can tell, so some kind of end marker will be needed. > The libsuperiodetect case doesn't care about LDNs at all. Having exactly one LDN definition per Super I/O which is always EOT looks like dead code to me, especially if nothing is looking at the LDN. >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> >> >> > > >> /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. */ >> @@ -765,7 +803,9 @@ >> uint8_t revreg) >> { >> uint8_t id, rev; >> +#ifndef LIBSUPERIODETECT >> uint16_t runtime_base; >> +#endif /* ! LIBSUPERIODETECT */ >> >> > Maybe this could be moved downwards to where it is used, to save an ifndef? > IIRC this would break on some compilers which don't allow variable declarations in the middle of some code. >> Index: superiotool_libsuperiodetect/superiotool.h >> =================================================================== >> --- superiotool_libsuperiodetect/superiotool.h (Revision 5651) >> +++ superiotool_libsuperiodetect/superiotool.h (Arbeitskopie) >> @@ -98,12 +98,19 @@ >> struct superio_registers { >> int32_t superio_id; /* Signed, as we need EOT. */ >> const char *name; /* Super I/O name */ >> +#ifndef LIBSUPERIODETECT >> struct { >> int8_t ldn; >> const char *name; /* LDN name */ >> int16_t idx[IDXSIZE]; >> int16_t def[IDXSIZE]; >> } ldn[LDNSIZE]; >> +#else /* LIBSUPERIODETECT */ >> + /* Ugly hack to avoid messing with EOT markers. */ >> + struct { >> + int8_t dummy; >> + } dummy[1]; >> +#endif /* LIBSUPERIODETECT */ >> }; >> >> > hm ... the comment is very terse. > struct dummy is there to avoid putting all those LDN {EOT} markers inside #ifndef LIBSUPERIODETECT. It is a hack to allow compilation and make the patch less invasive than it would have been without struct dummy. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[PATCH] superiotool: libsuperiodetect
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

Using the superiotool code to detect SuperI/O chips can be really useful even for applications besides superiotool, e.g. flashrom. The biggest hurdle right now is the excessive size of the superiotool binary (>2.2 MB) which is still ~15 kB after lzma compression. That's simply unacceptable for a library. This minimally invasive patch makes all dumping code optional and reduces binary size for the probe-only case (libsuperiodetect) a lot. Binary sizes: 2268258 (before) 31600 (after) 98.6% reduction LZMA compressed and stripped binary sizes: 14778 (before) 6709 (after) 54.6% reduction To test compilation of superiotool with probe-only functionality, run make CONFIG_LIB=yes This patch is the first step towards libsuperiodetect, and more will have to follow. IMHO the {EOT} markers should be killed in libsuperiodetect, at least for the LDNs. Such an operation would have increased the size of the patch and would have reduced readability as well. Due to that, I skipped it, but I plan to do that in a later operation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: superiotool_libsuperiodetect/fintek.c =================================================================== --- superiotool_libsuperiodetect/fintek.c (Revision 5651) +++ superiotool_libsuperiodetect/fintek.c (Arbeitskopie) @@ -31,6 +31,7 @@ static const struct superio_registers reg_table[] = { {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ +#ifndef LIBSUPERIODETECT /* We assume reserved bits are read as 0. */ {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, @@ -75,11 +76,13 @@ {0xa, "PME, ACPI", {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ {EOT}}}, {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */ /* We assume reserved bits are read as 0. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, 0x2b,0x2c,0x2d,EOT}, @@ -121,9 +124,11 @@ {0xa, "PME, ACPI", {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, {0x00,0x00,0x01,0x06,0x1c,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0604, "F71805F/FG", { /* We assume reserved bits are read as 0. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT}, {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}}, @@ -150,6 +155,7 @@ {0xa, "PME", {0x30,0xf0,0xf1,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0581, "F8000", { /* Fintek/ASUS F8000 */ {EOT}}}, @@ -181,7 +187,9 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("Fintek", reg_table, port, did, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_winbond_fintek_ite_8787(port); } Index: superiotool_libsuperiodetect/winbond.c =================================================================== --- superiotool_libsuperiodetect/winbond.c (Revision 5651) +++ superiotool_libsuperiodetect/winbond.c (Arbeitskopie) @@ -40,6 +40,7 @@ {0x527, "W83977CTF", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x52f, "W83977EF/EG", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -78,10 +79,12 @@ 0xf0,0xf1,0xf3,0xf4,0xf6,0xf7,0xf9,0xfe,0xff,EOT}, {0x00,0x00,0x00,0x00,MISC,MISC,MISC,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x595, "W83627SF", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x601, "W83697HF/F/HG", { /* No G version? */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, 0x2a,EOT}, @@ -126,12 +129,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x610, "W83L517D/D-F", { {EOT}}}, {0x708, "W83637HF/HG", { {EOT}}}, {0x828, "W83627THF/THG", { /* We assume rev is bits 3..0 of 0x21. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -175,12 +180,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, #if 0 {0x85x, "W83687THF", { /* TODO: sensors-detect: 0x85 */ {EOT}}}, #endif {0xa02, "W83627DHG", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -232,6 +239,7 @@ EOT}, {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */ {EOT}}}, @@ -250,6 +258,7 @@ */ {EOT}}}, {0x9773, "W83977TF", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x2a,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -294,12 +303,14 @@ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, NANA,MISC,RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x9774, "W83977ATF", { {EOT}}}, /* ID only */ {0x52, "W83627HF/F/HG/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, 0x2a,0x2b,0x2c,0x2e,0x2f,EOT}, @@ -342,6 +353,7 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x68, "W83697SF/UF/UG", { /* ID: 0x68 (for W83697SF/UF/UG) @@ -349,6 +361,7 @@ * 0x0X (for W83697SF) -- sic! * 0x1X (for W83697UF/UG) */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, 0x2b,0x2c,EOT}, @@ -405,6 +418,7 @@ {0xf, "GPIO 8", {0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0xff,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x88, "W83627EHF/EF/EHG/EG", { /* @@ -414,6 +428,7 @@ * (W83627EHF) has an ID of 0x8854 (verified on hardware). * So we now assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -460,12 +475,14 @@ {0xb, "Hardware monitor", {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, /* ID[3..0] */ {0xa, "W83877F", { {EOT}}}, {0xb, "W83877AF", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -475,6 +492,7 @@ 0x1f,0x0c,0x28,0xa3,RSVD,RSVD,0x00,0x00,0x00,0x00, 0x00,0x00,0x0e,0x00,MISC,MISC,MISC,MISC,MISC,MISC, MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xc, "W83877TF", { {EOT}}}, @@ -483,6 +501,7 @@ {EOT} }; +#ifndef LIBSUPERIODETECT static const struct superio_registers hwm_table[] = { {0x828, "W83627THF/THG", { {NOLDN, NULL, @@ -531,6 +550,7 @@ {EOT}}}, {EOT} }; +#endif /* ! LIBSUPERIODETECT */ static void enter_conf_mode_winbond_88(uint16_t port) { @@ -550,7 +570,10 @@ static void probe_idregs_winbond_helper(const char *init, uint16_t port) { - uint16_t id, hwmport; + uint16_t id; +#ifndef LIBSUPERIODETECT + uint16_t hwmport; +#endif /* LIBSUPERIODETECT */ uint8_t devid, rev, olddevid; probing_for("Winbond", init, port); @@ -586,6 +609,7 @@ get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("Winbond", reg_table, port, id, LDN_SEL); if (extra_dump) { @@ -607,6 +631,7 @@ dump_superio("Winbond-HWM", hwm_table, hwmport, id, WINBOND_HWM_SEL); } +#endif /* ! LIBSUPERIODETECT */ } void probe_idregs_winbond(uint16_t port) @@ -631,5 +656,7 @@ void print_winbond_chips(void) { print_vendor_chips("Winbond", reg_table); +#ifndef LIBSUPERIODETECT print_vendor_chips("Winbond-HWM", hwm_table); +#endif /* ! LIBSUPERIODETECT */ } Index: superiotool_libsuperiodetect/ite.c =================================================================== --- superiotool_libsuperiodetect/ite.c (Revision 5651) +++ superiotool_libsuperiodetect/ite.c (Arbeitskopie) @@ -30,6 +30,7 @@ {0x8228, "IT8228E", { {EOT}}}, {0x8502, "IT8502E/TE/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -67,10 +68,12 @@ {0x17, "Power Channel 3", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8510, "IT8510E/TE/G", { {EOT}}}, {0x8511, "IT8511E/TE/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -101,8 +104,10 @@ {0x12, "Power Channel 2", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8512, "IT8512E/F/G", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2A,0x2B,0x2C,0x2D,0x2E,EOT}, @@ -133,10 +138,12 @@ {0x12, "Power Channel 2", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8513, "IT8513E/F/G", { {EOT}}}, {0x8661, "IT8661F/IT8770F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, 0x23,0x24,EOT}, @@ -168,10 +175,12 @@ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8673, "IT8673F", { {EOT}}}, {0x8681, "IT8671F/IT8687R", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, 0x23,0x24,0x25,0x26,0x2e,0x2f,EOT}, @@ -211,8 +220,10 @@ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8701, "IT8703F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x23,0x24,0x26,0x29,0x2a,0x2b,EOT}, {0x87,0x00,0x00,0x80,0x00,0x00,0x7c,0xc0,EOT}}, @@ -253,10 +264,12 @@ {0xc, "GPIO set 5, 6 and 7", {0x30,0x60,0x61,0xf0,0xf3,0xf6,EOT}, {0x00,0x03,0x70,0x00,0xff,0xff,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8702, "IT8702F", { {EOT}}}, {0x8705, "IT8705F/AF / IT8700F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,EOT}, {0x87,0x05,0x00,0x00,NANA,EOT}}, @@ -303,11 +316,15 @@ {0x8, "MIDI port", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8706, "IT8706R", { /* TODO: Not yet in sensors-detect */ +#ifndef LIBSUPERIODETECT /* This is a "Special General Purpose I/O chip". */ +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8708, "IT8708F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2e,0x2f,EOT}, @@ -361,12 +378,14 @@ {0xa, "MIDI port", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8710, "IT8710F", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x8711, "IT8711F", { /* 0x8711 is a guess, not found in datasheet. */ {EOT}}}, {0x8712, "IT8712F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, @@ -416,8 +435,10 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8716, "IT8716F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x16,0x01,0x00,0x00,0x00,EOT}}, @@ -466,8 +487,10 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8718, "IT8718F", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x18,0x01,0x00,0x00,0x00,EOT}}, @@ -514,6 +537,7 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8720, "IT8720F", { /* From sensors-detect */ {EOT}}}, @@ -521,6 +545,7 @@ {EOT}}}, {0x8726, "IT8726F", { /* Datasheet wrongly says that the ID is 0x8716. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {0x87,0x26,0x01,0x00,MISC,0x00,EOT}}, @@ -571,6 +596,7 @@ {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, @@ -579,6 +605,7 @@ {EOT} }; +#ifndef LIBSUPERIODETECT static const struct superio_registers ec_table[] = { {0x8716, "IT8716F", { {NOLDN, NULL, @@ -636,6 +663,7 @@ {EOT}}}, {EOT} }; +#endif /* ! LIBSUPERIODETECT */ /* Works for: IT8661F/IT8770F */ static const uint8_t initkey_it8661f[][4] = { @@ -712,7 +740,10 @@ static void probe_idregs_ite_helper(const char *init, uint16_t port) { - uint16_t id, chipver, ecport; + uint16_t id, chipver; +#ifndef LIBSUPERIODETECT + uint16_t ecport; +#endif /* ! LIBSUPERIODETECT */ probing_for("ITE", init, port); @@ -730,6 +761,7 @@ get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("ITE", reg_table, port, id, LDN_SEL); if (extra_dump) { @@ -745,6 +777,7 @@ printf("Environment controller (0x%04x)\n", ecport); dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL); } +#endif /* ! LIBSUPERIODETECT */ } void probe_idregs_ite(uint16_t port) @@ -783,5 +816,7 @@ void print_ite_chips(void) { print_vendor_chips("ITE", reg_table); +#ifndef LIBSUPERIODETECT print_vendor_chips("ITE-EC", ec_table); +#endif /* ! LIBSUPERIODETECT */ } Index: superiotool_libsuperiodetect/nsc.c =================================================================== --- superiotool_libsuperiodetect/nsc.c (Revision 5651) +++ superiotool_libsuperiodetect/nsc.c (Arbeitskopie) @@ -26,6 +26,7 @@ static const struct superio_registers reg_table[] = { {0xcf, "PC97307", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x27,EOT}, {0xcf,MISC,MISC,0x00,0x00,NANA,EOT}}, @@ -60,8 +61,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xd0, "PC87317", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,EOT}, {0xd0,MISC,MISC,0x00,0x00,0x00,EOT}}, @@ -96,8 +99,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xdf, "PC97317", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x27,EOT}, {0xdf,MISC,MISC,0x00,0x00,0x00,NANA,EOT}}, @@ -132,8 +137,10 @@ {0x8, "Power management", {0x30,0x31,0x60,0x61,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe0, "PC87309", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x27,0x2e,EOT}, {0xe0,MISC,0x00,NANA,RSVD,EOT}}, @@ -162,8 +169,10 @@ 0xf0,EOT}, {0x01,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04, 0x40,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe1, "PC87360", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,EOT}, @@ -206,8 +215,10 @@ {0xa, "Watchdog timer", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe2, "PC87351", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x27,0x2e,EOT}, {0xe2,0x11,0xa1,0x00,MISC,NANA,RSVD,EOT}}, @@ -240,6 +251,7 @@ {0x8, "Fan speed control", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xe4, "PC87364", { {EOT}}}, @@ -248,6 +260,7 @@ {0xe8, "PC87363", { {EOT}}}, {0xe9, "PC87366", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x27,0x28,0x2a,0x2b, 0x2c,0x2d,0x2e,EOT}, @@ -304,10 +317,12 @@ {0xe, "Temperature sensor (TMS)", {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ {0xea, "PC8739x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -344,12 +359,14 @@ 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,EOT}, {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xec, "PC87591x", { /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */ {EOT}}}, {0xee, "PC8741x", { /* SRID[7..5] is marked as "not applicable for the PC8741x". */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -397,10 +414,12 @@ 0xf1,0xf2,0xf3,EOT}, {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00, 0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf0, "PC87372", { {EOT}}}, {0x0f1, "PC8374L", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -441,8 +460,10 @@ {0x8, "Health management", {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x8f1, "WPCD376I", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -480,9 +501,11 @@ 0xf2,0xf3,0xf8,EOT}, {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, 0x00,MISC,0x01,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf2, "PC87427", { /* SRID[7..5] is marked as "not applicable for the PC87427". */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x10,0x12,0x13,0x1d,0x20,0x21,0x22,0x23,0x24,0x25, 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, @@ -542,6 +565,7 @@ 0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, 0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0xf3, "PC87373", { {EOT}}}, @@ -592,8 +616,10 @@ get_superio_name(reg_table, magic), id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio(magic == 0x8f1 ? "Winbond" : "NSC", reg_table, port, magic, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ } void print_nsc_chips(void) Index: superiotool_libsuperiodetect/superiotool.c =================================================================== --- superiotool_libsuperiodetect/superiotool.c (Revision 5651) +++ superiotool_libsuperiodetect/superiotool.c (Arbeitskopie) @@ -81,6 +81,7 @@ return "<unknown>"; } +#ifndef LIBSUPERIODETECT static void dump_regs(const struct superio_registers reg_table[], int i, int j, uint16_t port, uint8_t ldn_sel) { @@ -170,6 +171,7 @@ printf("%02x ", INB(iobase + i)); printf("\n"); } +#endif /* ! LIBSUPERIODETECT */ void probing_for(const char *vendor, const char *info, uint16_t port) { @@ -189,9 +191,11 @@ for (i = 0; reg_table[i].superio_id != EOT; i++) { printf("%s %s", vendor, reg_table[i].name); +#ifndef LIBSUPERIODETECT /* Unless the ldn is empty, assume this chip has a dump. */ if (reg_table[i].ldn[0].ldn != EOT) printf(" (dump available)"); +#endif /* ! LIBSUPERIODETECT */ printf("\n"); } Index: superiotool_libsuperiodetect/ali.c =================================================================== --- superiotool_libsuperiodetect/ali.c (Revision 5651) +++ superiotool_libsuperiodetect/ali.c (Arbeitskopie) @@ -28,6 +28,7 @@ static const struct superio_registers reg_table[] = { /* TODO: M5113 doesn't seem to have ID registers? */ {0x5315, "M1535/M1535D/M1535+/M1535D+", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x1f,0x20,0x21,0x22,0x23,0x2c,0x2d,0x2e,EOT}, {NANA,0x53,0x15,0x00,0x00,RSVD,RSVD,RSVD,EOT}}, @@ -52,6 +53,7 @@ {0xc, "Hotkey", {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, {0x00,0x35,0x14,0x11,0x71,RSVD,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x2351, "M512x", { {EOT}}}, @@ -95,7 +97,9 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio("ALi", reg_table, port, id, LDN_SEL); +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_ali(port); } Index: superiotool_libsuperiodetect/smsc.c =================================================================== --- superiotool_libsuperiodetect/smsc.c (Revision 5651) +++ superiotool_libsuperiodetect/smsc.c (Arbeitskopie) @@ -30,6 +30,7 @@ static const struct superio_registers reg_table[] = { /* The following Super I/Os use the 0x20/0x21 ID registers. */ {0x02, "FDC37C932", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x2d,0x2e, 0x2f,EOT}, @@ -68,11 +69,13 @@ {0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00, 0x00,0x00,0x00,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, {0x0a, "FDC37N971", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -109,8 +112,10 @@ {0x9, "Mailbox", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0b, "FDC37N972", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -147,8 +152,10 @@ {0x9, "Mailbox", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x0e, "LPC47N252", { /* From sensors-detect */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -188,12 +195,14 @@ {0xa, "LPC/8051 addressable GPIO (LGPIO)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x14, "LPC47M172", { {EOT}}}, {0x30, "FDC37C93xAPM", { {EOT}}}, {0x40, "FDC37C67x", { /* E.g. FDC37C672. Chiprev: 0x01 */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b,0x2c, 0x2d,0x2e,0x2f,EOT}, @@ -225,10 +234,12 @@ {0x00,NANA,NANA,NANA,NANA,0x06,0x03,NANA,NANA,NANA, 0x00,0x00,0x00,MISC,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD, EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x42, "FDC37B80x/FDC37M707", { {EOT}}}, {0x09, "FDC37N958FR", { /* Found in e.g. Dell Latitude CPi A366XT. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -270,10 +281,12 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x43, "FDC37B77x", { {EOT}}}, {0x44, "FDC37B78x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -315,12 +328,14 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x46, "FDC37M602", { /* Found in Biostar M6TLD. */ {EOT}}}, {0x47, "FDC37M60x", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x4c, "FDC37B72x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -357,8 +372,10 @@ {0xa, "ACPI", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,NANA,NANA,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x4d, "FDC37M81x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b,0x2c, 0x2d,0x2e,0x2f,EOT}, @@ -389,8 +406,10 @@ {0x00,NANA,NANA,NANA,NANA,0x02,0x01,NANA,NANA,NANA, NANA,NANA,NANA,NANA,0x00,0x00,0x00,0x00,RSVD,RSVD, RSVD,RSVD,RSVD,RSVD,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x51, "LPC47B27x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -424,10 +443,12 @@ {0xb, "MIDI port (MPU-401)", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x52, "LPC47B37x", { {EOT}}}, {0x54, "LPC47U33x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2a,0x2b, 0x2c,0x2d,0x2e,0x2f,EOT}, @@ -459,12 +480,14 @@ {0xb, "SMBus", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x00,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x56, "LPC47B34x", { {EOT}}}, {0x57, "LPC47S42x", { {EOT}}}, {0x59, "LPC47M10x/112/13x", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -498,12 +521,14 @@ {0xb, "MPU-401", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x5d, "LPC47B357", { /* From sensors-detect (no datasheet) */ {EOT}}}, {0x5f, "LPC47M14x", { {EOT}}}, {0x60, "LPC47M15x/192/997", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -535,6 +560,7 @@ {0xb, "MPU-401", {0x30,0x60,0x61,0x70,EOT}, {0x00,0x03,0x30,0x05,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x62, "LPC47S45x", { {EOT}}}, @@ -550,6 +576,7 @@ {0x6f, "LPC47B397", { {EOT}}}, {0x74, "LPC47M182", { /* Only for LD_NUM = 0 */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27, 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -584,10 +611,12 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x76, "LPC47M584", { /* From sensors-detect (no datasheet) */ {EOT}}}, {0x77, "A8000", { /* ASUS A8000, a rebranded DME1737(?) */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -613,8 +642,10 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x78, "DME1737", { +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -640,6 +671,7 @@ {0xa, "Runtime registers", {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x79, "SCH5504", { /* From sensors-detect (no datasheet) */ {EOT}}}, @@ -682,6 +714,7 @@ {EOT}}}, {0x28, "FDC37N769", { /* Init: 0x55. Exit: 0xaa. Ports: 0x3f0/0x370. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -693,12 +726,14 @@ NANA,NANA,NANA,0x03,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD, 0x80,0x00,0x3c,RSVD,RSVD,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,RSVD,0x00,0x00,0x03,0x00,0x00,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x29, "FDC37N3869/FDC37N869", { /* Init: 0x55. Exit: 0xaa. Ports: 0x3f0/0x370. */ {EOT}}}, {0x5a, "LPC47N227", { /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -712,9 +747,11 @@ RSVD,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x80,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x5b, "SIO10N268", { /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ +#ifndef LIBSUPERIODETECT {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, @@ -734,6 +771,7 @@ 0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,0x50, NANA,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x01, 0x00,0x01,0x00,0x8c,MISC,EOT}}, +#endif /* ! LIBSUPERIODETECT */ {EOT}}}, {0x65, "FDC37C665GT/IR", { /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. */ @@ -765,7 +803,9 @@ uint8_t revreg) { uint8_t id, rev; +#ifndef LIBSUPERIODETECT uint16_t runtime_base; +#endif /* ! LIBSUPERIODETECT */ const char *info = (idreg == 0x20) ? "(idregs=0x20/0x21) " : "(idregs=0x0d/0x0e) "; @@ -788,6 +828,7 @@ id, rev, port); chip_found = 1; +#ifndef LIBSUPERIODETECT dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id, LDN_SEL); @@ -804,6 +845,7 @@ printf("No extra registers known for this chip.\n"); } } +#endif /* ! LIBSUPERIODETECT */ exit_conf_mode_smsc(port); } Index: superiotool_libsuperiodetect/superiotool.h =================================================================== --- superiotool_libsuperiodetect/superiotool.h (Revision 5651) +++ superiotool_libsuperiodetect/superiotool.h (Arbeitskopie) @@ -98,12 +98,19 @@ struct superio_registers { int32_t superio_id; /* Signed, as we need EOT. */ const char *name; /* Super I/O name */ +#ifndef LIBSUPERIODETECT struct { int8_t ldn; const char *name; /* LDN name */ int16_t idx[IDXSIZE]; int16_t def[IDXSIZE]; } ldn[LDNSIZE]; +#else /* LIBSUPERIODETECT */ + /* Ugly hack to avoid messing with EOT markers. */ + struct { + int8_t dummy; + } dummy[1]; +#endif /* LIBSUPERIODETECT */ }; /* pci.c */ Index: superiotool_libsuperiodetect/Makefile =================================================================== --- superiotool_libsuperiodetect/Makefile (Revision 5651) +++ superiotool_libsuperiodetect/Makefile (Arbeitskopie) @@ -32,6 +32,10 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) +ifeq ($(CONFIG_LIB), yes) +CFLAGS += -D'LIBSUPERIODETECT=1' +endif + OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o OS_ARCH = $(shell uname) -- http://www.hailfinger.org/

2 3

Re: [flashrom] Support of COM/LPT bit-bang SPI programmers in flashrom
by Carl-Daniel Hailfinger 30 Jun '10

30 Jun '10

On 29.06.2010 20:13, Andrew wrote: > 29.06.2010 20:18, Carl-Daniel Hailfinger пишет: >> would it be OK with you if I move this discussion to the flashrom >> mailing list? >> > Yes, it'll be good. Thanks. >> On 29.06.2010 19:11, Andrew wrote: >>> Is it possible to add support of some low-cost serial (for ex., >>> SI-Prog) >>> and parallel (for ex., Altera Byteblaster) SPI programming/interfacing >>> >> Yes. I have code for SPI bitbanging on the parallel port, but nobody has >> time to test. >> > I can test it in near future - I have some SPI flashes, and I have > 'universal' programmer (bunch of wires with protection resistors, 3.3V > power stabilizer and separate pins to connect to LPT holes - I use it > with SPIPGM; I assembled it when I need to program one SPI flash from MB) Oh, nice. I will update the SPIPGM support patch for flashrom and it would be great if you could test it. >>> devices? It'll be very useful (due to it's very simple schematic), and >>> IMHO it won't be much work to add them... >>> >> Sure. If someone sends me those devices, I can implement support for >> them. Or someone else uses my RayeR SPIPGM patch for flashrom and >> extends/changes it so it works with the Altera Byteblaster. >> > SPIPGM differs from ByteBlaster only by some LPT pins. + buffer. > Pinout for ByteBlasterMV: > JTAG (SPI) pins: > D0 -> TCK (SCK) > D1 -> TMS (CS-? or NC) > D6 -> TDI (SI) > Busy -> TDO (SO) > > Programmer pins (hardware detection): > D5 -> nACK > D7 -> PE (PaperEnd) via buffer (checking if buffer powered and > working) > nAutoFd -> buffer on (active in low) > nError -> pull-up to Vcc This can be supported easily by duplicating my SPIPGM driver. > For SI-Prog connection is also very simple: > SPI pins: > DSR -> SCK > DTR -> SI > CTS -> SO > > Programmer pins (hardware detection): > DSR -> RTS How does the SI-Prog handle CS? > About programmer detection pins - IMHO it'll be good to make hardware > detection, but just report hardware failure, not to break programming > process. Yes, a sanity check makes sense. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Check that the expected winbond Super I/O was found
by Carl-Daniel Hailfinger 29 Jun '10

29 Jun '10

On 29.06.2010 14:01, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1064 - trunk
by repository service 29 Jun '10

29 Jun '10

Author: mkarcher Date: Tue Jun 29 16:44:40 2010 New Revision: 1064 URL: http://flashrom.org/trac/coreboot/changeset/1064 Log: Check that the expected winbond Super I/O was found Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jun 27 17:07:52 2010 (r1063) +++ trunk/board_enable.c Tue Jun 29 16:44:40 2010 (r1064) @@ -264,6 +264,11 @@ msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; } + if (chip->device_id != chipid) { + msg_perr("\nERROR: Found Winbond chip with ID 0x%x, " + "expected %x\n", chip->device_id, chipid); + return -1; + } if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", pin);

1 0

[PATCH] Check that the expected winbond Super I/O was found
by Michael Karcher 29 Jun '10

29 Jun '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 940ecb9..9c88f0b 100644 --- a/board_enable.c +++ b/board_enable.c @@ -264,6 +264,11 @@ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; } + if (chip->device_id != chipid) { + msg_perr("\nERROR: Found Winbond chip with ID 0x%x, " + "expected %x\n", chip->device_id, chipid); + return -1; + } if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", pin); -- 1.7.1

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Re: [flashrom] Porting flashrom to OpenBSD
by Brynet 29 Jun '10

29 Jun '10

There is no sense having a port until the libpci/pci(4) issue is fixed, flashrom still doesn't work yet.. it compiles and runs, but AFAIK it always errors out. -Bryan.

2 1

[PATCH] Avoid scary warning if nothing changed
by Carl-Daniel Hailfinger 28 Jun '10

28 Jun '10

If flashrom encounters an erase or write error, it will complain loudly and tell the user that the flash chip is in an unknown state. Most of the time the erase/write failed completely, and this case can be detected by always reading the full chip before any write action and comparing the new contents against the old contents after any failed erase/write. This should spit out a much more harmless warning if write/erase failed, but the flash chip is completely unmodified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-always_read_no_scary_warning/flash.h =================================================================== --- flashrom-always_read_no_scary_warning/flash.h (Revision 1023) +++ flashrom-always_read_no_scary_warning/flash.h (Arbeitskopie) @@ -562,7 +562,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash(struct flashchip *flash, char *filename); +int read_flash_write_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); Index: flashrom-always_read_no_scary_warning/cli_classic.c =================================================================== --- flashrom-always_read_no_scary_warning/cli_classic.c (Revision 1023) +++ flashrom-always_read_no_scary_warning/cli_classic.c (Arbeitskopie) @@ -419,7 +419,7 @@ exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash(flashes[0], filename); + return read_flash_write_file(flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); Index: flashrom-always_read_no_scary_warning/flashrom.c =================================================================== --- flashrom-always_read_no_scary_warning/flashrom.c (Revision 1023) +++ flashrom-always_read_no_scary_warning/flashrom.c (Arbeitskopie) @@ -1003,12 +1003,10 @@ return ret; } -int read_flash(struct flashchip *flash, char *filename) +int write_buf_to_file(unsigned char *buf, unsigned long size, char *filename) { unsigned long numbytes; FILE *image; - unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { msg_gerr("Error: No filename specified.\n"); @@ -1018,23 +1016,32 @@ perror(filename); exit(1); } - msg_cinfo("Reading flash... "); - if (!flash->read) { - msg_cinfo("FAILED!\n"); - msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); - return 1; - } else - flash->read(flash, buf, 0, size); numbytes = fwrite(buf, 1, size, image); fclose(image); - free(buf); msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1; return 0; } +int read_flash_write_file(struct flashchip *flash, char *filename) +{ + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + + msg_cinfo("Reading flash... "); + if (!flash->read) { + msg_cinfo("FAILED!\n"); + msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); + return 1; + } + if (flash->read(flash, buf, 0, size)) + return 1; + + return write_buf_to_file(buf, flash->total_size * 1024, filename); +} + /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ @@ -1169,6 +1176,19 @@ return ret; } +void nonfatal_help_message(void) +{ + msg_gerr("Writing to the flash chip apparently didn't do anything.\n" + "This means we have to add special support for your board, " + "programmer or flash chip.\n" + "Please report this on IRC at irc.freenode.net (channel " + "#flashrom) or\n" + "mail flashrom(a)flashrom.org!\n" + "-------------------------------------------------------------" + "------------------\n" + "You may now reboot or simply leave the machine running.\n"); +} + void emergency_help_message(void) { msg_gerr("Your flash chip is in an unknown state.\n" @@ -1330,7 +1350,7 @@ */ int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) { - uint8_t *buf; + uint8_t *buf, *oldflashcontents; unsigned long numbytes; FILE *image; int ret = 0; @@ -1338,7 +1358,31 @@ size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); + oldflashcontents = (uint8_t *) calloc(size, sizeof(char)); + /* FIXME: This ignores --noverify. */ + if (read_it || write_it || erase_it) { + /* Useful for chips with read lock. */ + if (flash->unlock) + flash->unlock(flash); + + msg_cinfo("Reading flash... "); + if (!flash->read) { + msg_cinfo("FAILED!\n"); + msg_cerr("ERROR: flashrom has no read function for " + "this flash chip.\n"); + msg_cerr("Aborting.\n"); + programmer_shutdown(); + return 1; + } + if (flash->read(flash, oldflashcontents, 0, size)) { + msg_cinfo("FAILED!\n"); + msg_cerr("Aborting.\n"); + programmer_shutdown(); + return 1; + } + } + if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { msg_cerr("Erase is not working on this chip. "); @@ -1354,18 +1398,26 @@ flash->unlock(flash); if (erase_flash(flash)) { + msg_cerr("Uh oh. Erase failed. Checking if anything " + "changed.\n"); + if (!flash->read(flash, buf, 0, size)) { + if (!memcmp(oldflashcontents, buf, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; } } else if (read_it) { - if (flash->unlock) - flash->unlock(flash); + ret = write_buf_to_file(buf, flash->total_size * 1024, filename); - if (read_flash(flash, filename)) { - programmer_shutdown(); - return 1; - } + programmer_shutdown(); + return ret; } else { struct stat image_stat; @@ -1421,8 +1473,7 @@ } } - // This should be moved into each flash part's code to do it - // cleanly. This does the job. + /* FIXME: handle_romentries should reuse oldflashcontents. */ handle_romentries(buf, flash); // //////////////////////////////////////////////////////////// @@ -1436,7 +1487,18 @@ } ret = flash->write(flash, buf); if (ret) { - msg_cerr("FAILED!\n"); + msg_cerr("Uh oh. Write failed. Checking if anything " + "changed.\n"); + /* FIXME: Should we really reuse buf here? */ + if (!flash->read(flash, buf, 0, size)) { + if (!memcmp(oldflashcontents, buf, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; -- http://www.hailfinger.org/

2 3

Re: [flashrom] Porting flashrom to OpenBSD
by Carl-Daniel Hailfinger 28 Jun '10

28 Jun '10

Hi Stuart, hi Ian, thanks for the enthusiastic response. I added a few fixups to the flashrom tree in the meantime to get the OpenBSD patch size down a bit. After all, if it gets easier for you to test, we all win. Stuart, if this works for you, I'll commit the patches into flashrom subversion ASAP. My stated goal is to support every OS without the need for any local patches. A good first step to check if flashrom could run on your system is to run lspci. You may have to set machdep.allowaperture=2 and possibly other settings to get it working. flashrom uses raw memory access (/dev/mem), raw x86 port access (via inb/outb functions) and PCI access (via libpci). On 19.06.2010 03:38, Ian McWilliam wrote: > On 19/06/2010 10:42 AM, Stuart Henderson wrote: >> On 2010/06/19 02:33, Carl-Daniel Hailfinger wrote: >>> I'm one of the lead developers of flashrom, a GPLv2 application to >>> read/write/erase flash chips on mainboards, network/storage/graphics >>> cards and external programmers.[...] >>> >>> I have two patches which get flashrom to compile on OpenBSD on i386, >>> and >>> they should work on amd64 as well. Those patches will be merged into >>> the >>> official flashrom source tree once I know that they work. The big >>> obstacle for me is that I don't own any OpenBSD machine, and all I have >>> is shell access to a public OpenBSD i386 shell server. flashrom is >>> pretty small, you can compile it in ~5 seconds on a reasonably fast >>> machine, so compile testing shouldn't need too much time. >>> >> If you send me the patches I'll write a port Makefile for it. >> Then it's easier for people to test. Compile testing is no problem >> but I don't have any machines that I can spare to test actual bios >> updates on though. >> >> It would be great to have flashrom working on OpenBSD. > > I have 2 ASUS M2N-SLI deluxe motherboards that have a later bios > update that I can test under AMD64 && i386. > Create the port and throw my way for some testing. First patch (libpci fixups) is available at http://patchwork.coreboot.org/patch/1506/ (click the "patch" link there to download it). It is needed for gcc 3.x. The second patch (which has the actual OpenBSD support code) is below and will be available for download near the top of http://patchwork.coreboot.org/project/flashrom/list/ in case the patch gets mangled in transit. To compile flashrom, please check out svn://svn.coreboot.org/flashrom/trunk then apply the libpci fixup patch, then apply the patch below: Add OpenBSD support (i386 and amd64) to flashrom. Compile tested on i386. To compile flashrom, you need libpci from pciutils. flashrom expects /usr/local/include/pci/pci.h (see OpenBSD-specific CPPFLAGS in the Makefile patch) and /usr/local/lib/libpci.so or libpci.a or something which can be found by the linker. flashrom needs gmake. Depending on the cleanliness of your headers, you may have to set WARNERROR=no. Run gmake or gmake WARNERROR=no If /usr/local is not the place where ports end up, please tell me so I can fix the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-openbsd/hwaccess.h =================================================================== --- flashrom-openbsd/hwaccess.h (revision 1057) +++ flashrom-openbsd/hwaccess.h (working copy) @@ -221,17 +221,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Index: flashrom-openbsd/Makefile =================================================================== --- flashrom-openbsd/Makefile (revision 1057) +++ flashrom-openbsd/Makefile (working copy) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,9 +263,13 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) endif endif endif +endif ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' Index: flashrom-openbsd/README =================================================================== --- flashrom-openbsd/README (revision 1057) +++ flashrom-openbsd/README (working copy) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. -- http://www.hailfinger.org/

6 20

any recommended simple and cheap (USB) programmer?
by Stephan Raue 28 Jun '10

28 Jun '10

Hi all, i am looking for an simple and cheap programmer (i would prefer USB, because i want use it with my notebook) that i can use with linux tools and with flashrom support). it must be cheap, because i dont want program many BIOS chips and i would like it to buy in switzerland or germany (if possible). are there any recommendations? thanks and greetings Stephan -- ### OpenELEC.tv ### The free and open Mediacenter Distribution 4 you http://www.openelec.tv

1 0

flashrom -V : "NVIDIA MCP73"
by Noe 28 Jun '10

28 Jun '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Packard Bell BV" DMI string system-product-name: "IMEDIA D9181" DMI string system-version: "PB80134002" DMI string baseboard-manufacturer: "Packard Bell BV" DMI string baseboard-product-name: "MCP73VT-PM" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8718 Found chipset "NVIDIA MCP73", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:07d8 at 00:03:1 SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000 SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 682M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

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Re: [flashrom] Porting flashrom to OpenBSD
by Stuart Henderson 27 Jun '10

27 Jun '10

On 2010/06/26 14:47, Kevin Chadwick wrote: > On Fri, 25 Jun 2010 20:53:35 -0400 > Brynet <brynet(a)gmail.com> wrote: > > > I know of at least one OpenBSD developer wanting to update their BIOS > > from OpenBSD. > > Sorry, but it's an imperfect world and I'm sure everyone appreciates > your efforts. > > Personally I'd much prefer using a boot disk (OpenBSD or not) or > even a special kernel to do this and only this. I am disgusted with the > live updates of bios and video bios on windows. That's your opinion, feel free to handle flashing this way. Those who need to update flash ICs remotely and have experienced the pain of trying to get certain vendor tools to run under pxeboot + serial console will know there are cases where this is just not an option. > I'm sure that developer is perfectly capable of checksumming his bios > and updating. > > Many may not realise the risks, which are often there during every > boot and may not check their bioses or wish to do so so often. The ones > who do, may take precautions and still wish to do less checks. > > I'd prefer to know my bsd.rd environment cannot do this when I run > something from userland and the security of OpenBSD improved to the > highest level, when/if X solves the remaining issues. We already have a bios flasher in the ports tree (sysutils/dellflash). It requires special steps to be taken to use. Userland just does not and should not have this level of access to the system unless configuration changes are deliberately made. (In the case of dellflash, a kernel module handles access to the flash device which of course must be loaded before securelevel is raised). I don't see anybody here talking about permitting this sort of thing by default. It is at least going to take a reboot and either running in single- user mode or adjusting rc.securelevel. The system administrator must make a deliberate change; unless he is hard of thinking he will clearly understand that this will impact security.

2 1

Re: [flashrom] [PATCH 2/2] Board enable for Asus A8N-VM CSM
by Sean Nelson 27 Jun '10

27 Jun '10

I didn't see a Signoff, but I checked everything. Acked-by: Sean Nelson <audiohacked(a)gmail.com>

2 1

Re: [flashrom] [PATCH 1/2] W83627x code unification
by Sean Nelson 27 Jun '10

27 Jun '10

On 6/26/10 6:54 AM, Michael Karcher wrote: > This patch unifies the code for different Winbond W83627-family chips, > to be applied before I add another W83627 GPIO raise function. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > I've double checked with the datasheets, proof read, and did a compile test. I only saw one typo which I noted. Otherwise: Acked-by: Sean Nelson <audiohacked(a)gmail.com> > --- > board_enable.c | 206 ++++++++++++++++++++++++++++++++++++++++---------------- > 1 files changed, 148 insertions(+), 58 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 7d731c3..9a71f8f 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -134,86 +134,176 @@ static int fdc37b787_gpio50_raise_3f0(void) > return fdc37b787_gpio50_raise(0x3f0); > } > > -/** > - * Winbond W83627HF: Raise GPIO24. > - * > - * Suited for: > - * - Agami Aruma > - * - IWILL DK8-HTX > - */ > -static int w83627hf_gpio24_raise(uint16_t port) > -{ > - w836xx_ext_enter(port); > +struct winbond_mux { > + uint8_t reg; /* 0 if the corresponding pin is not muxed */ > + uint8_t data; /* reg/data/mask may be directly ... */ > + uint8_t mask; /* ... passed to sio_mask */ > +}; > > - /* Is this the W83627HF? */ > - if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ > - msg_perr("\nERROR: W83627HF: Wrong ID: 0x%02X.\n", > - sio_read(port, 0x20)); > - w836xx_ext_leave(port); > - return -1; > - } > +struct winbond_port { > + const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ > + uint8_t ldn; /* LDN this GPIO register is located in */ > + uint8_t enable_bit; /* bit in 0x30 of that LDN to enable > + the GPIO port */ > + uint8_t base; /* base register in that LDN for the port */ > +}; > > - /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ > - sio_mask(port, 0x2B, 0x10, 0x10); > +struct winbond_chip { > + uint8_t device_id; /* reg 0x20 of the expected w83626x */ > + uint8_t gpio_port_count; > + const struct winbond_port *port; > +}; > > - /* Select logical device 8: GPIO port 2 */ > - sio_write(port, 0x07, 0x08); > > - sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ > - sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ > - sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ > - sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ > +#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0} > > - w836xx_ext_leave(port); > +enum winbond_id { > + WINBOND_W83627HF_ID = 0x52, > + WINBOND_W83627THF_ID = 0x82, > +}; > > - return 0; > -} > +static const struct winbond_mux w83627hf_port2_mux[8] = { > + {0x2A, 0x01, 0x01}, /* or MIDI */ > + {0x2B, 0x80, 0x80}, /* or SPI */ > + {0x2B, 0x40, 0x40}, /* or SPI */ > + {0x2B, 0x20, 0x20}, /* or power LED */ > + {0x2B, 0x10, 0x10}, /* or watchdog */ > + {0x2B, 0x08, 0x08}, /* or infra red */ > + {0x2B, 0x04, 0x04}, /* or infra red */ > + {0x2B, 0x03, 0x03} /* or IRQ1 input */ > +}; > + > +static const struct winbond_port w83627hf[3] = { > + UNIMPLEMENTED_PORT, > + {w83627hf_port2_mux, 0x08, 0, 0xF0}, > + UNIMPLEMENTED_PORT > +}; > + > +static const struct winbond_mux w83627thf_port4_mux[8] = { > + {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */ > + {0x2D, 0x02, 0x02}, /* or resume reset */ > + {0x2D, 0x04, 0x04}, /* or S3 input */ > + {0x2D, 0x08, 0x08}, /* or PSON# */ > + {0x2D, 0x10, 0x10}, /* or PWROK */ > + {0x2D, 0x20, 0x20}, /* or suspend LED */ > + {0x2D, 0x40, 0x40}, /* or panel switch input */ > + {0x2D, 0x80, 0x80} /* or panel switch output */ > +}; > + > +static const struct winbond_port w83627thf[5] = { > + UNIMPLEMENTED_PORT, /* GPIO1 */ > + UNIMPLEMENTED_PORT, /* GPIO2 */ > + UNIMPLEMENTED_PORT, /* GPIO3 */ > + {w83627thf_port4_mux, 0x09, 1, 0xF4}, > + UNIMPLEMENTED_PORT /* GPIO5 */ > +}; > + > +static const struct winbond_chip winbond_chips[] = { > + {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf }, > + {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf}, > +}; > + > +/* Detects which Winbond Super I/O is responding at the given base > + address, but takes no effort to make sure the chip is really a > + Winbond Super I/O */ > > -static int w83627hf_gpio24_raise_2e(void) > +static const struct winbond_chip * winbond_superio_detect(uint16_t base) > { > - return w83627hf_gpio24_raise(0x2e); > + uint8_t chipid; > + const struct winbond_chip * chip = NULL; > + int i; > + > + w836xx_ext_enter(base); > + chipid = sio_read(base, 0x20); > + for (i = 0; i< ARRAY_SIZE(winbond_chips); i++) > + if (winbond_chips[i].device_id == chipid) > + { > + chip =&winbond_chips[i]; > + break; > + } > + > + w836xx_ext_leave(base); > + return chip; > } > > -/** > - * Winbond W83627THF: GPIO 4, bit 4 > - * > - * Suited for: > - * - MSI K8T Neo2-F > - * - MSI K8N-NEO3 > - */ > -static int w83627thf_gpio4_4_raise(uint16_t port) > +/* The chipid parameter goes away as soon as we have Super I/O matching in the > + board enable table. The call to winbond_superio_detect goes away as > + soon as we have generic Super I/O detection code. */ > +static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, > + int pin, int raise) > { > - w836xx_ext_enter(port); > + const struct winbond_chip * chip = NULL; > + const struct winbond_port * gpio; > + int port = pin / 10; > + int bit = pin % 10; > > - /* Is this the W83627THF? */ > - if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ > - msg_perr("\nERROR: W83627THF: Wrong ID: 0x%02X.\n", > - sio_read(port, 0x20)); > - w836xx_ext_leave(port); > + chip = winbond_superio_detect(base); > + if (!chip) { > + msg_perr("\nERROR: No supported Winbond Super I/O found\n"); > + return -1; > + } > + if (bit>= 8 || port == 0 || port> chip->gpio_port_count) { > + msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", > + pin); > return -1; > } > > - /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ > + gpio =&chip->port[port - 1]; > > - sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ > - sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ > - sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ > - sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ > - sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ > + w836xx_ext_enter(base); > > - w836xx_ext_leave(port); > + /* Select logical device */ > + sio_write(base, 0x07, gpio->ldn); > + > + /* Activate logical device. */ > + sio_mask(base, 0x30, 1<< gpio->enable_bit, 1<< gpio->enable_bit); > + > + /* Select GPIO function of that pin */ > + if(gpio->mux&& gpio->mux[bit].reg) > I remember Carl-Daniel wanted a space after the if. > + sio_mask(base, gpio->mux[bit].reg, > + gpio->mux[bit].data, gpio->mux[bit].mask); > + > + sio_mask(base, gpio->base + 0, 0, 1<< bit); /* make pin output */ > + sio_mask(base, gpio->base + 2, 0, 1<< bit); /* Clear inversion */ > + sio_mask(base, gpio->base + 1, raise<< bit, 1<< bit); > + > + w836xx_ext_leave(base); > > return 0; > } > > -static int w83627thf_gpio4_4_raise_2e(void) > +/** > + * Winbond W83627HF: Raise GPIO24. > + * > + * Suited for: > + * - Agami Aruma > + * - IWILL DK8-HTX > + */ > +static int w83627hf_gpio24_raise_2e() > +{ > + return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1); > +} > + > +/** > + * Winbond W83627THF: Raise GPIO 44. > + * > + * Suited for: > + * - MSI K8T Neo2-F > + */ > +static int w83627thf_gpio44_raise_2e() > { > - return w83627thf_gpio4_4_raise(0x2e); > + return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1); > } > > -static int w83627thf_gpio4_4_raise_4e(void) > +/** > + * Winbond W83627THF: Raise GPIO 44. > + * > + * Suited for: > + * - MSI K8N Neo3 > + */ > +static int w83627thf_gpio44_raise_4e() > { > - return w83627thf_gpio4_4_raise(0x4e); > + return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1); > } > > /** > @@ -1485,12 +1575,12 @@ struct board_pciid_enable board_pciid_enables[] = { > {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, > {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, > {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, > - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, > + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, > {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, > {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, > {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, > {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, > - {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, > + {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, > {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, > {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, > {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, >

2 1

[commit] r1063 - trunk
by repository service 27 Jun '10

27 Jun '10

Author: mkarcher Date: Sun Jun 27 17:07:52 2010 New Revision: 1063 URL: http://flashrom.org/trac/coreboot/changeset/1063 Log: Board enable for Asus A8N-VM CSM Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jun 27 17:07:49 2010 (r1062) +++ trunk/board_enable.c Sun Jun 27 17:07:52 2010 (r1063) @@ -159,6 +159,7 @@ enum winbond_id { WINBOND_W83627HF_ID = 0x52, + WINBOND_W83627EHF_ID = 0x88, WINBOND_W83627THF_ID = 0x82, }; @@ -179,6 +180,26 @@ UNIMPLEMENTED_PORT }; +static const struct winbond_mux w83627ehf_port2_mux[8] = { + {0x29, 0x06, 0x02}, /* or MIDI */ + {0x29, 0x06, 0x02}, + {0x24, 0x02, 0x00}, /* or SPI ROM interface */ + {0x24, 0x02, 0x00}, + {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */ + {0x2A, 0x01, 0x01}, + {0x2A, 0x01, 0x01}, + {0x2A, 0x01, 0x01} +}; + +static const struct winbond_port w83627ehf[6] = { + UNIMPLEMENTED_PORT, + {w83627ehf_port2_mux, 0x09, 0, 0xE3}, + UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT +}; + static const struct winbond_mux w83627thf_port4_mux[8] = { {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */ {0x2D, 0x02, 0x02}, /* or resume reset */ @@ -200,6 +221,7 @@ static const struct winbond_chip winbond_chips[] = { {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf }, + {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf}, {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf}, }; @@ -291,6 +313,17 @@ } /** + * Winbond W83627EHF: Raise GPIO24. + * + * Suited for: + * - Asus A8N VM CSM + */ +static int w83627ehf_gpio24_raise_2e() +{ + return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1); +} + +/** * Winbond W83627THF: Raise GPIO 44. * * Suited for: @@ -1549,6 +1582,7 @@ {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio24_raise_2e}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},

1 0

[commit] r1062 - trunk
by repository service 27 Jun '10

27 Jun '10

Author: mkarcher Date: Sun Jun 27 17:07:49 2010 New Revision: 1062 URL: http://flashrom.org/trac/coreboot/changeset/1062 Log: W83627x code unification This patch unifies the code for different Winbond W83627-family chips, to be applied before I add another W83627 GPIO raise function. After the Ack I added the check for unimplemented GPIO ports, but still dared to reuse the ack. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jun 25 15:18:48 2010 (r1061) +++ trunk/board_enable.c Sun Jun 27 17:07:49 2010 (r1062) @@ -134,86 +134,182 @@ return fdc37b787_gpio50_raise(0x3f0); } -/** - * Winbond W83627HF: Raise GPIO24. - * - * Suited for: - * - Agami Aruma - * - IWILL DK8-HTX - */ -static int w83627hf_gpio24_raise(uint16_t port) +struct winbond_mux { + uint8_t reg; /* 0 if the corresponding pin is not muxed */ + uint8_t data; /* reg/data/mask may be directly ... */ + uint8_t mask; /* ... passed to sio_mask */ +}; + +struct winbond_port { + const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ + uint8_t ldn; /* LDN this GPIO register is located in */ + uint8_t enable_bit; /* bit in 0x30 of that LDN to enable + the GPIO port */ + uint8_t base; /* base register in that LDN for the port */ +}; + +struct winbond_chip { + uint8_t device_id; /* reg 0x20 of the expected w83626x */ + uint8_t gpio_port_count; + const struct winbond_port *port; +}; + + +#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0} + +enum winbond_id { + WINBOND_W83627HF_ID = 0x52, + WINBOND_W83627THF_ID = 0x82, +}; + +static const struct winbond_mux w83627hf_port2_mux[8] = { + {0x2A, 0x01, 0x01}, /* or MIDI */ + {0x2B, 0x80, 0x80}, /* or SPI */ + {0x2B, 0x40, 0x40}, /* or SPI */ + {0x2B, 0x20, 0x20}, /* or power LED */ + {0x2B, 0x10, 0x10}, /* or watchdog */ + {0x2B, 0x08, 0x08}, /* or infra red */ + {0x2B, 0x04, 0x04}, /* or infra red */ + {0x2B, 0x03, 0x03} /* or IRQ1 input */ +}; + +static const struct winbond_port w83627hf[3] = { + UNIMPLEMENTED_PORT, + {w83627hf_port2_mux, 0x08, 0, 0xF0}, + UNIMPLEMENTED_PORT +}; + +static const struct winbond_mux w83627thf_port4_mux[8] = { + {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */ + {0x2D, 0x02, 0x02}, /* or resume reset */ + {0x2D, 0x04, 0x04}, /* or S3 input */ + {0x2D, 0x08, 0x08}, /* or PSON# */ + {0x2D, 0x10, 0x10}, /* or PWROK */ + {0x2D, 0x20, 0x20}, /* or suspend LED */ + {0x2D, 0x40, 0x40}, /* or panel switch input */ + {0x2D, 0x80, 0x80} /* or panel switch output */ +}; + +static const struct winbond_port w83627thf[5] = { + UNIMPLEMENTED_PORT, /* GPIO1 */ + UNIMPLEMENTED_PORT, /* GPIO2 */ + UNIMPLEMENTED_PORT, /* GPIO3 */ + {w83627thf_port4_mux, 0x09, 1, 0xF4}, + UNIMPLEMENTED_PORT /* GPIO5 */ +}; + +static const struct winbond_chip winbond_chips[] = { + {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf }, + {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf}, +}; + +/* Detects which Winbond Super I/O is responding at the given base + address, but takes no effort to make sure the chip is really a + Winbond Super I/O */ + +static const struct winbond_chip * winbond_superio_detect(uint16_t base) { - w836xx_ext_enter(port); + uint8_t chipid; + const struct winbond_chip * chip = NULL; + int i; - /* Is this the W83627HF? */ - if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ - msg_perr("\nERROR: W83627HF: Wrong ID: 0x%02X.\n", - sio_read(port, 0x20)); - w836xx_ext_leave(port); + w836xx_ext_enter(base); + chipid = sio_read(base, 0x20); + for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) + if (winbond_chips[i].device_id == chipid) + { + chip = &winbond_chips[i]; + break; + } + + w836xx_ext_leave(base); + return chip; +} + +/* The chipid parameter goes away as soon as we have Super I/O matching in the + board enable table. The call to winbond_superio_detect goes away as + soon as we have generic Super I/O detection code. */ +static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, + int pin, int raise) +{ + const struct winbond_chip * chip = NULL; + const struct winbond_port * gpio; + int port = pin / 10; + int bit = pin % 10; + + chip = winbond_superio_detect(base); + if (!chip) { + msg_perr("\nERROR: No supported Winbond Super I/O found\n"); + return -1; + } + if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { + msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", + pin); + return -1; + } + + gpio = &chip->port[port - 1]; + + if (gpio->ldn == 0) { + msg_perr("\nERROR: GPIO%d is not supported yet on this" + " winbond chip\n", port); return -1; } - /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ - sio_mask(port, 0x2B, 0x10, 0x10); + w836xx_ext_enter(base); - /* Select logical device 8: GPIO port 2 */ - sio_write(port, 0x07, 0x08); + /* Select logical device */ + sio_write(base, 0x07, gpio->ldn); - sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ - sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ - sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ - sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ + /* Activate logical device. */ + sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit); - w836xx_ext_leave(port); + /* Select GPIO function of that pin */ + if (gpio->mux && gpio->mux[bit].reg) + sio_mask(base, gpio->mux[bit].reg, + gpio->mux[bit].data, gpio->mux[bit].mask); + + sio_mask(base, gpio->base + 0, 0, 1 << bit); /* make pin output */ + sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ + sio_mask(base, gpio->base + 1, raise << bit, 1 << bit); + + w836xx_ext_leave(base); return 0; } -static int w83627hf_gpio24_raise_2e(void) +/** + * Winbond W83627HF: Raise GPIO24. + * + * Suited for: + * - Agami Aruma + * - IWILL DK8-HTX + */ +static int w83627hf_gpio24_raise_2e() { - return w83627hf_gpio24_raise(0x2e); + return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1); } /** - * Winbond W83627THF: GPIO 4, bit 4 + * Winbond W83627THF: Raise GPIO 44. * * Suited for: * - MSI K8T Neo2-F - * - MSI K8N-NEO3 */ -static int w83627thf_gpio4_4_raise(uint16_t port) -{ - w836xx_ext_enter(port); - - /* Is this the W83627THF? */ - if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ - msg_perr("\nERROR: W83627THF: Wrong ID: 0x%02X.\n", - sio_read(port, 0x20)); - w836xx_ext_leave(port); - return -1; - } - - /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ - - sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ - sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ - sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ - sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ - sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ - - w836xx_ext_leave(port); - - return 0; -} - -static int w83627thf_gpio4_4_raise_2e(void) +static int w83627thf_gpio44_raise_2e() { - return w83627thf_gpio4_4_raise(0x2e); + return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1); } -static int w83627thf_gpio4_4_raise_4e(void) +/** + * Winbond W83627THF: Raise GPIO 44. + * + * Suited for: + * - MSI K8N Neo3 + */ +static int w83627thf_gpio44_raise_4e() { - return w83627thf_gpio4_4_raise(0x4e); + return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1); } /** @@ -1485,12 +1581,12 @@ {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, - {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, + {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},

1 0

flashrom -V output for Compaq SR5413WM
by Andre Robatino 26 Jun '10

26 Jun '10

Attached is the output of the command flashrom -V > flashrom_compaq.txt for a Compaq SR5413WM.

1 0

Re: [flashrom] [PATCH] rfc: w83627 code unification
by Carl-Daniel Hailfinger 26 Jun '10

26 Jun '10

On 31.05.2010 18:17, Michael Karcher wrote: > This patch unifies the code for different Winbond W83627-family chips, > to be applied before I add another W83627 GPIO raise function. > > Pleas comment on whether this approach is too sophisticated or a good > idea. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > I think it's pretty good. There are a few stylistic changes I'd like to see, but other than that I see a huge potential for code cleanup coming from this. > diff --git a/board_enable.c b/board_enable.c > index b5eb63f..edba408 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -138,41 +138,67 @@ static int fdc37b787_gpio50_raise_3f0(const char *name) > return fdc37b787_gpio50_raise(0x3f0, name); > } > > -/** > - * Winbond W83627HF: Raise GPIO24. > - * > - * Suited for: > - * - Agami Aruma > - * - IWILL DK8-HTX > - */ > -static int w83627hf_gpio24_raise(uint16_t port, const char *name) > +struct w83627x_gpio { > + uint8_t device_id; /* reg 0x20 of the expected w83626x */ > + uint8_t ldn; /* LDN this GPIO register is located in */ > + > + uint8_t mux_reg; /* register that selects GPIO/special fn mux, > + or 0 if none */ > + uint8_t enable_bit; /* bit in 0x30 of that LDN to enable > + the GPIO port */ > + uint8_t base; /* base register in that LDN for the port */ > +}; > + > +static const struct w83627x_gpio w83627hf_2 = {0x52, 0x08, 0x2B, 0, 0xF0}; > +static const struct w83627x_gpio w83627thf_4 = {0x82, 0x09, 0, 1, 0xF4}; > + > +static int w83627x_gpio_set(uint16_t port, const struct w83627x_gpio * gpio, > Can you eliminate struct w83627x_gpio* from the parameter list? IMHO this function should take a look at the device ID it reads from the chip, and use that to pick the correct struct. > + int bit, int raise) > { > w836xx_ext_enter(port); > > - /* Is this the W83627HF? */ > - if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ > - msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", > - name, sio_read(port, 0x20)); > + /* Is this the right Super I/O chip? */ > + if (sio_read(port, 0x20) != gpio->device_id) { > + msg_perr("\nERROR: W83627x: Wrong ID: 0x%02X, expecting 0x%02X.\n", > + sio_read(port, 0x20), gpio->device_id); > w836xx_ext_leave(port); > return -1; > } > > - /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ > - sio_mask(port, 0x2B, 0x10, 0x10); > + /* Select logical device */ > + sio_write(port, 0x07, gpio->ldn); > > - /* Select logical device 8: GPIO port 2 */ > - sio_write(port, 0x07, 0x08); > + /* Activate logical device. */ > + sio_mask(port, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit); > > - sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ > - sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ > - sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ > - sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ > + /* Select GPIO function of that pin */ > + if(gpio->mux_reg) > Space after if. > + sio_mask(port, gpio->mux_reg, 1 << bit, 1 << bit); > If bit>7 this will invoke undefined behaviour, and I don't see any code checking if bit is in the range 0..7. > + > + sio_mask(port, gpio->base + 0, 0, 1 << bit); /* make pin output */ > + sio_mask(port, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ > + if(raise) > + sio_mask(port, gpio->base + 1, 1 << bit, 1 << bit); > + else > + sio_mask(port, gpio->base + 1, 0, 1 << bit); > Could you replace the if/else statement with this: sio_mask(port, gpio->base + 1, raise << bit, 1 << bit); > > w836xx_ext_leave(port); > > return 0; > } > > +/** > + * Winbond W83627HF: Raise GPIO24. > + * > + * Suited for: > + * - Agami Aruma > + * - IWILL DK8-HTX > + */ > +static int w83627hf_gpio24_raise(uint16_t port, const char *name) > +{ > + return w83627x_gpio_set(port, &w83627hf_2, 4, 1); > +} > + > static int w83627hf_gpio24_raise_2e(const char *name) > { > return w83627hf_gpio24_raise(0x2e, name); > @@ -187,27 +213,7 @@ static int w83627hf_gpio24_raise_2e(const char *name) > */ > static int w83627thf_gpio4_4_raise(uint16_t port, const char *name) > { > - w836xx_ext_enter(port); > - > - /* Is this the W83627THF? */ > - if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ > - msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", > - name, sio_read(port, 0x20)); > - w836xx_ext_leave(port); > - return -1; > > - } > - > - /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ > - > - sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ > - sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ > - sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ > - sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ > - sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ > - > - w836xx_ext_leave(port); > - > - return 0; > + return w83627x_gpio_set(port, &w83627thf_4, 4, 1); > } > > static int w83627thf_gpio4_4_raise_2e(const char *name) > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

zotac zbox HD-11 MCP SPI
by Craig Cook 26 Jun '10

26 Jun '10

Zotac ZBOXHD-H11 http://downloads.zotac.com/mediadrivers/mb/bios/pa140.zip # flashrom −V flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel NM10", enabling flash write... OK. This chipset supports the following protocols: SPI. Calibrating delay loop... OK. Found chip "Generic unknown SPI chip (RDID)" (0 KB, SPI) at physical address 0x0. === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. # lspci -nnvvvxxx 00:00.0 Host bridge [0600]: Intel Corporation N10 Family DMI Bridge [8086:a000] (rev 02) Subsystem: Intel Corporation N10 Family DMI Bridge [8086:a000] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort+ <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information <?> Kernel modules: intel-agp 00: 86 80 00 a0 06 00 90 30 02 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 a0 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d1 fe 00 00 00 00 00 40 d1 fe 00 00 00 00 50: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 11 00 00 33 33 00 ff 03 00 00 00 1a 39 00 a0: 20 00 00 08 00 00 00 80 00 00 00 80 00 00 f0 7f b0: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 49 00 00 00 00 00 00 6e e0: 09 00 08 d1 02 10 11 08 00 00 00 00 00 00 00 00 f0: 00 00 00 00 01 00 00 00 ad 0f 02 00 00 00 00 00 00:1b.0 Audio device [0403]: Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] (rev 02) Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at fe9fc000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Virtual Channel <?> Capabilities: [130] Root Complex Link <?> Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: 86 80 d8 27 06 00 10 00 02 00 03 04 08 00 00 00 10: 04 c0 9f fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 da 19 40 a1 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 01 00 00 03 00 00 00 00 00 00 00 00 00 80 00 00 50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 91 00 00 00 00 00 00 08 10 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.0 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 1 [8086:27d0] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fea00000-feafffff Prefetchable memory behind bridge: 00000000fbf00000-00000000fbffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 20, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0f00c Data: 4161 Capabilities: [90] Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 d0 27 07 05 10 00 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 d0 d0 00 00 20: a0 fe a0 fe f1 fb f1 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 06 00 40: 10 80 41 01 c0 0f 00 00 00 00 11 00 11 2c 11 01 50: 40 00 11 30 60 05 00 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 e0 fe 61 41 00 00 00 00 00 00 90: 0d a0 00 00 da 19 40 a1 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.1 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 2 [8086:27d2] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: feb00000-febfffff Prefetchable memory behind bridge: 0000000080000000-00000000801fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 21, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0f00c Data: 4169 Capabilities: [90] Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 d2 27 07 05 10 00 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 10 10 00 00 20: b0 fe b0 fe 01 80 11 80 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 06 00 40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 02 50: 40 00 11 30 60 05 08 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 e0 fe 69 41 00 00 00 00 00 00 90: 0d a0 00 00 da 19 40 a1 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.2 PCI bridge [0604]: Intel Corporation N10/ICH 7 Family PCI Express Port 3 [8086:27d4] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fcf00000-fdffffff Prefetchable memory behind bridge: 00000000ce000000-00000000dfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 22, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0f00c Data: 4171 Capabilities: [90] Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport Kernel modules: shpchp 00: 86 80 d4 27 07 05 10 40 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 e0 e0 00 00 20: f0 fc f0 fd 01 ce f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 03 1a 00 40: 10 80 41 01 c0 0f 00 00 00 00 12 00 11 2c 11 03 50: 40 00 11 30 60 05 10 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 e0 fe 71 41 00 00 00 00 00 00 90: 0d a0 00 00 da 19 40 a1 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8] (rev 02) Subsystem: Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 4: I/O ports at cc00 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 cc 00 00 00 00 00 00 00 00 00 00 86 80 c8 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 0e 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] (rev 02) Subsystem: Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at c880 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 c8 00 00 00 00 00 00 00 00 00 00 86 80 c9 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 0f 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] (rev 02) Subsystem: Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at c800 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 c8 00 00 00 00 00 00 00 00 00 00 86 80 ca 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.3 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] (rev 02) Subsystem: Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 16 Region 4: I/O ports at c480 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 c4 00 00 00 00 00 00 00 00 00 00 86 80 cb 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] (rev 02) (prog-if 20) Subsystem: Allied Telesis, Inc Device [0010:27cc] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at fe9fbc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 cc 27 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 bc 9f fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 cc 27 30: 00 00 00 00 50 00 00 00 00 00 00 00 0e 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 80 70: 00 00 df 3f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 ff 00 ff 00 20 00 00 88 e0: 00 00 00 00 db b6 6d 00 00 00 00 00 00 00 00 00 f0: 00 80 00 09 88 85 40 00 86 0f 02 00 0a 17 02 20 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev e2) (prog-if 01) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] 00: 86 80 48 24 04 01 10 00 e2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 20 f0 00 80 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 06 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 50: 0d 00 00 00 da 19 40 a1 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.0 ISA bridge [0601]: Intel Corporation NM10 Family LPC Controller [8086:27bc] (rev 02) Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information <?> 00: 86 80 bc 27 07 00 10 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 da 19 40 a1 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 80 00 00 00 81 04 00 00 10 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 8a 8b 85 8f d0 00 00 00 80 80 80 8e 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 0e 14 01 0a fc 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 06 00 00 38 00 00 00 13 00 00 00 00 03 00 00 b0: 00 00 f0 00 00 00 00 00 00 00 00 08 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 01 00 00 00 e0: 09 00 0c 10 a1 02 64 90 40 00 00 00 00 00 00 00 f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.2 SATA controller [0106]: Intel Corporation N10/ICH7 Family SATA AHCI Controller [8086:27c1] (rev 02) (prog-if 01) Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 28 Region 0: I/O ports at b880 [size=8] Region 1: I/O ports at c400 [size=4] Region 2: I/O ports at c080 [size=8] Region 3: I/O ports at c000 [size=4] Region 4: I/O ports at bc00 [size=32] Region 5: Memory at fe9fb800 (32-bit, non-prefetchable) [size=1K] Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Address: fee0f00c Data: 4191 Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a8] SATA HBA <?> Kernel driver in use: ahci Kernel modules: ahci 00: 86 80 c1 27 07 04 b0 02 02 01 06 01 00 00 00 00 10: 81 b8 00 00 01 c4 00 00 81 c0 00 00 01 c0 00 00 20: 01 bc 00 00 00 b8 9f fe 00 00 00 00 da 19 40 a1 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 a8 02 40 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 01 00 0c f0 e0 fe 91 41 00 00 00 00 00 00 90: 40 00 0f 10 80 01 80 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 12 00 10 00 48 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da] (rev 02) Subsystem: ZOTAC International (MCO) Ltd. Device [19da:a140] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 15 Region 4: I/O ports at 0400 [size=32] Kernel modules: i2c-i801 00: 86 80 da 27 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 da 19 40 a1 30: 00 00 00 00 00 00 00 00 00 00 00 00 0f 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 01:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 03) Subsystem: ZOTAC International (MCO) Ltd. Device [19da:8168] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 27 Region 0: I/O ports at d800 [size=256] Region 2: Memory at fbffb000 (64-bit, prefetchable) [size=4K] Region 4: Memory at fbffc000 (64-bit, prefetchable) [size=16K] [virtual] Expansion ROM at fbf00000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable+ Address: 00000000fee0f00c Data: 4189 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [ac] MSI-X: Enable- Mask- TabSize=4 Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data <?> Capabilities: [100] Advanced Error Reporting <?> Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 00-e0-4c-68-00-00-08-bc Kernel driver in use: r8169 Kernel modules: r8169 00: ec 10 68 81 07 04 10 00 03 00 00 02 08 00 00 00 10: 01 d8 00 00 00 00 00 00 0c b0 ff fb 00 00 00 00 20: 0c c0 ff fb 00 00 00 00 00 00 00 00 da 19 68 81 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c f0 e0 fe 00 00 00 00 89 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 28 00 10 50 19 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 03 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 Network controller [0280]: Atheros Communications Inc. AR9285 Wireless Network Adapter (PCI-Express) [168c:002b] (rev 01) Subsystem: Device [1a3b:1089] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at febf0000 (64-bit, non-prefetchable) [size=64K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Advanced Error Reporting <?> Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 12-14-24-ff-ff-17-15-00 Capabilities: [170] Power Budgeting <?> Kernel driver in use: ath9k Kernel modules: ath9k 00: 8c 16 2b 00 07 00 10 00 01 00 80 02 08 00 00 00 10: 04 00 bf fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3b 1a 89 10 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 40: 01 50 c3 db 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 12 00 c0 8c 28 00 10 20 19 00 11 3c 03 00 70: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.0 VGA compatible controller [0300]: nVidia Corporation GT218 [ION] [10de:0a64] (rev a2) Subsystem: PC Partner Limited Device [174b:3100] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at ce000000 (64-bit, prefetchable) [size=32M] Region 5: I/O ports at ec00 [size=128] [virtual] Expansion ROM at fcf80000 [disabled] [size=512K] Capabilities: [60] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 <64us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM+ Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [b4] Vendor Specific Information <?> Capabilities: [100] Virtual Channel <?> Capabilities: [128] Power Budgeting <?> Capabilities: [600] Vendor Specific Information <?> Kernel driver in use: nvidia Kernel modules: nvidia-current, nvidiafb, nouveau 00: de 10 64 0a 07 00 10 00 a2 00 00 03 00 00 80 00 10: 00 00 00 fd 0c 00 00 d0 00 00 00 00 0c 00 00 ce 20: 00 00 00 00 01 ec 00 00 00 00 00 00 4b 17 00 31 30: 00 00 00 00 60 00 00 00 00 00 00 00 05 01 00 00 40: 4b 17 00 31 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 03 00 08 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 b4 02 00 e0 8d 28 00 80: 10 29 00 00 01 3d 05 00 48 01 11 10 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 a0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 00 00 00 00 09 00 14 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.1 Audio device [0403]: nVidia Corporation High Definition Audio Controller [10de:0be3] (rev a1) Subsystem: PC Partner Limited Device [174b:3100] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at fcf7c000 (32-bit, non-prefetchable) [size=16K] Capabilities: [60] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 <64us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <1us ClockPM+ Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: de 10 e3 0b 06 00 10 00 a1 00 03 04 08 00 80 00 10: 00 c0 f7 fc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 00 31 30: 00 00 00 00 60 00 00 00 00 00 00 00 05 01 00 00 40: 4b 17 00 31 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 03 00 08 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 00 02 00 a0 8d 28 00 80: 10 29 00 00 01 3d 04 00 08 01 11 10 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

Re: [flashrom] [PATCH] Fix AAI code
by den_m＠hotmail.ru 25 Jun '10

25 Jun '10

Additional info (didn't have possibility to include it in previous message) Log of failed write (r1060 with your patch): >> ./flashrom -V -w ../A74M0315.ROM flashrom v0.9.2-r1060 on Linux 2.6.32-gentoo-r7.den_m (i686), built with libpci 3.0.0, GCC 4.3.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1398M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1004 us, 10000 myus = 10011 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "A740GM-M" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "A740GM-M" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8726 Found chipset "AMD SB700/SB710/SB750", enabling flash write... chipset PCI ID is 1002:439d, SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=0, DropOneClkOnRd=0 GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. SuperI/O ID 8726 is not on the controller list. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Chip status register is 00 Found chip "EMST F25L008A" (1024 KB, SPI) at physical address 0xfff00000. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0x8c, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0x8c, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x93, id2 0x3f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xfd, id2 0xee, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for EON unknown EON SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0x8c, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0x8c, id2 0x13 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. COMPLETE. Verifying flash... VERIFY FAILED at 0x00000000! Expected=0xff, Read=0x00, failed byte count from 0x00000000-0x000fffff: 0xc2d1f -- Den_M

1 0

[PATCH] Work around shadowing warnings in libpci headers
by Carl-Daniel Hailfinger 25 Jun '10

25 Jun '10

Work around shadowing warnings in libpci headers. This is needed for warning-free compilation on older gcc versions (3.x and probably older). Such a gcc version is the default on OpenBSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-libpci_header_shadow_warning/hwaccess.h =================================================================== --- flashrom-libpci_header_shadow_warning/hwaccess.h (Revision 1045) +++ flashrom-libpci_header_shadow_warning/hwaccess.h (Arbeitskopie) @@ -31,7 +31,14 @@ #endif #if NEED_PCI == 1 +/* + * libpci headers use the variable name "index" which triggers shadowing + * warnings on systems which have the index() function in a default #include + * or as builtin. + */ +#define index shadow_workaround_index #include <pci/pci.h> +#undef index #endif #if defined (__i386__) || defined (__x86_64__) Index: flashrom-libpci_header_shadow_warning/Makefile =================================================================== --- flashrom-libpci_header_shadow_warning/Makefile (Revision 1045) +++ flashrom-libpci_header_shadow_warning/Makefile (Arbeitskopie) @@ -289,7 +289,9 @@ ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " - @$(shell ( echo "#include <pci/pci.h>"; \ + @# Avoid a failing test due to libpci header symbol shadowing breakage + @$(shell ( echo "#define index shadow_workaround_index" \ + echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) -- http://www.hailfinger.org/

2 3

[commit] r1061 - trunk
by repository service 25 Jun '10

25 Jun '10

Author: hailfinger Date: Fri Jun 25 15:18:48 2010 New Revision: 1061 URL: http://flashrom.org/trac/coreboot/changeset/1061 Log: Work around shadowing warnings in libpci headers. This is needed for warning-free compilation on older gcc versions (3.x and probably older). Such a gcc version is the default on i386 OpenBSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stuart Henderson <sthen(a)openbsd.org> Modified: trunk/Makefile trunk/hwaccess.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jun 24 13:51:12 2010 (r1060) +++ trunk/Makefile Fri Jun 25 15:18:48 2010 (r1061) @@ -310,7 +310,9 @@ ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " - @$(shell ( echo "#include <pci/pci.h>"; \ + @# Avoid a failing test due to libpci header symbol shadowing breakage + @$(shell ( echo "#define index shadow_workaround_index"; \ + echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Jun 24 13:51:12 2010 (r1060) +++ trunk/hwaccess.h Fri Jun 25 15:18:48 2010 (r1061) @@ -31,7 +31,14 @@ #endif #if NEED_PCI == 1 +/* + * libpci headers use the variable name "index" which triggers shadowing + * warnings on systems which have the index() function in a default #include + * or as builtin. + */ +#define index shadow_workaround_index #include <pci/pci.h> +#undef index #endif #if defined (__i386__) || defined (__x86_64__)

1 0

[PATCH] Fix AAI code
by den_m＠hotmail.ru 24 Jun '10

24 Jun '10

Hi again! Sorry, but my mail'll be greater than simply 'acking' r1060 with your patch not working Index: flashrom-spi_aai_outsize_fix/spi.h =================================================================== --- flashrom-spi_aai_outsize_fix/spi.h (Revision 1058) +++ flashrom-spi_aai_outsize_fix/spi.h (Arbeitskopie) @@ -108,15 +108,15 @@ /* JEDEC_READ_INSIZE : any length */ /* Write memory byte */ -#define JEDEC_BYTE_PROGRAM 0x02 +#define JEDEC_BYTE_PROGRAM 0x02 #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 /* Write AAI word (SST25VF080B) */ -#define JEDEC_AAI_WORD_PROGRAM 0xad -#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 -#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 -#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 /* Error codes */ #define SPI_GENERIC_ERROR -1 r1060 with above patch and following patch also not working: Index: spi25.c =================================================================== --- spi25.c (revision 1060) +++ spi25.c (working copy) @@ -169,6 +169,7 @@ int probe_spi_rdid(struct flashchip *flash) { + spi_write_disable(); return probe_spi_rdid_generic(flash, 3); } but r1060 with all above patches and following patch working: Index: flashchips.c =================================================================== --- flashchips.c (revision 1060) +++ flashchips.c (working copy) @@ -1392,7 +1392,7 @@ .block_erase = spi_block_erase_c7, } }, - .write = spi_aai_write, + .write = spi_chip_write_1,//spi_aai_write, .read = read_memmapped, }, -- Den_M

1 0

report for AMIC A49LF040A
by Guenter 24 Jun '10

24 Jun '10

Hi, I've successfully used flashrom to read, write, verify the AMIC A49LF040A chip on a PC-Engines Alix 2C3 board. Can you please mark this chip as supported? BTW. I would like to subscribe with this email (lists(a)gknw.net) to the flashrom-devel list, but unfortunately the mailman interface doesnt work for me - I never get the confirmation mail (tried a couple of times, also with a gmx account); can you please manually subscribe me? Thanks, Günter. Attachment: flashrom verbose output.

3 11

Test Report: SST SST39SF020A
by Michael Marineau 24 Jun '10

24 Jun '10

Greetings, Flashrom is reporting the following to me, requesting a test report: Found chip "SST SST39SF020A" (256 KB, Parallel) at physical address 0xfffc0000. This flash part has status UNTESTED for operations: ERASE Erase/Write operations appear to work perfectly fine, attached is the verbose log from a write. The mainboard used is an VIA EPIA-MII. Cheers, -- Michael Marineau

2 1

[commit] r1060 - trunk
by repository service 24 Jun '10

24 Jun '10

Author: hailfinger Date: Thu Jun 24 13:51:12 2010 New Revision: 1060 URL: http://flashrom.org/trac/coreboot/changeset/1060 Log: SST39VF010 tested, works. Signed-off-by: Guenter Knauf <lists(a)gknw.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jun 24 13:39:57 2010 (r1059) +++ trunk/flashchips.c Thu Jun 24 13:51:12 2010 (r1060) @@ -4284,7 +4284,7 @@ .total_size = 128, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PRW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers =

1 0

[Patch] Winbond W25Q64 support
by David Hendricks 24 Jun '10

24 Jun '10

This patch adds support for the W25Q64. It's similar, but has its own datasheet [Link<http://www.winbond.com.tw/hq/enu/ProductAndSales/ProductLines/FlashMemory/S…>], although it's mentioned in the W25Q{80,16,32} datasheet once. Anyway, I happen to have one and was able to successfully read, erase, and write to it using an NM10 based device. I was only able to successfully erase with D8h block erase and C7h chip erase commands, but other than that it seemed to work great. Patch attached. Signed-off by: David Hendricks (dhendrix(a)google.com) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

2 3

[commit] r1059 - trunk
by repository service 24 Jun '10

24 Jun '10

Author: hailfinger Date: Thu Jun 24 13:39:57 2010 New Revision: 1059 URL: http://flashrom.org/trac/coreboot/changeset/1059 Log: Add Winbond W25Q64 support. Tested. Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jun 24 01:14:44 2010 (r1058) +++ trunk/flashchips.c Thu Jun 24 13:39:57 2010 (r1059) @@ -5839,6 +5839,40 @@ { .vendor = "Winbond", + .name = "W25Q64", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25Q64, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PRW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W25x10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jun 24 01:14:44 2010 (r1058) +++ trunk/flashchips.h Thu Jun 24 13:39:57 2010 (r1059) @@ -512,6 +512,7 @@ #define W_25Q80 0x4014 #define W_25Q16 0x4015 #define W_25Q32 0x4016 +#define W_25Q64 0x4017 #define W_29C011 0xC1 #define W_29C020C 0x45 /* Same as W29C020 and ASD AE29F2008 */ #define W_29C040P 0x46 /* Same as W29C040 */

1 0

[PATCH] Native DMI parser and cross checking with dmidecode
by Sean Nelson 24 Jun '10

24 Jun '10

The DMI Parser is based on dmidecode 2.10's dmidecode.c Stripped to bare minimums and only parses the System, Baseboard, and Chassis tables. Uses our physmap calls for hardware access. All of the cross-check code is contained in '#if 1' to easily find and shut off usage. Added my copyright line. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

1 0

[Patch] add support for SiS963
by David Borg 24 Jun '10

24 Jun '10

Patch to enable sis963 southbridge and W83697HF/F SuperIO. DO NOT APPLY IT, as it needs to be finalised, (tomorrow probably). Please comment on what else needs to be done (which variables need to be initialised for example). Yes, it's a bit too verbose, but I'm still learning hehe. Probe works and detects the flash chip. Regards, David

1 0

Re: [flashrom] Provide DMI stub for no-OS environments
by Patrick Georgi 24 Jun '10

24 Jun '10

Hi, just wanted to note that the DMI stub patch by Carl-Daniel works fine with flashrom on libpayload. > If flashrom is standalone and has no OS below, it can't call > dmidecode. Provide empty DMI stubs for that case until someone > implements our own dmidecode subset. > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

2 1

[commit] r1058 - trunk
by repository service 24 Jun '10

24 Jun '10

Author: hailfinger Date: Thu Jun 24 01:14:44 2010 New Revision: 1058 URL: http://flashrom.org/trac/coreboot/changeset/1058 Log: If flashrom is standalone and has no OS below, it can't call dmidecode. Provide empty DMI stubs for that case until someone implements our own dmidecode subset. Tested by Patrick Georgi on top of libpayload. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/dmi.c Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Tue Jun 22 01:20:15 2010 (r1057) +++ trunk/dmi.c Thu Jun 24 01:14:44 2010 (r1058) @@ -24,6 +24,26 @@ #include "flash.h" +int has_dmi_support = 0; + +#if STANDALONE + +/* Stub to indicate missing DMI functionality. + * has_dmi_support is 0 by default, so nothing to do here. + * Because dmidecode is not available on all systems, the goal is to implement + * the DMI subset we need directly in this file. + */ +void dmi_init(void) +{ +} + +int dmi_match(const char *pattern) +{ + return 0; +} + +#else /* STANDALONE */ + const char *dmidecode_names[] = { "system-manufacturer", "system-product-name", @@ -36,7 +56,6 @@ #define DMI_COMMAND_LEN_MAX 260 const char *dmidecode_command = "dmidecode"; -int has_dmi_support = 0; char *dmistrings[ARRAY_SIZE(dmidecode_names)]; /* Strings longer than 4096 in DMI are just insane. */ @@ -172,3 +191,5 @@ return 0; } + +#endif /* STANDALONE */

1 0

Re: [flashrom] [PATCH 1/2] Add hp xw9400 board enable.
by Cristian Grimaldo Macias 23 Jun '10

23 Jun '10

Hi. I need flash mi xw9400 mobo, but the flashrom cannot find mis system, I don't know how to use your patch, could yo say me how can I integrate it? Thank you

1 0

[PATCH] Provide DMI stub for no-OS environments
by Carl-Daniel Hailfinger 22 Jun '10

22 Jun '10

If flashrom is standalone and has no OS below, it can't call dmidecode. Provide empty DMI stubs for that case until someone implements our own dmidecode subset. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dmi_stub/dmi.c =================================================================== --- flashrom-dmi_stub/dmi.c (Revision 1056) +++ flashrom-dmi_stub/dmi.c (Arbeitskopie) @@ -24,6 +24,26 @@ #include "flash.h" +int has_dmi_support = 0; + +#if STANDALONE + +/* Stub to indicate missing DMI functionality. + * has_dmi_support is 0 by default, so nothing to do here. + * Because dmidecode is not available on all systems, the goal is to implement + * the DMI subset we need directly in this file. + */ +void dmi_init(void) +{ +} + +int dmi_match(const char *pattern) +{ + return 0; +} + +#else /* STANDALONE */ + const char *dmidecode_names[] = { "system-manufacturer", "system-product-name", @@ -36,7 +56,6 @@ #define DMI_COMMAND_LEN_MAX 260 const char *dmidecode_command = "dmidecode"; -int has_dmi_support = 0; char *dmistrings[ARRAY_SIZE(dmidecode_names)]; /* Strings longer than 4096 in DMI are just insane. */ @@ -172,3 +191,5 @@ return 0; } + +#endif /* STANDALONE */ -- http://www.hailfinger.org/

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[PATCH] Kill unneeded #include
by Carl-Daniel Hailfinger 22 Jun '10

22 Jun '10

Kill unneeded #include wherever possible. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-include_cleanup/hwaccess.c =================================================================== --- flashrom-include_cleanup/hwaccess.c (Revision 1056) +++ flashrom-include_cleanup/hwaccess.c (Arbeitskopie) @@ -21,10 +21,12 @@ #include <stdint.h> #include <string.h> #include <stdlib.h> +#include <sys/types.h> +#if !defined (__DJGPP__) #include <unistd.h> #include <fcntl.h> -#include <sys/types.h> #include <errno.h> +#endif #include "flash.h" #if defined(__i386__) || defined(__x86_64__) @@ -42,12 +44,14 @@ void get_io_perms(void) { +#if defined(__DJGPP__) + /* We have full permissions by default. */ + return; +#else #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif __DJGPP__ - if (0) { #else if (iopl(3) != 0) { #endif @@ -55,6 +59,7 @@ "You need to be root.\n", strerror(errno)); exit(1); } +#endif } void release_io_perms(void) Index: flashrom-include_cleanup/physmap.c =================================================================== --- flashrom-include_cleanup/physmap.c (Revision 1056) +++ flashrom-include_cleanup/physmap.c (Arbeitskopie) @@ -23,13 +23,17 @@ #include <unistd.h> #include <stdio.h> #include <sys/types.h> -#include <sys/stat.h> -#include <fcntl.h> #include <stdlib.h> #include <string.h> -#include <errno.h> #include "flash.h" +/* Do we need any file access or ioctl for physmap or MSR? */ +#if !defined(__DJGPP__) +#include <sys/stat.h> +#include <fcntl.h> +#include <errno.h> +#endif + #ifdef __DJGPP__ #include <dpmi.h> #include <sys/nearptr.h> Index: flashrom-include_cleanup/chipset_enable.c =================================================================== --- flashrom-include_cleanup/chipset_enable.c (Revision 1056) +++ flashrom-include_cleanup/chipset_enable.c (Arbeitskopie) @@ -27,12 +27,10 @@ #define _LARGEFILE64_SOURCE -#include <unistd.h> #include <stdlib.h> #include <string.h> #include <sys/types.h> -#include <sys/stat.h> -#include <fcntl.h> +#include <unistd.h> #include "flash.h" #if defined(__i386__) || defined(__x86_64__) Index: flashrom-include_cleanup/internal.c =================================================================== --- flashrom-include_cleanup/internal.c (Revision 1056) +++ flashrom-include_cleanup/internal.c (Arbeitskopie) @@ -21,10 +21,7 @@ #include <stdint.h> #include <string.h> #include <stdlib.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #if NEED_PCI == 1 -- http://www.hailfinger.org/

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[commit] r1057 - trunk
by repository service 22 Jun '10

22 Jun '10

Author: hailfinger Date: Tue Jun 22 01:20:15 2010 New Revision: 1057 URL: http://flashrom.org/trac/coreboot/changeset/1057 Log: Kill unneeded #include wherever possible. Tested on Linux, FreeBSD, NetBSD, OpenBSD, DOS. Thanks to Jonathan A. Kollasch and Idwer Vollering for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Idwer Vollering <vidwer+lists.flashrom(a)gmail.com> Modified: trunk/chipset_enable.c trunk/hwaccess.c trunk/internal.c trunk/physmap.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jun 21 18:12:22 2010 (r1056) +++ trunk/chipset_enable.c Tue Jun 22 01:20:15 2010 (r1057) @@ -27,12 +27,10 @@ #define _LARGEFILE64_SOURCE -#include <unistd.h> #include <stdlib.h> #include <string.h> #include <sys/types.h> -#include <sys/stat.h> -#include <fcntl.h> +#include <unistd.h> #include "flash.h" #if defined(__i386__) || defined(__x86_64__) Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Mon Jun 21 18:12:22 2010 (r1056) +++ trunk/hwaccess.c Tue Jun 22 01:20:15 2010 (r1057) @@ -21,10 +21,12 @@ #include <stdint.h> #include <string.h> #include <stdlib.h> +#include <sys/types.h> +#if !defined (__DJGPP__) #include <unistd.h> #include <fcntl.h> -#include <sys/types.h> #include <errno.h> +#endif #include "flash.h" #if defined(__i386__) || defined(__x86_64__) @@ -42,12 +44,14 @@ void get_io_perms(void) { +#if defined(__DJGPP__) + /* We have full permissions by default. */ + return; +#else #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif __DJGPP__ - if (0) { #else if (iopl(3) != 0) { #endif @@ -55,6 +59,7 @@ "You need to be root.\n", strerror(errno)); exit(1); } +#endif } void release_io_perms(void) Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Mon Jun 21 18:12:22 2010 (r1056) +++ trunk/internal.c Tue Jun 22 01:20:15 2010 (r1057) @@ -21,10 +21,7 @@ #include <stdint.h> #include <string.h> #include <stdlib.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #if NEED_PCI == 1 Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Mon Jun 21 18:12:22 2010 (r1056) +++ trunk/physmap.c Tue Jun 22 01:20:15 2010 (r1057) @@ -23,13 +23,17 @@ #include <unistd.h> #include <stdio.h> #include <sys/types.h> -#include <sys/stat.h> -#include <fcntl.h> #include <stdlib.h> #include <string.h> -#include <errno.h> #include "flash.h" +/* Do we need any file access or ioctl for physmap or MSR? */ +#if !defined(__DJGPP__) +#include <sys/stat.h> +#include <fcntl.h> +#include <errno.h> +#endif + #ifdef __DJGPP__ #include <dpmi.h> #include <sys/nearptr.h>

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Support for HY29F002TC-90 rom
by David Borg 21 Jun '10

21 Jun '10

Hey all, I have the HY29F002TC-90 ( http://www.alldatasheet.com/datasheet-pdf/pdf/82789/HYNIX/HY29F002TC-90.html) rom on a Gigabyte motherboard (GA-6VX7-4X) but flashrom is not detecting it. What can I do to have it recognized and enable reading and re-flashing? Output of flashrom -V is attached (flashrom.txt). Thanks, David

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[commit] r1056 - trunk
by repository service 21 Jun '10

21 Jun '10

Author: hailfinger Date: Mon Jun 21 18:12:22 2010 New Revision: 1056 URL: http://flashrom.org/trac/coreboot/changeset/1056 Log: Add support for Hyundai HY29F002 and HY29F002B. Signed-off-by: David Borg <borg.db(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jun 20 13:04:26 2010 (r1055) +++ trunk/flashchips.c Mon Jun 21 18:12:22 2010 (r1056) @@ -2363,6 +2363,68 @@ }, { + .vendor = "Hyundai", + .name = "HY29F002T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = HYUNDAI_ID, + .model_id = HY_29F002T, + .total_size = 256, + .page_size = 256 * 1024, + .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "Hyundai", + .name = "HY29F002B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = HYUNDAI_ID, + .model_id = HY_29F002B, + .total_size = 256, + .page_size = 256 * 1024, + .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { .vendor = "Intel", .name = "28F001BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jun 20 13:04:26 2010 (r1055) +++ trunk/flashchips.h Mon Jun 21 18:12:22 2010 (r1056) @@ -242,7 +242,8 @@ #define HY_29LV800B 0x5B #define HY_29F040A 0xA4 #define HY_29F400B 0xAB /* Same as HY_29F400AB */ -#define HY_29F002 0xB0 +#define HY_29F002B 0x34 +#define HY_29F002T 0xB0 #define HY_29LV400T 0xB9 #define HY_29LV400B 0xBA #define HY_29F080 0xD5

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probe for SST20EE010 fails
by Guenter 21 Jun '10

21 Jun '10

Hi, I've a chip which is from SST and labeled as PH29EE010 150-3CF. flashrom doesnt detect this chip although it should as -L stats: flashrom -L | grep 29EE010 SST SST29EE010 P R W 128 Parallel if I check for the chip it still fails and reads flash content: flashrom -V -c SST29EE010 flashrom v0.9.2-r1039 on Linux 2.6.27-3 (i586), built with libpci 2.2.4-pre4, GCC 4.1.2 20061115 (prerelease) (Debian 4.1.1-21), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 9 usecs, 200M loops per second, 10 myus = 17 us, 100 myus = 231 us, 1000 myus = 1042 us, 10000 myus = 10133 us, 36 myus = 45 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5A-B" DMI string baseboard-version: "REV 1.XX" DMI string chassis-type: "Unknown" Found chipset "ALi M1533", enabling flash write... chipset PCI ID is 10b9:1533, OK. This chipset supports the following protocols: Non-SPI. Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x25, id2 0xfb, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. but if I now probe for Winbond W29C011 then flashrom of course fails but shows the right flash ID: flashrom -V -c W29EE011 flashrom v0.9.2-r1039 on Linux 2.6.27-3 (i586), built with libpci 2.2.4-pre4, GCC 4.1.2 20061115 (prerelease) (Debian 4.1.1-21), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 8 usecs, 29M loops per second, delay more than 10% too short (got 24% of expected delay), recalculating... 32M loops per second, delay more than 10% too short (got 25% of expected delay), recalculating... 34M loops per second, delay more than 10% too short (got 27% of expected delay), recalculating... 33M loops per second, delay more than 10% too short (got 25% of expected delay), recalculating... 32M loops per second, delay loop is unreliable, trying to continue 10 myus = 11 us, 100 myus = 24 us, 1000 myus = 285 us, 10000 myus = 1605 us, 32 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5A-B" DMI string baseboard-version: "REV 1.XX" DMI string chassis-type: "Unknown" Found chipset "ALi M1533", enabling flash write... chipset PCI ID is 10b9:1533, OK. This chipset supports the following protocols: Non-SPI. Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0xbf, id2 0x07 No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. so what is obvious is the huge difference with the calibrating loop, and then that the probe for W29EE011 gives "id1 0xbf, id2 0x07" which is exactly what the datasheet from SST outlines for the SST29EE010 ... I really wonder what goes on there sine - as -L shows - this chip is marked as "P R W" ... Gün.

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