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[commit] r1303 - trunk
by repository service 18 May '11

18 May '11

Author: stefanct Date: Wed May 18 03:31:03 2011 New Revision: 1303 URL: http://flashrom.org/trac/flashrom/changeset/1303 Log: Mark w25q80, w25q32, and w25q64 chips tested for write and erase Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed May 18 03:30:56 2011 (r1302) +++ trunk/flashchips.c Wed May 18 03:31:03 2011 (r1303) @@ -3793,7 +3793,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7569,7 +7569,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7737,7 +7737,7 @@ .total_size = 128, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, /* used datasheet for the W29C011A */ .block_erasers =

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[commit] r1302 - trunk
by repository service 18 May '11

18 May '11

Author: stefanct Date: Wed May 18 03:30:56 2011 New Revision: 1302 URL: http://flashrom.org/trac/flashrom/changeset/1302 Log: Remove filename parameter from chip_safety_check() Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 18 01:30:13 2011 (r1301) +++ trunk/flashrom.c Wed May 18 03:30:56 2011 (r1302) @@ -1772,7 +1772,7 @@ /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ -int chip_safety_check(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) +int chip_safety_check(struct flashchip *flash, int force, int read_it, int write_it, int erase_it, int verify_it) { if (!programmer_may_write && (write_it || erase_it)) { msg_perr("Write/erase is not working yet on your programmer in " @@ -1836,7 +1836,7 @@ int ret = 0; unsigned long size = flash->total_size * 1024; - if (chip_safety_check(flash, force, filename, read_it, write_it, erase_it, verify_it)) { + if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); ret = 1; goto out_nofree;

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[PATCH 1/1] Kill unused __FLASHROM_HAVE_OUTB__ define
by Peter Lemenkov 18 May '11

18 May '11

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/hwaccess.h b/hwaccess.h index 63a2bf2..d125890 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -163,8 +163,6 @@ cpu_to_be(64) #if NEED_PCI == 1 #if defined (__i386__) || defined (__x86_64__) -#define __FLASHROM_HAVE_OUTB__ 1 - /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> -- 1.7.2.3

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[commit] r1301 - trunk
by repository service 18 May '11

18 May '11

Author: stefanct Date: Wed May 18 01:30:13 2011 New Revision: 1301 URL: http://flashrom.org/trac/flashrom/changeset/1301 Log: fix typo "not not" in board_enable.c Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue May 17 15:31:55 2011 (r1300) +++ trunk/board_enable.c Wed May 18 01:30:13 2011 (r1301) @@ -2152,7 +2152,7 @@ if (!force_boardenable) { msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" - "code has not been tested, and thus will not not be executed by default.\n" + "code has not been tested, and thus will not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"

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[PATCH 5/5] introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code
by Stefan Tauner 18 May '11

18 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 45 +++++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 24 deletions(-) diff --git a/ichspi.c b/ichspi.c index aaf4df8..ab6af18 100644 --- a/ichspi.c +++ b/ichspi.c @@ -155,6 +155,9 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +/* Indicates maximum number of data bytes for each SPI transaction. */ +static int ichspi_maxdata = -1; + uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -911,37 +914,28 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + if (spi_programmer->type == SPI_CONTROLLER_NONE) { + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > ichspi_maxdata) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, ichspi_maxdata); + return SPI_INVALID_LENGTH; + } + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, ichspi_maxdata); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -1206,6 +1200,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, break; } + ichspi_maxdata = 64; + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); @@ -1356,6 +1352,7 @@ int via_init_spi(struct pci_dev *dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; register_spi_programmer(&spi_programmer_via); + ichspi_maxdata = 16; msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); -- 1.7.1

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[PATCH 4/5] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 18 May '11

18 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 62 insertions(+), 12 deletions(-) diff --git a/ichspi.c b/ichspi.c index f5d6bbc..aaf4df8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -46,6 +46,37 @@ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status Register */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control Register */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x1 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) @@ -259,6 +290,28 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1201,14 +1254,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1255,10 +1309,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 3/5] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 18 May '11

18 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 50 ++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 44 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 67c4efb..f5d6bbc 100644 --- a/ichspi.c +++ b/ichspi.c @@ -242,6 +242,44 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -518,6 +556,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); return 0; } } @@ -792,6 +831,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1193,16 +1234,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

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[PATCH 2/5] improve macros for SSFS and SSFC bits
by Stefan Tauner 18 May '11

18 May '11

- introduce offset macros and use them to (re)define the existing mask macros - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 18 deletions(-) diff --git a/ichspi.c b/ichspi.c index 0569d33..67c4efb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -47,23 +47,35 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, * therefore SSFC bits are off by 8. * The following bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ @@ -708,8 +720,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -719,7 +731,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -766,7 +778,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

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[PATCH 1/5] whitespace fixes (space to tabs mostly) and (additional) comments
by Stefan Tauner 18 May '11

18 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 54 +++++++++++++++++++++++++++++------------------------- 1 files changed, 29 insertions(+), 25 deletions(-) diff --git a/ichspi.c b/ichspi.c index ddd14d3..0569d33 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,17 +43,17 @@ #include "spi.h" /* ICH9 controller register definition */ -#define ICH9_REG_FADDR 0x08 /* 32 Bits */ -#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ -#define ICH9_REG_SSFS 0x90 /* 08 Bits */ +#define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 #define SSFS_RESERVED_MASK 0x000000e2 -#define ICH9_REG_SSFC 0x91 /* 24 Bits */ +#define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 #define SSFC_ACS 0x00000400 #define SSFC_SPOP 0x00000800 @@ -64,20 +64,23 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +/* We combine SSFS and SSFC to one 32-bit word, + * therefore SSFC bits are off by 8. + * The following bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ #define SSFC_RESERVED_MASK 0xf8008100 -#define ICH9_REG_PREOP 0x94 /* 16 Bits */ -#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ -#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_PREOP 0x94 /* 16 Bits */ +#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ +#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ // ICH9R SPI commands -#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 -#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 -#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 -#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 // ICH7 registers -#define ICH7_REG_SPIS 0x00 /* 16 Bits */ +#define ICH7_REG_SPIS 0x00 /* 16 Bits */ #define SPIS_SCIP 0x0001 #define SPIS_GRANT 0x0002 #define SPIS_CDS 0x0004 @@ -94,17 +97,17 @@ bit 7 is used with fast read and one shot controls CS de-assert? */ -#define ICH7_REG_SPIC 0x02 /* 16 Bits */ -#define SPIC_SCGO 0x0002 -#define SPIC_ACS 0x0004 -#define SPIC_SPOP 0x0008 -#define SPIC_DS 0x4000 +#define ICH7_REG_SPIC 0x02 /* 16 Bits */ +#define SPIC_SCGO 0x0002 +#define SPIC_ACS 0x0004 +#define SPIC_SPOP 0x0008 +#define SPIC_DS 0x4000 -#define ICH7_REG_SPIA 0x04 /* 32 Bits */ -#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ -#define ICH7_REG_PREOP 0x54 /* 16 Bits */ -#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ -#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +#define ICH7_REG_SPIA 0x04 /* 32 Bits */ +#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ +#define ICH7_REG_PREOP 0x54 /* 16 Bits */ +#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ +#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -597,7 +600,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -703,7 +706,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); - /* keep reserved bits */ + /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); @@ -712,6 +715,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; + /* Set data byte count (DBC) and data cycle bit (DS) */ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; @@ -742,7 +746,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ -- 1.7.1

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[PATCH 0/5] ichspi patches 2.0
by Stefan Tauner 18 May '11

18 May '11

I have revised my first patch set which does nothing fancy but improves the output of ichspi mostly. I combined 1/6 and 2/6 to this one's 1/5 because they are tiny anyway. 1/6 did not receive an ack yet, but since it's trivial i'll self-ack 1/5 if no one objects. 2/5 now uses the offsets to define the bit masks as suggested by stefan reinauer. 3/5 (4/6) and 5/5 (6/6) were already acked (via irc) iirc. the latter has been changed due to r1299 (kill central list of SPI programmers). 5/6 is already committed. 4/5 introduces new macros and pretty printing for the hardware sequencing registers. Stefan Tauner (5): whitespace fixes (space to tabs mostly) and (additional) comments improve macros for SSFS and SSFC bits add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them add macros and pretty printing for HSFS and HSFC introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code ichspi.c | 273 ++++++++++++++++++++++++++++++++++++++++++-------------------- 1 files changed, 187 insertions(+), 86 deletions(-)

1 0

erase failed: ASUS A8AE-LE
by Kris King 17 May '11

17 May '11

Thank you for helping, even if there is no fix, or my mobo dies waiting. This is exactly why I joined the linux community. Incase this is helpful this is the failure in progress... falserunes@TITANIUM:~$ cd bios falserunes@TITANIUM:~/bios$ sudo flashrom -w 315.rom [sudo] password for falserunes: flashrom v0.9.3-r1291 on Linux 2.6.35-28-generic (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. Found chipset "ATI SB400", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00000fff: 0xfed ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x0000ffff: 0xfee8 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x0007ffff: 0x590c1 ERASE FAILED! Done. Verifying flash... VERIFY FAILED at 0x00000000! Expected=0x24, Read=0x25, failed byte count from 0x00000000-0x0007ffff: 0x51472 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! falserunes@TITANIUM:~/bios$

5 8

[commit] r1300 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Tue May 17 15:31:55 2011 New Revision: 1300 URL: http://flashrom.org/trac/flashrom/changeset/1300 Log: add board enable for Asus A8AE-LE (HP OEM) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed May 11 19:07:07 2011 (r1299) +++ trunk/board_enable.c Tue May 17 15:31:55 2011 (r1300) @@ -1081,6 +1081,35 @@ } /* + * Suited for: + * - Asus A8AE-LE (Codename AmberineM; used in Compaq Presario 061) + * Datasheet(s) used: + * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00 + */ +static int amd_sbxxx_gpio9_raise(void) +{ + struct pci_dev *dev; + uint32_t reg; + + dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */ + if (!dev) { + msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); + return -1; + } + + reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ + /* enable output (0: enable, 1: tristate): + GPIO9 output enable is at bit 5 in 0xA9 */ + reg &= ~((uint32_t)1<<(8+5)); + /* raise: + GPIO9 output register is at bit 5 in 0xA8 */ + reg |= (1<<5); + pci_write_long(dev, 0xA8, reg); + + return 0; +} + +/* * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) @@ -1924,6 +1953,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, P3, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */

1 0

Re: [flashrom] [coreboot] BIOS Protection Guidelines from NIST
by Paul Menzel 17 May '11

17 May '11

Am Dienstag, den 17.05.2011, 12:59 +0400 schrieb Антон Кочков: > April 2011: > > http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011… Thank you for the URL. coreboot is not even mentioned. Searching for »source« or »closed« did not turn anything up either, so I guess having access to the source code is not mentioned as an essential way of protection. I guess you guys (adding flashrom to CC) will have more comments. Will you post them in your answers? Maybe we can contact the authors of this article too. Thanks, Paul

1 0

Set DST bit in RTC clock?
by Peter Daum 17 May '11

17 May '11

Hi, this is admittedly a little off-topic but I with all the BIOS-experts here, I hope there might be somebody who knows about this: Is there any way to modify the daylight savings time bit (see http://www.plasma-online.de/textual/download/misc/cmos_registers.html) of the "realtime" clock of a i386 machine running linux? "nvramtool" won't touch the 1st 14 bytes of the CMOS. I tried changing "hwclock" but this uses the kernel rtc driver which obviously also does not allow to change the DST setting. (This is of course useless for Linux - I need it in connection with problems involving some well-known system from Redmond ...) Any ideas? Regards, Peter

2 2

[PATCH] Add lock printing for AMD8111 chipset
by Joshua Roys 16 May '11

16 May '11

Hello, This is for csugah from IRC. http://paste.flashrom.org/view.php?id=570 http://paste.flashrom.org/view.php?id=571 http://paste.flashrom.org/view.php?id=572 http://paste.flashrom.org/view.php?id=573 The attached patch should help diagnose your board. Also, csugah, try this patch to fix the segv you were seeing: http://patchwork.coreboot.org/patch/2878/ Add lock printing for the AMD8111. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Joshua Roys

1 0

VIA VT6421A LPC programmer
by XVilka Haos of System 16 May '11

16 May '11

This board contain Winbond W39V040BPZ chip http://paste.flashrom.org/view.php?id=569 Best regards, XVilka.

1 0

XW9400 upgrade
by Nigel R 16 May '11

16 May '11

Sorry if this has been gone through before but... I've been put off by the various problems I've read about updating the BIOS on my XW9400 motherboard to support quad core processors. There seem to be various problems ( mac addresses going awol ) and things that need to be done ( connecting jumpers etc. ) which have made me think it isn't worth it. But - I've decided I want to give it a go... My understanding is that I need to short out a jumper on the board - I think I know which points I have to bridge - but does anyone have a picture - just to make me feel sure I'm not going to blow the entire board up :-/ I have the latest version of flashrom - the process I think I need to go through is ... I've used sudo flashrom -r biosbackup.rom -m hp:xw9400 to copy the current image. I'm assuming I have to use sudo flashrom -m hp:xw9400 -w 7D6_0403.bin to flash it with the 4.03 image off the HP web site. I'm assuming that with the write enable, this will update the boot block - but will this also remove the MAC addresses - or is that some other problem people have had? Thanks for any help. Nigel

1 0

My USB+AVR-based flasher (w/ serprog protocol fw) gets spi support and a little webpage
by Urja Rannikko 15 May '11

15 May '11

Hi, I didnt want to mix this randomness into my patch mail, so I'm sending two. I set up a simple web page for serving all the files related to this little project of mine: http://urjaman.dyndns.info/usbavrprog/ . You might be able to see that there is a reason for why I dont normally do web design stuff ;), but it gets this stuff out. (FYI: This webserver is going to be down starting 2011/05/21, hopefully ending before end of 2011/06.) Also, I've written code for it and for flashrom to support SPI protocol over serprog, so I will be sending a patch to flashrom next. -- Urja Rannikko aka urjaman

2 1

jidacmos
by Taylor Thomson Wisbeck 13 May '11

13 May '11

Hi, Someone can send me the executable "jidacmos.exe". Thanks Taylor

1 0

fail update bios
by Abashev Danila 12 May '11

12 May '11

Hello! I have EPoX EP-8RDAEI. I I can not update bios. Details in the attached files. Restored the bios from a previously created backup. The system reboots normally.

2 1

Re: [flashrom] Erase faild
by Stefan Reinauer 12 May '11

12 May '11

* Marco Runge <Marco_Runge(a)raykiel.com> [110512 14:46]: > I am a Software Engineer from Raytheon Ansch tz Germany and wanted to use > flashrom to update the bios of our embedded bord form emerson. Unfortuneately > s.th. must have gone wrong. First write of the bios was fine but after reboot I > got a crisis report that the two flash banks are corrupt. I could boot from > thumb drive anyway and wanted to write the backup copy but got the following > error message: > > Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from > 0x00000000 - 0x0000ffff: 0xd092. > > We are using the following board: http://www.emersonnetworkpower.com/en-US/ > Products/EmbeddedComputing/CompactPCI/Pages/EmbCompCPCI7203.aspx > > Chipset: Intel Ibex Peak > Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 > > I hope you can help Please post the full log (possibly with --verbose) Also, does the image in flash match what you previously read from the chip? In that case it's most likely that the flash is write protected Stefan

1 0

Erase faild
by Marco Runge 12 May '11

12 May '11

Hi, I am a Software Engineer from Raytheon Anschütz Germany and wanted to use flashrom to update the bios of our embedded bord form emerson. Unfortuneately s.th. must have gone wrong. First write of the bios was fine but after reboot I got a crisis report that the two flash banks are corrupt. I could boot from thumb drive anyway and wanted to write the backup copy but got the following error message: Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from 0x00000000 - 0x0000ffff: 0xd092. We are using the following board: http://www.emersonnetworkpower.com/en-US/Products/EmbeddedComputing/Compact… Chipset: Intel Ibex Peak Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 I hope you can help Best regards Marco Runge Marco Runge Software Engineer EDA BAD Raytheon Anschuetz GmbH +49 431 3019 646 office +49 431 3019 291 fax Marco_Runge(a)raykiel.com Zeyestrasse 16 - 24 D-24106 Kiel Germany www.raytheon-anschuetz.com Raytheon Anschuetz GmbH Sitz der Gesellschaft: Kiel Registergericht: Amtsgericht Kiel HRB 4086 Geschaeftsfuehrer: Dr. Lueder Hogrefe Vorsitzender des Aufsichtsrats: Patrick K. Peppe Diese Nachricht enthaelt vertrauliche oder rechtlich geschuetzte Informationen. Wenn Sie nicht der beabsichtigte Empfaenger sind, informieren Sie bitte sofort den Absender und loeschen Sie diese Nachricht. Das unbefugte Kopieren dieser Nachricht oder die unbefugte Weitergabe der enthaltenen Informationen ist nicht gestattet. The information contained in this message is confidential or protected by law. If you are not the intended recipient, please contact the sender and delete this message. Any unauthorized copying of this message or unauthorized distribution of the information contained herein is prohibited.

1 0

Re: [flashrom] [PATCH 1/3] Factor out SPI write/read chunking wrappers.
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Hi Michael, thanks for your patch! Am 05.05.2011 03:04 schrieb Michael Karcher: > diff --git a/dummyflasher.c b/dummyflasher.c > index d818a84..b6e67db 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -507,12 +507,6 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > -{ > - /* Maximum read length is unlimited, use 64kB. */ > - return spi_read_chunked(flash, buf, start, len, 64 * 1024); > -} > - > int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > Any reason you didn't kill dummy_write_256()? If you kill it, please remove it from programmer.h and adjust SPI_CONTROLLER_DUMMY in spi.c accordingly. Thanks. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

Re: [flashrom] [PATCH 3/3] kill central list of SPI programmers
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Am 05.05.2011 03:04 schrieb Michael Karcher: > Remove the array spi_programmer, replace it by dynamic registration > instead. Also initially start with no busses supported, and switch to > the default non-SPI only for the internal programmer. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for your patch! I have a few minor nitpicks and design questions, but the code changes seem to be bug-free, so you get an Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Your patch is very readable and got me thinking about future directions of that code, especially multiple registrations... so take the review with a grain of salt. > diff --git a/dummyflasher.c b/dummyflasher.c > index c4c9c4e..fdaa5f2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -339,7 +339,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt > } > #endif > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -375,12 +375,22 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > spi_write_256_chunksize); > } > > +static const struct spi_programmer spi_programmer_dummyflasher = { > + .type = SPI_CONTROLLER_DUMMY, > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_UNSPECIFIED, > 256 instead? > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = dummy_spi_write_256, > Same comment as for patch 1 of the series. AFAICS dummy_spi_write_256 should be replaced by the default one. > +}; > + > int dummy_init(void) > { > char *bustext = NULL; > Please fix the whitespace (spaces instead of tabs) in it87spi.c and dummyflasher.c. Apparently a newline is missing at the end of spi.c. > diff --git a/bitbang_spi.c b/bitbang_spi.c > index be30944..ca28434 100644 > --- a/bitbang_spi.c > +++ b/bitbang_spi.c > @@ -81,7 +81,7 @@ static uint8_t bitbang_spi_readwrite_byte(uint8_t val) > return ret; > } > > -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -106,6 +106,16 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_bitbang = { > Can you make this one non-const to allow changing .type? > + .type = SPI_CONTROLLER_BITBANG, > And leave type empty, to be filled by bitbang_spi_init()? > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_WRITE_UNLIMITED, > + .command = bitbang_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = default_spi_write_256, > +}; > + > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) > Could you extend this function signature to have an additional enum spi_controller parameter? If each bitbang-using programmer calls bitbang_spi_init(spi_controller, master, halfperiod) we can keep the spi_controller enums unchanged for now which would help us keep things consistent (for example, ichspi.c uses 3 different spi_controller enums for the same functions). > { > /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, > Insert in this function: spi_programmer_bitbang.type=spi_controller; > diff --git a/programmer.h b/programmer.h > index fefb9cd..53a50f6 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -527,7 +518,6 @@ enum spi_controller { > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > - SPI_CONTROLLER_MCP6X_BITBANG, > #endif > #endif > #if CONFIG_FT2232_SPI == 1 > @@ -542,16 +532,9 @@ enum spi_controller { > #if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > #endif > -#if CONFIG_RAYER_SPI == 1 > - SPI_CONTROLLER_RAYER, > -#endif > -#if CONFIG_NICINTEL_SPI == 1 > - SPI_CONTROLLER_NICINTEL, > -#endif > -#if CONFIG_OGP_SPI == 1 > - SPI_CONTROLLER_OGP, > +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1&& (defined(__i386__) || defined(__x86_64__))) > + SPI_CONTROLLER_BITBANG, > #endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > }; > extern const int spi_programmer_count; > If you use enum spi_controller as parameter for bitbang_spi_init(), we don't need an extra SPI_CONTROLLER_BITBANG and can keep the programmer-specific ones. The calls to bitbang_spi_init() in mcp6x_spi.c, nicintel_spi.c, ogp_spi.c and rayer_spi.c would need to be adjusted as well. I plan to add a union private_data{} to struct spi_programmer to allow storing stuff like struct bitbang_spi_master, avoiding the need for programmer-internal static configuration variables. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 5

[commit] r1299 - trunk
by repository service 11 May '11

11 May '11

Author: mkarcher Date: Wed May 11 19:07:07 2011 New Revision: 1299 URL: http://flashrom.org/trac/flashrom/changeset/1299 Log: kill central list of SPI programmers Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/dediprog.c trunk/dummyflasher.c trunk/flashrom.c trunk/ft2232_spi.c trunk/ichspi.c trunk/internal.c trunk/it85spi.c trunk/it87spi.c trunk/mcp6x_spi.c trunk/nicintel_spi.c trunk/ogp_spi.c trunk/programmer.h trunk/rayer_spi.c trunk/sb600spi.c trunk/spi.c trunk/spi25.c trunk/wbsio_spi.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/bitbang_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -64,6 +64,19 @@ bitbang_spi_master->release_bus(); } +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_bitbang = { + .type = SPI_CONTROLLER_BITBANG, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, @@ -85,6 +98,8 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; + register_spi_programmer(&spi_programmer_bitbang); + /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); @@ -127,7 +142,7 @@ return ret; } -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/buspirate_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -81,6 +81,19 @@ return 0; } +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .max_data_read = 12, + .max_data_write = 12, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + static const struct buspirate_spispeeds spispeeds[] = { {"30k", 0x0}, {"125k", 0x1}, @@ -230,8 +243,7 @@ return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + register_spi_programmer(&spi_programmer_buspirate); return 0; } @@ -271,7 +283,7 @@ return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/dediprog.c Wed May 11 19:07:07 2011 (r1299) @@ -248,7 +248,7 @@ return 0; } -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; /* chunksize must be 512, other sizes will NOT work at all. */ @@ -293,7 +293,7 @@ return 0; } -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; @@ -310,7 +310,7 @@ return ret; } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -526,6 +526,16 @@ return millivolt; } +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = dediprog_spi_write_256, +}; + /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { @@ -606,8 +616,7 @@ return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + register_spi_programmer(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/dummyflasher.c Wed May 11 19:07:07 2011 (r1299) @@ -60,6 +60,19 @@ static int spi_write_256_chunksize = 256; +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_dummyflasher = { + .type = SPI_CONTROLLER_DUMMY, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = dummy_spi_write_256, +}; int dummy_init(void) { char *bustext = NULL; @@ -91,8 +104,7 @@ msg_pdbg("Enabling support for %s flash.\n", "FWH"); } if (strstr(bustext, "spi")) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) @@ -471,7 +483,7 @@ } #endif -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -507,7 +519,7 @@ return 0; } -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/flashrom.c Wed May 11 19:07:07 2011 (r1299) @@ -521,10 +521,7 @@ .fwh = 0xffffffff, .spi = 0xffffffff }; - /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. - */ - buses_supported = CHIP_BUSTYPE_NONSPI; + buses_supported = CHIP_BUSTYPE_NONE; /* Default to top aligned flash at 4 GB. */ flashbase = 0; /* Registering shutdown functions is now allowed. */ @@ -1712,10 +1709,6 @@ msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ft2232_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -128,6 +128,19 @@ return 0; } +static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .max_data_read = 64 * 1024, + .max_data_write = 256, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ft2232_spi_init(void) { int f; @@ -261,13 +274,12 @@ // msg_pdbg("\nft2232 chosen\n"); - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + register_spi_programmer(&spi_programmer_ft2232); return 0; } -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ichspi.c Wed May 11 19:07:07 2011 (r1299) @@ -313,7 +313,7 @@ return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -388,7 +388,7 @@ } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: /* Register undo only for enable_undo=1, i.e. first call. */ @@ -432,7 +432,7 @@ { #define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; @@ -801,7 +801,7 @@ static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -834,7 +834,7 @@ return -1; } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -900,7 +900,7 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_ICH9: @@ -953,7 +953,7 @@ return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1051,6 +1051,26 @@ access_names[rwperms]); } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1059,20 +1079,19 @@ uint16_t spibar_offset, tmp2; uint32_t tmp; - buses_supported |= CHIP_BUSTYPE_SPI; switch (ich_generation) { case 7: - spi_controller = SPI_CONTROLLER_ICH7; + register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1083,7 +1102,7 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1211,6 +1230,16 @@ return 0; } +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .max_data_read = 16, + .max_data_write = 16, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int via_init_spi(struct pci_dev *dev) { uint32_t mmio_base; @@ -1221,8 +1250,8 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/internal.c Wed May 11 19:07:07 2011 (r1299) @@ -179,6 +179,11 @@ get_io_perms(); + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ /* Set all options you want -- here we stick with the defaults */ Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/it85spi.c Wed May 11 19:07:07 2011 (r1299) @@ -262,12 +262,22 @@ ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */ #endif - /* Set this as spi controller. */ - spi_controller = SPI_CONTROLLER_IT85XX; - return 0; } +static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static const struct spi_programmer spi_programmer_it85xx = { + .type = SPI_CONTROLLER_IT85XX, + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int it85xx_spi_init(struct superio s) { int ret; @@ -284,7 +294,8 @@ if (buses_supported & CHIP_BUSTYPE_FWH) msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); /* Really leave FWH enabled? */ - buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + /* Set this as spi controller. */ + register_spi_programmer(&spi_programmer_it85xx); } return ret; } @@ -303,7 +314,7 @@ * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/it87spi.c Wed May 11 19:07:07 2011 (r1299) @@ -104,6 +104,21 @@ return; } +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; @@ -180,9 +195,8 @@ it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; /* FIXME: Add the SPI bus or replace the other buses with it? */ - buses_supported |= CHIP_BUSTYPE_SPI; + register_spi_programmer(&spi_programmer_it87xx); return 0; } @@ -234,7 +248,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -327,7 +341,7 @@ * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { fast_spi = 0; @@ -344,7 +358,7 @@ return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/mcp6x_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -166,9 +166,6 @@ return 1; } - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; - return 0; } Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/nicintel_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -162,9 +162,6 @@ if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_NICINTEL; - return 0; } Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/ogp_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -128,9 +128,6 @@ if (bitbang_spi_init(&bitbang_spi_master_ogp, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_OGP; - return 0; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed May 11 19:07:02 2011 (r1298) +++ trunk/programmer.h Wed May 11 19:07:07 2011 (r1299) @@ -372,9 +372,6 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -485,7 +482,6 @@ const char *device_name; }; int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -505,7 +501,6 @@ /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -514,14 +509,10 @@ }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ struct decode_sizes { @@ -552,7 +543,6 @@ SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, - SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -567,16 +557,9 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif -#if CONFIG_RAYER_SPI == 1 - SPI_CONTROLLER_RAYER, -#endif -#if CONFIG_NICINTEL_SPI == 1 - SPI_CONTROLLER_NICINTEL, -#endif -#if CONFIG_OGP_SPI == 1 - SPI_CONTROLLER_OGP, +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) + SPI_CONTROLLER_BITBANG, #endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; @@ -584,6 +567,7 @@ #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + enum spi_controller type; int max_data_read; int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, @@ -595,13 +579,13 @@ int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -609,40 +593,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); int via_init_spi(struct pci_dev *dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_send_multicommand(struct spi_command *cmds); #endif /* it85spi.c */ int it85xx_spi_init(struct superio s); int it85xx_shutdown(void); -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); int init_superio_ite(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ #if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); #endif /* wbsio_spi.c */ #if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serprog.c */ Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/rayer_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -134,9 +134,6 @@ if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_RAYER; - return 0; } Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/sb600spi.c Wed May 11 19:07:07 2011 (r1299) @@ -89,7 +89,7 @@ ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -192,6 +192,16 @@ return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .max_data_read = 8, + .max_data_write = 5, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int sb600_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; @@ -304,8 +314,7 @@ /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + register_spi_programmer(&spi_programmer_sb600); return 0; } Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/spi.c Wed May 11 19:07:07 2011 (r1299) @@ -30,200 +30,42 @@ #include "programmer.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT85XX */ - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .max_data_read = 8, - .max_data_write = 5, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .max_data_read = 16, - .max_data_write = 16, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1, - }, - - { /* SPI_CONTROLLER_MCP6X_BITBANG */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .max_data_read = 64 * 1024, - .max_data_write = 256, - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .max_data_read = 12, - .max_data_write = 12, - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = dediprog_spi_write_256, - }, -#endif - -#if CONFIG_RAYER_SPI == 1 - { /* SPI_CONTROLLER_RAYER */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_NICINTEL_SPI == 1 - { /* SPI_CONTROLLER_NICINTEL */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_OGP_SPI == 1 - { /* SPI_CONTROLLER_OGP */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ +const struct spi_programmer spi_programmer_none = { + .type = SPI_CONTROLLER_NONE, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = NULL, + .multicommand = NULL, + .read = NULL, + .write_256 = NULL, }; -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer = &spi_programmer_none; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -257,7 +99,7 @@ int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_read; + int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -269,7 +111,7 @@ int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_write; + int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -282,7 +124,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); @@ -308,7 +150,7 @@ "access window.\n"); msg_perr("Read will probably return garbage.\n"); } - return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len); + return spi_programmer->read(flash, buf, addrbase + start, len); } /* @@ -320,14 +162,14 @@ /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* @@ -337,7 +179,7 @@ */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: @@ -349,3 +191,9 @@ return 0; } } + +void register_spi_programmer(const struct spi_programmer *pgm) +{ + spi_programmer = pgm; + buses_supported |= CHIP_BUSTYPE_SPI; +} \ No newline at end of file Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/spi25.c Wed May 11 19:07:07 2011 (r1299) @@ -178,7 +178,7 @@ /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1351,7 +1351,7 @@ .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Wed May 11 19:07:02 2011 (r1298) +++ trunk/wbsio_spi.c Wed May 11 19:07:07 2011 (r1299) @@ -60,6 +60,20 @@ return flashport; } +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); + +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1, +}; + int wbsio_check_for_spi(void) { if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) @@ -68,8 +82,7 @@ msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; @@ -97,7 +110,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -181,7 +194,7 @@ return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); }

1 0

[commit] r1298 - trunk
by repository service 11 May '11

11 May '11

Author: mkarcher Date: Wed May 11 19:07:02 2011 New Revision: 1298 URL: http://flashrom.org/trac/flashrom/changeset/1298 Log: Factor out SPI write/read chunking wrappers. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/dummyflasher.c trunk/ft2232_spi.c trunk/ichspi.c trunk/it85spi.c trunk/programmer.h trunk/sb600spi.c trunk/spi.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/bitbang_spi.c Wed May 11 19:07:02 2011 (r1298) @@ -151,14 +151,3 @@ return 0; } - -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/buspirate_spi.c Wed May 11 19:07:02 2011 (r1298) @@ -326,13 +326,3 @@ return ret; } - -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 12); -} - -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 12); -} Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/dummyflasher.c Wed May 11 19:07:02 2011 (r1298) @@ -507,12 +507,6 @@ return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64kB. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/ft2232_spi.c Wed May 11 19:07:02 2011 (r1298) @@ -352,17 +352,6 @@ return failed ? -1 : 0; } -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} - void print_supported_usbdevs(const struct usbdev_status *devs) { int i; Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/ichspi.c Wed May 11 19:07:02 2011 (r1298) @@ -834,26 +834,6 @@ return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_read_chunked(flash, buf, start, len, maxdata); -} - -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_write_chunked(flash, buf, start, len, maxdata); -} - int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/it85spi.c Wed May 11 19:07:02 2011 (r1298) @@ -347,14 +347,4 @@ return 0; } -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 64); -} - -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 64); -} - #endif Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun May 8 02:24:18 2011 (r1297) +++ trunk/programmer.h Wed May 11 19:07:02 2011 (r1298) @@ -374,7 +374,6 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif @@ -487,8 +486,6 @@ }; int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -509,8 +506,6 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -520,8 +515,6 @@ int buspirate_spi_init(void); int buspirate_spi_shutdown(void); int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); @@ -586,7 +579,13 @@ SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; + +#define MAX_DATA_UNSPECIFIED 0 +#define MAX_DATA_READ_UNLIMITED 64 * 1024 +#define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + int max_data_read; + int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -601,6 +600,8 @@ int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -610,8 +611,6 @@ int via_init_spi(struct pci_dev *dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); #endif @@ -620,8 +619,6 @@ int it85xx_shutdown(void); int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len); -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -638,8 +635,6 @@ int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* wbsio_spi.c */ Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/sb600spi.c Wed May 11 19:07:02 2011 (r1298) @@ -43,17 +43,6 @@ static uint8_t *sb600_spibar = NULL; -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 8 bytes. */ - return spi_read_chunked(flash, buf, start, len, 8); -} - -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 5); -} - static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun May 8 02:24:18 2011 (r1297) +++ trunk/spi.c Wed May 11 19:07:02 2011 (r1298) @@ -34,6 +34,8 @@ const struct spi_programmer spi_programmer[] = { { /* SPI_CONTROLLER_NONE */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = NULL, .multicommand = NULL, .read = NULL, @@ -43,27 +45,35 @@ #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_ICH9 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT85XX */ + .max_data_read = 64, + .max_data_write = 64, .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = it85_spi_read, - .write_256 = it85_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT87XX */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand, .read = it8716f_spi_chip_read, @@ -71,20 +81,26 @@ }, { /* SPI_CONTROLLER_SB600 */ + .max_data_read = 8, + .max_data_write = 5, .command = sb600_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_VIA */ + .max_data_read = 16, + .max_data_write = 16, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_WBSIO */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, .multicommand = default_spi_send_multicommand, .read = wbsio_spi_read, @@ -92,43 +108,53 @@ }, { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #endif #if CONFIG_FT2232_SPI == 1 { /* SPI_CONTROLLER_FT2232 */ + .max_data_read = 64 * 1024, + .max_data_write = 256, .command = ft2232_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DUMMY == 1 { /* SPI_CONTROLLER_DUMMY */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, + .read = default_spi_read, .write_256 = dummy_spi_write_256, }, #endif #if CONFIG_BUSPIRATE_SPI == 1 { /* SPI_CONTROLLER_BUSPIRATE */ + .max_data_read = 12, + .max_data_write = 12, .command = buspirate_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DEDIPROG == 1 { /* SPI_CONTROLLER_DEDIPROG */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, @@ -138,28 +164,34 @@ #if CONFIG_RAYER_SPI == 1 { /* SPI_CONTROLLER_RAYER */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_NICINTEL_SPI == 1 { /* SPI_CONTROLLER_NICINTEL */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_OGP_SPI == 1 { /* SPI_CONTROLLER_OGP */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif @@ -223,6 +255,30 @@ return result; } +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_read; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI read chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_read_chunked(flash, buf, start, len, max_data); +} + +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_write; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI write chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_write_chunked(flash, buf, start, len, max_data); +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0;

1 0

flashrom, hardened gentoo (grsecurity) and iopl()
by Антон Кочков 10 May '11

10 May '11

Good day! Just found that flashrom doesnt work on some hardened configuration - Hardened Gentoo - on hardened kernel-2.6.38 Linux xserver 2.6.38-hardened #1 SMP Wed Apr 20 02:19:23 CEST 2011 x86_64 Intel(R) Core(TM) i7 CPU 930 @ 2.80GHz GenuineIntel GNU/Linux flashrom v0.9.3-r1297 on Linux 2.6.38-hardened (x86_64), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1530M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 996 us, 10000 myus = 9977 us, 4 myus = 4 us, OK. Initializing internal programmer ERROR: Could not get I/O privileges (Operation not permitted). You need to be root. And this from dmesg: [1578171.686680] grsec: From 79.111.220.160: denied use of iopl() by /home/xvilka/flashrom/flashrom[flashrom:10596] uid/euid:0/0 gid/egid:0/0, parent /bin/bash[bash:10591] uid/euid:0/0 gid/egid:0/0 [1578218.043347] grsec: From 79.111.220.160: denied use of iopl() by /home/xvilka/flashrom/flashrom[flashrom:10612] uid/euid:0/0 gid/egid:0/0, parent /bin/bash[bash:10606] uid/euid:0/0 gid/egid:0/0 [1578388.047996] grsec: From 79.111.220.160: denied use of iopl() by /home/xvilka/flashrom/flashrom[flashrom:10645] uid/euid:0/0 gid/egid:0/0, parent /bin/bash[bash:10606] uid/euid:0/0 gid/egid:0/0 And found this theme http://forums.grsecurity.net/viewtopic.php?t=1654 So, for access ioperm() and iopl() you need disable "Disable Privileged I/O (CONFIG_GRKERSEC_IO)" option in kernel config. Can we print this message when found such configuration? Are there way to make port access without iopl()? Best regards, Anton Kochkov.

3 3

Tyan S8230 support
by Anton Rommerskirchen 08 May '11

08 May '11

Hello ! got a littel talk with the helpstar guys from tyan. The problem is to get a S8230 to be updated. the suggested way of using a usb stick means to take a windows 98 or 95, format and so on. I tried freedos and their tool stuck - no flash at all. for linux i got a hint to flashrom, but the board seems to be not supportet now. is their any way to circumvent this or do i have a chance to get support for the S8230 board in near future ? according to the doc its a AMD SP5100 and SR5690, winbond w83627 chispset. best regards Anton Rommerskirchen

1 0

[PATCH] Intel NIC with parallel flash
by Carl-Daniel Hailfinger 08 May '11

08 May '11

Intel NIC with parallel flash support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> -- http://www.hailfinger.org/

2 4

[commit] r1297 - trunk
by repository service 08 May '11

08 May '11

Author: hailfinger Date: Sun May 8 02:24:18 2011 New Revision: 1297 URL: http://flashrom.org/trac/flashrom/changeset/1297 Log: Intel NIC with parallel flash support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Anton Kochkov <anton.kochkov(a)gmail.com> Acked-by: Anton Kochkov <anton.kochkov(a)gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Added: trunk/nicintel.c Modified: trunk/Makefile trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat May 7 21:19:36 2011 (r1296) +++ trunk/Makefile Sun May 8 02:24:18 2011 (r1297) @@ -178,6 +178,9 @@ # Disable National Semiconductor NICs until support is complete and tested. CONFIG_NICNATSEMI ?= no +# Always enable Intel NICs for now. +CONFIG_NICINTEL ?= yes + # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes @@ -297,6 +300,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1' +PROGRAMMER_OBJS += nicintel.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_NICINTEL_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_NICINTEL_SPI=1' PROGRAMMER_OBJS += nicintel_spi.o Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat May 7 21:19:36 2011 (r1296) +++ trunk/flashrom.c Sun May 8 02:24:18 2011 (r1297) @@ -52,7 +52,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -92,6 +92,9 @@ #if CONFIG_RAYER_SPI == 1 PROGRAMMER_RAYER_SPI #endif +#if CONFIG_NICINTEL == 1 + PROGRAMMER_NICINTEL +#endif #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI #endif @@ -386,6 +389,25 @@ .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + +#if CONFIG_NICINTEL == 1 + { + .name = "nicintel", + .init = nicintel_init, + .shutdown = nicintel_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif Added: trunk/nicintel.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/nicintel.c Sun May 8 02:24:18 2011 (r1297) @@ -0,0 +1,109 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multi… */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +uint8_t *nicintel_bar; +uint8_t *nicintel_control_bar; + +const struct pcidev_status nics_intel[] = { + {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, + + {}, +}; + +/* Arbitrary limit, taken from the datasheet I just had lying around. + * 128 kByte on the 82559 device. Or not. Depends on whom you ask. + */ +#define NICINTEL_MEMMAP_SIZE (128 * 1024) +#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1) + +#define CSR_FCR 0x0c + +int nicintel_init(void) +{ + uintptr_t addr; + + /* Needed only for PCI accesses on some platforms. + * FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms? + */ + get_io_perms(); + + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + * FIXME: BAR2 is not available if the device uses the CardBus function. + */ + addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); + + nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); + if (nicintel_bar == ERROR_PTR) + goto error_out; + + /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */ + addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel); + /* FIXME: This is not an aligned mapping. Use 4k? */ + nicintel_control_bar = physmap("Intel NIC control/status reg", addr, 0x10); + if (nicintel_control_bar == ERROR_PTR) + goto error_out; + + /* FIXME: This register is pretty undocumented in all publicly available + * documentation from Intel. Let me quote the complete info we have: + * "Flash Control Register: The Flash Control register allows the CPU to + * enable writes to an external Flash. The Flash Control Register is a + * 32-bit field that allows access to an external Flash device." + * Ah yes, we also know where it is, but we have absolutely _no_ idea + * what we should do with it. Write 0x0001 because we have nothing + * better to do with our time. + */ + pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + + return 0; + +error_out: + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +int nicintel_shutdown(void) +{ + physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void nicintel_chip_writeb(uint8_t val, chipaddr addr) +{ + pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} + +uint8_t nicintel_chip_readb(const chipaddr addr) +{ + return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat May 7 21:19:36 2011 (r1296) +++ trunk/print.c Sun May 8 02:24:18 2011 (r1297) @@ -304,6 +304,11 @@ /* FIXME */ printf("RayeR parallel port programmer\n"); #endif +#if CONFIG_NICINTEL == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICINTEL].name); + print_supported_pcidevs(nics_intel); +#endif #if CONFIG_NICINTEL_SPI == 1 printf("\nSupported devices for the %s programmer:\n", programmer_table[PROGRAMMER_NICINTEL_SPI].name); Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Sat May 7 21:19:36 2011 (r1296) +++ trunk/print_wiki.c Sun May 8 02:24:18 2011 (r1297) @@ -247,7 +247,7 @@ } /* Not needed for CONFIG_INTERNAL, but for all other PCI-based programmers. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; @@ -298,6 +298,9 @@ #if CONFIG_ATAHPT == 1 print_supported_pcidevs_wiki(ata_hpt); #endif +#if CONFIG_NICINTEL == 1 + print_supported_pcidevs_wiki(nics_intel); +#endif #if CONFIG_NICINTEL_SPI == 1 print_supported_pcidevs_wiki(nics_intel_spi); #endif Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat May 7 21:19:36 2011 (r1296) +++ trunk/programmer.h Sun May 8 02:24:18 2011 (r1297) @@ -67,6 +67,9 @@ #if CONFIG_RAYER_SPI == 1 PROGRAMMER_RAYER_SPI, #endif +#if CONFIG_NICINTEL == 1 + PROGRAMMER_NICINTEL, +#endif #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif @@ -232,7 +235,7 @@ #endif /* print.c */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 void print_supported_pcidevs(const struct pcidev_status *devs); #endif @@ -420,6 +423,15 @@ extern const struct pcidev_status nics_natsemi[]; #endif +/* nicintel.c */ +#if CONFIG_NICINTEL == 1 +int nicintel_init(void); +int nicintel_shutdown(void); +void nicintel_chip_writeb(uint8_t val, chipaddr addr); +uint8_t nicintel_chip_readb(const chipaddr addr); +extern const struct pcidev_status nics_intel[]; +#endif + /* nicintel_spi.c */ #if CONFIG_NICINTEL_SPI == 1 int nicintel_spi_init(void);

1 0

[PATCH] Fix multiple detection of the same chip
by Carl-Daniel Hailfinger 07 May '11

07 May '11

Fix multiple detection of the same chip. r1293 introduced a bug which caused probing to loop at the first found chip. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> -- http://www.hailfinger.org/

2 2

[commit] r1296 - trunk
by repository service 07 May '11

07 May '11

Author: hailfinger Date: Sat May 7 21:19:36 2011 New Revision: 1296 URL: http://flashrom.org/trac/flashrom/changeset/1296 Log: Fix multiple detection of the same chip. r1293 introduced a bug which caused probing to loop at the first found chip. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/cli_classic.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Thu May 5 19:52:07 2011 (r1295) +++ trunk/cli_classic.c Sat May 7 21:19:36 2011 (r1296) @@ -368,6 +368,7 @@ if (startchip == -1) break; chipcount++; + startchip++; } if (chipcount > 1) {

1 0

Re: [flashrom] flashrom log file
by Idwer Vollering 07 May '11

07 May '11

2011/5/7 Alexander <Volosaty(a)i.ua>: >> > Motherboad - AsRock K10N78, chipset GeForce8200 >> flashrom v0.9.2-r1028 on Linux 2.6.35-24-generic (x86_64), built with libpci >> > 3.0.0, GCC 4.4.4, little endian >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> >> Version 0.9.3 supports your mainboard: >> http://flashrom.org/trac/flashrom/changeset/1113 > Still no go. Updated today via CVS, chipset and flash device detected, but still with quirks. > > Output 'flashrom -V': > > flashrom v0.9.3-r1295 on Linux 2.6.35-24-generic (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian Can you try r1292 ? Right now, newer revsions have a bug that.. (read on) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 933M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10004 us, 4 myus = 5 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "To Be Filled By O.E.M." > DMI string system-product-name: "To Be Filled By O.E.M." > DMI string system-version: "To Be Filled By O.E.M." > DMI string baseboard-manufacturer: "ASRock" > DMI string baseboard-product-name: "K10N78" > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found chipset "NVIDIA MCP78S", enabling flash write... chipset PCI ID is 10de:075c, This chipset is not really supported yet. Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 > Flash bus type is SPI > Found SMBus device 10de:0752 at 00:01:1 > MCP SPI BAR is at 0xf9e80000 > SPI control is 0xc052, req=0, gnt=0 > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for your > chipset. Thanks. > OK. > This chipset supports the following protocols: SPI. > Probing for AMD Am29F010A/B, 128 KB: skipped. > Probing for AMD Am29F002(N)BB, 256 KB: skipped. > Probing for AMD Am29F002(N)BT, 256 KB: skipped. > Probing for AMD Am29F016D, 2048 KB: skipped. > Probing for AMD Am29F040B, 512 KB: skipped. > Probing for AMD Am29F080B, 1024 KB: skipped. > Probing for AMD Am29LV001BB, 128 KB: skipped. > Probing for AMD Am29LV001BT, 128 KB: skipped. > Probing for AMD Am29LV002BB, 256 KB: skipped. > Probing for AMD Am29LV002BT, 256 KB: skipped. > Probing for AMD Am29LV004BB, 512 KB: skipped. > Probing for AMD Am29LV004BT, 512 KB: skipped. > Probing for AMD Am29LV008BB, 1024 KB: skipped. > Probing for AMD Am29LV008BT, 1024 KB: skipped. > Probing for AMD Am29LV040B, 512 KB: skipped. > Probing for AMD Am29LV081B, 1024 KB: skipped. > Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for AMIC A29002B, 256 KB: skipped. > Probing for AMIC A29002T, 256 KB: skipped. > Probing for AMIC A29040B, 512 KB: skipped. > Probing for AMIC A49LF040A, 512 KB: skipped. > Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT29C512, 64 KB: skipped. > Probing for Atmel AT29C010A, 128 KB: skipped. > Probing for Atmel AT29C020, 256 KB: skipped. > Probing for Atmel AT29C040A, 512 KB: skipped. > Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Atmel AT49BV512, 64 KB: skipped. > Probing for Atmel AT49F020, 256 KB: skipped. > Probing for Atmel AT49F002(N), 256 KB: skipped. > Probing for Atmel AT49F002(N)T, 256 KB: skipped. > Probing for Bright BM29F040, 512 KB: skipped. > Probing for EMST F49B002UA, 256 KB: skipped. > Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Eon EN29F010, 128 KB: skipped. > Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. > Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. > Probing for Fujitsu MBM29F004BC, 512 KB: skipped. > Probing for Fujitsu MBM29F004TC, 512 KB: skipped. > Probing for Fujitsu MBM29F400BC, 512 KB: skipped. > Probing for Fujitsu MBM29F400TC, 512 KB: skipped. > Probing for Hyundai HY29F002T, 256 KB: skipped. > Probing for Hyundai HY29F002B, 256 KB: skipped. > Probing for Hyundai HY29F040A, 512 KB: skipped. > Probing for Intel 28F001BN/BX-B, 128 KB: skipped. > Probing for Intel 28F001BN/BX-T, 128 KB: skipped. > Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. > Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. > Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. > Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. > Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. > Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. > Probing for Intel 82802AB, 512 KB: skipped. > Probing for Intel 82802AC, 1024 KB: skipped. > Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. > Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. > Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set Show a chip being present multiple times, even if this is not the case: > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. > Multiple flash chips were detected: MX25L8005 MX25L8005 MX25L8005 > Please specify which chip to use with the -c <chipname> option. > > Best regards. ShuricK > [Меломан][Hard&Heavy Rock][Киголюб] > [Сентиментальный романтик от сурового Hi-Tech] > > -- реклама ----------------------------------------------------------- > Никогда не покупали в интернете? > Лучшее место для покупок онлайн - http://aukro.ua > >

1 0

flashrom log file
by Alexander 07 May '11

07 May '11

Motherboad - AsRock K10N78, chipset GeForce8200 Best regards. ShuricK [Меломан][Hard&Heavy Rock][Киголюб] [Сентиментальный романтик от сурового Hi-Tech] -- реклама ----------------------------------------------------------- Никогда не покупали в интернете? Лучшее место для покупок онлайн - http://aukro.ua

2 3

EN25F40
by Olivier Schonken 07 May '11

07 May '11

Hi Just wanted to let you guys know that the probe, read and write for a EN 25F40 chip worked beautifully with a ft2232H device. Unfortunately didn't work in circuit, but when I removed the EEPROM from its circuit, the programming worked like a charm. Thanks for a very good product. Regards Olivier Schonken

1 0

help me finish support for my chipset
by 密思刘 07 May '11

07 May '11

flashrom -V flashrom v0.9.2-r1141 on Linux 2.6.36.1-ck2-amd64-21 (x86_64), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 261M loops per second, 10 myus = 11 us, 100 myus = 99 us, 1000 myus = 1561 us, 10000 myus = 17172 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer, inc." DMI string system-product-name: "Aspire 4520G " DMI string system-version: "Not Applicable" DMI string baseboard-manufacturer: "Acer, Inc." DMI string baseboard-product-name: "Mono " DMI string baseboard-version: "Not Applicable" DMI string chassis-type: "Other" Found chipset "NVIDIA MCP67", enabling flash write... chipset PCI ID is 10de:0548, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0542 at 00:01:1 MCP SPI BAR is at 0xf2200000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f56, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. debian6:~#

1 0

flashrom -V for M4N78
by Niels Boehm 07 May '11

07 May '11

Hello, this is a vanilla M4N78 (_no_ Pro, SE, AM, VM) from ASUS. While the DMI only says Rev X.0x, the print on the board says REV. 1.01G. flashrom -V output attached. Feel free to contact me if you need further information. Regards, Niels Böhm

1 0

New possible parallel programmator - BiDiPro
by Антон Кочков 06 May '11

06 May '11

Found one more cheap parallel programmator -BiDiPro LPT read: 90 Кб/сек power voltage: 4.5 - 6.0 V (4 levels) flash voltage: 5.5 - 26.0 V (32 levels) erase voltage: 12.0, 14.0 V 6 LEDs Support: 27cXXX - UV EPROM 28fXXX - EEPROM 29cXXX - Flash memory 29fXXX - Flash memory 49fXXX - Flash memory 49FHW - Firmware Hub 62cXXX - STATIC RAM 24cXXX - I2C SEEPROM 93cXX - MW SEEPROM 89c5x - FLASH/EPROM MCU 89cx051 - ATMEL FLASH MCU PIC16F8x - Microchip MCU Attached schematics, flash utility and its sources Best regards, Anton Kochkov.

1 0

[commit] r1295 - trunk
by repository service 05 May '11

05 May '11

Author: mkarcher Date: Thu May 5 19:52:07 2011 New Revision: 1295 URL: http://flashrom.org/trac/flashrom/changeset/1295 Log: Add support for the Via VX855 chipset Signed-off-by: John Schmerge <jbschmerge(a)gmail.com> for Devon IT Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu May 5 09:12:40 2011 (r1294) +++ trunk/chipset_enable.c Thu May 5 19:52:07 2011 (r1295) @@ -1164,6 +1164,7 @@ {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, + {0x1106, 0x8409, OK, "VIA", "VX855", enable_flash_vt823x}, {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},

1 0

[PATCH] Revamp board-specific quirk handling, laptop support
by Carl-Daniel Hailfinger 05 May '11

05 May '11

Currently flashrom runs all board-specific quirks after laptop detection is done. This means there is no way to reflash a laptop without using the programmer parameter laptop=force_I_want_a_brick. Handle board-specific quirks in three phases: 1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes, or unhiding the Super I/O) 2. Before the laptop enforcement decision (e.g. whitelisting a laptop for flashing) 3. After chipset enabling (all current board enables) Implementation note: All entries in board_pciid_enables get an additional phase parameter. With this patch, it should be possible to whitelist supported laptops with a matching entry (phase P2) in board_pciid_enables which points to a function setting laptop_ok=1. (In case DMI is broken, matching might be a little bit more difficult, but it is still doable.) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-whitelist_laptops/internal.c =================================================================== --- flashrom-whitelist_laptops/internal.c (Revision 1263) +++ flashrom-whitelist_laptops/internal.c (Arbeitskopie) @@ -113,6 +113,7 @@ #endif int is_laptop = 0; +int laptop_ok = 0; int internal_init(void) { @@ -186,6 +187,9 @@ dmi_init(); + /* In case Super I/O probing would cause pretty explosions. */ + board_handle_before_superio(); + /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); #else @@ -196,10 +200,13 @@ */ #endif - /* Warn if a laptop is detected. */ - if (is_laptop) { + /* Check laptop whitelist. */ + board_handle_before_laptop(); + + /* Warn if a non-whitelisted laptop is detected. */ + if (is_laptop && !laptop_ok) { msg_perr("========================================================================\n" - "WARNING! You seem to be running flashrom on a laptop.\n" + "WARNING! You seem to be running flashrom on an unsupported laptop.\n" "Laptops, notebooks and netbooks are difficult to support and we recommend\n" "to use the vendor flashing utility. The embedded controller (EC) in these\n" "machines often interacts badly with flashing.\n" Index: flashrom-whitelist_laptops/programmer.h =================================================================== --- flashrom-whitelist_laptops/programmer.h (Revision 1263) +++ flashrom-whitelist_laptops/programmer.h (Arbeitskopie) @@ -156,6 +156,12 @@ extern const struct penable chipset_enables[]; +enum board_match_phase { + P1, + P2, + P3 +}; + struct board_pciid_enable { /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; @@ -182,6 +188,7 @@ const char *board_name; int max_rom_decode_parallel; + enum board_match_phase phase; int status; int (*enable) (void); }; @@ -234,6 +241,7 @@ void print_supported_pcidevs(const struct pcidev_status *devs); #endif +#if CONFIG_INTERNAL /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); @@ -241,6 +249,8 @@ uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); +void board_handle_before_superio(void); +void board_handle_before_laptop(void); int board_flash_enable(const char *vendor, const char *part); /* chipset_enable.c */ @@ -248,6 +258,7 @@ /* processor_enable.c */ int processor_flash_enable(void); +#endif /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); @@ -287,6 +298,7 @@ void release_io_perms(void); #if CONFIG_INTERNAL == 1 extern int is_laptop; +extern int laptop_ok; extern int force_boardenable; extern int force_boardmismatch; void probe_superio(void); Index: flashrom-whitelist_laptops/board_enable.c =================================================================== --- flashrom-whitelist_laptops/board_enable.c (Revision 1263) +++ flashrom-whitelist_laptops/board_enable.c (Arbeitskopie) @@ -1882,106 +1882,106 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) - {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, - {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, - {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, - {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, - {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, - {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, - {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, - {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, - {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, - {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, - {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, - {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, - {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, - {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, - {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */ - {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, - {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, - {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, - {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, - {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, - {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, - {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, - {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, - {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, - {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, - {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, - {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, - {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, - {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, - {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, - {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, - {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise}, - {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, - {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, - {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, - {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, - {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, - {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, - {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, - {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, - {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, - {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, - {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, - {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, - {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, - {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, - {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, - {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, - {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, - {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, - {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, - {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e}, - {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, - {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, - {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, - {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, - {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, - {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, - {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, P3, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, P3, OK, intel_piix4_gpo26_lower}, + {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, P3, NT, intel_ich_gpio23_raise}, + {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, P3, OK, intel_ich_gpio16_raise}, + {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, P3, OK, intel_ich_gpio16_raise}, + {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, P3, NT, nvidia_mcp_gpio2_lower}, + {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, P3, OK, nvidia_mcp_gpio8_raise}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, P3, NT, nvidia_mcp_gpio4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, P3, OK, via_apollo_gpo4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, P3, OK, via_apollo_gpo4_lower}, + {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, P3, OK, board_acorp_6a815epd}, + {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, P3, OK, w83627hf_gpio24_raise_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, P3, OK, w836xx_memw_enable_2e}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, P3, OK, board_artecgroup_dbe6x}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, P3, OK, board_artecgroup_dbe6x}, + {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, P3, OK, w836xx_memw_enable_2e}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, P3, OK, intel_ich_gpio23_raise}, + {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, P3, OK, intel_ich_gpio23_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, P3, OK, it8712f_gpio3_1_raise}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, P3, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, P3, OK, it8703f_gpio51_raise}, + {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V333", 0, P3, OK, it8703f_gpio51_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, P3, OK, it8712f_gpio3_1_raise}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8Jm", 0, P3, NT, intel_ich_gpio34_raise}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, P3, OK, nvidia_mcp_gpio0_raise}, + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, P3, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */ + {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, P3, NT, w83627ehf_gpio24_raise_2e}, + {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, P3, OK, nvidia_mcp_gpio0_raise}, + {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, P3, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, P3, OK, intel_piix4_gpo18_lower}, + {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, P3, OK, intel_ich_gpio21_raise}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, P3, OK, intel_ich_gpio22_raise}, + {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, P3, NT, intel_ich_gpio22_raise}, + {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, P3, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, P3, NT, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, P3, OK, intel_ich_gpio21_raise}, + {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, P3, OK, it8707f_write_enable_2e}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, P3, NT, intel_ich_gpio32_raise}, + {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, P3, OK, w836xx_memw_enable_2e}, + {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, P3, OK, board_asus_p5a}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, "ASUS", "P5GD1 Pro", 0, P3, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, P3, OK, intel_ich_gpio21_raise}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, P3, OK, nvidia_mcp_gpio10_raise}, + {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, P3, OK, intel_ich_gpio21_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, P3, OK, intel_piix4_gpo30_lower}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, P3, OK, intel_ich_gpio23_raise}, + {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, P3, OK, board_ecs_geforce6100sm_m}, + {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, P3, OK, NULL}, + {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, P3, OK, w836xx_memw_enable_2e}, + {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, "EPoX", "EP-8NPA7I", 0, P3, OK, nvidia_mcp_gpio4_raise}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, P3, OK, nvidia_mcp_gpio31_raise}, + {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, P3, NT, intel_piix4_gpo22_raise}, + {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, "GIGABYTE", "GA-6IEM", 0, P3, NT, intel_ich_gpio25_raise}, + {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, P3, OK, NULL}, + {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, P3, OK, intel_ich_gpio25_raise}, + {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, P3, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, P3, OK, nvidia_mcp_gpio3b_raise}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, P3, OK, nvidia_mcp_gpio21_raise}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, P3, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, P3, OK, board_hp_dl165_g6_enable}, + {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, P3, OK, intel_ich_gpio18_raise}, + {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, P3, OK, board_hp_vl400}, + {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, P3, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, P3, OK, nvidia_mcp_gpio5_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, P3, OK, intel_ich_gpio26_raise}, + {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, P3, OK, board_ibm_x3455}, + {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, P3, OK, wbsio_check_for_spi}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, P3, NT, intel_piix4_gpo27_lower}, + {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, P3, OK, w83627hf_gpio24_raise_2e}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, P3, OK, board_kontron_986lcd_m}, + {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, P3, OK, board_mitac_6513wu}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, P3, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, "MSI", "MS-6163 (MS-6163 Pro)", 0, P3, OK, intel_piix4_gpo14_raise}, + {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, "MSI", "MS-6561 (745 Ultra)", 0, P3, OK, w836xx_memw_enable_2e}, + {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577 (Xenon)", 0, P3, OK, w83627hf_gpio25_raise_2e}, + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, P3, OK, board_msi_kt4v}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, P3, OK, w83627thf_gpio44_raise_2e}, + {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, P3, OK, board_msi_kt4v}, + {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, P3, OK, w836xx_memw_enable_2e}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, P3, OK, board_msi_651ml}, + {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, P3, OK, nvidia_mcp_gpio0c_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, P3, OK, intel_ich_gpio19_raise}, + {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, "MSI", "MS-6391 (845 Pro4)", 0, P3, OK, intel_ich_gpio23_raise}, + {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, P3, OK, w836xx_memw_enable_2e}, + {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, P3, OK, w83627thf_gpio44_raise_4e}, + {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8NGM2-L)", 0, P3, NT, nvidia_mcp_gpio2_raise}, + {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, P3, OK, fdc37b787_gpio50_raise_3f0}, + {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, P3, OK, intel_ich_gpio21_raise}, + {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, P3, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, P3, OK, NULL}, + {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, P3, OK, board_shuttle_fn25}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, P3, OK, via_apollo_gpo0_lower}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, P3, OK, NULL}, + {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, P3, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, P3, OK, w836xx_memw_enable_2e}, + {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, P3, NT, via_vt823x_gpio9_raise}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, P3, OK, via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, P3, OK, via_vt823x_gpio9_raise}, #endif - { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ + { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, P3, NT, NULL}, /* end marker */ }; /* @@ -2041,7 +2041,7 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -const static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase) { const struct board_pciid_enable *board = board_pciid_enables; @@ -2049,6 +2049,8 @@ if ((!board->first_card_vendor || !board->first_card_device) && !board->dmi_pattern) continue; + if (board->phase != phase) + continue; if (!pci_card_find(board->first_vendor, board->first_device, board->first_card_vendor, @@ -2087,6 +2089,62 @@ return NULL; } +static int unsafe_board_handler(const struct board_pciid_enable *board) +{ + if (!board) + return 1; + + if (board->status == OK) + return 0; + + if (!force_boardenable) { + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + "code has not been tested, and thus will not not be executed by default.\n" + "Depending on your hardware environment, erasing, writing or even probing\n" + "can fail without running the board specific code.\n\n" + "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" + "\"internal programmer\") for details.\n", + board->vendor_name, board->board_name); + return 1; + } + msg_pinfo("NOTE: Running an untested board enable procedure.\n" + "Please report success/failure to flashrom(a)flashrom.org\n" + "with your board name and SUCCESS or FAILURE in the subject.\n"); + return 0; +} + +/* FIXME: Should this be identical to board_flash_enable? */ +static int board_handle_phase(enum board_match_phase phase) +{ + const struct board_pciid_enable *board = NULL; + + board = board_match_pci_card_ids(phase); + + if (unsafe_board_handler(board)) + board = NULL; + + if (!board) + return 0; + + if (!board->enable) { + /* Not sure if there is a valid case for this. */ + msg_perr("Board match found, but nothing to do?\n"); + return 0; + } + + return board->enable(); +} + +void board_handle_before_superio(void) +{ + board_handle_phase(P1); +} + +void board_handle_before_laptop(void) +{ + board_handle_phase(P2); +} + int board_flash_enable(const char *vendor, const char *part) { const struct board_pciid_enable *board = NULL; @@ -2096,24 +2154,10 @@ board = board_match_coreboot_name(vendor, part); if (!board) - board = board_match_pci_card_ids(); + board = board_match_pci_card_ids(P3); - if (board && board->status == NT) { - if (!force_boardenable) { - msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" - "code has not been tested, and thus will not not be executed by default.\n" - "Depending on your hardware environment, erasing, writing or even probing\n" - "can fail without running the board specific code.\n\n" - "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" - "\"internal programmer\") for details.\n", - board->vendor_name, board->board_name); + if (unsafe_board_handler(board)) board = NULL; - } else { - msg_pinfo("NOTE: Running an untested board enable procedure.\n" - "Please report success/failure to flashrom(a)flashrom.org\n" - "with your board name and SUCCESS or FAILURE in the subject.\n"); - } - } if (board) { if (board->max_rom_decode_parallel) -- http://www.hailfinger.org/

1 1

[commit] r1294 - trunk
by repository service 05 May '11

05 May '11

Author: hailfinger Date: Thu May 5 09:12:40 2011 New Revision: 1294 URL: http://flashrom.org/trac/flashrom/changeset/1294 Log: Revamp board-specific quirk handling, allow for laptop support Handle board-specific quirks in three phases: 1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes, or unhiding the Super I/O) 2. Before the laptop enforcement decision (e.g. whitelisting a laptop for flashing) 3. After chipset enabling (all current board enables) Implementation note: All entries in board_pciid_enables get an additional phase parameter. Alternative variants (3 tables instead of 1) also have their downsides, and I chose table bloat over table multiplication). With this patch, it should be possible to whitelist supported laptops with a matching entry (phase P2) in board_pciid_enables which points to a function setting laptop_ok=1. (In case DMI is broken, matching might be a little bit more difficult, but it is still doable.) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c trunk/internal.c trunk/programmer.h Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed May 4 02:39:50 2011 (r1293) +++ trunk/board_enable.c Thu May 5 09:12:40 2011 (r1294) @@ -1899,112 +1899,112 @@ /* Please keep this list alphabetically ordered by vendor/board name. */ const struct board_pciid_enable board_pciid_enables[] = { - /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ + /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) - {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, - {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, - {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, - {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, - {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, - {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, - {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, - {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, - {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, - {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, - {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, - {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, - {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, - {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, - {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, - {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */ - {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, - {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, - {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, - {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, - {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, - {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, - {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, - {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, - {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, - {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, - {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, - {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, - {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, - {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, - {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, - {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, - {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, - {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise}, - {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise}, - {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, - {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, - {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, - {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, - {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, - {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, - {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, - {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, - {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, - {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, - {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, - {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, - {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, - {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, - {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, - {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, - {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, - {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, - {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, - {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, - {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, - {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e}, - {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, - {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, - {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, - {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, - {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, - {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, - {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, + {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, + {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, + {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, + {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, + {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, + {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, + {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, + {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, + {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, P3, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */ + {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, + {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, + {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, + {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, + {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, + {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, + {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, + {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, + {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, + {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, + {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, + {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL}, + {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, + {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, + {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, + {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise}, + {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, + {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, + {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, + {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, + {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, + {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, + {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, + {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, + {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455}, + {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, + {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, + {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, + {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, + {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, + {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, + {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e}, + {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, + {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, + {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, + {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, + {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, + {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, + {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif - { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ + { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ }; /* @@ -2064,7 +2064,7 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -const static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase) { const struct board_pciid_enable *board = board_pciid_enables; @@ -2072,6 +2072,8 @@ if ((!board->first_card_vendor || !board->first_card_device) && !board->dmi_pattern) continue; + if (board->phase != phase) + continue; if (!pci_card_find(board->first_vendor, board->first_device, board->first_card_vendor, @@ -2110,6 +2112,62 @@ return NULL; } +static int unsafe_board_handler(const struct board_pciid_enable *board) +{ + if (!board) + return 1; + + if (board->status == OK) + return 0; + + if (!force_boardenable) { + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + "code has not been tested, and thus will not not be executed by default.\n" + "Depending on your hardware environment, erasing, writing or even probing\n" + "can fail without running the board specific code.\n\n" + "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" + "\"internal programmer\") for details.\n", + board->vendor_name, board->board_name); + return 1; + } + msg_pinfo("NOTE: Running an untested board enable procedure.\n" + "Please report success/failure to flashrom(a)flashrom.org\n" + "with your board name and SUCCESS or FAILURE in the subject.\n"); + return 0; +} + +/* FIXME: Should this be identical to board_flash_enable? */ +static int board_handle_phase(enum board_match_phase phase) +{ + const struct board_pciid_enable *board = NULL; + + board = board_match_pci_card_ids(phase); + + if (unsafe_board_handler(board)) + board = NULL; + + if (!board) + return 0; + + if (!board->enable) { + /* Not sure if there is a valid case for this. */ + msg_perr("Board match found, but nothing to do?\n"); + return 0; + } + + return board->enable(); +} + +void board_handle_before_superio(void) +{ + board_handle_phase(P1); +} + +void board_handle_before_laptop(void) +{ + board_handle_phase(P2); +} + int board_flash_enable(const char *vendor, const char *part) { const struct board_pciid_enable *board = NULL; @@ -2119,24 +2177,10 @@ board = board_match_coreboot_name(vendor, part); if (!board) - board = board_match_pci_card_ids(); + board = board_match_pci_card_ids(P3); - if (board && board->status == NT) { - if (!force_boardenable) { - msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" - "code has not been tested, and thus will not not be executed by default.\n" - "Depending on your hardware environment, erasing, writing or even probing\n" - "can fail without running the board specific code.\n\n" - "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" - "\"internal programmer\") for details.\n", - board->vendor_name, board->board_name); + if (unsafe_board_handler(board)) board = NULL; - } else { - msg_pinfo("NOTE: Running an untested board enable procedure.\n" - "Please report success/failure to flashrom(a)flashrom.org\n" - "with your board name and SUCCESS or FAILURE in the subject.\n"); - } - } if (board) { if (board->max_rom_decode_parallel) Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed May 4 02:39:50 2011 (r1293) +++ trunk/internal.c Thu May 5 09:12:40 2011 (r1294) @@ -125,6 +125,7 @@ #endif int is_laptop = 0; +int laptop_ok = 0; int internal_init(void) { @@ -198,6 +199,9 @@ dmi_init(); + /* In case Super I/O probing would cause pretty explosions. */ + board_handle_before_superio(); + /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); #else @@ -208,10 +212,13 @@ */ #endif - /* Warn if a laptop is detected. */ - if (is_laptop) { + /* Check laptop whitelist. */ + board_handle_before_laptop(); + + /* Warn if a non-whitelisted laptop is detected. */ + if (is_laptop && !laptop_ok) { msg_perr("========================================================================\n" - "WARNING! You seem to be running flashrom on a laptop.\n" + "WARNING! You seem to be running flashrom on an unsupported laptop.\n" "Laptops, notebooks and netbooks are difficult to support and we recommend\n" "to use the vendor flashing utility. The embedded controller (EC) in these\n" "machines often interacts badly with flashing.\n" Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed May 4 02:39:50 2011 (r1293) +++ trunk/programmer.h Thu May 5 09:12:40 2011 (r1294) @@ -150,6 +150,12 @@ extern const struct penable chipset_enables[]; +enum board_match_phase { + P1, + P2, + P3 +}; + struct board_pciid_enable { /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; @@ -172,6 +178,8 @@ const char *lb_vendor; const char *lb_part; + enum board_match_phase phase; + const char *vendor_name; const char *board_name; @@ -228,6 +236,7 @@ void print_supported_pcidevs(const struct pcidev_status *devs); #endif +#if CONFIG_INTERNAL /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); @@ -235,6 +244,8 @@ uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); +void board_handle_before_superio(void); +void board_handle_before_laptop(void); int board_flash_enable(const char *vendor, const char *part); /* chipset_enable.c */ @@ -242,6 +253,7 @@ /* processor_enable.c */ int processor_flash_enable(void); +#endif /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); @@ -282,6 +294,7 @@ void release_io_perms(void); #if CONFIG_INTERNAL == 1 extern int is_laptop; +extern int laptop_ok; extern int force_boardenable; extern int force_boardmismatch; void probe_superio(void);

1 0

[PATCH 3/3] kill central list of SPI programmers
by Michael Karcher 05 May '11

05 May '11

Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- bitbang_spi.c | 14 ++++- buspirate_spi.c | 15 +++- dediprog.c | 19 ++++-- dummyflasher.c | 17 ++++- flashrom.c | 9 +-- ft2232_spi.c | 15 +++- ichspi.c | 57 ++++++++++++---- internal.c | 5 ++ it85spi.c | 18 ++++-- it87spi.c | 19 ++++-- mcp6x_spi.c | 3 - nicintel_spi.c | 3 - ogp_spi.c | 3 - programmer.h | 40 ++---------- rayer_spi.c | 3 - sb600spi.c | 15 +++- spi.c | 204 +++++++------------------------------------------------ spi25.c | 4 +- wbsio_spi.c | 17 ++++- 19 files changed, 198 insertions(+), 282 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index be30944..ca28434 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -81,7 +81,7 @@ static uint8_t bitbang_spi_readwrite_byte(uint8_t val) return ret; } -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -106,6 +106,16 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } +static const struct spi_programmer spi_programmer_bitbang = { + .type = SPI_CONTROLLER_BITBANG, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, @@ -127,6 +137,8 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; + register_spi_programmer(&spi_programmer_bitbang); + /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); diff --git a/buspirate_spi.c b/buspirate_spi.c index 89f529d..57d5ce2 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -116,7 +116,7 @@ int buspirate_spi_shutdown(void) return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; @@ -172,6 +172,16 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .max_data_read = 12, + .max_data_write = 12, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + static const struct buspirate_spispeeds spispeeds[] = { {"30k", 0x0}, {"125k", 0x1}, @@ -321,8 +331,7 @@ int buspirate_spi_init(void) return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + register_spi_programmer(&spi_programmer_buspirate); return 0; } diff --git a/dediprog.c b/dediprog.c index 989306a..1c54c66 100644 --- a/dediprog.c +++ b/dediprog.c @@ -248,7 +248,7 @@ static int dediprog_spi_bulk_read(struct flashchip *flash, uint8_t *buf, return 0; } -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; /* chunksize must be 512, other sizes will NOT work at all. */ @@ -293,7 +293,7 @@ int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) return 0; } -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { int ret; @@ -310,7 +310,7 @@ int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int return ret; } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -526,6 +526,16 @@ static int parse_voltage(char *voltage) return millivolt; } +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = dediprog_spi_write_256, +}; + /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { @@ -606,8 +616,7 @@ int dediprog_init(void) return 1; } - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + register_spi_programmer(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 diff --git a/dummyflasher.c b/dummyflasher.c index c4c9c4e..fdaa5f2 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -339,7 +339,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt } #endif -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -375,12 +375,22 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); } +static const struct spi_programmer spi_programmer_dummyflasher = { + .type = SPI_CONTROLLER_DUMMY, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = dummy_spi_write_256, +}; + int dummy_init(void) { char *bustext = NULL; @@ -412,8 +422,7 @@ int dummy_init(void) msg_pdbg("Enabling support for %s flash.\n", "FWH"); } if (strstr(bustext, "spi")) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) diff --git a/flashrom.c b/flashrom.c index 1083abe..dc9e1d1 100644 --- a/flashrom.c +++ b/flashrom.c @@ -499,10 +499,7 @@ int programmer_init(char *param) .fwh = 0xffffffff, .spi = 0xffffffff }; - /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. - */ - buses_supported = CHIP_BUSTYPE_NONSPI; + buses_supported = CHIP_BUSTYPE_NONE; /* Default to top aligned flash at 4 GB. */ flashbase = 0; /* Registering shutdown functions is now allowed. */ @@ -1690,10 +1687,6 @@ int selfcheck(void) msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; diff --git a/ft2232_spi.c b/ft2232_spi.c index 4e0fc67..c114e41 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -128,7 +128,7 @@ static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, return 0; } -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -213,6 +213,16 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, return failed ? -1 : 0; } +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .max_data_read = 64 * 1024, + .max_data_write = 256, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ft2232_spi_init(void) { int f; @@ -346,8 +356,7 @@ int ft2232_spi_init(void) // msg_pdbg("\nft2232 chosen\n"); - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + register_spi_programmer(&spi_programmer_ft2232); return 0; } diff --git a/ichspi.c b/ichspi.c index 4315e78..ddd14d3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -313,7 +313,7 @@ static int generate_opcodes(OPCODES * op) return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -388,7 +388,7 @@ static int program_opcodes(OPCODES *op, int enable_undo) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: /* Register undo only for enable_undo=1, i.e. first call. */ @@ -432,7 +432,7 @@ void ich_set_bbar(uint32_t minaddr) { #define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; @@ -801,7 +801,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -834,7 +834,7 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -900,7 +900,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_ICH9: @@ -953,7 +953,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1051,6 +1051,26 @@ static void do_ich9_spi_frap(uint32_t frap, int i) access_names[rwperms]); } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1059,20 +1079,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint16_t spibar_offset, tmp2; uint32_t tmp; - buses_supported |= CHIP_BUSTYPE_SPI; switch (ich_generation) { case 7: - spi_controller = SPI_CONTROLLER_ICH7; + register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - spi_controller = SPI_CONTROLLER_ICH9; + register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1083,7 +1102,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1211,6 +1230,16 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, return 0; } +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .max_data_read = 16, + .max_data_write = 16, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int via_init_spi(struct pci_dev *dev) { uint32_t mmio_base; @@ -1221,8 +1250,8 @@ int via_init_spi(struct pci_dev *dev) ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); diff --git a/internal.c b/internal.c index d3866ba..9639460 100644 --- a/internal.c +++ b/internal.c @@ -178,6 +178,11 @@ int internal_init(void) get_io_perms(); + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ /* Set all options you want -- here we stick with the defaults */ diff --git a/it85spi.c b/it85spi.c index 11a2ff5..acd84ab 100644 --- a/it85spi.c +++ b/it85spi.c @@ -233,7 +233,7 @@ void it85xx_exit_scratch_rom() * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get * data from MISO) */ -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -313,12 +313,19 @@ static int it85xx_spi_common_init(struct superio s) ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */ #endif - /* Set this as spi controller. */ - spi_controller = SPI_CONTROLLER_IT85XX; - return 0; } +static const struct spi_programmer spi_programmer_it85xx = { + .type = SPI_CONTROLLER_IT85XX, + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int it85xx_spi_init(struct superio s) { int ret; @@ -335,7 +342,8 @@ int it85xx_spi_init(struct superio s) if (buses_supported & CHIP_BUSTYPE_FWH) msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); /* Really leave FWH enabled? */ - buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + /* Set this as spi controller. */ + register_spi_programmer(&spi_programmer_it85xx); } return ret; } diff --git a/it87spi.c b/it87spi.c index fdf6ccb..fadf5a1 100644 --- a/it87spi.c +++ b/it87spi.c @@ -113,7 +113,7 @@ void probe_superio_ite(void) * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -206,7 +206,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { fast_spi = 0; @@ -223,7 +223,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory @@ -265,6 +265,16 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; @@ -341,9 +351,8 @@ static uint16_t it87spi_probe(uint16_t port) it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; /* FIXME: Add the SPI bus or replace the other buses with it? */ - buses_supported |= CHIP_BUSTYPE_SPI; + register_spi_programmer(&spi_programmer_it87xx); return 0; } diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 0e0d311..d2c31be 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -166,9 +166,6 @@ int mcp6x_spi_init(int want_spi) return 1; } - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; - return 0; } diff --git a/nicintel_spi.c b/nicintel_spi.c index 28d332e..ee7046c 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -162,9 +162,6 @@ int nicintel_spi_init(void) if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_NICINTEL; - return 0; } diff --git a/ogp_spi.c b/ogp_spi.c index 6932f06..2916ae1 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -128,9 +128,6 @@ int ogp_spi_init(void) if (bitbang_spi_init(&bitbang_spi_master_ogp, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_OGP; - return 0; } diff --git a/programmer.h b/programmer.h index fefb9cd..53a50f6 100644 --- a/programmer.h +++ b/programmer.h @@ -356,9 +356,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -460,7 +457,6 @@ struct usbdev_status { const char *device_name; }; int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -480,7 +476,6 @@ int mcp6x_spi_init(int want_spi); /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -489,14 +484,10 @@ struct buspirate_spispeeds { }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ struct decode_sizes { @@ -527,7 +518,6 @@ enum spi_controller { SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, - SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -542,16 +532,9 @@ enum spi_controller { #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif -#if CONFIG_RAYER_SPI == 1 - SPI_CONTROLLER_RAYER, -#endif -#if CONFIG_NICINTEL_SPI == 1 - SPI_CONTROLLER_NICINTEL, -#endif -#if CONFIG_OGP_SPI == 1 - SPI_CONTROLLER_OGP, +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) + SPI_CONTROLLER_BITBANG, #endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; @@ -559,6 +542,7 @@ extern const int spi_programmer_count; #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + enum spi_controller type; int max_data_read; int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, @@ -570,13 +554,13 @@ struct spi_programmer { int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -584,40 +568,26 @@ extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); int via_init_spi(struct pci_dev *dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_send_multicommand(struct spi_command *cmds); #endif /* it85spi.c */ int it85xx_spi_init(struct superio s); int it85xx_shutdown(void); -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); int init_superio_ite(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ #if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); #endif /* wbsio_spi.c */ #if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serprog.c */ diff --git a/rayer_spi.c b/rayer_spi.c index a01ee80..0807487 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -134,9 +134,6 @@ int rayer_spi_init(void) if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_RAYER; - return 0; } diff --git a/sb600spi.c b/sb600spi.c index 269af8a..37aac3b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -89,7 +89,7 @@ static void execute_command(void) ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -192,6 +192,16 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .max_data_read = 8, + .max_data_write = 5, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + int sb600_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; @@ -304,8 +314,7 @@ int sb600_probe_spi(struct pci_dev *dev) /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + register_spi_programmer(&spi_programmer_sb600); return 0; } diff --git a/spi.c b/spi.c index 5857fda..4610102 100644 --- a/spi.c +++ b/spi.c @@ -30,200 +30,42 @@ #include "programmer.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .max_data_read = 64, - .max_data_write = 64, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT85XX */ - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .max_data_read = 8, - .max_data_write = 5, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .max_data_read = 16, - .max_data_write = 16, - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1, - }, - - { /* SPI_CONTROLLER_MCP6X_BITBANG */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .max_data_read = 64 * 1024, - .max_data_write = 256, - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .max_data_read = 12, - .max_data_write = 12, - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = dediprog_spi_write_256, - }, -#endif - -#if CONFIG_RAYER_SPI == 1 - { /* SPI_CONTROLLER_RAYER */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_NICINTEL_SPI == 1 - { /* SPI_CONTROLLER_NICINTEL */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - -#if CONFIG_OGP_SPI == 1 - { /* SPI_CONTROLLER_OGP */ - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ +const struct spi_programmer spi_programmer_none = { + .type = SPI_CONTROLLER_NONE, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = NULL, + .multicommand = NULL, + .read = NULL, + .write_256 = NULL, }; -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer = &spi_programmer_none; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -257,7 +99,7 @@ int default_spi_send_multicommand(struct spi_command *cmds) int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_read; + int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -269,7 +111,7 @@ int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int max_data = spi_programmer[spi_controller].max_data_write; + int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -282,7 +124,7 @@ int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); @@ -308,7 +150,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) "access window.\n"); msg_perr("Read will probably return garbage.\n"); } - return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len); + return spi_programmer->read(flash, buf, addrbase + start, len); } /* @@ -320,14 +162,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* @@ -337,7 +179,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: @@ -349,3 +191,9 @@ uint32_t spi_get_valid_read_addr(void) return 0; } } + +void register_spi_programmer(const struct spi_programmer *pgm) +{ + spi_programmer = pgm; + buses_supported |= CHIP_BUSTYPE_SPI; +} \ No newline at end of file diff --git a/spi25.c b/spi25.c index c9e1ebf..b3bd7a1 100644 --- a/spi25.c +++ b/spi25.c @@ -178,7 +178,7 @@ int probe_spi_rdid4(struct flashchip *flash) /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1351,7 +1351,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: diff --git a/wbsio_spi.c b/wbsio_spi.c index 12c458e..734732e 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -50,7 +50,7 @@ static uint16_t wbsio_spibase = 0; * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -134,7 +134,7 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); } @@ -169,6 +169,16 @@ done: return flashport; } +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1, +}; + int wbsio_check_for_spi(void) { if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) @@ -177,8 +187,7 @@ int wbsio_check_for_spi(void) msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; -- 1.7.4.1

1 0

[PATCH 2/3] Shuffle code around (no other changes)
by Michael Karcher 05 May '11

05 May '11

This is to prepare the SPI registration patch without needing to do forward declarations. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- bitbang_spi.c | 84 +++++++++--------- buspirate_spi.c | 182 +++++++++++++++++++------------------- dummyflasher.c | 264 +++++++++++++++++++++++++++--------------------------- ft2232_spi.c | 170 ++++++++++++++++++------------------ it85spi.c | 103 +++++++++++----------- it87spi.c | 242 +++++++++++++++++++++++++------------------------- wbsio_spi.c | 94 ++++++++++---------- 7 files changed, 569 insertions(+), 570 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index d63c769..be30944 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -64,6 +64,48 @@ static void bitbang_spi_release_bus(void) bitbang_spi_master->release_bus(); } +static uint8_t bitbang_spi_readwrite_byte(uint8_t val) +{ + uint8_t ret = 0; + int i; + + for (i = 7; i >= 0; i--) { + bitbang_spi_set_mosi((val >> i) & 1); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(1); + ret <<= 1; + ret |= bitbang_spi_get_miso(); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(0); + } + return ret; +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + /* FIXME: Run bitbang_spi_request_bus here or in programmer init? + * Requesting and releasing the SPI bus is handled in here to allow the + * programmer to use its own SPI engine for native accesses. + */ + bitbang_spi_request_bus(); + bitbang_spi_set_cs(0); + for (i = 0; i < writecnt; i++) + bitbang_spi_readwrite_byte(writearr[i]); + for (i = 0; i < readcnt; i++) + readarr[i] = bitbang_spi_readwrite_byte(0); + + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_cs(1); + programmer_delay(bitbang_spi_half_period); + /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ + bitbang_spi_release_bus(); + + return 0; +} + int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, @@ -109,45 +151,3 @@ int bitbang_spi_shutdown(const struct bitbang_spi_master *master) bitbang_spi_master = NULL; return 0; } - -static uint8_t bitbang_spi_readwrite_byte(uint8_t val) -{ - uint8_t ret = 0; - int i; - - for (i = 7; i >= 0; i--) { - bitbang_spi_set_mosi((val >> i) & 1); - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_sck(1); - ret <<= 1; - ret |= bitbang_spi_get_miso(); - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_sck(0); - } - return ret; -} - -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - int i; - - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? - * Requesting and releasing the SPI bus is handled in here to allow the - * programmer to use its own SPI engine for native accesses. - */ - bitbang_spi_request_bus(); - bitbang_spi_set_cs(0); - for (i = 0; i < writecnt; i++) - bitbang_spi_readwrite_byte(writearr[i]); - for (i = 0; i < readcnt; i++) - readarr[i] = bitbang_spi_readwrite_byte(0); - - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_cs(1); - programmer_delay(bitbang_spi_half_period); - /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ - bitbang_spi_release_bus(); - - return 0; -} diff --git a/buspirate_spi.c b/buspirate_spi.c index e7a7a10..89f529d 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -81,6 +81,97 @@ static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigne return 0; } +int buspirate_spi_shutdown(void) +{ + unsigned char buf[5]; + int ret = 0; + + /* Exit raw SPI mode (enter raw bitbang mode) */ + buf[0] = 0x00; + ret = buspirate_sendrecv(buf, 1, 5); + if (ret) + return ret; + if (memcmp(buf, "BBIO", 4)) { + msg_perr("Entering raw bitbang mode failed!\n"); + return 1; + } + msg_pdbg("Raw bitbang mode version %c\n", buf[4]); + if (buf[4] != '1') { + msg_perr("Can't handle raw bitbang mode version %c!\n", + buf[4]); + return 1; + } + /* Reset Bus Pirate (return to user terminal) */ + buf[0] = 0x0f; + ret = buspirate_sendrecv(buf, 1, 0); + if (ret) + return ret; + + /* Shut down serial port communication */ + ret = serialport_shutdown(); + if (ret) + return ret; + msg_pdbg("Bus Pirate shutdown completed.\n"); + + return 0; +} + +int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *buf = NULL; + int i = 0, ret = 0; + + if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) + return SPI_INVALID_LENGTH; + + /* 3 bytes extra for CS#, len, CS#. */ + buf = realloc(buf, writecnt + readcnt + 3); + if (!buf) { + msg_perr("Out of memory!\n"); + exit(1); // -1 + } + + /* Assert CS# */ + buf[i++] = 0x02; + + buf[i++] = 0x10 | (writecnt + readcnt - 1); + memcpy(buf + i, writearr, writecnt); + i += writecnt; + memset(buf + i, 0, readcnt); + + i += readcnt; + /* De-assert CS# */ + buf[i++] = 0x03; + + ret = buspirate_sendrecv(buf, i, i); + + if (ret) { + msg_perr("Bus Pirate communication error!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[0] != 0x01) { + msg_perr("Protocol error while lowering CS#!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[1] != 0x01) { + msg_perr("Protocol error while reading/writing SPI!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[i - 1] != 0x01) { + msg_perr("Protocol error while raising CS#!\n"); + return SPI_GENERIC_ERROR; + } + + /* Skip CS#, length, writearr. */ + memcpy(readarr, buf + 2 + writecnt, readcnt); + + return ret; +} + static const struct buspirate_spispeeds spispeeds[] = { {"30k", 0x0}, {"125k", 0x1}, @@ -235,94 +326,3 @@ int buspirate_spi_init(void) return 0; } - -int buspirate_spi_shutdown(void) -{ - unsigned char buf[5]; - int ret = 0; - - /* Exit raw SPI mode (enter raw bitbang mode) */ - buf[0] = 0x00; - ret = buspirate_sendrecv(buf, 1, 5); - if (ret) - return ret; - if (memcmp(buf, "BBIO", 4)) { - msg_perr("Entering raw bitbang mode failed!\n"); - return 1; - } - msg_pdbg("Raw bitbang mode version %c\n", buf[4]); - if (buf[4] != '1') { - msg_perr("Can't handle raw bitbang mode version %c!\n", - buf[4]); - return 1; - } - /* Reset Bus Pirate (return to user terminal) */ - buf[0] = 0x0f; - ret = buspirate_sendrecv(buf, 1, 0); - if (ret) - return ret; - - /* Shut down serial port communication */ - ret = serialport_shutdown(); - if (ret) - return ret; - msg_pdbg("Bus Pirate shutdown completed.\n"); - - return 0; -} - -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - static unsigned char *buf = NULL; - int i = 0, ret = 0; - - if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) - return SPI_INVALID_LENGTH; - - /* 3 bytes extra for CS#, len, CS#. */ - buf = realloc(buf, writecnt + readcnt + 3); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); // -1 - } - - /* Assert CS# */ - buf[i++] = 0x02; - - buf[i++] = 0x10 | (writecnt + readcnt - 1); - memcpy(buf + i, writearr, writecnt); - i += writecnt; - memset(buf + i, 0, readcnt); - - i += readcnt; - /* De-assert CS# */ - buf[i++] = 0x03; - - ret = buspirate_sendrecv(buf, i, i); - - if (ret) { - msg_perr("Bus Pirate communication error!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[0] != 0x01) { - msg_perr("Protocol error while lowering CS#!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[1] != 0x01) { - msg_perr("Protocol error while reading/writing SPI!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[i - 1] != 0x01) { - msg_perr("Protocol error while raising CS#!\n"); - return SPI_GENERIC_ERROR; - } - - /* Skip CS#, length, writearr. */ - memcpy(readarr, buf + 2 + writecnt, readcnt); - - return ret; -} diff --git a/dummyflasher.c b/dummyflasher.c index b6e67db..c4c9c4e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -60,138 +60,6 @@ static int emu_jedec_ce_c7_size = 0; static int spi_write_256_chunksize = 256; -int dummy_init(void) -{ - char *bustext = NULL; - char *tmp = NULL; -#if EMULATE_CHIP - struct stat image_stat; -#endif - - msg_pspew("%s\n", __func__); - - bustext = extract_programmer_param("bus"); - msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default"); - if (!bustext) - bustext = strdup("parallel+lpc+fwh+spi"); - /* Convert the parameters to lowercase. */ - tolower_string(bustext); - - buses_supported = CHIP_BUSTYPE_NONE; - if (strstr(bustext, "parallel")) { - buses_supported |= CHIP_BUSTYPE_PARALLEL; - msg_pdbg("Enabling support for %s flash.\n", "parallel"); - } - if (strstr(bustext, "lpc")) { - buses_supported |= CHIP_BUSTYPE_LPC; - msg_pdbg("Enabling support for %s flash.\n", "LPC"); - } - if (strstr(bustext, "fwh")) { - buses_supported |= CHIP_BUSTYPE_FWH; - msg_pdbg("Enabling support for %s flash.\n", "FWH"); - } - if (strstr(bustext, "spi")) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; - msg_pdbg("Enabling support for %s flash.\n", "SPI"); - } - if (buses_supported == CHIP_BUSTYPE_NONE) - msg_pdbg("Support for all flash bus types disabled.\n"); - free(bustext); - - tmp = extract_programmer_param("spi_write_256_chunksize"); - if (tmp) { - spi_write_256_chunksize = atoi(tmp); - free(tmp); - if (spi_write_256_chunksize < 1) { - msg_perr("invalid spi_write_256_chunksize\n"); - return 1; - } - } - -#if EMULATE_CHIP - tmp = extract_programmer_param("emulate"); - if (!tmp) { - msg_pdbg("Not emulating any flash chip.\n"); - /* Nothing else to do. */ - return 0; - } -#if EMULATE_SPI_CHIP - if (!strcmp(tmp, "M25P10.RES")) { - emu_chip = EMULATE_ST_M25P10_RES; - emu_chip_size = 128 * 1024; - emu_max_byteprogram_size = 128; - emu_max_aai_size = 0; - emu_jedec_se_size = 0; - emu_jedec_be_52_size = 0; - emu_jedec_be_d8_size = 32 * 1024; - emu_jedec_ce_60_size = 0; - emu_jedec_ce_c7_size = emu_chip_size; - msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page " - "write)\n"); - } - if (!strcmp(tmp, "SST25VF040.REMS")) { - emu_chip = EMULATE_SST_SST25VF040_REMS; - emu_chip_size = 512 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 0; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = 0; - msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, " - "byte write)\n"); - } - if (!strcmp(tmp, "SST25VF032B")) { - emu_chip = EMULATE_SST_SST25VF032B; - emu_chip_size = 4 * 1024 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 2; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; - msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI " - "write)\n"); - } -#endif - if (emu_chip == EMULATE_NONE) { - msg_perr("Invalid chip specified for emulation: %s\n", tmp); - free(tmp); - return 1; - } - free(tmp); - flashchip_contents = malloc(emu_chip_size); - if (!flashchip_contents) { - msg_perr("Out of memory!\n"); - return 1; - } - msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); - memset(flashchip_contents, 0xff, emu_chip_size); - - emu_persistent_image = extract_programmer_param("image"); - if (!emu_persistent_image) { - /* Nothing else to do. */ - return 0; - } - if (!stat(emu_persistent_image, &image_stat)) { - msg_pdbg("Found persistent image %s, size %li ", - emu_persistent_image, (long)image_stat.st_size); - if (image_stat.st_size == emu_chip_size) { - msg_pdbg("matches.\n"); - msg_pdbg("Reading %s\n", emu_persistent_image); - read_buf_from_file(flashchip_contents, emu_chip_size, - emu_persistent_image); - } else { - msg_pdbg("doesn't match.\n"); - } - } -#endif - return 0; -} - int dummy_shutdown(void) { msg_pspew("%s\n", __func__); @@ -512,3 +380,135 @@ int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int le return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); } + +int dummy_init(void) +{ + char *bustext = NULL; + char *tmp = NULL; +#if EMULATE_CHIP + struct stat image_stat; +#endif + + msg_pspew("%s\n", __func__); + + bustext = extract_programmer_param("bus"); + msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default"); + if (!bustext) + bustext = strdup("parallel+lpc+fwh+spi"); + /* Convert the parameters to lowercase. */ + tolower_string(bustext); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(bustext, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + msg_pdbg("Enabling support for %s flash.\n", "parallel"); + } + if (strstr(bustext, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + msg_pdbg("Enabling support for %s flash.\n", "LPC"); + } + if (strstr(bustext, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + msg_pdbg("Enabling support for %s flash.\n", "FWH"); + } + if (strstr(bustext, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + msg_pdbg("Enabling support for %s flash.\n", "SPI"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + msg_pdbg("Support for all flash bus types disabled.\n"); + free(bustext); + + tmp = extract_programmer_param("spi_write_256_chunksize"); + if (tmp) { + spi_write_256_chunksize = atoi(tmp); + free(tmp); + if (spi_write_256_chunksize < 1) { + msg_perr("invalid spi_write_256_chunksize\n"); + return 1; + } + } + +#if EMULATE_CHIP + tmp = extract_programmer_param("emulate"); + if (!tmp) { + msg_pdbg("Not emulating any flash chip.\n"); + /* Nothing else to do. */ + return 0; + } +#if EMULATE_SPI_CHIP + if (!strcmp(tmp, "M25P10.RES")) { + emu_chip = EMULATE_ST_M25P10_RES; + emu_chip_size = 128 * 1024; + emu_max_byteprogram_size = 128; + emu_max_aai_size = 0; + emu_jedec_se_size = 0; + emu_jedec_be_52_size = 0; + emu_jedec_be_d8_size = 32 * 1024; + emu_jedec_ce_60_size = 0; + emu_jedec_ce_c7_size = emu_chip_size; + msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page " + "write)\n"); + } + if (!strcmp(tmp, "SST25VF040.REMS")) { + emu_chip = EMULATE_SST_SST25VF040_REMS; + emu_chip_size = 512 * 1024; + emu_max_byteprogram_size = 1; + emu_max_aai_size = 0; + emu_jedec_se_size = 4 * 1024; + emu_jedec_be_52_size = 32 * 1024; + emu_jedec_be_d8_size = 0; + emu_jedec_ce_60_size = emu_chip_size; + emu_jedec_ce_c7_size = 0; + msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, " + "byte write)\n"); + } + if (!strcmp(tmp, "SST25VF032B")) { + emu_chip = EMULATE_SST_SST25VF032B; + emu_chip_size = 4 * 1024 * 1024; + emu_max_byteprogram_size = 1; + emu_max_aai_size = 2; + emu_jedec_se_size = 4 * 1024; + emu_jedec_be_52_size = 32 * 1024; + emu_jedec_be_d8_size = 64 * 1024; + emu_jedec_ce_60_size = emu_chip_size; + emu_jedec_ce_c7_size = emu_chip_size; + msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI " + "write)\n"); + } +#endif + if (emu_chip == EMULATE_NONE) { + msg_perr("Invalid chip specified for emulation: %s\n", tmp); + free(tmp); + return 1; + } + free(tmp); + flashchip_contents = malloc(emu_chip_size); + if (!flashchip_contents) { + msg_perr("Out of memory!\n"); + return 1; + } + msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); + memset(flashchip_contents, 0xff, emu_chip_size); + + emu_persistent_image = extract_programmer_param("image"); + if (!emu_persistent_image) { + /* Nothing else to do. */ + return 0; + } + if (!stat(emu_persistent_image, &image_stat)) { + msg_pdbg("Found persistent image %s, size %li ", + emu_persistent_image, (long)image_stat.st_size); + if (image_stat.st_size == emu_chip_size) { + msg_pdbg("matches.\n"); + msg_pdbg("Reading %s\n", emu_persistent_image); + read_buf_from_file(flashchip_contents, emu_chip_size, + emu_persistent_image); + } else { + msg_pdbg("doesn't match.\n"); + } + } +#endif + return 0; +} diff --git a/ft2232_spi.c b/ft2232_spi.c index 7ff1d81..4e0fc67 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -128,6 +128,91 @@ static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, return 0; } +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + struct ftdi_context *ftdic = &ftdic_context; + static unsigned char *buf = NULL; + /* failed is special. We use bitwise ops, but it is essentially bool. */ + int i = 0, ret = 0, failed = 0; + int bufsize; + static int oldbufsize = 0; + + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + + /* buf is not used for the response from the chip. */ + bufsize = max(writecnt + 9, 260 + 9); + /* Never shrink. realloc() calls are expensive. */ + if (bufsize > oldbufsize) { + buf = realloc(buf, bufsize); + if (!buf) { + msg_perr("Out of memory!\n"); + exit(1); + } + oldbufsize = bufsize; + } + + /* + * Minimize USB transfers by packing as many commands as possible + * together. If we're not expecting to read, we can assert CS#, write, + * and deassert CS# all in one shot. If reading, we do three separate + * operations. + */ + msg_pspew("Assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; + + if (writecnt) { + buf[i++] = 0x11; + buf[i++] = (writecnt - 1) & 0xff; + buf[i++] = ((writecnt - 1) >> 8) & 0xff; + memcpy(buf + i, writearr, writecnt); + i += writecnt; + } + + /* + * Optionally terminate this batch of commands with a + * read command, then do the fetch of the results. + */ + if (readcnt) { + buf[i++] = 0x20; + buf[i++] = (readcnt - 1) & 0xff; + buf[i++] = ((readcnt - 1) >> 8) & 0xff; + ret = send_buf(ftdic, buf, i); + failed = ret; + /* We can't abort here, we still have to deassert CS#. */ + if (ret) + msg_perr("send_buf failed before read: %i\n", + ret); + i = 0; + if (ret == 0) { + /* + * FIXME: This is unreliable. There's no guarantee that + * we read the response directly after sending the read + * command. We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + failed |= ret; + /* We can't abort here either. */ + if (ret) + msg_perr("get_buf failed: %i\n", ret); + } + } + + msg_pspew("De-assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = cs_bits; + buf[i++] = pindir; + ret = send_buf(ftdic, buf, i); + failed |= ret; + if (ret) + msg_perr("send_buf failed at end: %i\n", ret); + + return failed ? -1 : 0; +} + int ft2232_spi_init(void) { int f; @@ -267,91 +352,6 @@ int ft2232_spi_init(void) return 0; } -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - struct ftdi_context *ftdic = &ftdic_context; - static unsigned char *buf = NULL; - /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; - int bufsize; - static int oldbufsize = 0; - - if (writecnt > 65536 || readcnt > 65536) - return SPI_INVALID_LENGTH; - - /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); - /* Never shrink. realloc() calls are expensive. */ - if (bufsize > oldbufsize) { - buf = realloc(buf, bufsize); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); - } - oldbufsize = bufsize; - } - - /* - * Minimize USB transfers by packing as many commands as possible - * together. If we're not expecting to read, we can assert CS#, write, - * and deassert CS# all in one shot. If reading, we do three separate - * operations. - */ - msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ - buf[i++] = pindir; - - if (writecnt) { - buf[i++] = 0x11; - buf[i++] = (writecnt - 1) & 0xff; - buf[i++] = ((writecnt - 1) >> 8) & 0xff; - memcpy(buf + i, writearr, writecnt); - i += writecnt; - } - - /* - * Optionally terminate this batch of commands with a - * read command, then do the fetch of the results. - */ - if (readcnt) { - buf[i++] = 0x20; - buf[i++] = (readcnt - 1) & 0xff; - buf[i++] = ((readcnt - 1) >> 8) & 0xff; - ret = send_buf(ftdic, buf, i); - failed = ret; - /* We can't abort here, we still have to deassert CS#. */ - if (ret) - msg_perr("send_buf failed before read: %i\n", - ret); - i = 0; - if (ret == 0) { - /* - * FIXME: This is unreliable. There's no guarantee that - * we read the response directly after sending the read - * command. We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - failed |= ret; - /* We can't abort here either. */ - if (ret) - msg_perr("get_buf failed: %i\n", ret); - } - } - - msg_pspew("De-assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = cs_bits; - buf[i++] = pindir; - ret = send_buf(ftdic, buf, i); - failed |= ret; - if (ret) - msg_perr("send_buf failed at end: %i\n", ret); - - return failed ? -1 : 0; -} - void print_supported_usbdevs(const struct usbdev_status *devs) { int i; diff --git a/it85spi.c b/it85spi.c index a388d10..11a2ff5 100644 --- a/it85spi.c +++ b/it85spi.c @@ -226,6 +226,57 @@ void it85xx_exit_scratch_rom() #endif } +/* According to ITE 8502 document, the procedure to follow mode is following: + * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) + * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI + * with data) + * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get + * data from MISO) + */ +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + it85xx_enter_scratch_rom(); + /* exit scratch rom ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt EC. */ + +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + for (i = 0; i < writecnt; ++i) { +#ifdef LPC_IO + INDIRECT_WRITE(shm_io_base, writearr[i]); +#endif +#ifdef LPC_MEMORY + mmio_writeb(writearr[i], ce_low); +#endif + } + for (i = 0; i < readcnt; ++i) { +#ifdef LPC_IO + readarr[i] = INDIRECT_READ(shm_io_base); +#endif +#ifdef LPC_MEMORY + readarr[i] = mmio_readb(ce_low); +#endif + } +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + + return 0; +} + static int it85xx_spi_common_init(struct superio s) { chipaddr base; @@ -295,56 +346,4 @@ int it85xx_shutdown(void) it85xx_exit_scratch_rom(); return 0; } - -/* According to ITE 8502 document, the procedure to follow mode is following: - * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) - * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI - * with data) - * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get - * data from MISO) - */ -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - int i; - - it85xx_enter_scratch_rom(); - /* exit scratch rom ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt EC. */ - -#ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); -#endif -#ifdef LPC_MEMORY - mmio_writeb(0, ce_high); -#endif - for (i = 0; i < writecnt; ++i) { -#ifdef LPC_IO - INDIRECT_WRITE(shm_io_base, writearr[i]); -#endif -#ifdef LPC_MEMORY - mmio_writeb(writearr[i], ce_low); -#endif - } - for (i = 0; i < readcnt; ++i) { -#ifdef LPC_IO - readarr[i] = INDIRECT_READ(shm_io_base); -#endif -#ifdef LPC_MEMORY - readarr[i] = mmio_readb(ce_low); -#endif - } -#ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ -#endif -#ifdef LPC_MEMORY - mmio_writeb(0, ce_high); -#endif - - return 0; -} - #endif diff --git a/it87spi.c b/it87spi.c index 2b09d64..fdf6ccb 100644 --- a/it87spi.c +++ b/it87spi.c @@ -104,127 +104,6 @@ void probe_superio_ite(void) return; } -static uint16_t it87spi_probe(uint16_t port) -{ - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t flashport = 0; - - enter_conf_mode_ite(port); - /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ - tmp = sio_read(port, 0x24) & 0xFE; - /* If IT87SPI was not explicitly selected, we want to check - * quickly if LPC->SPI translation is active. - */ - if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { - msg_pdbg("No IT87* serial flash segment enabled.\n"); - exit_conf_mode_ite(port); - /* Nothing to do. */ - return 0; - } - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); - msg_pdbg("LPC write to serial flash %sabled\n", - (tmp & 1 << 4) ? "en" : "dis"); - /* The LPC->SPI force write enable below only makes sense for - * non-programmer mode. - */ - /* If any serial flash segment is enabled, enable writing. */ - if ((tmp & 0xe) && (!(tmp & 1 << 4))) { - msg_pdbg("Enabling LPC write to serial flash\n"); - tmp |= 1 << 4; - sio_write(port, 0x24, tmp); - } - msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); - /* LDN 0x7, reg 0x64/0x65 */ - sio_write(port, 0x07, 0x7); - flashport = sio_read(port, 0x64) << 8; - flashport |= sio_read(port, 0x65); - msg_pdbg("Serial flash port 0x%04x\n", flashport); - /* Non-default port requested? */ - portpos = extract_programmer_param("it87spiport"); - if (portpos) { - char *endptr = NULL; - unsigned long forced_flashport; - forced_flashport = strtoul(portpos, &endptr, 0); - /* Port 0, port >0x1000, unaligned ports and garbage strings - * are rejected. - */ - if (!forced_flashport || (forced_flashport >= 0x1000) || - (forced_flashport & 0x7) || (*endptr != '\0')) { - /* Using ports below 0x100 is a really bad idea, and - * should only be done if no port between 0x100 and - * 0xff8 works due to routing issues. - */ - msg_perr("Error: it87spiport specified, but no valid " - "port specified.\nPort must be a multiple of " - "0x8 and lie between 0x100 and 0xff8.\n"); - free(portpos); - return 1; - } else { - flashport = (uint16_t)forced_flashport; - msg_pinfo("Forcing serial flash port 0x%04x\n", - flashport); - sio_write(port, 0x64, (flashport >> 8)); - sio_write(port, 0x65, (flashport & 0xff)); - } - } - free(portpos); - exit_conf_mode_ite(port); - it8716f_flashport = flashport; - if (buses_supported & CHIP_BUSTYPE_SPI) - msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; - /* FIXME: Add the SPI bus or replace the other buses with it? */ - buses_supported |= CHIP_BUSTYPE_SPI; - return 0; -} - -int init_superio_ite(void) -{ - int i; - int ret = 0; - - for (i = 0; i < superio_count; i++) { - if (superios[i].vendor != SUPERIO_VENDOR_ITE) - continue; - - switch (superios[i].model) { - case 0x8500: - case 0x8502: - case 0x8510: - case 0x8511: - case 0x8512: - /* FIXME: This should be enabled, but we need a check - * for laptop whitelisting due to the amount of things - * which can go wrong if the EC firmware does not - * implement the interface we want. - */ - //it85xx_spi_init(superios[i]); - break; - case 0x8705: - ret |= it8705f_write_enable(superios[i].port); - break; - case 0x8716: - case 0x8718: - case 0x8720: - ret |= it87spi_probe(superios[i].port); - break; - default: - msg_pdbg("Super I/O ID 0x%04hx is not on the list of " - "flash capable controllers.\n", - superios[i].model); - } - } - return ret; -} - /* * The IT8716F only supports commands with length 1,2,4,5 bytes including * command byte and can not read more than 3 bytes from the device. @@ -386,4 +265,125 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static uint16_t it87spi_probe(uint16_t port) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + enter_conf_mode_ite(port); + /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ + tmp = sio_read(port, 0x24) & 0xFE; + /* If IT87SPI was not explicitly selected, we want to check + * quickly if LPC->SPI translation is active. + */ + if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { + msg_pdbg("No IT87* serial flash segment enabled.\n"); + exit_conf_mode_ite(port); + /* Nothing to do. */ + return 0; + } + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); + msg_pdbg("LPC write to serial flash %sabled\n", + (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ + /* If any serial flash segment is enabled, enable writing. */ + if ((tmp & 0xe) && (!(tmp & 1 << 4))) { + msg_pdbg("Enabling LPC write to serial flash\n"); + tmp |= 1 << 4; + sio_write(port, 0x24, tmp); + } + msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + /* LDN 0x7, reg 0x64/0x65 */ + sio_write(port, 0x07, 0x7); + flashport = sio_read(port, 0x64) << 8; + flashport |= sio_read(port, 0x65); + msg_pdbg("Serial flash port 0x%04x\n", flashport); + /* Non-default port requested? */ + portpos = extract_programmer_param("it87spiport"); + if (portpos) { + char *endptr = NULL; + unsigned long forced_flashport; + forced_flashport = strtoul(portpos, &endptr, 0); + /* Port 0, port >0x1000, unaligned ports and garbage strings + * are rejected. + */ + if (!forced_flashport || (forced_flashport >= 0x1000) || + (forced_flashport & 0x7) || (*endptr != '\0')) { + /* Using ports below 0x100 is a really bad idea, and + * should only be done if no port between 0x100 and + * 0xff8 works due to routing issues. + */ + msg_perr("Error: it87spiport specified, but no valid " + "port specified.\nPort must be a multiple of " + "0x8 and lie between 0x100 and 0xff8.\n"); + free(portpos); + return 1; + } else { + flashport = (uint16_t)forced_flashport; + msg_pinfo("Forcing serial flash port 0x%04x\n", + flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } + } + free(portpos); + exit_conf_mode_ite(port); + it8716f_flashport = flashport; + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); + spi_controller = SPI_CONTROLLER_IT87XX; + /* FIXME: Add the SPI bus or replace the other buses with it? */ + buses_supported |= CHIP_BUSTYPE_SPI; + return 0; +} + +int init_superio_ite(void) +{ + int i; + int ret = 0; + + for (i = 0; i < superio_count; i++) { + if (superios[i].vendor != SUPERIO_VENDOR_ITE) + continue; + + switch (superios[i].model) { + case 0x8500: + case 0x8502: + case 0x8510: + case 0x8511: + case 0x8512: + /* FIXME: This should be enabled, but we need a check + * for laptop whitelisting due to the amount of things + * which can go wrong if the EC firmware does not + * implement the interface we want. + */ + //it85xx_spi_init(superios[i]); + break; + case 0x8705: + ret |= it8705f_write_enable(superios[i].port); + break; + case 0x8716: + case 0x8718: + case 0x8720: + ret |= it87spi_probe(superios[i].port); + break; + default: + msg_pdbg("Super I/O ID 0x%04hx is not on the list of " + "flash capable controllers.\n", + superios[i].model); + } + } + return ret; +} + #endif diff --git a/wbsio_spi.c b/wbsio_spi.c index acf9cb2..12c458e 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -30,53 +30,6 @@ static uint16_t wbsio_spibase = 0; -static uint16_t wbsio_get_spibase(uint16_t port) -{ - uint8_t id; - uint16_t flashport = 0; - - w836xx_ext_enter(port); - id = sio_read(port, 0x20); - if (id != 0xa0) { - msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); - goto done; - } - - if (0 == (sio_read(port, 0x24) & 2)) { - msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); - goto done; - } - - sio_write(port, 0x07, 0x06); - if (0 == (sio_read(port, 0x30) & 1)) { - msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); - goto done; - } - - flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63); - -done: - w836xx_ext_leave(port); - return flashport; -} - -int wbsio_check_for_spi(void) -{ - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) - return 1; - - msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; - msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " - "1024 KB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; - - return 0; -} - /* W83627DHG has 11 command modes: * 1=1 command only * 2=1 command+1 data write @@ -186,4 +139,51 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) return read_memmapped(flash, buf, start, len); } +static uint16_t wbsio_get_spibase(uint16_t port) +{ + uint8_t id; + uint16_t flashport = 0; + + w836xx_ext_enter(port); + id = sio_read(port, 0x20); + if (id != 0xa0) { + msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); + goto done; + } + + if (0 == (sio_read(port, 0x24) & 2)) { + msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); + goto done; + } + + sio_write(port, 0x07, 0x06); + if (0 == (sio_read(port, 0x30) & 1)) { + msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); + goto done; + } + + flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63); + +done: + w836xx_ext_leave(port); + return flashport; +} + +int wbsio_check_for_spi(void) +{ + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) + return 1; + + msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_WBSIO; + msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " + "1024 KB!\n", __func__); + max_rom_decode.spi = 1024 * 1024; + + return 0; +} + #endif -- 1.7.4.1

1 0

[PATCH 1/3] Factor out SPI write/read chunking wrappers.
by Michael Karcher 05 May '11

05 May '11

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- bitbang_spi.c | 11 ------ buspirate_spi.c | 10 ----- dummyflasher.c | 6 --- ft2232_spi.c | 11 ------ ichspi.c | 20 ----------- it85spi.c | 10 ----- programmer.h | 21 ++++------- sb600spi.c | 11 ------ spi.c | 102 ++++++++++++++++++++++++++++++++++++++++++------------ 9 files changed, 87 insertions(+), 115 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index fb404ac..d63c769 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -151,14 +151,3 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } - -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} diff --git a/buspirate_spi.c b/buspirate_spi.c index d24f890..e7a7a10 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -326,13 +326,3 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } - -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 12); -} - -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 12); -} diff --git a/dummyflasher.c b/dummyflasher.c index d818a84..b6e67db 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -507,12 +507,6 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64kB. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, diff --git a/ft2232_spi.c b/ft2232_spi.c index 7373624..7ff1d81 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -352,17 +352,6 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, return failed ? -1 : 0; } -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} - void print_supported_usbdevs(const struct usbdev_status *devs) { int i; diff --git a/ichspi.c b/ichspi.c index f2814d1..4315e78 100644 --- a/ichspi.c +++ b/ichspi.c @@ -834,26 +834,6 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_read_chunked(flash, buf, start, len, maxdata); -} - -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_write_chunked(flash, buf, start, len, maxdata); -} - int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { diff --git a/it85spi.c b/it85spi.c index 1710d8e..a388d10 100644 --- a/it85spi.c +++ b/it85spi.c @@ -347,14 +347,4 @@ int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 64); -} - -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 64); -} - #endif diff --git a/programmer.h b/programmer.h index 19c3a30..fefb9cd 100644 --- a/programmer.h +++ b/programmer.h @@ -358,7 +358,6 @@ uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif @@ -462,8 +461,6 @@ struct usbdev_status { }; int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -484,8 +481,6 @@ int mcp6x_spi_init(int want_spi); int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -495,8 +490,6 @@ struct buspirate_spispeeds { int buspirate_spi_init(void); int buspirate_spi_shutdown(void); int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); @@ -561,7 +554,13 @@ enum spi_controller { SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; + +#define MAX_DATA_UNSPECIFIED 0 +#define MAX_DATA_READ_UNLIMITED 64 * 1024 +#define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + int max_data_read; + int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -576,6 +575,8 @@ extern const struct spi_programmer spi_programmer[]; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -585,8 +586,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int via_init_spi(struct pci_dev *dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); #endif @@ -595,8 +594,6 @@ int it85xx_spi_init(struct superio s); int it85xx_shutdown(void); int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len); -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -613,8 +610,6 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* wbsio_spi.c */ diff --git a/sb600spi.c b/sb600spi.c index 845cf58..269af8a 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -43,17 +43,6 @@ static uint8_t *sb600_spibar = NULL; -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 8 bytes. */ - return spi_read_chunked(flash, buf, start, len, 8); -} - -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 5); -} - static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); diff --git a/spi.c b/spi.c index 7e9ff1a..5857fda 100644 --- a/spi.c +++ b/spi.c @@ -34,6 +34,8 @@ enum spi_controller spi_controller = SPI_CONTROLLER_NONE; const struct spi_programmer spi_programmer[] = { { /* SPI_CONTROLLER_NONE */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = NULL, .multicommand = NULL, .read = NULL, @@ -43,27 +45,35 @@ const struct spi_programmer spi_programmer[] = { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_ICH9 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT85XX */ + .max_data_read = 64, + .max_data_write = 64, .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = it85_spi_read, - .write_256 = it85_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT87XX */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand, .read = it8716f_spi_chip_read, @@ -71,20 +81,26 @@ const struct spi_programmer spi_programmer[] = { }, { /* SPI_CONTROLLER_SB600 */ + .max_data_read = 8, + .max_data_write = 5, .command = sb600_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_VIA */ + .max_data_read = 16, + .max_data_write = 16, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_WBSIO */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, .multicommand = default_spi_send_multicommand, .read = wbsio_spi_read, @@ -92,43 +108,53 @@ const struct spi_programmer spi_programmer[] = { }, { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #endif #if CONFIG_FT2232_SPI == 1 { /* SPI_CONTROLLER_FT2232 */ + .max_data_read = 64 * 1024, + .max_data_write = 256, .command = ft2232_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DUMMY == 1 { /* SPI_CONTROLLER_DUMMY */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, + .read = default_spi_read, .write_256 = dummy_spi_write_256, }, #endif #if CONFIG_BUSPIRATE_SPI == 1 { /* SPI_CONTROLLER_BUSPIRATE */ + .max_data_read = 12, + .max_data_write = 12, .command = buspirate_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DEDIPROG == 1 { /* SPI_CONTROLLER_DEDIPROG */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, @@ -138,28 +164,34 @@ const struct spi_programmer spi_programmer[] = { #if CONFIG_RAYER_SPI == 1 { /* SPI_CONTROLLER_RAYER */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_NICINTEL_SPI == 1 { /* SPI_CONTROLLER_NICINTEL */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_OGP_SPI == 1 { /* SPI_CONTROLLER_OGP */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif @@ -223,6 +255,30 @@ int default_spi_send_multicommand(struct spi_command *cmds) return result; } +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_read; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI read chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_read_chunked(flash, buf, start, len, max_data); +} + +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_write; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI write chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_write_chunked(flash, buf, start, len, max_data); +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; -- 1.7.4.1

1 0

Problem G41MXE Foxconn
by Marcelo Sales Moreira 04 May '11

04 May '11

Good morning, I am having problem with the motherboard model G41MXE - DDR3 Foxconn, I wonder if there any solution to solve this problem. Attached file with the information with command flashrom -V Att Marcelo Moreira Sales

2 1

jmiteff flashrom -V output
by jmiteff＠charter.net 04 May '11

04 May '11

1 0

FAILED; K9N PLATINUM A7250NMS
by jmiteff＠charter.net 04 May '11

04 May '11

Help, it failed. Says that erase failed at 0x000165c0

1 0

FAILED; k9n a7250nms platinum
by jmiteff＠charter.net 04 May '11

04 May '11

Help, the bios flash failed. Program says not to reboot or shutdown. What do I do next? Have I lost my motherboard?

1 0

RFC: precious regions
by Michael Karcher 04 May '11

04 May '11

Hello flashrom developers, INTRO (may be skipped): ----------------------- while I know that I should spend my time for flashrom with polishing my patches instead of proposing even more changes, I need to write down the idea about "precious regions", as we had two incidentes of descriptor-mode ICH southbridges recently. Some of them would have been prevented by using current HEAD, but even svn HEAD is able to some destruct typical descriptor mode systems. Imagine: Descriptor: 0-8K (r/o) Gigabit: 8K-32K (r/w) BIOS: 32K-2M (r/w) flashrom HEAD will first read the whole chip, then try to erase. All block erase instructions will fail, as the descriptor is r/o. But the chip erase instruction still can be sucessfully sent, and erase verification works, too. In the last step, the new image gets written - but not to the descriptor, as that on is R/O. IDEA: ----- Introduce the concept of "precious regions", i.e. parts of the flash chip that may never be erased. Flashrom would deny to send erase commands to blocks that overlap with precious regions. This might cause flashrom to fail in certain cases where a block that crosses a border between precious and non-precios needs to be erased to modify the contents of the non-precious region, so "precious regions" should not be overused (i.e. declare all not-to-be-modified regions from the layout file as "precious" unconditionally). I see the main use case for precious regions in these two items: - Regions we know we can't write, because of the flash firewall in the chipset. Most flash chips implement their locks in a way that a non-programmable area is non-eraseable, so flash chip locks don't need the "erase forbidden" handling. - Embedded controller code and boot block code precious regions for unwritable areas are mandatory, as flashrom will leave a messed up system behind otherwise, while precious regions for boot block and EC code of course should be optional, but are very nice to have as safety net on computers with soldered flash. I explicitly don't suggest trying to implement a general algorithm to find boot block and EC code in vendor images in flashrom, but a 3rd-party tool to generate layout files might be nice. I do think of extending layout file syntax to be able to flag layout parts (e.g. as precious, but other flags like "prefer big erase/prefer small erase" might make sense too), though. What are your thoughts about this? BACKUP IDEA: ------------ If the precious region stuff seems as overdesigned, we should abort as soon as we find any non-rw region on the ichspi driver. Regards, Michael Karcher

2 3

[PATCH] Constify flashchips array
by Carl-Daniel Hailfinger 04 May '11

04 May '11

Constify flashchips array. This moves 99.5% of the .data section to .rodata (which ends up in .text). Disadvantages: We have one additional memcpy with sizeof(struct flashchip) per executed probe. This is purely startup cost and won't have any impact on operation after probing. Tests would be appreciated, especially with machines having multiple chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-const_flashchips/flash.h =================================================================== --- flashrom-const_flashchips/flash.h (Revision 1252) +++ flashrom-const_flashchips/flash.h (Arbeitskopie) @@ -173,7 +173,7 @@ #define TIMING_IGNORED -1 #define TIMING_ZERO -2 -extern struct flashchip flashchips[]; +extern const struct flashchip flashchips[]; /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); @@ -193,7 +193,7 @@ void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); +int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-const_flashchips/cli_classic.c =================================================================== --- flashrom-const_flashchips/cli_classic.c (Revision 1252) +++ flashrom-const_flashchips/cli_classic.c (Arbeitskopie) @@ -100,7 +100,11 @@ { unsigned long size; /* Probe for up to three flash chips. */ - struct flashchip *flash, *flashes[3]; + const struct flashchip *flash; + struct flashchip flashes[3]; + struct flashchip *fill_flash; + int startchip = 0; + int chipcount = 0; const char *name; int namelen; int opt; @@ -359,49 +363,47 @@ exit(1); } - /* FIXME: Delay calibration should happen in programmer code. */ for (i = 0; i < ARRAY_SIZE(flashes); i++) { - flashes[i] = - probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); - if (!flashes[i]) - for (i++; i < ARRAY_SIZE(flashes); i++) - flashes[i] = NULL; + startchip = probe_flash(startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; } - if (flashes[1]) { + if (chipcount > 1) { printf("Multiple flash chips were detected:"); - for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + for (i = 0; i < chipcount; i++) + printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); - } else if (!flashes[0]) { + } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); - flashes[0] = probe_flash(flashchips, 1); - if (!flashes[0]) { + startchip = probe_flash(0, &flashes[0], 1); + if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash_to_file(flashes[0], filename); + return read_flash_to_file(&flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } - flash = flashes[0]; + fill_flash = &flashes[0]; - check_chip_supported(flash); + check_chip_supported(fill_flash); - size = flash->total_size * 1024; - if (check_max_decode((buses_supported & flash->bustype), size) && + size = fill_flash->total_size * 1024; + if (check_max_decode((buses_supported & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); @@ -432,5 +434,5 @@ * Give the chip time to settle. */ programmer_delay(100000); - return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); + return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); } Index: flashrom-const_flashchips/print_wiki.c =================================================================== --- flashrom-const_flashchips/print_wiki.c (Revision 1252) +++ flashrom-const_flashchips/print_wiki.c (Arbeitskopie) @@ -201,7 +201,7 @@ static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; + const struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) Index: flashrom-const_flashchips/flashchips.c =================================================================== --- flashrom-const_flashchips/flashchips.c (Revision 1252) +++ flashrom-const_flashchips/flashchips.c (Arbeitskopie) @@ -32,7 +32,7 @@ * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ -struct flashchip flashchips[] = { +const struct flashchip flashchips[] = { /* * .vendor = Vendor name Index: flashrom-const_flashchips/flashrom.c =================================================================== --- flashrom-const_flashchips/flashrom.c (Revision 1252) +++ flashrom-const_flashchips/flashrom.c (Arbeitskopie) @@ -1123,15 +1123,15 @@ return 1; } -struct flashchip *probe_flash(struct flashchip *first_flash, int force) +int probe_flash(int startchip, struct flashchip *fill_flash, int force) { - struct flashchip *flash; + const struct flashchip *flash; unsigned long base = 0; uint32_t size; enum chipbustype buses_common; char *tmp; - for (flash = first_flash; flash && flash->name; flash++) { + for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; msg_gdbg("Probing for %s %s, %d KB: ", @@ -1158,25 +1158,35 @@ size = flash->total_size * 1024; check_max_decode(buses_common, size); + /* Start filling in the dynamic data. */ + *fill_flash = *flash; + base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); if (force) break; - if (flash->probe(flash) != 1) + if (fill_flash->probe(fill_flash) != 1) goto notfound; - if (first_flash == flashchips - || flash->model_id != GENERIC_DEVICE_ID) + /* If this is the first chip found, accept it. + * If this is not the first chip found, accept it only if it is + * a non-generic match. + * We could either make chipcount global or provide it as + * parameter, or we assume that startchip==0 means this call to + * probe_flash() is the first one and thus no chip has been + * found before. + */ + if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); + programmer_unmap_flash_region((void *)fill_flash->virtual_memory, size); } if (!flash || !flash->name) - return NULL; + return -1; msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", force ? "Assuming" : "Found", @@ -1187,10 +1197,11 @@ * may be stored in registers, so avoid lock info printing. */ if (!force) - if (flash->printlock) - flash->printlock(flash); + if (fill_flash->printlock) + fill_flash->printlock(fill_flash); - return flash; + /* Return position of matching chip. */ + return flash - flashchips; } int verify_flash(struct flashchip *flash, uint8_t *buf) @@ -1299,7 +1310,7 @@ * walk_eraseregions(). * Even if an error is found, the function will keep going and check the rest. */ -static int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(const struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1676,7 +1687,7 @@ int selfcheck(void) { int ret = 0; - struct flashchip *flash; + const struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. @@ -1695,7 +1706,7 @@ return ret; } -void check_chip_supported(struct flashchip *flash) +void check_chip_supported(const struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); Index: flashrom-const_flashchips/programmer.h =================================================================== --- flashrom-const_flashchips/programmer.h (Revision 1252) +++ flashrom-const_flashchips/programmer.h (Arbeitskopie) @@ -497,7 +497,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(struct flashchip *flash); +void check_chip_supported(const struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(char *param_name); Index: flashrom-const_flashchips/print.c =================================================================== --- flashrom-const_flashchips/print.c (Revision 1252) +++ flashrom-const_flashchips/print.c (Arbeitskopie) @@ -78,7 +78,7 @@ { int okcol = 0, pos = 0, i, chipcount = 0; int maxchiplen = 0, maxvendorlen = 0; - struct flashchip *f; + const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ -- http://www.hailfinger.org/

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