- flashrom - mail.coreboot.org

Gigabyte M720-US3
by Grim Reaper 05 Jul '11

05 Jul '11

Hi, I sucessfully flash my BIOS using flashrom, but warning apear. See attachement - there is output from "flashrom -V". studio@studio:~$ sudo dmidecode -t baseboard # dmidecode 2.9 SMBIOS 2.4 present. Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: Gigabyte Technology Co., Ltd. Product Name: M720-US3 Version: Serial Number: If you need some more info simply ask. BTW. great APP ;-) Best Regards XJ

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[PATCH] Kill unused "log" argument of count_usable_erasers()
by Sylvain 'ythier' Hitier 04 Jul '11

04 Jul '11

Kill unused "log" argument of count_usable_erasers(). Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> Index: flashrom.c =================================================================== --- flashrom.c (revision 1362) +++ flashrom.c (working copy) @@ -713,9 +713,8 @@ return extract_param(&programmer_param, param_name, ","); } -/* Returns the number of well-defined erasers for a chip. - * The log parameter controls output. */ -static unsigned int count_usable_erasers(const struct flashchip *flash, int log) +/* Returns the number of well-defined erasers for a chip. */ +static unsigned int count_usable_erasers(const struct flashchip *flash) { unsigned int usable_erasefunctions = 0; int k; @@ -1511,7 +1510,7 @@ int k, ret = 0; uint8_t *curcontents; unsigned long size = flash->total_size * 1024; - unsigned int usable_erasefunctions = count_usable_erasers(flash, 0); + unsigned int usable_erasefunctions = count_usable_erasers(flash); msg_cinfo("Erasing and writing flash chip... "); curcontents = (uint8_t *) malloc(size); @@ -1831,7 +1830,7 @@ return 1; msg_cerr("Continuing anyway.\n"); } - if(count_usable_erasers(flash, 0) == 0) { + if(count_usable_erasers(flash) == 0) { msg_cerr("flashrom has no erase function for this " "flash chip.\n"); return 1; Regards, Sylvain "ythier" Hitier -- Business is about being busy, not being rich... Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse

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[commit] r1364 - trunk
by repository service 04 Jul '11

04 Jul '11

Author: stefanct Date: Mon Jul 4 09:27:17 2011 New Revision: 1364 URL: http://flashrom.org/trac/flashrom/changeset/1364 Log: Kill unused "log" argument of count_usable_erasers(). Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 3 21:44:12 2011 (r1363) +++ trunk/flashrom.c Mon Jul 4 09:27:17 2011 (r1364) @@ -713,9 +713,8 @@ return extract_param(&programmer_param, param_name, ","); } -/* Returns the number of well-defined erasers for a chip. - * The log parameter controls output. */ -static unsigned int count_usable_erasers(const struct flashchip *flash, int log) +/* Returns the number of well-defined erasers for a chip. */ +static unsigned int count_usable_erasers(const struct flashchip *flash) { unsigned int usable_erasefunctions = 0; int k; @@ -1511,7 +1510,7 @@ int k, ret = 0; uint8_t *curcontents; unsigned long size = flash->total_size * 1024; - unsigned int usable_erasefunctions = count_usable_erasers(flash, 0); + unsigned int usable_erasefunctions = count_usable_erasers(flash); msg_cinfo("Erasing and writing flash chip... "); curcontents = (uint8_t *) malloc(size); @@ -1831,7 +1830,7 @@ return 1; msg_cerr("Continuing anyway.\n"); } - if(count_usable_erasers(flash, 0) == 0) { + if(count_usable_erasers(flash) == 0) { msg_cerr("flashrom has no erase function for this " "flash chip.\n"); return 1;

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[PATCH] Fix and improve Windows/MinGW/MSYS build
by Uwe Hermann 03 Jul '11

03 Jul '11

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1363 - trunk
by repository service 03 Jul '11

03 Jul '11

Author: uwe Date: Sun Jul 3 21:44:12 2011 New Revision: 1363 URL: http://flashrom.org/trac/flashrom/changeset/1363 Log: Fix and improve Windows/MinGW/MSYS build. - Makefile: Use $(OS_ARCH) to add some MinGW-specific workarounds and settings, so that a simple "make" is sufficient on MinGW (instead of manual Makefile hacking). - Explicitly set CC=gcc in the Makefile, otherwise you get an error like "cc: command not found" on MinGW. - MinGW doesn't have ffs(), use gcc's __builtin_ffs() instead. - Add /usr/local/include and /usr/local/lib to CPPFLAGS/LDFLAGS, that's where libusb-win32 and libftdi stuff is usually placed on MinGW/MSYS. - Disable serprog (no sockets) and all PCI-based programmers (no libpci) for now. That leaves dummy, ft2232_spi, and buspirate_spi enabled on MinGW per default. - serial.c: Use correct type for 'tmp', both on Windows/MinGW (DWORD) and POSIX (ssize_t). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/serial.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Jul 1 02:39:23 2011 (r1362) +++ trunk/Makefile Sun Jul 3 21:44:12 2011 (r1363) @@ -84,6 +84,88 @@ endif endif +ifeq ($(OS_ARCH), MINGW32_NT-5.1) +# Explicitly set CC = gcc on MinGW, otherwise: "cc: command not found". +CC = gcc +# MinGW doesn't have the ffs() function, but we can use gcc's __builtin_ffs(). +CFLAGS += -Dffs=__builtin_ffs +# libusb-win32/libftdi stuff is usually installed in /usr/local. +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +# Serprog is not supported under Windows/MinGW (missing sockets support). +ifeq ($(CONFIG_SERPROG), yes) +UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +else +override CONFIG_SERPROG = no +endif +# For now we disable all PCI-based programmers on Windows/MinGW (no libpci). +ifeq ($(CONFIG_INTERNAL), yes) +UNSUPPORTED_FEATURES += CONFIG_INTERNAL=yes +else +override CONFIG_INTERNAL = no +endif +ifeq ($(CONFIG_RAYER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes +else +override CONFIG_RAYER_SPI = no +endif +ifeq ($(CONFIG_NIC3COM), yes) +UNSUPPORTED_FEATURES += CONFIG_NIC3COM=yes +else +override CONFIG_NIC3COM = no +endif +ifeq ($(CONFIG_GFXNVIDIA), yes) +UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes +else +override CONFIG_GFXNVIDIA = no +endif +ifeq ($(CONFIG_SATASII), yes) +UNSUPPORTED_FEATURES += CONFIG_SATASII=yes +else +override CONFIG_SATASII = no +endif +ifeq ($(CONFIG_ATAHPT), yes) +UNSUPPORTED_FEATURES += CONFIG_ATAHPT=yes +else +override CONFIG_ATAHPT = no +endif +ifeq ($(CONFIG_DRKAISER), yes) +UNSUPPORTED_FEATURES += CONFIG_DRKAISER=yes +else +override CONFIG_DRKAISER = no +endif +ifeq ($(CONFIG_NICREALTEK), yes) +UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes +else +override CONFIG_NICREALTEK = no +endif +ifeq ($(CONFIG_NICNATSEMI), yes) +UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes +else +override CONFIG_NICNATSEMI = no +endif +ifeq ($(CONFIG_NICINTEL), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes +else +override CONFIG_NICINTEL = no +endif +ifeq ($(CONFIG_NICINTEL_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes +else +override CONFIG_NICINTEL_SPI = no +endif +ifeq ($(CONFIG_OGP_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_OGP_SPI=yes +else +override CONFIG_OGP_SPI = no +endif +ifeq ($(CONFIG_SATAMV), yes) +UNSUPPORTED_FEATURES += CONFIG_SATAMV=yes +else +override CONFIG_SATAMV = no +endif +endif + ifeq ($(OS_ARCH), libpayload) CC:=CC=i386-elf-gcc lpgcc AR:=i386-elf-ar Modified: trunk/serial.c ============================================================================== --- trunk/serial.c Fri Jul 1 02:39:23 2011 (r1362) +++ trunk/serial.c Sun Jul 3 21:44:12 2011 (r1363) @@ -192,7 +192,11 @@ int serialport_write(unsigned char *buf, unsigned int writecnt) { - long tmp = 0; +#ifdef _WIN32 + DWORD tmp = 0; +#else + ssize_t tmp = 0; +#endif while (writecnt > 0) { #ifdef _WIN32 @@ -215,7 +219,11 @@ int serialport_read(unsigned char *buf, unsigned int readcnt) { - long tmp = 0; +#ifdef _WIN32 + DWORD tmp = 0; +#else + ssize_t tmp = 0; +#endif while (readcnt > 0) { #ifdef _WIN32

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Re: [flashrom] PCCHIPS M863G V5.1A + Winbond W49V002AP - Write OK
by Stefan Tauner 03 Jul '11

03 Jul '11

On Sat, 2 Jul 2011 12:27:45 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > Tested with a PCCHIPS M863G V5.1A board w/ a Winbond W49V002AP flash. > I programmed "050518S.rom" BIOS. Worked OK. hello and thanks for your report! i have added the board to our supported hw list and marked the W49V002A as fully tested and will commit that later. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Asus M3A
by Fabio Semino 03 Jul '11

03 Jul '11

Erase and write ok with 12.06 bios, i'm attaching the output of the operation and lspci Fabio

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PCCHIPS M863G V5.1A + Winbond W49V002AP - Write OK
by Marcos Felipe Rasia de Mello 02 Jul '11

02 Jul '11

Tested with a PCCHIPS M863G V5.1A board w/ a Winbond W49V002AP flash. I programmed "050518S.rom" BIOS. Worked OK. Marcos ---------------------------------------------------------- # flashrom -Vw 050518S.rom flashrom v0.9.3-r1362 on Linux 2.6.39.2-zero (i686), built with libpci 3.1.4, GCC 4.4.4 20100726 (Red Hat 4.4.4-13), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 750M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "M863" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "M863" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8705 on port 0x2e Found ITE Super I/O, ID 0x8705 on port 0x4e Found chipset "SiS 741", enabling flash write... chipset PCI ID is 1039:0741, Found southbridge 1039:0964 at 00:02:0 OK. This chipset supports the following protocols: Non-SP. No IT8705F flash segment enabled. No IT8705F flash segment enabled. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Found chip "Winbond W49V002A" (256 kB, LPC) at physical address 0xfffc0000. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0xb0 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0xb0 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x00ffff:W, 0x010000-0x01ffff:W, 0x020000-0x02ffff:W, 0x030000-0x037fff:W, 0x038000-0x039fff:S, 0x03a000-0x03bfff:S, 0x03c000-0x03ffff:W Done. Verifying flash... VERIFIED. Restoring PCI config space for 00:02:0 reg 0x45 Restoring PCI config space for 00:02:0 reg 0x40

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Re: [flashrom] [PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 01.07.2011 04:45 schrieb David Hendricks: > On Tue, Jun 28, 2011 at 7:26 PM, Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > >> Autodetect target processor architecture. >> Enable architecture dependent compilation of individual sub-drivers for >> the internal programmer. >> >> With this patch, you no longer have to edit the Makefile to compile the >> internal driver on MIPS/ARM/... >> >> TODO: arch.h is not suitable for inclusion in a .c/.h file because of >> its last line. Any ideas how to change that (move arch.h as "here >> document" into the Makefile, use other trickery like more #ifdefs)? >> >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> >> >> Index: flashrom-target_arch/Makefile >> =================================================================== >> --- flashrom-target_arch/Makefile (Revision 1357) >> +++ flashrom-target_arch/Makefile (Arbeitskopie) >> @@ -37,7 +37,10 @@ >> CFLAGS += -Werror >> endif >> >> -# FIXME We have to differentiate between host and target arch. >> +# Determine the destination processor architecture >> +ARCH = $(strip $(shell LC_ALL=C gcc -E arch.h|grep -v '^\#')) >> >> > Use $(CC) instead of "gcc" so stuff like "armv7a-cros-linux-gnueabi-gcc" > Ouch, yes! This was a cut-n-paste error. Thanks for spotting it. > gets handled properly. I still think assigning ARCH conditionally is wise > since package managers should set it when cross-compiling, though > using $(CC) should yield the same result. > > Aside from that, I was able to cross-compile successfully for ARM (using the > same CONFIG_* settings as before) after adding this minor patch on top of > yours: > > diff -Nru a/Makefile b/Makefile > --- a/Makefile 2011-06-30 19:35:53.410049173 -0700 > +++ b/Makefile 2011-06-30 19:35:39.140049283 -0700 > @@ -38,7 +38,7 @@ > endif > > # Determine the destination processor architecture > -ARCH = $(strip $(shell LC_ALL=C gcc -E arch.h|grep -v '^\#')) > +ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) > Right. > # FIXME We have to differentiate between host and target OS architecture. > OS_ARCH ?= $(shell uname) > @@ -228,6 +228,10 @@ > ifeq ($(ARCH),"x86") > PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o > mcp6x_spi.o > else > +ifeq ($(ARCH),"arm") > +PROGRAMMER_OBJS += tegra2_spi.o > +else > +endif > endif > NEED_PCI := yes > endif > diff -Nru a/arch.h b/arch.h > --- a/arch.h 2011-06-30 19:35:50.190944388 -0700 > +++ b/arch.h 2011-06-30 19:35:35.280103884 -0700 > @@ -27,5 +27,7 @@ > #define __FLASHROM_ARCH__ "mips" > #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || > defined(__ppc64__) > #define __FLASHROM_ARCH__ "ppc" > +#elif defined(__arm__) > +#define __FLASHROM_ARCH__ "arm" > #endif > __FLASHROM_ARCH__ > Should I extend my patch to cover ARM as well, or should we perform all AR related changes in your big ARM suppport patch? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 3/3] add support for SFDP (JESD216)
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 24.06.2011 16:53 schrieb Stefan Tauner: > Similar to ICH Hardware Sequencing this uses a generic struct flashchip > element in flashrom.c with dummy values and a special probe function that fills the > obtained values into that generic struct. > Documentation used: > http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) > W25Q32BV data sheet Revision F (2011-04-01) > EN25QH16 data sheet Revision F (2011-06-01) > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Nice feature. > --- > chipdrivers.h | 1 + > flashchips.c | 24 +++++ > flashchips.h | 1 + > flashrom.c | 28 ++++++- > spi.h | 5 + > spi25.c | 273 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 6 files changed, 331 insertions(+), 1 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 92ddbea..0a3df50 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -26,6 +26,7 @@ > #define __CHIPDRIVERS_H__ 1 > > /* spi.c, should probably be in spi_chip.c */ > +int probe_spi_sfdp(struct flashchip *flash); > int probe_spi_rdid(struct flashchip *flash); > int probe_spi_rdid4(struct flashchip *flash); > int probe_spi_rems(struct flashchip *flash); > diff --git a/flashchips.c b/flashchips.c > index 865ba2f..6fbbd2c 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -8507,6 +8507,30 @@ const struct flashchip flashchips[] = { > .write = write_jedec_1, > .read = read_memmapped, > }, > + > + { > + .vendor = "Unknown", > + .name = "SFDP device", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = GENERIC_MANUF_ID, > + .model_id = SFDP_DEVICE_ID, > + /* We present our own "report this" text hence we do not > + * want the default "This flash part has status UNTESTED..." > + * text to be printed. */ > + .tested = TEST_OK_PREW, > + .probe = probe_spi_sfdp, > + .page_size = 256, > + .write = spi_chip_write_256, > Does SFDP really specify 256-byte write capability? > + .read = spi_chip_read, > + /* FIXME: some vendor extensions define this */ > + .voltage = {}, > + /* Everything below will be set by the probing function. */ > + .total_size = 0, > + .feature_bits = 0, > + .block_erasers = {}, > + .unlock = NULL, > + .printlock = NULL, > + }, > > { > .vendor = "AMIC", > diff --git a/flashchips.h b/flashchips.h > index 3b2b94f..82333c8 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -36,6 +36,7 @@ > > #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ > #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ > +#define SFDP_DEVICE_ID 0xfffe > Just a comment, not something that needs to be changed: We probably need CFI_DEVICE_ID as well once we support CFI (which is SFDP for non-SPI flash). > > #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ > #define ALLIANCE_AS29F002B 0x34 > diff --git a/flashrom.c b/flashrom.c > index aed10aa..56af373 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1206,7 +1206,33 @@ int probe_flash(int startchip, struct flashchip *fill_flash, int force) > * probe_flash() is the first one and thus no chip has been > * found before. > */ > - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) > + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { > + msg_cinfo("===\n" > + "SFDP has autodetected a flash chip which is " > + "not natively supported by flashrom yet.\n"); > + if (!check_block_erasers(flash, 0)) > + msg_cinfo("The standard operations read and " > + "verify should work, but to support " > + "erase, write and all other " > + "possible features"); > + else > + msg_cinfo("All standard operations (read, " > + "verify, erase and write) should " > + "work, but to support all possible " > + "features"); > + > + msg_cinfo(" we need to add them manually.\nYou " > + "can help us by mailing us the output of " > + "the following command to flashrom@flashrom." > + "org: \n'flashrom -VV [plus the " > + "-p/--programmer parameter (if needed)]" > + "'\nThanks for your help!\n" > + "===\n"); > + } > Should we refactor those SFDP messages into a separate function and do that for the untested chip messages as well? It would probably improve code readability here. > + > + if (startchip == 0 || > + ((fill_flash->model_id != GENERIC_DEVICE_ID) && > + (fill_flash->model_id != SFDP_DEVICE_ID))) > break; > > notfound: > diff --git a/spi.h b/spi.h > index b908603..5f07eae 100644 > --- a/spi.h > +++ b/spi.h > @@ -40,6 +40,11 @@ > #define JEDEC_REMS_OUTSIZE 0x04 > #define JEDEC_REMS_INSIZE 0x02 > > +/* Read Serial Flash Discoverable Parameters (SFDP) */ > +#define JEDEC_SFDP 0x5a > +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ > Ouch. A few SPI masters will have pretty explosions with that outsize. This reminds me... I should resend my patch which can deal with dummy bytes between write and read in a SPI command. > +/* JEDEC_SFDP_INSIZE : any length */ > + > /* Read Electronic Signature */ > #define JEDEC_RES 0xab > #define JEDEC_RES_OUTSIZE 0x04 > diff --git a/spi25.c b/spi25.c > index d3680fb..af81f19 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -23,6 +23,7 @@ > */ > > #include <string.h> > +#include <stdlib.h> > #include "flash.h" > #include "flashchips.h" > #include "chipdrivers.h" > @@ -113,6 +114,278 @@ int spi_write_disable(void) > return spi_send_command(sizeof(cmd), 0, cmd, NULL); > } > > The code below is huge, and I'd argue it is for a chip family and should live in sfdp25.c (or something with a similar name). > +static int spi_sfdp(uint32_t address, uint8_t *buf, int len) > +{ > + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { > + JEDEC_SFDP, > + (address >> 16) & 0xff, > + (address >> 8) & 0xff, > + (address >> 0) & 0xff, > + 0 > + }; > + return spi_send_command(sizeof(cmd), len, cmd, buf); > +} > + > +struct sfdp_tbl_hdr { > + uint8_t id; > + uint8_t v_minor; > + uint8_t v_major; > + uint8_t len; > + uint32_t ptp; /* 24b pointer */ > +}; > + > +struct sfdp_tbl_0 { > + uint8_t id; > + uint8_t v_minor; > + uint8_t v_major; > + uint8_t len; > + uint32_t ptp; /* 24b pointer */ > +}; > + > +static int sfdp_fill_flash(struct flashchip *f, uint8_t *buf, uint16_t len) > +{ > + uint32_t tmp32; > + uint8_t tmp8; > + uint32_t total_size; /* in bytes */ > + uint32_t bsize; > + int i, j; > + > + msg_cspew("Parsing JEDEC SFDP parameter table...\n"); > + if (len == 9 * 4) { > + msg_cerr("%s: len out of spec\n", __func__); > + return 1; > + } > + > + /* 1. double word */ > + i = 0; > + tmp32 = buf[(4 * i) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * i) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * i) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * i) + 3]) << 24; > + > + tmp8 = (tmp32 >> 17) & 0x3; > + switch (tmp8) { > + case 0x0: > + msg_cspew(" 3-Byte only addressing.\n"); > + break; > + case 0x1: > + msg_cspew(" 3-Byte (and optionally 4-Byte) addressing.\n"); > + break; > + case 0x2: > + msg_cdbg(" 4-Byte only addressing not supported.\n"); > + return 1; > + default: > + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", > + tmp8); > + return 1; > + } > + > + msg_cspew(" Writes to the status register have "); > + if (tmp32 & (1 << 3)) { > + f->unlock = spi_disable_blockprotect; > + msg_cspew("to be enabled with "); > + if (tmp32 & (1 << 4)) { > + f->feature_bits = FEATURE_WRSR_WREN; > + msg_cspew("WREN (0x06).\n"); > + } else { > + f->feature_bits = FEATURE_WRSR_EWSR; > + msg_cspew("EWSR (0x50).\n"); > + } > + } else > + msg_cspew("not to be especially enabled.\n"); > + > + /* 2. double word */ > + i = 1; > + tmp32 = buf[(4 * i) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * i) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * i) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * i) + 3]) << 24; > + > + if (tmp32 & (1<<31)) { > + msg_cdbg(" Flash chip size >= 4 Gb/ 500 MB not supported.\n"); > + return 1; > + } > + total_size = (tmp32 & 0x7FFFFFFF) / 8; > + f->total_size = total_size / 1024; > + msg_cspew(" Flash chip size is %d kB.\n", f->total_size); > + > + i = 8; > + for(j = 0; j < 4; j++) { > + /* 8 double words from the start + 2 words for every eraser */ > + bsize = 2^(buf[(4 * i) + (2 * j)]); > + if (bsize == 0) > + continue; > + > + tmp32 = buf[(4 * i) + (2 * j) + 1]; > + switch(tmp32){ > + case 0x00: > + case 0xff: > + /* Not specified, assuming "not supported". */ > + continue; > + case 0x20: > + f->block_erasers[j].block_erase = spi_block_erase_20; > + break; > + case 0x52: > + f->block_erasers[j].block_erase = spi_block_erase_52; > + break; > + case 0x60: > + f->block_erasers[j].block_erase = spi_block_erase_60; > + break; > + case 0xc7: > + f->block_erasers[j].block_erase = spi_block_erase_c7; > + break; > + case 0xd7: > + f->block_erasers[j].block_erase = spi_block_erase_d7; > + break; > + case 0xd8: > + f->block_erasers[j].block_erase = spi_block_erase_d8; > + break; > + default: > + msg_cinfo("%s: unknown opcode (0x%02x) in SFDP table. " > + "Please report this at " > + "flashrom(a)flashrom.org\n", > + __func__, tmp32); > + continue; > + } > + f->block_erasers[j].eraseblocks[0].size = bsize; > + f->block_erasers[j].eraseblocks[0].count = total_size/bsize; > + msg_cspew(" Block eraser %d: %d x %d B with opcode 0x%02x\n", > + j, total_size/bsize, bsize, tmp32); > + } > + return 0; > +} > + > +static int sfdp_fetch_pt(uint32_t addr, uint8_t *buf, uint16_t len) > +{ > + uint16_t i; > + if (spi_sfdp(addr, buf, len)) { > + msg_cerr("Receiving SFDP parameter table failed.\n"); > + return 1; > + } > + msg_cspew(" Parameter table contents:\n"); > + for(i = 0; i < len; i++) { > + if ((i % 8) == 0) { > + msg_cspew(" 0x%03x: ", i); > + } > + msg_cspew(" 0x%02x", buf[i]); > + if ((i % 8) == 7) { > + msg_cspew("\n"); > + continue; > + } > + if ((i % 8) == 3) { > + msg_cspew(" "); > + continue; > + } > + } > + msg_cspew("\n"); > + return 0; > +} > + > +int probe_spi_sfdp(struct flashchip *flash) > +{ > + int ret = 0; > + uint8_t buf[8]; > + uint16_t tmp16; > + uint32_t tmp32; > + uint8_t nph; > + uint8_t i; > + struct sfdp_tbl_hdr *hdrs; > + uint8_t *hbuf; > + uint8_t *tbuf; > + > + if (spi_sfdp(0x0, buf, 4)) { > + msg_cerr("Receiving SFDP signature failed.\n"); > + return 0; > + } > + tmp32 = buf[0]; > + tmp32 |= ((unsigned int)buf[1]) << 8; > + tmp32 |= ((unsigned int)buf[2]) << 16; > + tmp32 |= ((unsigned int)buf[3]) << 24; > + > + msg_cspew("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); > + if (tmp32 != 0x50444653) { > + msg_cdbg("No SFDP signature found.\n"); > + return 0; > + } > + if (spi_sfdp(0x4, buf, 3)) { > + msg_cerr("Receiving SFDP revision and number of parameter " > + "headers (NPH) failed. "); > + return 0; > + } > + msg_cspew("SFDP revision = %d.%d\n", buf[1], buf[0]); > + nph = buf[3]; > + msg_cspew("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" > + "\n", nph); > + > + /* Fetch all parameter headers, even if we don't use them all (yet). */ > + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); > + hdrs = malloc((nph + 1) * 8); > + if (hbuf == NULL || hdrs == NULL ) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (spi_sfdp(0x8, hbuf, (nph + 1) * 8)) { > + msg_cerr("Receiving SFDP parameter table headers failed.\n"); > + goto cleanup_hdrs; > + } > + > + i = 0; > + do{ > + hdrs[i].id = hbuf[(8 * i) + 0]; > + hdrs[i].v_minor = hbuf[(8 * i) + 1]; > + hdrs[i].v_major = hbuf[(8 * i) + 2]; > + hdrs[i].len = hbuf[(8 * i) + 3]; > + hdrs[i].ptp = hbuf[(8 * i) + 4]; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; > + msg_cspew("SFDP parameter table header %d:\n", i); > + msg_cspew(" ID 0x%02x, version %d.%d\n", hdrs[i].id, > + hdrs[i].v_major, hdrs[i].v_minor); > + tmp16 = hdrs[i].len * 4; > + tmp32 = hdrs[i].ptp; > + msg_cspew(" Length %d B, Parameter Table Pointer 0x%06x\n", > + tmp16, tmp32); > + > + tbuf = malloc(tmp16); > + if (tbuf == NULL) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (sfdp_fetch_pt(tmp32, tbuf, tmp16)){ > + msg_cerr("Fetching SFDP parameter table %d failed.\n", > + i); > + free(tbuf); > + break; > + } > + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ > + if (hdrs[i].id != 0) > + msg_cdbg("ID of the mandatory JEDEC SFDP " > + "parameter table is not 0 as demanded " > + "by JESD216 (warning only).\n"); > + > + if (hdrs[i].len != (9 * 4)) { > + msg_cdbg("Length of the mandatory JEDEC SFDP " > + "parameter table is not 24 B as " > + "demanded by JESD216.\n"); > + if (hdrs[i].len == (4 * 4)) > + msg_cdbg("It seems like it is the " > + "preliminary Intel version of " > + "SFDP, which we don't support." > + "\n"); > + } else if (sfdp_fill_flash(flash, tbuf, tmp16) == 0) > + ret = 1; > + } > + > + free(tbuf); > + i++; > + } while(i <= nph); > + > +cleanup_hdrs: > + free(hdrs); > + free(hbuf); > + return ret; > +} > + > static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) > { > unsigned char readarr[4]; > Could you resend this with the comments addressed and with the squash patch merged in? I didn't review the SFDP code yet, but the right presentation makes reviewing easier. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 5

[PATCH] fix unchecked malloc calls
by Stefan Tauner 01 Jul '11

01 Jul '11

compile tested only. btw... why dont we wrap malloc to automatically include these checks? there is probably a patch somewhere that adds totally awesome shutdown code in OOM cases, but afaics we just print a warning and exit right now... it is just stupid to do the checks in the real code then. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.c | 12 ++++++++++++ hwaccess.c | 4 ++++ pcidev.c | 4 ++++ serial.c | 2 ++ 4 files changed, 22 insertions(+), 0 deletions(-) diff --git a/flashrom.c b/flashrom.c index 12a51ad..a41d0c9 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1515,6 +1515,10 @@ int erase_and_write_flash(struct flashchip *flash, uint8_t *oldcontents, uint8_t msg_cinfo("Erasing and writing flash chip... "); curcontents = (uint8_t *) malloc(size); + if (!curcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Copy oldcontents to curcontents to avoid clobbering oldcontents. */ memcpy(curcontents, oldcontents, size); @@ -1882,9 +1886,17 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, } oldcontents = (uint8_t *) malloc(size); + if (!oldcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Assume worst case: All bits are 0. */ memset(oldcontents, 0x00, size); newcontents = (uint8_t *) malloc(size); + if (!newcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Assume best case: All bits should be 1. */ memset(newcontents, 0xff, size); /* Side effect of the assumptions above: Default write action is erase diff --git a/hwaccess.c b/hwaccess.c index efe8bb0..8c89925 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -226,6 +226,10 @@ int undo_mmio_write(void *p) { \ struct undo_mmio_write_data *undo_mmio_write_data; \ undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + if (!undo_mmio_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ undo_mmio_write_data->addr = a; \ undo_mmio_write_data->type = mmio_write_type_##c; \ undo_mmio_write_data->c##data = mmio_read##c(a); \ diff --git a/pcidev.c b/pcidev.c index 1f9a5cc..d4ad8bc 100644 --- a/pcidev.c +++ b/pcidev.c @@ -295,6 +295,10 @@ int undo_pci_write(void *p) { \ struct undo_pci_write_data *undo_pci_write_data; \ undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \ + if (!undo_pci_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ undo_pci_write_data->dev = *a; \ undo_pci_write_data->reg = b; \ undo_pci_write_data->type = pci_write_type_##c; \ diff --git a/serial.c b/serial.c index 37ea422..31d76e3 100644 --- a/serial.c +++ b/serial.c @@ -110,6 +110,8 @@ fdtype sp_openserport(char *dev, unsigned int baud) (tolower((unsigned char)dev[1]) == 'o') && (tolower((unsigned char)dev[2]) == 'm')) { dev2 = malloc(strlen(dev) + 5); + if (!dev2) + sp_die("Error: Out of memory"); strcpy(dev2, "\\\\.\\"); strcpy(dev2 + 4, dev); } -- 1.7.1

1 0

[PATCH 3/3] ichspi.c: add support for Intel Hardware Sequencing
by Stefan Tauner 01 Jul '11

01 Jul '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? when should swseq be forbidden? etc. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Tested-by: David Hendricks <dhendrix(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ichspi.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 5 files changed, 346 insertions(+), 12 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 865ba2f..5d2b6a8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8507,7 +8507,27 @@ const struct flashchip flashchips[] = { .write = write_jedec_1, .read = read_memmapped, }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8640,6 +8660,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index 3b2b94f..6b8d574 100644 --- a/flashchips.h +++ b/flashchips.h @@ -340,6 +340,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ichspi.c b/ichspi.c index 5783272..3a694f2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -35,10 +35,11 @@ * */ -#if defined(__i386__) || defined(__x86_64__) +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) #include <string.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1093,6 +1094,293 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + extern struct flash_descriptor fdbar; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = (getFCBA_component_density(0) + + getFCBA_component_density(1)); + msg_cdbg("Found %d attached SPI flash chip", fdbar.NC + 1); + if (fdbar.NC) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len >= flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len >= flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len >= flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = ich_fill_data(buf, len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1211,6 +1499,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1219,20 +1517,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint16_t spibar_offset, tmp2; uint32_t tmp; int ichspi_desc = 0; + /* used for hw sequencing detection */ + extern struct flash_descriptor fdbar; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1243,8 +1540,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1280,9 +1577,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1359,10 +1660,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, read_ich_descriptors_from_fdo(ich_spibar); prettyprint_ich_descriptors(CHIPSET_UNKNOWN); } - ich_init_opcodes(); - break; - default: - /* Nothing */ + + if (ichspi_lock || fdbar.NC != 0) + register_spi_programmer(&spi_programmer_ich_hwseq); + else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); + } break; } diff --git a/programmer.h b/programmer.h index cd82dcb..2c71754 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 2/3] add ICH/PCH flash descriptor decoding
by Stefan Tauner 01 Jul '11

01 Jul '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds... - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers) - a new tool to the util directory that is able to decode all flash descriptors stored in a flash dump file. it also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the prettyprinting function is used by the descriptor code too: the properties of flash chips supported by the ME are stored in the same format in a descriptor table. this is also the reason why the pp function and the register bit macros are not defined in ichspi.c but ich_descriptors.h TODO: - is endianess important? and other questions related to the struct/union pattern used. - how to detect the chipset used for the strap descriptors which differ a lot between chipset versions? when called from flashrom this is easy (1. because we know the chipset and 2. we don't need to know currently, because we can't read it via registers anyway. do we wanna try to read the descriptor block from flash for this?). there is afaics no way to deduce the chipset from image files so we should introduce a parameter for that in the tool...? - file naming and partitioning was not discussed. we may want a ichspi.h. and/or rename ichspi.c to ich_spi.c or similar... Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 3 +- ich_descriptors.c | 494 ++++++++++++++++++++++ ich_descriptors.h | 449 ++++++++++++++++++++ ichspi.c | 35 ++- util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 271 ++++++++++++ 7 files changed, 1294 insertions(+), 5 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/Makefile b/Makefile index 456c6ae..bee664f 100644 --- a/Makefile +++ b/Makefile @@ -223,7 +223,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o NEED_PCI := yes endif diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..b41eee4 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,494 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "ich_descriptors.h" + +#if defined(__i386__) || defined(__x86_64__) + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#define msg_perr printf +#include <stdio.h> + +struct flash_strap fisba; +struct flash_upper_map flumap; + +#else + +#include "flash.h" /* for msg_* */ + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +struct flash_descriptor fdbar = { 0 }; +struct flash_component fcba = { {0} }; +struct flash_region frba = { {0} }; +struct flash_master fmba = { {0} }; + +uint32_t getFCBA(void) +{ + return (fdbar.FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA(void) +{ + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA(void) +{ + return (fdbar.FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA(void) +{ + return (fdbar.FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA(void) +{ + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; +} + +/** Returns the integer representation of the component density with index +comp in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t comp) +{ + uint8_t size_enc; + const int dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(comp) { + case 0: + size_enc = fcba.comp1_density; + break; + case 1: + if (fdbar.NC == 0) + return 0; + size_enc = fcba.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d illegal or " + "unsupported. Encoded density is 0x%x.\n", comp, + size_enc); + return 0; + } + return dec_mem[size_enc]; +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA(void) +{ /* The bits in FLUMAP1 describe bits 4-11 out of 24 in total; + * others are 0. */ + return (flumap.FLUMAP1 << 4) & 0x0ff0; +} +#endif + +const struct flash_descriptor_addresses desc_addr = { + .FCBA = getFCBA, + .FRBA = getFRBA, + .FMBA = getFMBA, + .FMSBA = getFMSBA, + .FISBA = getFISBA, + .FLREG_limit = getFLREG_limit, + .FLREG_base = getFLREG_base, +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + .VTBA = getVTBA, +#endif +}; + +void prettyprint_ich_descriptors(enum chipset cs) +{ + prettyprint_ich_descriptor_map(); + prettyprint_ich_descriptor_component(); + prettyprint_ich_descriptor_region(); + prettyprint_ich_descriptor_master(); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(); + prettyprint_ich_descriptor_straps(cs); + } +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + msg_pdbg("\n"); +} + +void prettyprint_ich_descriptor_map(void) +{ + msg_pdbg("=== FDBAR ===\n"); + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); + msg_pdbg("\n"); + msg_pdbg("--- FDBAR details ---\n"); + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); +} + +void prettyprint_ich_descriptor_component(void) +{ + const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved/illegal", /* 010 */ + "reserved/illegal", /* 011 */ + "50 MHz", /* 100 */ + "reserved/illegal", /* 101 */ + "reserved/illegal", /* 110 */ + "reserved/illegal" /* 111 */ + }; + const char * const str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "undocumented/illegal", + "reserved/illegal" + }; + + msg_pdbg("\n"); + msg_pdbg("=== FCBA ===\n"); + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); + msg_pdbg("\n"); + msg_pdbg("--- FCBA details ---\n"); + msg_pdbg("0x%2.2x freq_read_id %s\n", + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); + msg_pdbg("0x%2.2x freq_write %s\n", + fcba.freq_write , str_freq[fcba.freq_write ]); + msg_pdbg("0x%2.2x freq_fastread %s\n", + fcba.freq_fastread, str_freq[fcba.freq_fastread]); + msg_pdbg("0x%2.2x fastread %ssupported\n", + fcba.fastread, fcba.fastread ? "" : "not "); + msg_pdbg("0x%2.2x freq_read %s\n", + fcba.freq_read, str_freq[fcba.freq_read ]); + msg_pdbg("0x%2.2x comp 1 density %s\n", + fcba.comp1_density, str_mem[fcba.comp1_density]); + if (fdbar.NC) + msg_pdbg("0x%2.2x comp 2 density %s\n", + fcba.comp2_density, str_mem[fcba.comp2_density]); + else + msg_pdbg("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", + fcba.comp2_density); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); +} + +void prettyprint_ich_descriptor_region(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FRBA ===\n"); + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); + msg_pdbg("\n"); + msg_pdbg("--- FRBA details ---\n"); + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); +} + +void prettyprint_ich_descriptor_master(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FMBA ===\n"); + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); + + msg_pdbg("\n"); + msg_pdbg("--- FMBA details ---\n"); + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); +} + +void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, BES, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void prettyprint_ich_descriptor_straps_ich8(void) +{ + const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg("\n"); + msg_pdbg("=== FISBA ===\n"); + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); + + msg_pdbg("\n"); + msg_pdbg("--- FISBA details ---\n"); + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg("\n"); + msg_pdbg("=== FMSBA ===\n"); + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); + + msg_pdbg("\n"); + msg_pdbg("--- FMSBA details ---\n"); + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); +} + +void prettyprint_ich_descriptor_straps_ibex(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FPSBA ===\n"); + for(i = 0; i <= 15; i++) + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); +} + +void prettyprint_ich_descriptor_straps(enum chipset cs) +{ + switch (cs) { + case CHIPSET_ICH8: + prettyprint_ich_descriptor_straps_ich8(); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + prettyprint_ich_descriptor_straps_ibex(); + break; + case CHIPSET_UNKNOWN: + break; + default: + msg_pdbg("\n"); + msg_pdbg("The meaning of the descriptor straps are unknown yet.\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FLUMAP ===\n"); + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); + + msg_pdbg("\n"); + msg_pdbg("--- FLUMAP details ---\n"); + msg_pdbg("VTL (length) = %d\n", flumap.VTL); + msg_pdbg("VTBA (base address) = 0x%6.6x\n", desc_addr.VTBA()); + msg_pdbg("\n"); + + for (i=0; i < flumap.VTL/2; i++) + { + uint32_t jid = flumap.vscc_table[i].JID; + uint32_t vscc = flumap.vscc_table[i].VSCC; + msg_pdbg(" JID%d = 0x%8.8x\n", i, jid); + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, vscc); + msg_pdbg(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg(" "); /* indention */ + prettyprint_ich9_reg_vscc(vscc); + } +} + +int read_ich_descriptors_from_dump(uint32_t *dump, enum chipset cs) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; + + /* region */ + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; + + /* master */ + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; + + /* upper map */ + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < flumap.VTL; i++) + { + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; + } + /* straps */ + /* FIXME: detect chipset correctly */ + switch (cs) { + case CHIPSET_ICH8: + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_from_fdo(void *spibar) +{ + msg_pdbg("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* descriptor map section */ + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); + fcba.FLILL = read_descriptor_reg(1, 1, spibar); + fcba.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* accessing strap section and upper map is impossible via FDOC/D(?) */ + msg_pdbg(" done\n"); +} + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..ca435f3 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,449 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +/* should probably be in ichspi.h */ +#define msg_pdbg2 msg_pspew + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +void prettyprint_ich9_reg_vscc(uint32_t reg_val); + +enum chipset { + CHIPSET_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_descriptor_addresses { + uint32_t (*FCBA)(void); + uint32_t (*FRBA)(void); + uint32_t (*FMBA)(void); + uint32_t (*FMSBA)(void); + uint32_t (*FLREG_limit)(uint32_t flreg); + uint32_t (*FLREG_base)(uint32_t flreg); + uint32_t (*FISBA)(void); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t (*VTBA)(void); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +}; + +struct flash_descriptor { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint8_t FCBA :8; + uint8_t NC :2; + unsigned :6; + uint8_t FRBA :8; + uint8_t NR :3; + unsigned :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint8_t FMBA :8; + uint8_t NM :3; + unsigned :5; + union { + uint8_t FISBA :8; + uint8_t FPSBA :8; + }; + uint8_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint8_t FMSBA :8; + uint8_t MSL :8; + unsigned :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint8_t comp1_density :3; + uint8_t comp2_density :3; + unsigned :11; + uint8_t freq_read :3; + uint8_t fastread :1; + uint8_t freq_fastread :3; + uint8_t freq_write :3; + uint8_t freq_read_id :3; + unsigned :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint8_t invalid_instr0; + uint8_t invalid_instr1; + uint8_t invalid_instr2; + uint8_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint16_t FPBA :13; + unsigned :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint16_t reg0_base :13; + unsigned :3; + uint16_t reg0_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint16_t reg1_base :13; + unsigned :3; + uint16_t reg1_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint16_t reg2_base :13; + unsigned :3; + uint16_t reg2_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint16_t reg3_base :13; + unsigned :3; + uint16_t reg3_limit :13; + unsigned :3; + }; + }; +} frba; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint16_t BIOS_req_ID :16; + uint8_t BIOS_descr_read :1; + uint8_t BIOS_BIOS_read :1; + uint8_t BIOS_ME_read :1; + uint8_t BIOS_GbE_read :1; + uint8_t BIOS_plat_read :1; + unsigned :3; + uint8_t BIOS_descr_write :1; + uint8_t BIOS_BIOS_write :1; + uint8_t BIOS_ME_write :1; + uint8_t BIOS_GbE_write :1; + uint8_t BIOS_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint16_t ME_req_ID :16; + uint8_t ME_descr_read :1; + uint8_t ME_BIOS_read :1; + uint8_t ME_ME_read :1; + uint8_t ME_GbE_read :1; + uint8_t ME_plat_read :1; + unsigned :3; + uint8_t ME_descr_write :1; + uint8_t ME_BIOS_write :1; + uint8_t ME_ME_write :1; + uint8_t ME_GbE_write :1; + uint8_t ME_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint16_t GbE_req_ID :16; + uint8_t GbE_descr_read :1; + uint8_t GbE_BIOS_read :1; + uint8_t GbE_ME_read :1; + uint8_t GbE_GbE_read :1; + uint8_t GbE_plat_read :1; + unsigned :3; + uint8_t GbE_descr_write :1; + uint8_t GbE_BIOS_write :1; + uint8_t GbE_ME_write :1; + uint8_t GbE_GbE_write :1; + uint8_t GbE_plat_write :1; + unsigned :3; + }; + }; +}; + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + struct { + union { + uint32_t STRP0; + struct { + uint8_t ME_DISABLE :1; + unsigned :6; + uint8_t TCOMODE :1; + uint8_t ASD :7; + uint8_t BMCMODE :1; + unsigned :3; + uint8_t GLAN_PCIE_SEL :1; + uint8_t GPIO12_SEL :2; + uint8_t SPICS1_LANPHYPC_SEL :1; + uint8_t MESM2SEL :1; + unsigned :1; + uint8_t ASD2 :7; + }; + }; + union { + uint32_t STRP1; + struct { + uint8_t ME_disable_B :1; + unsigned :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + union { + uint32_t STRP0; + struct { + unsigned :1; + uint8_t cs_ss2 :1; + unsigned :5; + uint8_t SMB_EN :1; + uint8_t SML0_EN :1; + uint8_t SML1_EN :1; + uint8_t SML1FRQ :2; + uint8_t SMB0FRQ :2; + uint8_t SML0FRQ :2; + unsigned :4; + uint8_t LANPHYPC_GP12_SEL :1; + uint8_t cs_ss1 :1; + unsigned :2; + uint8_t DMI_REQID_DIS :1; + unsigned :4; + uint8_t BBBS :2; + unsigned :1; + }; + }; + union { + uint32_t STRP1; + struct { + }; + }; + union { + uint32_t STRP2; + struct { + }; + }; + union { + uint32_t STRP3; + struct { + }; + }; + union { + uint32_t STRP4; + struct { + }; + }; + union { + uint32_t STRP5; + struct { + }; + }; + union { + uint32_t STRP6; + struct { + }; + }; + union { + uint32_t STRP7; + struct { + }; + }; + union { + uint32_t STRP8; + struct { + }; + }; + union { + uint32_t STRP9; + struct { + }; + }; + union { + uint32_t STRP10; + struct { + }; + }; + union { + uint32_t STRP11; + struct { + }; + }; + union { + uint32_t STRP12; + struct { + }; + }; + union { + uint32_t STRP13; + struct { + }; + }; + union { + uint32_t STRP14; + struct { + }; + }; + union { + uint32_t STRP15; + struct { + }; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint8_t VTBA :8; + uint8_t VTL :8; + unsigned :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + unsigned :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint8_t ubes :2; + uint8_t uwg :1; + uint8_t uwsr :1; + uint8_t uwews :1; + unsigned :3; + uint8_t ueo :8; + uint8_t lbes :2; + uint8_t lwg :1; + uint8_t lwsr :1; + uint8_t lwews :1; + unsigned :3; + uint16_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptors(enum chipset); + +void prettyprint_ich_descriptor_map(void); +void prettyprint_ich_descriptor_component(void); +void prettyprint_ich_descriptor_region(void); +void prettyprint_ich_descriptor_master(void); + +int getFCBA_component_density(uint8_t comp); + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptor_upper_map(void); +void prettyprint_ich_descriptor_straps(enum chipset cs); +int read_ich_descriptors_from_dump(uint32_t *dump, enum chipset cs); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void read_ich_descriptors_from_fdo(void *spibar); + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 905ed70..5783272 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,6 +42,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -131,6 +133,14 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same fields are also used in the + * flash descriptors to define the properties of the different flash chips + * supported by the BIOS image. These descriptors are also the source for the + * registers above. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -293,7 +303,7 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -313,8 +323,6 @@ static void pretty_print_opcodes(OPCODES *ops) } } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) - static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -678,7 +686,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -1210,6 +1218,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1281,6 +1290,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1329,9 +1340,25 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); + if (ichspi_desc) { + read_ich_descriptors_from_fdo(ich_spibar); + prettyprint_ich_descriptors(CHIPSET_UNKNOWN); + } ich_init_opcodes(); break; default: diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..0592b67 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain dump arrays +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to NOT share object files with flashrom, +# which would lead to unexpected results otherwise (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..a4fb1c8 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,271 @@ +/* + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + * + * */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "flash.h" +#include "ich_descriptors.h" + +extern struct flash_descriptor fdbar; +extern struct flash_component fcba; +extern struct flash_region frba; +extern struct flash_master fmba; +extern struct flash_strap fisba; +extern struct flash_upper_map flumap; +extern struct flash_descriptor_addresses desc_addr; + +void dump_file_descriptor(char *fn, uint32_t *fm) +{ + char * n = malloc(strlen(fn) + 11); + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); + if (ret != frba.reg0_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_BIOS(char *fn, uint32_t *fm) +{ + char * n = malloc(strlen(fn) + 10); + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); + if (ret != frba.reg1_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_ME(char *fn, uint32_t *fm) +{ + char * n = malloc(strlen(fn) + 8); + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); + if (ret != frba.reg2_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_GbE(char *fn, uint32_t *fm) +{ + char * n = malloc(strlen(fn) + 9); + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); + if (ret != frba.reg3_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + + close(fh); +} + +void dump_files(char *n, uint32_t *fm) +{ + printf("=== dumping section files ===\n"); + if (frba.reg0_limit) + dump_file_descriptor(n, fm); + if (frba.reg1_limit) + dump_file_BIOS(n, fm); + if (frba.reg2_limit) + dump_file_ME(n, fm); + if (frba.reg3_limit) + dump_file_GbE(n, fm); +} + +void usage(char *argv[], char *error) +{ + if (error != NULL) { + printf("%s\n", error); + printf("\n"); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some sections such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int f; /* file descriptor to flash file */ + unsigned int fs; /* file size */ + uint32_t *fm; /* mmap'd file */ + + int opt; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum chipset cs = CHIPSET_UNKNOWN; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + f = open(fn, O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image has a size of %d [0x%x] bytes.\n", fs, fs); + close(f); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_SERIES_5_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_SERIES_6_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_SERIES_7_PANTHER_POINT; + } + + if(read_ich_descriptors_from_dump(fm, cs)){ + printf("not in descriptor mode\n"); + exit(1); + } + + prettyprint_ich_descriptors(cs); + + if (dump == 1) + dump_files(argv[1], fm); + + return 0; +} + -- 1.7.1

1 0

[PATCH 1/3] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 01 Jul '11

01 Jul '11

- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions NB: this changes the semantic of the *run_opcode functions a bit: previously they could trash the chipset registers following the data registers because there was no (explicit) length check (it was and is checked by the dispatching run_opcode method). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 118 ++++++++++++++++++++++++++++++------------------------------- 1 files changed, 58 insertions(+), 60 deletions(-) diff --git a/ichspi.c b/ichspi.c index 19e52d2..905ed70 100644 --- a/ichspi.c +++ b/ichspi.c @@ -592,6 +592,57 @@ static void ich_set_bbar(uint32_t min_addr) msg_perr("Setting BBAR failed!\n"); } +/* Reads up to len byte from the fdata/spid register into the data array. + * The amount actually read is limited by the maximum read size of the + * chipset. */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int a; + uint32_t temp32 = 0; + + if (len > spi_programmer->max_data_read) + len = spi_programmer->max_data_read; + + for (a = 0; a < len; a++) { + if ((a % 4) == 0) + temp32 = REGREAD32(reg0_off + (a)); + + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) + >> ((a % 4) * 8); + } +} + +/* Fills up to len bytes from the data array into the fdata/spid registers. + * The amount actually written is limited by the maximum write size of the + * chipset and is returned by the function. */ +static uint8_t ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int a; + + if (len > spi_programmer->max_data_write) + len = spi_programmer->max_data_write; + + if (len <= 0) + return 0; + + for (a = 0; a < len; a++) { + if ((a % 4) == 0) { + temp32 = 0; + } + + temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); + + if ((a % 4) == 3) { + REGWRITE32(reg0_off + (a - (a % 4)), temp32); + } + } + if (((a - 1) % 4) != 3) { + REGWRITE32(reg0_off + ((a - 1) - ((a - 1) % 4)), temp32); + } + return len; +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -638,9 +689,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +714,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -765,15 +797,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, } if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } + ich_read_data(data, datalength, ICH7_REG_SPID0); } return 0; @@ -785,7 +809,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -917,15 +923,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } + ich_read_data(data, datalength, ICH9_REG_FDATA0); } return 0; -- 1.7.1

1 0

[PATCH 0/3] ichspi 6.1
by Stefan Tauner 01 Jul '11

01 Jul '11

we got rid of most of the support patches by committing them, yay. to ease review, everything left is tightly packed it in this sub-thread now. i have also changed the descriptor tool a bit. it now uses getopt and supports selecting the chipset with a command line switch. this changes the output of the soft straps and the upper map (the latter one is the database of flash chips that the ME supports). Stefan Tauner (3): ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding ichspi.c: add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 494 ++++++++++++++++++++++ ich_descriptors.h | 449 ++++++++++++++++++++ ichspi.c | 479 ++++++++++++++++++---- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 271 ++++++++++++ 11 files changed, 1698 insertions(+), 77 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

[PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. With this patch, you no longer have to edit the Makefile to compile the internal driver on MIPS/ARM/... TODO: arch.h is not suitable for inclusion in a .c/.h file because of its last line. Any ideas how to change that (move arch.h as "here document" into the Makefile, use other trickery like more #ifdefs)? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-target_arch/Makefile =================================================================== --- flashrom-target_arch/Makefile (Revision 1357) +++ flashrom-target_arch/Makefile (Arbeitskopie) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +ARCH = $(strip $(shell LC_ALL=C gcc -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -222,8 +225,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -418,6 +423,9 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @echo $(ARCH)|wc -l|grep -q ^1$ || ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Index: flashrom-target_arch/arch.h =================================================================== --- flashrom-target_arch/arch.h (Revision 0) +++ flashrom-target_arch/arch.h (Revision 0) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__ -- http://www.hailfinger.org/

5 9

Re: [flashrom] [PATCH 7/8] ichspi:c add support for Intel Hardware Sequencing
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > --- a/flashchips.c > +++ b/flashchips.c > @@ -8507,7 +8507,27 @@ const struct flashchip flashchips[] = { > .write = write_jedec_1, > .read = read_memmapped, > }, > - > +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > + { > + .vendor = "Intel", > + .name = "Hardware Sequencing", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = INTEL_ID, > + .model_id = INTEL_HWSEQ, > + .total_size = 0, > + .page_size = 256, > + .tested = TEST_OK_PREW, > + .probe = ich_hwseq_probe, > + .block_erasers = > + { > + { /* erase blocks will be set by the probing function */ > + .block_erase = ich_hwseq_block_erase, > + } > + }, > + .write = ich_hwseq_write_256, > + .read = ich_hwseq_read, > + }, > +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > { > .vendor = "AMIC", > .name = "unknown AMIC SPI chip", > I consider a chip called "Hardware Sequencing" to be a really evil thing. Hooking up a programmer with the help of a programmer-specific flash chip seems to be quite popular, and it was rejected each time and an alternative solution was found. That said, if probing for the real chip ID is impossible here and you only have read/write/erase primitives without any SPI access, this is essentially not a SPI bus chip, but a programmer-specific bus chip. The struct flashchip should probably look more like this: +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Unknown", + .name = "Abstract opaque chip", + .bustype = CHIP_BUSTYPE_ABSTRACT, + .manufacture_id = ABSTRACT_MANUF_ID, + .model_id = ABSTRACT_MODEL_ID, + .total_size = 0, + .page_size = 0, + .tested = TEST_OK_PREW, + .probe = abstract_probe, //abstract_probe points to programmer->abstract_probe which points to ich_hwseq_probe + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = abstract_erase, // points to programmer->abstract_erase which points to ich_hwseq_block_erase + } + }, + .write = ich_hwseq_write_256, Same abstract_ game as above. + .read = ich_hwseq_read, Dito. + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", Yes, the programmer struct would have to be extended for this, but at least that allows us to drive anything without having to care about the bus if we can't access the bus anyway. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 3/8] ichspi.c: add FPB (Flash Partition Boundary) macros and init printing
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > I think we really have to introduce a dbg2 level for messages and cut down on printing such stuff for -V. Until that happens, we can use dbg. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 2/8] ichspi.c: simplify ich_set_bbar
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > less code, documenting better what the differences are (i.e. offset of BBAR only). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Good code simplification. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 1/8] ichspi.c: make REGWRITE* macros safer
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > '+' does have a quite high precedence so "calling" those macros with a term including weaker > operators in the off parameter may have unexpected consequences > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Good find! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1362 - trunk
by repository service 01 Jul '11

01 Jul '11

Author: stefanct Date: Fri Jul 1 02:39:23 2011 New Revision: 1362 URL: http://flashrom.org/trac/flashrom/changeset/1362 Log: ichspi.c: preserve reserved bits in address registers Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 1 02:39:16 2011 (r1361) +++ trunk/ichspi.c Fri Jul 1 02:39:23 2011 (r1362) @@ -659,10 +659,11 @@ return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into SPIA while preserving reserved bits. */ + temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; + REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); - /* Program data into FDATA0 to N */ + /* Program data into SPID0 to N */ if (write_cmd && (datalength != 0)) { temp32 = 0; for (a = 0; a < datalength; a++) { @@ -803,8 +804,10 @@ return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into FADDR while preserve the reserved bits + * and clearing the 25. address bit which is only useable in hwseq. */ + temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ if (write_cmd && (datalength != 0)) {

1 0

[commit] r1361 - trunk
by repository service 01 Jul '11

01 Jul '11

Author: stefanct Date: Fri Jul 1 02:39:16 2011 New Revision: 1361 URL: http://flashrom.org/trac/flashrom/changeset/1361 Log: ichspi.c: add FPB (Flash Partition Boundary) macros and init printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 1 02:39:09 2011 (r1360) +++ trunk/ichspi.c Fri Jul 1 02:39:16 2011 (r1361) @@ -131,6 +131,10 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ +#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ +#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -1324,6 +1328,9 @@ ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_init_opcodes(); break; default:

1 0

[commit] r1360 - trunk
by repository service 01 Jul '11

01 Jul '11

Author: stefanct Date: Fri Jul 1 02:39:09 2011 New Revision: 1360 URL: http://flashrom.org/trac/flashrom/changeset/1360 Log: ichspi.c: simplify ich_set_bbar Less code, documenting better what the differences are (i.e. offset of BBAR only). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 1 02:39:01 2011 (r1359) +++ trunk/ichspi.c Fri Jul 1 02:39:09 2011 (r1360) @@ -555,43 +555,37 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(uint32_t min_addr) { - minaddr &= BBAR_MASK; + int bbar_off; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0x50); - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = 0x50; break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = ICH9_REG_BBAR; break; default: msg_perr("Unknown chipset for BBAR setting!\n"); - break; + return; + } + + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; + if (ichspi_bbar) { + msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", + ichspi_bbar); } + min_addr &= BBAR_MASK; + ichspi_bbar |= min_addr; + rmmio_writel(ichspi_bbar, ich_spibar + bbar_off); + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK; + + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ + if (ichspi_bbar != min_addr) + msg_perr("Setting BBAR failed!\n"); } /* This function generates OPCODES from or programs OPCODES to ICH according to

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[commit] r1359 - trunk
by repository service 01 Jul '11

01 Jul '11

Author: stefanct Date: Fri Jul 1 02:39:01 2011 New Revision: 1359 URL: http://flashrom.org/trac/flashrom/changeset/1359 Log: ichspi.c: make REGWRITE* macros safer '+' does have a quite high precedence so "calling" those macros with a term including weaker operators in the off parameter may have unexpected consequences. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 1 02:19:12 2011 (r1358) +++ trunk/ichspi.c Fri Jul 1 02:39:01 2011 (r1359) @@ -216,9 +216,9 @@ return mmio_readb(ich_spibar + X); } -#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off) -#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off) -#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off) +#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off)) +#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off)) +#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off)) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode);

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Re: [flashrom] [PATCH 2/3] add check_block_erasers which returns the number of well-defined erasers for a chip
by Carl-Daniel Hailfinger 01 Jul '11

01 Jul '11

Am 24.06.2011 16:53 schrieb Stefan Tauner: > This can be used in various situations (including one in the upcoming SFDP patch) and > removes one FIXME in current HEAD. Needed to move check_block_eraser (which checks a > single eraser) up to avoid (upcoming) forward declaration(s). > Since nobody objected to the "forward declarations" RFC, I think we can safely say that moving code around inside a file is a bad idea. Please kill that part. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flashrom.c | 70 ++++++++++++++++++++++++++++++++++------------------------- > 1 files changed, 40 insertions(+), 30 deletions(-) > > diff --git a/flashrom.c b/flashrom.c > index 6979d84..aed10aa 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ @@ > +/* Returns the number of well-defined erasers for a chip. > + * The log parameter controls output. */ > +static int check_block_erasers(const struct flashchip *flash, int log) > Hm. Can you call it count_usable_erasers or count_usable_block_erasers instead? > +{ > + int usable_erasefunctions = 0; > + int k; > + for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { > + if (!check_block_eraser(flash, k, 0)) > + usable_erasefunctions++; > + } > + return usable_erasefunctions; > +} > + > Rest looks good to me. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1358 - trunk
by repository service 01 Jul '11

01 Jul '11

Author: stefanct Date: Fri Jul 1 02:19:12 2011 New Revision: 1358 URL: http://flashrom.org/trac/flashrom/changeset/1358 Log: add count_usable_erasers which returns the number of well-defined erasers for a chip It solves one FIXME and consequentially allows to remove a later check right now, and is used in the upcoming SFDP patch. Adds a forward declaration of check_block_eraser. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jun 26 22:45:35 2011 (r1357) +++ trunk/flashrom.c Fri Jul 1 02:19:12 2011 (r1358) @@ -465,6 +465,8 @@ */ static int may_register_shutdown = 0; +static int check_block_eraser(const struct flashchip *flash, int k, int log); + /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will * be used as parameter to the registered function upon programmer shutdown. @@ -711,6 +713,19 @@ return extract_param(&programmer_param, param_name, ","); } +/* Returns the number of well-defined erasers for a chip. + * The log parameter controls output. */ +static unsigned int count_usable_erasers(const struct flashchip *flash, int log) +{ + unsigned int usable_erasefunctions = 0; + int k; + for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { + if (!check_block_eraser(flash, k, 0)) + usable_erasefunctions++; + } + return usable_erasefunctions; +} + /* start is an offset to the base address of the flash chip */ int check_erased_range(struct flashchip *flash, int start, int len) { @@ -1467,7 +1482,7 @@ return 0; } -static int check_block_eraser(struct flashchip *flash, int k, int log) +static int check_block_eraser(const struct flashchip *flash, int k, int log) { struct block_eraser eraser = flash->block_erasers[k]; @@ -1496,18 +1511,9 @@ int k, ret = 0; uint8_t *curcontents; unsigned long size = flash->total_size * 1024; - int usable_erasefunctions = 0; + unsigned int usable_erasefunctions = count_usable_erasers(flash, 0); - for (k = 0; k < NUM_ERASEFUNCTIONS; k++) - if (!check_block_eraser(flash, k, 0)) - usable_erasefunctions++; msg_cinfo("Erasing and writing flash chip... "); - if (!usable_erasefunctions) { - msg_cerr("ERROR: flashrom has no erase function for this flash " - "chip.\n"); - return 1; - } - curcontents = (uint8_t *) malloc(size); /* Copy oldcontents to curcontents to avoid clobbering oldcontents. */ memcpy(curcontents, oldcontents, size); @@ -1825,7 +1831,11 @@ return 1; msg_cerr("Continuing anyway.\n"); } - /* FIXME: Check if at least one erase function exists. */ + if(count_usable_erasers(flash, 0) == 0) { + msg_cerr("flashrom has no erase function for this " + "flash chip.\n"); + return 1; + } } if (write_it) { if (flash->tested & TEST_BAD_WRITE) {

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[PATCH 09/10] fixup! ichspi.c: refactor filling and reading the fdata/spid registers (was Re: [PATCH 5/8] ichspi.c: refactor filling and reading the fdata/spid registers)
by Stefan Tauner 01 Jul '11

01 Jul '11

On Wed, 29 Jun 2011 15:06:00 -0700 David Hendricks <dhendrix(a)google.com> wrote: > A couple quick comments in-line below... > > On Mon, Jun 27, 2011 at 8:33 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > > > + static void ich_read_data(uint8_t *data, uint8_t len, int reg0_off) > > + { > > + int a; > > + uint32_t temp32 = 0; > > + > > + if (len > spi_programmer->max_data_read) > > + len = spi_programmer->max_data_read; > > + > > + for (a = 0; a < len; a++) { > > + if ((a % 4) == 0) > > + temp32 = REGREAD32(reg0_off + (a)); > > + > > + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > > + >> ((a % 4) * 8); > > > > How about "data[a] = (temp32 >> ((a % 4) * 8)) & 0xff" instead? That is > clearer IMHO, and you won't even need to break the line. (80 columns really > *is* enough :-P) i just copied the existing code from swseq and did not change it at all on purpose. improvements are welcome... the code certainly is not very readable. i wonder if this is due to some compiler optimization friendly style... but changes should be in their on commit though anyway and so we can postpone it. > On Mon, Jun 27, 2011 at 8:33 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > +static uint8_t ich_fill_data(const uint8_t *data, uint8_t len, int > > reg0_off) > > > As mentioned on IRC, the caller tends to pass in a "len" value > 255, e.g. 1 > block of 4096 bytes or more. Since len is handled as an int in the caller, > it should probably get passed in as an int here. inderdaad. i would have expected the compiler to warn in such cases. obviously i am too used to my usual embedded makefile with ~20 -W terms :) please see 9/10 and 10/10 for my proposed fixes of this (and other problems like the possibility of setting SME ) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Flashrom as a payload with usb flash drive support
by Tadas Slotkus 01 Jul '11

01 Jul '11

Hi, this is for testing. Works for me with seabios. First optimize coreboot for your board, to get some space (remove microcode updates or sth, we need about 60 KB). Sorry haven't checked latest libpayload changes, so something might not work. I will write a blog post about this tomorrow. Thanks, Tadas Slotkus

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msi-E350IA-E45 e-350 amd cpu
by Fabio Semino 30 Jun '11

30 Jun '11

Erase and write ok with 1.50 bios, i'm attaching the output of the operation. Nice piece of software guys Fabio from Italy

3 3

[patch] typo fix
by Mark Johnston 30 Jun '11

30 Jun '11

Fixed a small typo in an output message. Signed-off-by: Mark Johnston <markjdb at gmail.com> --- Index: dmi.c =================================================================== --- dmi.c (revision 1357) +++ dmi.c (working copy) @@ -119,7 +119,7 @@ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - msg_pinfo("dmidecode execution unsucessfull - continuing " + msg_pinfo("dmidecode execution unsuccessful - continuing " "without DMI info\n"); return NULL; }

2 2

Asus E35M1-I Deluxe / Winbond W25Q32
by Mattias Mattsson 30 Jun '11

30 Jun '11

Hi, I have tested flashrom r1349 on an Asus E35M1-I Deluxe rev. 1.01 (revision silk-screened on PCB) board with a Winbond W25Q32 flash chip. Probe, read, erase and write all work. Logs attached. Details for the flash part: Winbond 25Q32BVAIG 1114 This MB has an ITE IT8771E Super I/O chip (currently not fully detected by superiotool). I have confirmed the part number by visual inspection (it is not visible on photos because it is located under the heat sink). This chip seems to be specially made for Asus: http://vip.asus.com/forum/view.aspx?id=20110319032211863#20110327052243133 (Just like IT8707F..) Another interesting thing with this board is that it has a 5-pin debug port with unknown pinout. I have checked with a meter and none of the pins (except ground) are directly connected to the flash chip. Thanks, -mattias

2 2

Re: [flashrom] [Patch] Add support for EN25Q series SPI flash chips
by Carl-Daniel Hailfinger 30 Jun '11

30 Jun '11

Am 23.06.2011 01:04 schrieb David Hendricks: > I'm still not sure what the best course of action is for dealing with the > D16 versus Q16 evil twin scenario. Let's see if Carl-Daniel has further > comments. > > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > As we discussed on IRC, this particular chip supports "Serial Flash > Discoverable Parameters" (SFDP). I tried to add support using the values > listed in Table 9 of their datasheet, and left a TODO to update the probe > routine later on. > Ah yes, SFDP. Stefan has implemented a patch to support that in the meantime. > On Wed, Jun 22, 2011 at 9:15 AM, Stefan Tauner wrote: >> somewhere below... >> +#define EON_EN25QH16 0x7015 > > Done. I rearranged the EN25Q* #defines a bit so they're in alphabetical > order with respect to the other EN25* chips. > > > >>> Index: flashchips.c >>> =================================================================== >>> --- flashchips.c (revision 1285) >>> +++ flashchips.c (working copy) >>> @@ -2807,6 +2807,8 @@ >>> }, >>> >>> { >>> + /* Note: EN25Q16 is an evil twin which shares the model ID >>> + but has different write protection capabilities */ >>> .vendor = "Eon", >>> .name = "EN25D16", >>> >> change according to the macro name chosen (if applicable see above) >> > The EN25D16 was there first... I'm not sure if we should change it. I > imagine the D16 is out of production, but I assume *somebody* is using it. > > WWCDD? (What Would Carl-Daniel Do?) > Evil twins... I have a patch for that: http://patchwork.coreboot.org/patch/1861/ The rules are simple: If two chips are identical from a flashrom POV (same command set and write/erase characteristics), combine them into one entry. If those chips differ, give them two entries and mark them as evil twins. Differing write protection is a corner case... we don't really have a good write protection handling in flashrom (yet), and until one of the four suggested/implemented designs is chosen, this is difficult to handle. Is there a way to probe for the write protection capabilities? Side note: Probing could be a bit more intelligent for the case of almost-identical chips. It could calculate the greatest common command set and offer to use that merging result. Other tricks are possible as well. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] flashrom: fix typos in comments
by Peter Huewe 30 Jun '11

30 Jun '11

This patch fixes some common misspellings/typos in comments. Changes generated using codespell and reviewed manually lenght->length 2 ocassional->occasional 1 unsucessfull->unsuccessful 1 upto->up to 5 Signed-off-by: Peter Huewe <peterhuewe(a)gmx.de> --- buspirate_spi.c | 2 +- dmi.c | 2 +- serprog-protocol.txt | 2 +- serprog.c | 10 +++++----- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index 3b9f487..f872309 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -203,7 +203,7 @@ int buspirate_spi_init(void) * sufficient either. Use a 1.5 ms delay inside the loop to make * mostly sure that at least one USB frame had time to arrive. * Looping only 5 times is not sufficient and causes the - * ocassional failure. + * occasional failure. * Folding the delay into the loop above is not reliable either. */ for (i = 0; i < 10; i++) { diff --git a/dmi.c b/dmi.c index cda6656..836b38b 100644 --- a/dmi.c +++ b/dmi.c @@ -119,7 +119,7 @@ static char *get_dmi_string(const char *string_name) while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - msg_pinfo("dmidecode execution unsucessfull - continuing " + msg_pinfo("dmidecode execution unsuccessful - continuing " "without DMI info\n"); return NULL; } diff --git a/serprog-protocol.txt b/serprog-protocol.txt index c5464a4..52f901a 100644 --- a/serprog-protocol.txt +++ b/serprog-protocol.txt @@ -88,7 +88,7 @@ This define listing should help C coders - (it's here to be the single source fo #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ diff --git a/serprog.c b/serprog.c index b91e376..124aa41 100644 --- a/serprog.c +++ b/serprog.c @@ -56,7 +56,7 @@ static int serprog_shutdown(void *data); #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ @@ -168,9 +168,9 @@ static void sp_synchronize(void) usleep(1000 * 1000); sp_flush_incoming(); - /* Then try upto 8 times to send syncnop and get the correct special * - * return of NAK+ACK. Timing note: upto 10 characters, 10*50ms = * - * upto 500ms per try, 8*0.5s = 4s; +1s (above) = upto 5s sync * + /* Then try up to 8 times to send syncnop and get the correct special * + * return of NAK+ACK. Timing note: up to 10 characters, 10*50ms = * + * up to 500ms per try, 8*0.5s = 4s; +1s (above) = up to 5s sync * * attempt, ~1s if immediate success. */ for (i = 0; i < 8; i++) { int n; @@ -180,7 +180,7 @@ static void sp_synchronize(void) msg_pdbg("."); fflush(stdout); for (n = 0; n < 10; n++) { - c = sp_sync_read_timeout(5); /* wait upto 50ms */ + c = sp_sync_read_timeout(5); /* wait up to 50ms */ if (c != S_NAK) continue; c = sp_sync_read_timeout(2); -- 1.7.3.4

2 1

[PATCH 10/10] fixup! ichspi.c: add support for Intel Hardware Sequencing (was Re: [PATCH 8/8] squash! ichspi:c add support for Intel Hardware Sequencing)
by Stefan Tauner 30 Jun '11

30 Jun '11

the missing "& HSFC_FDBC" there makes it possible to enable smm interrupts as happened to dhendrix. lesson to learn: always check/limit input values even if they were previously constants ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH 5/8] ichspi.c: refactor filling and reading the fdata/spid registers
by David Hendricks 30 Jun '11

30 Jun '11

A couple quick comments in-line below... On Mon, Jun 27, 2011 at 8:33 PM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > > + static void ich_read_data(uint8_t *data, uint8_t len, int reg0_off) > + { > + int a; > + uint32_t temp32 = 0; > + > + if (len > spi_programmer->max_data_read) > + len = spi_programmer->max_data_read; > + > + for (a = 0; a < len; a++) { > + if ((a % 4) == 0) > + temp32 = REGREAD32(reg0_off + (a)); > + > + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > + >> ((a % 4) * 8); > How about "data[a] = (temp32 >> ((a % 4) * 8)) & 0xff" instead? That is clearer IMHO, and you won't even need to break the line. (80 columns really *is* enough :-P) On Mon, Jun 27, 2011 at 8:33 PM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > +static uint8_t ich_fill_data(const uint8_t *data, uint8_t len, int > reg0_off) As mentioned on IRC, the caller tends to pass in a "len" value > 255, e.g. 1 block of 4096 bytes or more. Since len is handled as an int in the caller, it should probably get passed in as an int here. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

Re: [flashrom] [PATCH] Macronix MX25L6445E
by Wagner, Helge (GE Intelligent Platforms) 29 Jun '11

29 Jun '11

Sending once again 'cause my outlook introduced many extra line breaks in the patch. Now I am attaching it. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> Regards, Helge -----Original Message----- From: flashrom-bounces(a)flashrom.org [mailto:flashrom-bounces@flashrom.org] On Behalf Of Wagner, Helge (GE Intelligent Platforms) Sent: Mittwoch, 29. Juni 2011 15:56 To: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] Macronix MX25L6445E Hello all, i have now re-worked my patch. This is the full description of the complete patch: -Fixed spi_block_erase_d8() block size for MX25L3205 was wrong. -Now using spi_block_erase_20_4or64k() erase function instead of spi_block_erase_20() which can handle both 4KB and 64KB block sizes for those flash chips that might have same id but different erase block sizes. -New probe function added (probe_spi_mx_2017()) to differentiate MX25L6445E and MX25L6405. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> I have also included log files for the MX25L6445E. Regards, Helge Wagner diff -u flashrom/chipdrivers.h flashrom-patched/chipdrivers.h --- flashrom/chipdrivers.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/chipdrivers.h 2011-06-28 14:38:54.000000000 +0200 @@ -31,9 +31,11 @@ int probe_spi_rems(struct flashchip *flash); int probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct flashchip *flash); +int probe_spi_mx_2017(struct flashchip *flash); int spi_write_enable(void); int spi_write_disable(void); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4or64k(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); diff -u flashrom/flashchips.c flashrom-patched/flashchips.c --- flashrom/flashchips.c 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/flashchips.c 2011-06-29 13:22:51.000000000 +0200 @@ -3959,14 +3959,14 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_20_4or64k, /* This erase function has 64k blocksize for eLiteFlash */ }, { .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ .block_erase = spi_block_erase_52, @@ -4063,16 +4063,16 @@ .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 1024} }, - .block_erase = spi_block_erase_20, + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_20_4or64k, }, { - .eraseblocks = { {4 * 1024, 1024} }, + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, @@ -4132,12 +4132,46 @@ .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PROBE, - .probe = probe_spi_rdid, + .probe = probe_spi_mx_2017, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_20_4or64k, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L6445E", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6445E, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_mx_2017, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {64 * 1024, 128} }, diff -u flashrom/flashchips.h flashrom-patched/flashchips.h --- flashrom/flashchips.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/flashchips.h 2011-06-28 16:24:07.000000000 +0200 @@ -356,7 +356,8 @@ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6406E */ +#define MACRONIX_MX25L6445E 0x16 /* MX25L6445E, MX25L6405D ID = REMS2 answer */ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ diff -u flashrom/spi.h flashrom-patched/spi.h --- flashrom/spi.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/spi.h 2011-06-29 13:32:55.000000000 +0200 @@ -40,6 +40,21 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Electronic Manufacturer Signature for 2x I/O mode */ +#define JEDEC_REMS2 0xef +#define JEDEC_REMS2_OUTSIZE 0x04 +#define JEDEC_REMS2_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature for 4x I/O mode */ +#define JEDEC_REMS4 0xdf +#define JEDEC_REMS4_OUTSIZE 0x04 +#define JEDEC_REMS4_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature for 4x I/O DT mode */ +#define JEDEC_REMS4D 0xcf +#define JEDEC_REMS4D_OUTSIZE 0x04 +#define JEDEC_REMS4D_INSIZE 0x02 + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff -u flashrom/spi25.c flashrom-patched/spi25.c --- flashrom/spi25.c 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/spi25.c 2011-06-29 13:09:59.000000000 +0200 @@ -22,6 +22,7 @@ * Contains the common SPI chip driver functions */ +#include <stdlib.h> #include <string.h> #include "flash.h" #include "flashchips.h" @@ -66,6 +67,27 @@ return 0; } +static int spi_rems2(unsigned char *readarr) { + unsigned char cmd[JEDEC_REMS2_OUTSIZE] = { JEDEC_REMS2, 0, 0, 0 }; + uint32_t readaddr; + int ret; + + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); + if (ret == SPI_INVALID_ADDRESS) { + /* Find the lowest even address allowed for reads. */ + readaddr = (spi_get_valid_read_addr() + 1) & ~1; + cmd[1] = (readaddr >> 16) & 0xff, + cmd[2] = (readaddr >> 8) & 0xff, + cmd[3] = (readaddr >> 0) & 0xff, + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); + } + if (ret) + return ret; + msg_cspew("REMS2 returned %02x %02x. ", readarr[0], readarr[1]); + return 0; +} + static int spi_res(unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; @@ -173,6 +195,58 @@ return probe_spi_rdid_generic(flash, 3); } +int probe_spi_mx_2017(struct flashchip *flash) { + unsigned char readarr[4]; + uint32_t id1; + uint32_t id2; + uint32_t id3; + uint32_t id4; + + if (spi_rdid(readarr, 3)) { + msg_cdbg("\n"); + return 0; + } + id1 = readarr[0]; + id2 = (readarr[1] << 8) | readarr[2]; + + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6405) { + /* Now we have detected the 2017h class of Macronix flash devices. + * We can further differentiate two classes: + * -those who support the REMS2 function do always have 4KB sector size + * (at least i have not found one with 64KB yet), + * and + * -those who don't support the REMS2 function might have 4KB or 64KB + * (some have 4KB, e.g. MX25L6406E, some have 64KB, e.g. MX25L6405 (not D)) + * for erase function 20h. + */ + if (spi_rems2(readarr)) { + msg_cdbg("\n"); + return 0; + } + id3 = readarr[0]; + id4 = readarr[1]; + msg_cdbg("%s: id1 0x%02x, id2 0x%02x, id3 0x%02x, id4 0x%02x\n", __func__, id1, id2, id3, id4); + if (id3 == MACRONIX_ID && id4 == MACRONIX_MX25L6445E) { + /* MACRONIX_MX25L6445E class, always 4KB sector */ + if (flash->model_id == MACRONIX_MX25L6445E) + return 1; + else + return 0; + } else { + /* MACRONIX_MX25L6405 class, might have 4KB or 64KB sector */ + if (flash->model_id == MACRONIX_MX25L6405) + return 1; + else + return 0; + } + } else { + msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); + } + /* neither MACRONIX_MX25L6405 nor MACRONIX_MX25L6445E */ + return 0; +} + int probe_spi_rdid4(struct flashchip *flash) { /* Some SPI controllers do not support commands with writecnt=1 and @@ -694,6 +768,79 @@ return 0; } +/* Sector size might be 4KB or 64KB, but on call to this function this is unknown. + * So we do a first erase command and then check if mem in the complete 64KB sector is erased. + * If not we assume 4KB and so we repeat the erase for each 4KB sector in the 64KB block + * (which is not erased already). + * PLEASE NOTE: the .eraseblocks block size must be set to 64KB if you use this function. + */ +int spi_block_erase_20_4or64k(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result, i, j, fully_erased, sector_erased; + unsigned int curraddr, currblocklen; + uint8_t *readbuf; + + if (blocklen != (64 * 1024)) { + msg_gerr("%s: blocklen not 64KB! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + readbuf = malloc(blocklen); + if (!readbuf) { + msg_gerr("Out of memory!\n"); + exit(1); + } + + for (i = 0; i < 16; i++) { /* there are 16 4KB sectors in 64KB */ + + curraddr = addr + (i * (4 * 1024)); + + if (i > 0) { + /* Skip the sector erase if the sector is already erased */ + sector_erased = 1; + result = flash->read(flash, readbuf, curraddr, (4 * 1024)); + if (result) { + msg_gerr("Erase impossible because read failed " + "at 0x%x (len 0x%x)\n", curraddr, (4 * 1024)); + break; + } + for (j = 0; j < currblocklen; j++) + if (readbuf[j] != 0xFF) + sector_erased = 0; + if (sector_erased) + continue; /* Sector is already erased */ + } + + result = spi_block_erase_20 (flash, curraddr, (4 * 1024)); /* last parameter (blocklen) is unused */ + if (result) break; + + if (0 == i) { + curraddr += 4 * 1024; + currblocklen = (64*1024)-(4*1024); + fully_erased = 1; + result = flash->read(flash, readbuf, curraddr, currblocklen); + if (result) { + msg_gerr("Erase impossible because read failed " + "at 0x%x (len 0x%x)\n", curraddr, currblocklen); + break; + } + for (j = 0; j < currblocklen; j++) + if (readbuf[j] != 0xFF) + fully_erased = 0; + if (fully_erased) { + /* This means either that the SE command has erased the full 64KB + * or that the remaining 64KB sector was already erased before. + * Anyhow, we can now exit without calling the SE command again. + */ + break; + } + } + } + free(readbuf); + return result; +} + int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { -----Original Message----- From: flashrom-bounces(a)flashrom.org [mailto:flashrom-bounces@flashrom.org] On Behalf Of Wagner, Helge (GE Intelligent Platforms) Sent: Mittwoch, 29. Juni 2011 13:57 To: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] Macronix MX25L6445E Hello all, as Stefan suggested ("what about 0x2015, 0x2016, 0x2018? do they also have such problems?"), I was looking at some more Macronix data sheets. While doing this, I found out that my solution is NOT sufficient for some of the Macronix 0x2017 flash chips. I am currently working on a solution for this problem. Please stand by. Regards, Helge -----Original Message----- From: flashrom-bounces+helge.wagner=ge.com(a)flashrom.org [mailto:flashrom-bounces+helge.wagner=ge.com@flashrom.org] On Behalf Of Carl-Daniel Hailfinger Sent: Montag, 27. Juni 2011 20:28 To: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] Macronix MX25L6445E Hello Helge, thanks for your patch. It looks good to me on a first glance, and I hope to review it in detail soon. A short comment (in reply to Stefan's review) is at the end of this mail. Am 27.06.2011 17:50 schrieb Stefan Tauner: > On Mon, 27 Jun 2011 17:06:42 +0200 > "Wagner, Helge (GE Intelligent Platforms)" <Helge.Wagner(a)ge.com> wrote: > > >> Hello Stefan, >> >> >>> i have not looked at the datasheet(s), but maybe there is a way to distinguish the two devices (with another id command for example)? >>> >> I have asked Macronix, and they suggest to use the REMS2 function, which is supported on the MX25L6445E (returns 0xC216) and is not supported on the MX25L6405 (according to Macronix, it returns 0x0000 or 0xFFFF for this command). >> >> So now there is no longer a need to re-order the erase functions for the MX25L6405. >> >> Here is my new patch. >> >> Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> >> >> Regards, >> Helge Wagner >> >> diff -u flashrom/chipdrivers.h flashrom-patched/chipdrivers.h >> --- flashrom/chipdrivers.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/chipdrivers.h 2011-06-27 16:29:25.000000000 +0200 >> @@ -31,6 +31,7 @@ >> int probe_spi_rems(struct flashchip *flash); int >> probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct >> flashchip *flash); >> +int probe_spi_mx_2017(struct flashchip *flash); >> int spi_write_enable(void); >> int spi_write_disable(void); >> int spi_block_erase_20(struct flashchip *flash, unsigned int addr, >> unsigned int blocklen); diff -u flashrom/flashchips.c flashrom-patched/flashchips.c >> --- flashrom/flashchips.c 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/flashchips.c 2011-06-27 16:26:34.000000000 +0200 >> @@ -4131,8 +4131,8 @@ >> .total_size = 8192, >> .page_size = 256, >> .feature_bits = FEATURE_WRSR_WREN, >> - .tested = TEST_OK_PROBE, >> - .probe = probe_spi_rdid, >> + .tested = TEST_UNTESTED, >> + .probe = probe_spi_mx_2017, >> .probe_timing = TIMING_ZERO, >> .block_erasers = >> { >> @@ -4141,6 +4141,40 @@ >> .block_erase = spi_block_erase_20, >> }, { >> .eraseblocks = { {64 * 1024, 128} }, >> + .block_erase = spi_block_erase_d8, >> + }, { >> + .eraseblocks = { {8 * 1024 * 1024, 1} }, >> + .block_erase = spi_block_erase_60, >> + }, { >> + .eraseblocks = { {8 * 1024 * 1024, 1} }, >> + .block_erase = spi_block_erase_c7, >> + } >> + }, >> + .unlock = spi_disable_blockprotect, >> + .write = spi_chip_write_256, >> + .read = spi_chip_read, >> + .voltage = {2700, 3600}, >> + }, >> + >> + { >> + .vendor = "Macronix", >> + .name = "MX25L6445E", >> + .bustype = CHIP_BUSTYPE_SPI, >> + .manufacture_id = MACRONIX_ID, >> + .model_id = MACRONIX_MX25L6445E, >> + .total_size = 8192, >> + .page_size = 256, >> + .feature_bits = FEATURE_WRSR_WREN, >> + .tested = TEST_OK_PREW, >> + .probe = probe_spi_mx_2017, >> + .probe_timing = TIMING_ZERO, >> + .block_erasers = >> + { >> + { >> + .eraseblocks = { {4 * 1024, 2048} }, >> + .block_erase = spi_block_erase_20, >> + }, { >> + .eraseblocks = { {64 * 1024, 128} }, >> .block_erase = spi_block_erase_d8, >> }, { >> .eraseblocks = { {8 * 1024 * 1024, 1} }, diff -u >> flashrom/flashchips.h flashrom-patched/flashchips.h >> --- flashrom/flashchips.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/flashchips.h 2011-06-27 15:46:22.000000000 +0200 >> @@ -356,7 +356,8 @@ >> #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ >> #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ >> #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ >> -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ >> +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D} */ >> +#define MACRONIX_MX25L6445E 0x16 /* MX25L6445E, ID = REMS2 answer */ >> #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ >> #define MACRONIX_MX25L1635D 0x2415 >> #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ >> diff -u flashrom/spi.h flashrom-patched/spi.h >> --- flashrom/spi.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/spi.h 2011-06-27 16:29:38.000000000 +0200 >> @@ -40,6 +40,11 @@ >> #define JEDEC_REMS_OUTSIZE 0x04 >> #define JEDEC_REMS_INSIZE 0x02 >> >> +/* Read Electronic Manufacturer Signature 2 */ >> +#define JEDEC_REMS2 0xEF >> +#define JEDEC_REMS2_OUTSIZE 0x04 >> +#define JEDEC_REMS2_INSIZE 0x02 >> + >> /* Read Electronic Signature */ >> #define JEDEC_RES 0xab >> #define JEDEC_RES_OUTSIZE 0x04 >> diff -u flashrom/spi25.c flashrom-patched/spi25.c >> --- flashrom/spi25.c 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/spi25.c 2011-06-27 16:30:33.000000000 +0200 >> @@ -66,6 +66,27 @@ >> return 0; >> } >> >> +static int spi_rems2(unsigned char *readarr) { >> + unsigned char cmd[JEDEC_REMS2_OUTSIZE] = { JEDEC_REMS2, 0, 0, 0 }; >> + uint32_t readaddr; >> + int ret; >> + >> + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); >> + if (ret == SPI_INVALID_ADDRESS) { >> + /* Find the lowest even address allowed for reads. */ >> + readaddr = (spi_get_valid_read_addr() + 1) & ~1; >> + cmd[1] = (readaddr >> 16) & 0xff, >> + cmd[2] = (readaddr >> 8) & 0xff, >> + cmd[3] = (readaddr >> 0) & 0xff, >> + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); >> + } >> + if (ret) >> + return ret; >> + msg_cspew("REMS2 returned %02x %02x. ", readarr[0], readarr[1]); >> + return 0; >> +} >> + >> static int spi_res(unsigned char *readarr, int bytes) { >> unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; @@ >> -173,6 +194,49 @@ >> return probe_spi_rdid_generic(flash, 3); } >> >> +int probe_spi_mx_2017(struct flashchip *flash) { >> + unsigned char readarr[4]; >> + uint32_t id1; >> + uint32_t id2; >> + >> + if (spi_rdid(readarr, 3)) { >> + msg_cdbg("\n"); >> + return 0; >> + } >> + id1 = readarr[0]; >> + id2 = (readarr[1] << 8) | readarr[2]; >> + >> + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6405) { >> + /* We have either MACRONIX_MX25L6405 or MACRONIX_MX25L6445E. >> + * MACRONIX_MX25L6405 has 64KB for erase function 20h and does not support REMS2 function, >> + * MACRONIX_MX25L6445E has 4KB for erase function 20h and does support REMS2 function. >> + * So to differentiate both, we execute REMS2 function (this is suggested by macronix). >> + */ >> + if (spi_rems2(readarr)) { >> + msg_cdbg("\n"); >> + return 0; >> + } >> + id1 = readarr[0]; >> + id2 = readarr[1]; >> + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6445E) { >> + /* MACRONIX_MX25L6445E */ >> + if (flash->model_id == MACRONIX_MX25L6445E) >> + return 1; >> + else >> + return 0; >> + } else { >> + /* MACRONIX_MX25L6405 */ >> + if (flash->model_id == MACRONIX_MX25L6405) >> + return 1; >> + else >> + return 0; >> + } >> + } >> + /* neither MACRONIX_MX25L6405 nor MACRONIX_MX25L6445E */ >> + return 0; >> +} >> + >> int probe_spi_rdid4(struct flashchip *flash) { >> /* Some SPI controllers do not support commands with writecnt=1 and >> >> >> > hello again and thanks for all you have done. > > without looking at your patch in too much detail i would like to > mention another possibility to implement this. as i have done in my > sfdp and intel hardware sequencing patch you can alter the struct > flashchip *flash the probing function gets as parameter. > you can then change the erase block size (and name) according to the id > instead of using two chips and returning 0/1 respectively. > Please avoid changing struct flashchip *flash in the probe function unless it is absolutely necessary. The hack needed for SFDP should not spread elsewhere, especially if we can handle this nicely with two separate flashchip entries. Regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list flashrom(a)flashrom.org http://www.flashrom.org/mailman/listinfo/flashrom _______________________________________________ flashrom mailing list flashrom(a)flashrom.org http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] [PATCH] Macronix MX25L6445E
by Wagner, Helge (GE Intelligent Platforms) 29 Jun '11

29 Jun '11

Hello all, i have now re-worked my patch. This is the full description of the complete patch: -Fixed spi_block_erase_d8() block size for MX25L3205 was wrong. -Now using spi_block_erase_20_4or64k() erase function instead of spi_block_erase_20() which can handle both 4KB and 64KB block sizes for those flash chips that might have same id but different erase block sizes. -New probe function added (probe_spi_mx_2017()) to differentiate MX25L6445E and MX25L6405. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> I have also included log files for the MX25L6445E. Regards, Helge Wagner diff -u flashrom/chipdrivers.h flashrom-patched/chipdrivers.h --- flashrom/chipdrivers.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/chipdrivers.h 2011-06-28 14:38:54.000000000 +0200 @@ -31,9 +31,11 @@ int probe_spi_rems(struct flashchip *flash); int probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct flashchip *flash); +int probe_spi_mx_2017(struct flashchip *flash); int spi_write_enable(void); int spi_write_disable(void); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4or64k(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); diff -u flashrom/flashchips.c flashrom-patched/flashchips.c --- flashrom/flashchips.c 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/flashchips.c 2011-06-29 13:22:51.000000000 +0200 @@ -3959,14 +3959,14 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_20_4or64k, /* This erase function has 64k blocksize for eLiteFlash */ }, { .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ .block_erase = spi_block_erase_52, @@ -4063,16 +4063,16 @@ .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 1024} }, - .block_erase = spi_block_erase_20, + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_20_4or64k, }, { - .eraseblocks = { {4 * 1024, 1024} }, + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, @@ -4132,12 +4132,46 @@ .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PROBE, - .probe = probe_spi_rdid, + .probe = probe_spi_mx_2017, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_20_4or64k, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L6445E", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6445E, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_mx_2017, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {64 * 1024, 128} }, diff -u flashrom/flashchips.h flashrom-patched/flashchips.h --- flashrom/flashchips.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/flashchips.h 2011-06-28 16:24:07.000000000 +0200 @@ -356,7 +356,8 @@ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6406E */ +#define MACRONIX_MX25L6445E 0x16 /* MX25L6445E, MX25L6405D ID = REMS2 answer */ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ diff -u flashrom/spi.h flashrom-patched/spi.h --- flashrom/spi.h 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/spi.h 2011-06-29 13:32:55.000000000 +0200 @@ -40,6 +40,21 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Electronic Manufacturer Signature for 2x I/O mode */ +#define JEDEC_REMS2 0xef +#define JEDEC_REMS2_OUTSIZE 0x04 +#define JEDEC_REMS2_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature for 4x I/O mode */ +#define JEDEC_REMS4 0xdf +#define JEDEC_REMS4_OUTSIZE 0x04 +#define JEDEC_REMS4_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature for 4x I/O DT mode */ +#define JEDEC_REMS4D 0xcf +#define JEDEC_REMS4D_OUTSIZE 0x04 +#define JEDEC_REMS4D_INSIZE 0x02 + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff -u flashrom/spi25.c flashrom-patched/spi25.c --- flashrom/spi25.c 2011-06-27 15:21:57.000000000 +0200 +++ flashrom-patched/spi25.c 2011-06-29 13:09:59.000000000 +0200 @@ -22,6 +22,7 @@ * Contains the common SPI chip driver functions */ +#include <stdlib.h> #include <string.h> #include "flash.h" #include "flashchips.h" @@ -66,6 +67,27 @@ return 0; } +static int spi_rems2(unsigned char *readarr) +{ + unsigned char cmd[JEDEC_REMS2_OUTSIZE] = { JEDEC_REMS2, 0, 0, 0 }; + uint32_t readaddr; + int ret; + + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); + if (ret == SPI_INVALID_ADDRESS) { + /* Find the lowest even address allowed for reads. */ + readaddr = (spi_get_valid_read_addr() + 1) & ~1; + cmd[1] = (readaddr >> 16) & 0xff, + cmd[2] = (readaddr >> 8) & 0xff, + cmd[3] = (readaddr >> 0) & 0xff, + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); + } + if (ret) + return ret; + msg_cspew("REMS2 returned %02x %02x. ", readarr[0], readarr[1]); + return 0; +} + static int spi_res(unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; @@ -173,6 +195,58 @@ return probe_spi_rdid_generic(flash, 3); } +int probe_spi_mx_2017(struct flashchip *flash) +{ + unsigned char readarr[4]; + uint32_t id1; + uint32_t id2; + uint32_t id3; + uint32_t id4; + + if (spi_rdid(readarr, 3)) { + msg_cdbg("\n"); + return 0; + } + id1 = readarr[0]; + id2 = (readarr[1] << 8) | readarr[2]; + + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6405) { + /* Now we have detected the 2017h class of Macronix flash devices. + * We can further differentiate two classes: + * -those who support the REMS2 function do always have 4KB sector size + * (at least i have not found one with 64KB yet), + * and + * -those who don't support the REMS2 function might have 4KB or 64KB + * (some have 4KB, e.g. MX25L6406E, some have 64KB, e.g. MX25L6405 (not D)) + * for erase function 20h. + */ + if (spi_rems2(readarr)) { + msg_cdbg("\n"); + return 0; + } + id3 = readarr[0]; + id4 = readarr[1]; + msg_cdbg("%s: id1 0x%02x, id2 0x%02x, id3 0x%02x, id4 0x%02x\n", __func__, id1, id2, id3, id4); + if (id3 == MACRONIX_ID && id4 == MACRONIX_MX25L6445E) { + /* MACRONIX_MX25L6445E class, always 4KB sector */ + if (flash->model_id == MACRONIX_MX25L6445E) + return 1; + else + return 0; + } else { + /* MACRONIX_MX25L6405 class, might have 4KB or 64KB sector */ + if (flash->model_id == MACRONIX_MX25L6405) + return 1; + else + return 0; + } + } else { + msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); + } + /* neither MACRONIX_MX25L6405 nor MACRONIX_MX25L6445E */ + return 0; +} + int probe_spi_rdid4(struct flashchip *flash) { /* Some SPI controllers do not support commands with writecnt=1 and @@ -694,6 +768,79 @@ return 0; } +/* Sector size might be 4KB or 64KB, but on call to this function this is unknown. + * So we do a first erase command and then check if mem in the complete 64KB sector is erased. + * If not we assume 4KB and so we repeat the erase for each 4KB sector in the 64KB block + * (which is not erased already). + * PLEASE NOTE: the .eraseblocks block size must be set to 64KB if you use this function. + */ +int spi_block_erase_20_4or64k(struct flashchip *flash, unsigned int addr, unsigned int blocklen) +{ + int result, i, j, fully_erased, sector_erased; + unsigned int curraddr, currblocklen; + uint8_t *readbuf; + + if (blocklen != (64 * 1024)) { + msg_gerr("%s: blocklen not 64KB! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + readbuf = malloc(blocklen); + if (!readbuf) { + msg_gerr("Out of memory!\n"); + exit(1); + } + + for (i = 0; i < 16; i++) { /* there are 16 4KB sectors in 64KB */ + + curraddr = addr + (i * (4 * 1024)); + + if (i > 0) { + /* Skip the sector erase if the sector is already erased */ + sector_erased = 1; + result = flash->read(flash, readbuf, curraddr, (4 * 1024)); + if (result) { + msg_gerr("Erase impossible because read failed " + "at 0x%x (len 0x%x)\n", curraddr, (4 * 1024)); + break; + } + for (j = 0; j < currblocklen; j++) + if (readbuf[j] != 0xFF) + sector_erased = 0; + if (sector_erased) + continue; /* Sector is already erased */ + } + + result = spi_block_erase_20 (flash, curraddr, (4 * 1024)); /* last parameter (blocklen) is unused */ + if (result) break; + + if (0 == i) { + curraddr += 4 * 1024; + currblocklen = (64*1024)-(4*1024); + fully_erased = 1; + result = flash->read(flash, readbuf, curraddr, currblocklen); + if (result) { + msg_gerr("Erase impossible because read failed " + "at 0x%x (len 0x%x)\n", curraddr, currblocklen); + break; + } + for (j = 0; j < currblocklen; j++) + if (readbuf[j] != 0xFF) + fully_erased = 0; + if (fully_erased) { + /* This means either that the SE command has erased the full 64KB + * or that the remaining 64KB sector was already erased before. + * Anyhow, we can now exit without calling the SE command again. + */ + break; + } + } + } + free(readbuf); + return result; +} + int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { -----Original Message----- From: flashrom-bounces(a)flashrom.org [mailto:flashrom-bounces@flashrom.org] On Behalf Of Wagner, Helge (GE Intelligent Platforms) Sent: Mittwoch, 29. Juni 2011 13:57 To: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] Macronix MX25L6445E Hello all, as Stefan suggested ("what about 0x2015, 0x2016, 0x2018? do they also have such problems?"), I was looking at some more Macronix data sheets. While doing this, I found out that my solution is NOT sufficient for some of the Macronix 0x2017 flash chips. I am currently working on a solution for this problem. Please stand by. Regards, Helge -----Original Message----- From: flashrom-bounces+helge.wagner=ge.com(a)flashrom.org [mailto:flashrom-bounces+helge.wagner=ge.com@flashrom.org] On Behalf Of Carl-Daniel Hailfinger Sent: Montag, 27. Juni 2011 20:28 To: flashrom(a)flashrom.org Subject: Re: [flashrom] [PATCH] Macronix MX25L6445E Hello Helge, thanks for your patch. It looks good to me on a first glance, and I hope to review it in detail soon. A short comment (in reply to Stefan's review) is at the end of this mail. Am 27.06.2011 17:50 schrieb Stefan Tauner: > On Mon, 27 Jun 2011 17:06:42 +0200 > "Wagner, Helge (GE Intelligent Platforms)" <Helge.Wagner(a)ge.com> wrote: > > >> Hello Stefan, >> >> >>> i have not looked at the datasheet(s), but maybe there is a way to distinguish the two devices (with another id command for example)? >>> >> I have asked Macronix, and they suggest to use the REMS2 function, which is supported on the MX25L6445E (returns 0xC216) and is not supported on the MX25L6405 (according to Macronix, it returns 0x0000 or 0xFFFF for this command). >> >> So now there is no longer a need to re-order the erase functions for the MX25L6405. >> >> Here is my new patch. >> >> Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> >> >> Regards, >> Helge Wagner >> >> diff -u flashrom/chipdrivers.h flashrom-patched/chipdrivers.h >> --- flashrom/chipdrivers.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/chipdrivers.h 2011-06-27 16:29:25.000000000 +0200 >> @@ -31,6 +31,7 @@ >> int probe_spi_rems(struct flashchip *flash); int >> probe_spi_res1(struct flashchip *flash); int probe_spi_res2(struct >> flashchip *flash); >> +int probe_spi_mx_2017(struct flashchip *flash); >> int spi_write_enable(void); >> int spi_write_disable(void); >> int spi_block_erase_20(struct flashchip *flash, unsigned int addr, >> unsigned int blocklen); diff -u flashrom/flashchips.c flashrom-patched/flashchips.c >> --- flashrom/flashchips.c 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/flashchips.c 2011-06-27 16:26:34.000000000 +0200 >> @@ -4131,8 +4131,8 @@ >> .total_size = 8192, >> .page_size = 256, >> .feature_bits = FEATURE_WRSR_WREN, >> - .tested = TEST_OK_PROBE, >> - .probe = probe_spi_rdid, >> + .tested = TEST_UNTESTED, >> + .probe = probe_spi_mx_2017, >> .probe_timing = TIMING_ZERO, >> .block_erasers = >> { >> @@ -4141,6 +4141,40 @@ >> .block_erase = spi_block_erase_20, >> }, { >> .eraseblocks = { {64 * 1024, 128} }, >> + .block_erase = spi_block_erase_d8, >> + }, { >> + .eraseblocks = { {8 * 1024 * 1024, 1} }, >> + .block_erase = spi_block_erase_60, >> + }, { >> + .eraseblocks = { {8 * 1024 * 1024, 1} }, >> + .block_erase = spi_block_erase_c7, >> + } >> + }, >> + .unlock = spi_disable_blockprotect, >> + .write = spi_chip_write_256, >> + .read = spi_chip_read, >> + .voltage = {2700, 3600}, >> + }, >> + >> + { >> + .vendor = "Macronix", >> + .name = "MX25L6445E", >> + .bustype = CHIP_BUSTYPE_SPI, >> + .manufacture_id = MACRONIX_ID, >> + .model_id = MACRONIX_MX25L6445E, >> + .total_size = 8192, >> + .page_size = 256, >> + .feature_bits = FEATURE_WRSR_WREN, >> + .tested = TEST_OK_PREW, >> + .probe = probe_spi_mx_2017, >> + .probe_timing = TIMING_ZERO, >> + .block_erasers = >> + { >> + { >> + .eraseblocks = { {4 * 1024, 2048} }, >> + .block_erase = spi_block_erase_20, >> + }, { >> + .eraseblocks = { {64 * 1024, 128} }, >> .block_erase = spi_block_erase_d8, >> }, { >> .eraseblocks = { {8 * 1024 * 1024, 1} }, diff -u >> flashrom/flashchips.h flashrom-patched/flashchips.h >> --- flashrom/flashchips.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/flashchips.h 2011-06-27 15:46:22.000000000 +0200 >> @@ -356,7 +356,8 @@ >> #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ >> #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ >> #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ >> -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ >> +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D} */ >> +#define MACRONIX_MX25L6445E 0x16 /* MX25L6445E, ID = REMS2 answer */ >> #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ >> #define MACRONIX_MX25L1635D 0x2415 >> #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ >> diff -u flashrom/spi.h flashrom-patched/spi.h >> --- flashrom/spi.h 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/spi.h 2011-06-27 16:29:38.000000000 +0200 >> @@ -40,6 +40,11 @@ >> #define JEDEC_REMS_OUTSIZE 0x04 >> #define JEDEC_REMS_INSIZE 0x02 >> >> +/* Read Electronic Manufacturer Signature 2 */ >> +#define JEDEC_REMS2 0xEF >> +#define JEDEC_REMS2_OUTSIZE 0x04 >> +#define JEDEC_REMS2_INSIZE 0x02 >> + >> /* Read Electronic Signature */ >> #define JEDEC_RES 0xab >> #define JEDEC_RES_OUTSIZE 0x04 >> diff -u flashrom/spi25.c flashrom-patched/spi25.c >> --- flashrom/spi25.c 2011-06-27 15:21:57.000000000 +0200 >> +++ flashrom-patched/spi25.c 2011-06-27 16:30:33.000000000 +0200 >> @@ -66,6 +66,27 @@ >> return 0; >> } >> >> +static int spi_rems2(unsigned char *readarr) { >> + unsigned char cmd[JEDEC_REMS2_OUTSIZE] = { JEDEC_REMS2, 0, 0, 0 }; >> + uint32_t readaddr; >> + int ret; >> + >> + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); >> + if (ret == SPI_INVALID_ADDRESS) { >> + /* Find the lowest even address allowed for reads. */ >> + readaddr = (spi_get_valid_read_addr() + 1) & ~1; >> + cmd[1] = (readaddr >> 16) & 0xff, >> + cmd[2] = (readaddr >> 8) & 0xff, >> + cmd[3] = (readaddr >> 0) & 0xff, >> + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); >> + } >> + if (ret) >> + return ret; >> + msg_cspew("REMS2 returned %02x %02x. ", readarr[0], readarr[1]); >> + return 0; >> +} >> + >> static int spi_res(unsigned char *readarr, int bytes) { >> unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; @@ >> -173,6 +194,49 @@ >> return probe_spi_rdid_generic(flash, 3); } >> >> +int probe_spi_mx_2017(struct flashchip *flash) { >> + unsigned char readarr[4]; >> + uint32_t id1; >> + uint32_t id2; >> + >> + if (spi_rdid(readarr, 3)) { >> + msg_cdbg("\n"); >> + return 0; >> + } >> + id1 = readarr[0]; >> + id2 = (readarr[1] << 8) | readarr[2]; >> + >> + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6405) { >> + /* We have either MACRONIX_MX25L6405 or MACRONIX_MX25L6445E. >> + * MACRONIX_MX25L6405 has 64KB for erase function 20h and does not support REMS2 function, >> + * MACRONIX_MX25L6445E has 4KB for erase function 20h and does support REMS2 function. >> + * So to differentiate both, we execute REMS2 function (this is suggested by macronix). >> + */ >> + if (spi_rems2(readarr)) { >> + msg_cdbg("\n"); >> + return 0; >> + } >> + id1 = readarr[0]; >> + id2 = readarr[1]; >> + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6445E) { >> + /* MACRONIX_MX25L6445E */ >> + if (flash->model_id == MACRONIX_MX25L6445E) >> + return 1; >> + else >> + return 0; >> + } else { >> + /* MACRONIX_MX25L6405 */ >> + if (flash->model_id == MACRONIX_MX25L6405) >> + return 1; >> + else >> + return 0; >> + } >> + } >> + /* neither MACRONIX_MX25L6405 nor MACRONIX_MX25L6445E */ >> + return 0; >> +} >> + >> int probe_spi_rdid4(struct flashchip *flash) { >> /* Some SPI controllers do not support commands with writecnt=1 and >> >> >> > hello again and thanks for all you have done. > > without looking at your patch in too much detail i would like to > mention another possibility to implement this. as i have done in my > sfdp and intel hardware sequencing patch you can alter the struct > flashchip *flash the probing function gets as parameter. > you can then change the erase block size (and name) according to the id > instead of using two chips and returning 0/1 respectively. > Please avoid changing struct flashchip *flash in the probe function unless it is absolutely necessary. The hack needed for SFDP should not spread elsewhere, especially if we can handle this nicely with two separate flashchip entries. Regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list flashrom(a)flashrom.org http://www.flashrom.org/mailman/listinfo/flashrom _______________________________________________ flashrom mailing list flashrom(a)flashrom.org http://www.flashrom.org/mailman/listinfo/flashrom

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Re: [flashrom] [PATCH] Macronix MX25L6445E
by Stefan Tauner 29 Jun '11

29 Jun '11

On Mon, 27 Jun 2011 17:06:42 +0200 "Wagner, Helge (GE Intelligent Platforms)" <Helge.Wagner(a)ge.com> wrote: > Hello Stefan, > > >i have not looked at the datasheet(s), but maybe there is a way to distinguish the two devices (with another id command for example)? > I have asked Macronix, and they suggest to use the REMS2 function, which is supported on the MX25L6445E (returns 0xC216) and is not supported on the MX25L6405 (according to Macronix, it returns 0x0000 or 0xFFFF for this command). > > So now there is no longer a need to re-order the erase functions for the MX25L6405. > > Here is my new patch. > > Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> > > Regards, > Helge Wagner > > diff -u flashrom/chipdrivers.h flashrom-patched/chipdrivers.h > --- flashrom/chipdrivers.h 2011-06-27 15:21:57.000000000 +0200 > +++ flashrom-patched/chipdrivers.h 2011-06-27 16:29:25.000000000 +0200 > @@ -31,6 +31,7 @@ > int probe_spi_rems(struct flashchip *flash); > int probe_spi_res1(struct flashchip *flash); > int probe_spi_res2(struct flashchip *flash); > +int probe_spi_mx_2017(struct flashchip *flash); > int spi_write_enable(void); > int spi_write_disable(void); > int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > diff -u flashrom/flashchips.c flashrom-patched/flashchips.c > --- flashrom/flashchips.c 2011-06-27 15:21:57.000000000 +0200 > +++ flashrom-patched/flashchips.c 2011-06-27 16:26:34.000000000 +0200 > @@ -4131,8 +4131,8 @@ > .total_size = 8192, > .page_size = 256, > .feature_bits = FEATURE_WRSR_WREN, > - .tested = TEST_OK_PROBE, > - .probe = probe_spi_rdid, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_mx_2017, > .probe_timing = TIMING_ZERO, > .block_erasers = > { > @@ -4141,6 +4141,40 @@ > .block_erase = spi_block_erase_20, > }, { > .eraseblocks = { {64 * 1024, 128} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { {8 * 1024 * 1024, 1} }, > + .block_erase = spi_block_erase_60, > + }, { > + .eraseblocks = { {8 * 1024 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .unlock = spi_disable_blockprotect, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Macronix", > + .name = "MX25L6445E", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = MACRONIX_ID, > + .model_id = MACRONIX_MX25L6445E, > + .total_size = 8192, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_OK_PREW, > + .probe = probe_spi_mx_2017, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {4 * 1024, 2048} }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 128} }, > .block_erase = spi_block_erase_d8, > }, { > .eraseblocks = { {8 * 1024 * 1024, 1} }, > diff -u flashrom/flashchips.h flashrom-patched/flashchips.h > --- flashrom/flashchips.h 2011-06-27 15:21:57.000000000 +0200 > +++ flashrom-patched/flashchips.h 2011-06-27 15:46:22.000000000 +0200 > @@ -356,7 +356,8 @@ > #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ > #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ > #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ > -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ > +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D} */ > +#define MACRONIX_MX25L6445E 0x16 /* MX25L6445E, ID = REMS2 answer */ > #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ > #define MACRONIX_MX25L1635D 0x2415 > #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ > diff -u flashrom/spi.h flashrom-patched/spi.h > --- flashrom/spi.h 2011-06-27 15:21:57.000000000 +0200 > +++ flashrom-patched/spi.h 2011-06-27 16:29:38.000000000 +0200 > @@ -40,6 +40,11 @@ > #define JEDEC_REMS_OUTSIZE 0x04 > #define JEDEC_REMS_INSIZE 0x02 > > +/* Read Electronic Manufacturer Signature 2 */ > +#define JEDEC_REMS2 0xEF > +#define JEDEC_REMS2_OUTSIZE 0x04 > +#define JEDEC_REMS2_INSIZE 0x02 > + > /* Read Electronic Signature */ > #define JEDEC_RES 0xab > #define JEDEC_RES_OUTSIZE 0x04 > diff -u flashrom/spi25.c flashrom-patched/spi25.c > --- flashrom/spi25.c 2011-06-27 15:21:57.000000000 +0200 > +++ flashrom-patched/spi25.c 2011-06-27 16:30:33.000000000 +0200 > @@ -66,6 +66,27 @@ > return 0; > } > > +static int spi_rems2(unsigned char *readarr) > +{ > + unsigned char cmd[JEDEC_REMS2_OUTSIZE] = { JEDEC_REMS2, 0, 0, 0 }; > + uint32_t readaddr; > + int ret; > + > + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); > + if (ret == SPI_INVALID_ADDRESS) { > + /* Find the lowest even address allowed for reads. */ > + readaddr = (spi_get_valid_read_addr() + 1) & ~1; > + cmd[1] = (readaddr >> 16) & 0xff, > + cmd[2] = (readaddr >> 8) & 0xff, > + cmd[3] = (readaddr >> 0) & 0xff, > + ret = spi_send_command(sizeof(cmd), JEDEC_REMS2_INSIZE, cmd, readarr); > + } > + if (ret) > + return ret; > + msg_cspew("REMS2 returned %02x %02x. ", readarr[0], readarr[1]); > + return 0; > +} > + > static int spi_res(unsigned char *readarr, int bytes) > { > unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; > @@ -173,6 +194,49 @@ > return probe_spi_rdid_generic(flash, 3); > } > > +int probe_spi_mx_2017(struct flashchip *flash) > +{ > + unsigned char readarr[4]; > + uint32_t id1; > + uint32_t id2; > + > + if (spi_rdid(readarr, 3)) { > + msg_cdbg("\n"); > + return 0; > + } > + id1 = readarr[0]; > + id2 = (readarr[1] << 8) | readarr[2]; > + > + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6405) { > + /* We have either MACRONIX_MX25L6405 or MACRONIX_MX25L6445E. > + * MACRONIX_MX25L6405 has 64KB for erase function 20h and does not support REMS2 function, > + * MACRONIX_MX25L6445E has 4KB for erase function 20h and does support REMS2 function. > + * So to differentiate both, we execute REMS2 function (this is suggested by macronix). > + */ > + if (spi_rems2(readarr)) { > + msg_cdbg("\n"); > + return 0; > + } > + id1 = readarr[0]; > + id2 = readarr[1]; > + if (id1 == MACRONIX_ID && id2 == MACRONIX_MX25L6445E) { > + /* MACRONIX_MX25L6445E */ > + if (flash->model_id == MACRONIX_MX25L6445E) > + return 1; > + else > + return 0; > + } else { > + /* MACRONIX_MX25L6405 */ > + if (flash->model_id == MACRONIX_MX25L6405) > + return 1; > + else > + return 0; > + } > + } > + /* neither MACRONIX_MX25L6405 nor MACRONIX_MX25L6445E */ > + return 0; > +} > + > int probe_spi_rdid4(struct flashchip *flash) > { > /* Some SPI controllers do not support commands with writecnt=1 and > > hello again and thanks for all you have done. without looking at your patch in too much detail i would like to mention another possibility to implement this. as i have done in my sfdp and intel hardware sequencing patch you can alter the struct flashchip *flash the probing function gets as parameter. you can then change the erase block size (and name) according to the id instead of using two chips and returning 0/1 respectively. i dont know if that alternative is any better. one can argue that these really are two independent chips and deserve their own flashchip struct. OTOH are they almost identical. but that's probably true for many chip (variants). so i think the scheme you have used is the right one and this mail is mostly for documenting/educating (read: blahblahblah :) the other thing that sprang to my mind is the question if there are other mx chips that need this kind of differentiation and if the scheme should be more generalized. what about 0x2015, 0x2016, 0x2018? do they also have such problems? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger 29 Jun '11

29 Jun '11

Am 29.06.2011 03:32 schrieb Stefan Reinauer: > On Tue, Jun 28, 2011 at 5:54 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > >>> 2. Due to issues with libpci, you can't use the same binary on machines with >>> PCI and without PCI. So for example, you can't program a SPI ROM onboard a >>> PCI card that is connected to your ARM SoC. >>> >> Could you explain more? IIRC some people were using flashrom on ARM >> (independent patch) with PCI support. Not calling any PCI functions >> should be enough to avoid any and all interactions between libpci and >> the hardware. >> > One of the problems is that if you call libpci's init function on a > system with no PCI support, libpci will not return an error but just > end the program right away. This makes it hard to have one binary that > works on PCI and non-PCI ARM systems. > Just set pci_access->error to a function with printf signature (e.g. my_libpci_error_interceptor) before calling pci_init and make sure my_libpci_error_interceptor sets a global variable pci_failed=1 once it is called. That is ugly, but it should work. Regards, Carl-Daniel -- http://www.hailfinger.org/

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SST 49LF008A and Poulsbo - still having erase problem
by Joel Brinton 29 Jun '11

29 Jun '11

Hello, First thanks all for the hard work - flashrom is a great utility! I'm currently having trouble on the Intel SCH (Poulsbo) with a 49LF008A (Toradex Z530 COMExpress board). I found an old mail message [http://www.flashrom.org/pipermail/flashrom/2010-March/002481.html] of someone experiencing the same problem I have - blockwise erase failure. There was two proposed patches to SVN revision 988. I checked out revision 988 but neither patch fixes the issue. I then checked out the latest (both patched and unpatched) and it doesn't fix the problem and now segfaults. I've spent a good day digging through the source and datasheets to no avail. thank you, joel Here's my dump: flashrom v0.9.3-r1324 on Linux 2.6.24-26-generic (i686), built with libpci 2.2.4, GCC 4.2.4 (Ubuntu 4.2.4-1ubuntu4), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 2 usecs, 793M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1009 us, 10000 myus = 9986 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Toradex" DMI string system-product-name: "POULSBO" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "Toradex" DMI string baseboard-product-name: "WoodPecker" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "Intel Poulsbo", enabling flash write... chipset PCI ID is 8086:8119, BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 BIOS Prefetch Enable: disabled, OK. This chipset supports the following protocols: FWH. Probing for AMD Am29F010A/B, 128 kB: skipped. Probing for AMD Am29F002(N)BB, 256 kB: skipped. Probing for AMD Am29F002(N)BT, 256 kB: skipped. Probing for AMD Am29F016D, 2048 kB: skipped. Probing for AMD Am29F040B, 512 kB: skipped. Probing for AMD Am29F080B, 1024 kB: skipped. Probing for AMD Am29LV001BB, 128 kB: skipped. Probing for AMD Am29LV001BT, 128 kB: skipped. Probing for AMD Am29LV002BB, 256 kB: skipped. Probing for AMD Am29LV002BT, 256 kB: skipped. Probing for AMD Am29LV004BB, 512 kB: skipped. Probing for AMD Am29LV004BT, 512 kB: skipped. Probing for AMD Am29LV008BB, 1024 kB: skipped. Probing for AMD Am29LV008BT, 1024 kB: skipped. Probing for AMD Am29LV040B, 512 kB: skipped. Probing for AMD Am29LV081B, 1024 kB: skipped. Probing for AMIC A25L05PT, 64 kB: skipped. Probing for AMIC A25L05PU, 64 kB: skipped. Probing for AMIC A25L10PT, 128 kB: skipped. Probing for AMIC A25L10PU, 128 kB: skipped. Probing for AMIC A25L20PT, 256 kB: skipped. Probing for AMIC A25L20PU, 256 kB: skipped. Probing for AMIC A25L40PT, 512 kB: skipped. Probing for AMIC A25L40PU, 512 kB: skipped. Probing for AMIC A25L80P, 1024 kB: skipped. Probing for AMIC A25L16PT, 2048 kB: skipped. Probing for AMIC A25L16PU, 2048 kB: skipped. Probing for AMIC A25L512, 64 kB: skipped. Probing for AMIC A25L010, 128 kB: skipped. Probing for AMIC A25L020, 256 kB: skipped. Probing for AMIC A25L040, 512 kB: skipped. Probing for AMIC A25L080, 1024 kB: skipped. Probing for AMIC A25L016, 2048 kB: skipped. Probing for AMIC A25L032, 4096 kB: skipped. Probing for AMIC A25LQ032, 4096 kB: skipped. Probing for AMIC A29002B, 256 kB: skipped. Probing for AMIC A29002T, 256 kB: skipped. Probing for AMIC A29040B, 512 kB: skipped. Probing for AMIC A49LF040A, 512 kB: skipped. Probing for Atmel AT25DF021, 256 kB: skipped. Probing for Atmel AT25DF041A, 512 kB: skipped. Probing for Atmel AT25DF081, 1024 kB: skipped. Probing for Atmel AT25DF081A, 1024 kB: skipped. Probing for Atmel AT25DF161, 2048 kB: skipped. Probing for Atmel AT25DF321, 4096 kB: skipped. Probing for Atmel AT25DF321A, 4096 kB: skipped. Probing for Atmel AT25DF641, 8192 kB: skipped. Probing for Atmel AT25DQ161, 2048 kB: skipped. Probing for Atmel AT25F512B, 64 kB: skipped. Probing for Atmel AT25FS010, 128 kB: skipped. Probing for Atmel AT25FS040, 512 kB: skipped. Probing for Atmel AT26DF041, 512 kB: skipped. Probing for Atmel AT26DF081A, 1024 kB: skipped. Probing for Atmel AT26DF161, 2048 kB: skipped. Probing for Atmel AT26DF161A, 2048 kB: skipped. Probing for Atmel AT26F004, 512 kB: skipped. Probing for Atmel AT29C512, 64 kB: skipped. Probing for Atmel AT29C010A, 128 kB: skipped. Probing for Atmel AT29C020, 256 kB: skipped. Probing for Atmel AT29C040A, 512 kB: skipped. Probing for Atmel AT45CS1282, 16896 kB: skipped. Probing for Atmel AT45DB011D, 128 kB: skipped. Probing for Atmel AT45DB021D, 256 kB: skipped. Probing for Atmel AT45DB041D, 512 kB: skipped. Probing for Atmel AT45DB081D, 1024 kB: skipped. Probing for Atmel AT45DB161D, 2048 kB: skipped Probing for Atmel AT45DB321C, 4224 kB: skipped. Probing for Atmel AT45DB321D, 4096 kB: skipped. Probing for Atmel AT45DB642D, 8192 kB: skipped. Probing for Atmel AT49BV512, 64 kB: skipped. Probing for Atmel AT49F020, 256 kB: skipped. Probing for Atmel AT49F002(N), 256 kB: skipped. Probing for Atmel AT49F002(N)T, 256 kB: skipped. Probing for Bright BM29F040, 512 kB: skipped. Probing for EMST F49B002UA, 256 kB: skipped. Probing for EMST F25L008A, 1024 kB: skipped. Probing for Eon EN25B05, 64 kB: skipped. Probing for Eon EN25B05T, 64 kB: skipped Probing for Eon EN25B10, 128 kB: skipped. Probing for Eon EN25B10T, 128 kB: skipped. Probing for Eon EN25B20, 256 kB: skipped. Probing for Eon EN25B20T, 256 kB: skipped. Probing for Eon EN25B40, 512 kB: skipped. Probing for Eon EN25B40T, 512 kB: skipped. Probing for Eon EN25B80, 1024 kB: skipped. Probing for Eon EN25B80T, 1024 kB: skipped. Probing for Eon EN25B16, 2048 kB: skipped. Probing for Eon EN25B16T, 2048 kB: skipped. Probing for Eon EN25B32, 4096 kB: skipped. Probing for Eon EN25B32T, 4096 kB: skipped. Probing for Eon EN25B64, 8192 kB: skipped. Probing for Eon EN25B64T, 8192 kB: skipped. Probing for Eon EN25D16, 2048 kB: skipped. Probing for Eon EN25F05, 64 kB: skipped. Probing for Eon EN25F10, 128 kB: skipped. Probing for Eon EN25F20, 256 kB: skipped. Probing for Eon EN25F40, 512 kB: skipped. Probing for Eon EN25F80, 1024 kB: skipped. Probing for Eon EN25F16, 2048 kB: skipped. Probing for Eon EN25F32, 4096 kB: skipped. Probing for Eon EN29F010, 128 kB: skipped. Probing for Eon EN29F002(A)(N)B, 256 kB: skipped. Probing for Eon EN29F002(A)(N)T, 256 kB: skipped. Probing for Fujitsu MBM29F004BC, 512 kB: skipped. Probing for Fujitsu MBM29F004TC, 512 kB: skipped. Probing for Fujitsu MBM29F400BC, 512 kB: skipped. Probing for Fujitsu MBM29F400TC, 512 kB: skipped. Probing for Hyundai HY29F002T, 256 kB: skipped. Probing for Hyundai HY29F002B, 256 kB: skipped. Probing for Hyundai HY29F040A, 512 kB: skipped. Probing for Intel 28F001BN/BX-B, 128 kB: skipped. Probing for Intel 28F001BN/BX-T, 128 kB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: skipped. Probing for Intel 28F008S3/S5/SC, 512 kB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: skipped. Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: skipped. Probing for Macronix MX25L1005, 128 kB: skipped. Probing for Macronix MX25L2005, 256 kB: skipped. Probing for Macronix MX25L4005, 512 kB: skipped. Probing for Macronix MX25L8005, 1024 kB: skipped. Probing for Macronix MX25L1605, 2048 kB: skipped. Probing for Macronix MX25L1635D, 2048 kB: skipped. Probing for Macronix MX25L1635E, 2048 kB: skipped. Probing for Macronix MX25L3205, 4096 kB: skipped. Probing for Macronix MX25L3235D, 4096 kB: skipped. Probing for Macronix MX25L6405, 8192 kB: skipped. Probing for Macronix MX25L12805, 16384 kB: skipped. Probing for Macronix MX29F001B, 128 kB: skipped. Probing for Macronix MX29F001T, 128 kB: skipped. Probing for Macronix MX29F002B, 256 kB: skipped. Probing for Macronix MX29F002T, 256 kB: skipped. Probing for Macronix MX29F040, 512 kB: skipped. Probing for Macronix MX29LV040, 512 kB: skipped. Probing for MoselVitelic V29C51000B, 64 kB: skipped. Probing for MoselVitelic V29C51000T, 64 kB: skipped. Probing for MoselVitelic V29C51400B, 512 kB: skipped. Probing for MoselVitelic V29C51400T, 512 kB: skipped. Probing for MoselVitelic V29LC51000, 64 kB: skipped. Probing for MoselVitelic V29LC51001, 128 kB: skipped. Probing for MoselVitelic V29LC51002, 256 kB: skipped. Probing for Numonyx M25PE10, 128 kB: skipped. Probing for Numonyx M25PE20, 256 kB: skipped. Probing for Numonyx M25PE40, 512 kB: skipped. Probing for Numonyx M25PE80, 1024 kB: skipped. Probing for Numonyx M25PE16, 2048 kB: skipped. Probing for PMC Pm25LV010, 128 kB: skipped. Probing for PMC Pm25LV016B, 2048 kB: skipped. Probing for PMC Pm25LV020, 256 kB: skipped. Probing for PMC Pm25LV040, 512 kB: skipped. Probing for PMC Pm25LV080B, 1024 kB: skipped. Probing for PMC Pm25LV512, 64 kB: skipped. Probing for PMC Pm29F002T, 256 kB: skipped. Probing for PMC Pm29F002B, 256 kB: skipped. Probing for PMC Pm39LV010, 128 kB: skipped. Probing for PMC Pm39LV020, 256 kB: skipped. Probing for PMC Pm39LV040, 512 kB: skipped. Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Sanyo LF25FW203A, 2048 kB: skipped. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: skipped. Probing for Spansion S25FL008A, 1024 kB: skipped. Probing for Spansion S25FL016A, 2048 kB: skipped. Probing for Spansion S25FL032A, 4096 kB: skipped. Probing for Spansion S25FL064A, 8192 kB: skipped. Probing for SST SST25VF010.REMS, 128 kB: skipped. Probing for SST SST25VF016B, 2048 kB: skipped. Probing for SST SST25VF032B, 4096 kB: skipped. Probing for SST SST25VF064C, 8192 kB: skipped. Probing for SST SST25VF040.REMS, 512 kB: skipped. Probing for SST SST25VF040B, 512 kB: skipped. Probing for SST SST25LF040A.RES, 512 kB: skipped. Probing for SST SST25VF040B.REMS, 512 kB: skipped. Probing for SST SST25VF080B, 1024 kB: skipped. Probing for SST SST28SF040A, 512 kB: skipped. Probing for SST SST29EE010, 128 kB: skipped. Probing for SST SST29LE010, 128 kB: skipped. Probing for SST SST29EE020A, 256 kB: skipped. Probing for SST SST29LE020, 256 kB: skipped. Probing for SST SST39SF512, 64 kB: skipped. Probing for SST SST39SF010A, 128 kB: skipped. Probing for SST SST39SF020A, 256 kB: skipped. Probing for SST SST39SF040, 512 kB: skipped. Probing for SST SST39VF512, 64 kB: skipped. Probing for SST SST39VF010, 128 kB: skipped. Probing for SST SST39VF020, 256 kB: skipped. Probing for SST SST39VF040, 512 kB: skipped. Probing for SST SST39VF080, 1024 kB: skipped. Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5a Found chip "SST SST49LF008A" (1024 kB, FWH) at physical address 0xfff00000. Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Lock status for 0x080000 (size 0x010000) is 00, full access Lock status for 0x090000 (size 0x010000) is 00, full access Lock status for 0x0a0000 (size 0x010000) is 00, full access Lock status for 0x0b0000 (size 0x010000) is 00, full access Lock status for 0x0c0000 (size 0x010000) is 00, full access Lock status for 0x0d0000 (size 0x010000) is 00, full access Lock status for 0x0e0000 (size 0x010000) is 00, full access Lock status for 0x0f0000 (size 0x010000) is 00, full access Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: skipped. Probing for SST SST49LF020A, 256 kB: skipped. Probing for SST SST49LF040, 512 kB: skipped. Probing for SST SST49LF040B, 512 kB: skipped Probing for SST SST49LF080A, 1024 kB: skipped. Probing for SST SST49LF160C, 2048 kB: skipped. Probing for ST M25P05-A, 64 kB: skipped. Probing for ST M25P05.RES, 64 kB: skipped. Probing for ST M25P10-A, 128 kB: skipped. Probing for ST M25P10.RES, 128 kB: skipped. Probing for ST M25P20, 256 kB: skipped. Probing for ST M25P40, 512 kB: skipped. Probing for ST M25P40-old, 512 kB: skipped. Probing for ST M25P80, 1024 kB: skipped. Probing for ST M25P16, 2048 kB: skipped. Probing for ST M25P32, 4096 kB: skipped. Probing for ST M25P64, 8192 kB: skipped. Probing for ST M25P128, 16384 kB: skipped. Probing for ST M25PX16, 2048 kB: skipped. Probing for ST M25PX32, 4096 kB: skipped. Probing for ST M25PX64, 8192 kB: skipped. Probing for ST M29F002B, 256 kB: skipped. Probing for ST M29F002T/NT, 256 kB: skipped. Probing for ST M29F040B, 512 kB: skipped. Probing for ST M29F400BB, 512 kB: skipped. Probing for ST M29F400BT, 512 kB: skipped. Probing for ST M29W010B, 128 kB: skipped. Probing for ST M29W040B, 512 kB: skipped. Probing for ST M29W512B, 64 kB: skipped. Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: skipped. Probing for TI TMS29F002RB, 256 kB: skipped. Probing for TI TMS29F002RT, 256 kB: skipped. Probing for Winbond W25Q80, 1024 kB: skipped Probing for Winbond W25Q16, 2048 kB: skipped. Probing for Winbond W25Q32, 4096 kB: skipped. Probing for Winbond W25Q64, 8192 kB: skipped. Probing for Winbond W25Q128, 16384 kB: skipped. Probing for Winbond W25x10, 128 kB: skipped. Probing for Winbond W25x20, 256 kB: skipped. Probing for Winbond W25x40, 512 kB: skipped. Probing for Winbond W25x80, 1024 kB: skipped. Probing for Winbond W25x16, 2048 kB: skipped. Probing for Winbond W25x32, 4096 kB: skipped. Probing for Winbond W25x64, 8192 kB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 kB: skipped. Probing for Winbond W29C040/P, 512 kB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: skipped. Probing for Winbond W39L040, 512 kB: skipped. Probing for Winbond W39V040A, 512 kB: skipped. Probing for Winbond W39V040B, 512 kB: skipped. Probing for Winbond W39V040C, 512 kB: skipped. Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080A, 1024 kB: skipped. Probing for Winbond W49F002U/N, 256 kB: skipped. Probing for Winbond W49F020, 256 kB: skipped. Probing for Winbond W49V002A, 256 kB: skipped. Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for AMIC unknown AMIC SPI chip, 0 kB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 kB: skipped. Probing for Eon unknown Eon SPI chip, 0 kB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 kB: skipped. Probing for PMC unknown PMC SPI chip, 0 kB: skipped. Probing for SST unknown SST SPI chip, 0 kB: skipped. Probing for ST unknown ST SPI chip, 0 kB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 kB: skipped. Probing for Generic unknown SPI chip (RDID), 0 kB: skipped. Probing for Generic unknown SPI chip (REMS), 0 kB: skipped. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Lock status for 0x080000 (size 0x010000) is 00, full access Lock status for 0x090000 (size 0x010000) is 00, full access Lock status for 0x0a0000 (size 0x010000) is 00, full access Lock status for 0x0b0000 (size 0x010000) is 00, full access Lock status for 0x0c0000 (size 0x010000) is 00, full access Lock status for 0x0d0000 (size 0x010000) is 00, full access Lock status for 0x0e0000 (size 0x010000) is 00, full access Lock status for 0x0f0000 (size 0x010000) is 00, full access coreboot last image size (not ROM size) is 1048576 bytes. Manufacturer: iWave Mainboard ID: iWRainbowG6 Note: If the following flash access fails, try -m :. Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:E Looking at blockwise erase function 1.. trying... 0x000000-0x00ffff:E Looking at blockwise erase function 2... eraseblock layout is known, but matching block erase function is not implemented. trying... 0x000000-0x0fffff:E Segmentation fault

1 2

This report flashrom-V
by Senior College Krikoon Hilton Enterprise 29 Jun '11

29 Jun '11

This report flashrom-V Please help [root@magnet alexander]# flashrom flashrom v0.9.3-r1299 on Linux 2.6.34.9-69.fc13.i686.PAE (i686), built with libpci 3.1.7, GCC 4.4.5 20101112 (Red Hat 4.4.5-2), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Write is unsupported! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. [root@magnet alexander]# flashrom -V flashrom v0.9.3-r1299 on Linux 2.6.34.9-69.fc13.i686.PAE (i686), built with libpci 3.1.7, GCC 4.4.5 20101112 (Red Hat 4.4.5-2), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 421M loops per second, delay more than 10% too short (got 85% of expected delay), recalculating... 455M loops per second, 10 myus = 10 us, 100 myus = 92 us, 1000 myus = 1950 us, 10000 myus = 11243 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M2N-MX SE Plus" DMI string baseboard-version: "Rev x.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA MCP61", enabling flash write... chipset PCI ID is 10de:03e0, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Write is unsupported! Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV001BB, 128 KB: skipped. Probing for AMD Am29LV001BT, 128 KB: skipped. Probing for AMD Am29LV002BB, 256 KB: skipped. Probing for AMD Am29LV002BT, 256 KB: skipped. Probing for AMD Am29LV004BB, 512 KB: skipped. Probing for AMD Am29LV004BT, 512 KB: skipped. Probing for AMD Am29LV008BB, 1024 KB: skipped. Probing for AMD Am29LV008BT, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39L040, 512 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V040FB, 512 KB: skipped. Probing for Winbond W39V040FC, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. [root@magnet alexander]#

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[PATCH 8/8] squash! ichspi:c add support for Intel Hardware Sequencing
by Stefan Tauner 28 Jun '11

28 Jun '11

- add SPI_CONTROLLER_ICH_HWSEQ support to ich_set_bbar although unused atm - remove ich_hwseq_get_flash_boundary - use all fdata registers for transfers - allow 25b addresses and add ich_hwseq_set_addr Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 83 ++++++++++++++++++++++++++++--------------------------------- 1 files changed, 38 insertions(+), 45 deletions(-) diff --git a/ichspi.c b/ichspi.c index 361006d..fd3b808 100644 --- a/ichspi.c +++ b/ichspi.c @@ -577,6 +577,7 @@ static void ich_set_bbar(uint32_t min_addr) bbar_off = 0x50; break; case SPI_CONTROLLER_ICH9: + case SPI_CONTROLLER_ICH_HWSEQ: bbar_off = ICH9_REG_BBAR; break; default: @@ -1092,9 +1093,10 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -static uint32_t ich_hwseq_get_flash_boundary(void) +static void ich_hwseq_set_addr(uint32_t addr) { - return (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); } /* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes @@ -1109,7 +1111,7 @@ static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) 64 * 1024 }; - REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + ich_hwseq_set_addr(addr); enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF; return dec_berase[enc_berase]; @@ -1132,9 +1134,9 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout) { - addr = REGREAD32(ICH9_REG_FADDR); - msg_perr("Timeout error between offset 0x%06x and " - "0x%06x + %d (=0x%06x)!\n", + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", addr, addr, len - 1, addr + len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); @@ -1142,9 +1144,9 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } if (hsfs & HSFS_FCERR) { - addr = REGREAD32(ICH9_REG_FADDR); - msg_perr("Transaction error between offset 0x%06x and " - "0x%06x + %d (=0x%06x)!\n", + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", addr, addr, len - 1, addr + len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); @@ -1175,8 +1177,8 @@ int ich_hwseq_probe(struct flashchip *flash) msg_cdbg("not met.\n"); return 0; } - msg_cdbg("met.\n"); + total_size = (getFCBA_component_density(0) + getFCBA_component_density(1)); msg_cdbg("Found %d attached SPI flash chip", fdbar.NC + 1); @@ -1188,7 +1190,7 @@ int ich_hwseq_probe(struct flashchip *flash) flash->total_size = total_size / 1024; eraser = &(flash->block_erasers[0]); - boundary = ich_hwseq_get_flash_boundary(); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; size_high = total_size - boundary; erase_size_high = ich_hwseq_get_erase_block_size(boundary); @@ -1292,10 +1294,9 @@ int ich_hwseq_block_erase(struct flashchip *flash, int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) { - uint32_t *buf32 = (uint32_t *)buf; uint16_t hsfc; uint16_t timeout = 100 * 60; - int i; + uint8_t block_len; if (flash->manufacture_id != INTEL_ID || flash->model_id != INTEL_HWSEQ) { @@ -1304,14 +1305,8 @@ int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) return -1; } - if (len % 4 != 0) { - msg_perr("Read size has to be a multiple of 4 for this " - "implementation of hardware sequencing mode.\n"); - return -1; - } - - if (addr < 0 || addr + len > 0x00FFFFFF) { - msg_perr("Request to read from inaccessible memory address " + if (addr < 0 || addr + len > 0x01FFFFFF) { + msg_perr("Request to read from an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; } @@ -1320,30 +1315,32 @@ int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - for (i = 0; i < len; i += 4) { - /* FIXME: reserved bits */ - REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ - hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= ((block_len - 1) << HSFC_FDBC_OFF); /* set byte count */ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, 4)) return 1; - *buf32++ = REGREAD32(ICH9_REG_FDATA0); - addr += 4; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; } return 0; } int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) { - uint32_t *buf32 = (uint32_t *)buf; uint16_t hsfc; uint16_t timeout = 100 * 60; - int i; + uint8_t block_len; + if (flash->manufacture_id != INTEL_ID || flash->model_id != INTEL_HWSEQ) { msg_perr("This chip (%s) is not supported in hardware" @@ -1351,14 +1348,8 @@ int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len return -1; } - if ((len % 4 != 0)) { - msg_perr("Write size has to be a multiple of 4 for this " - "implementation of hardware sequencing mode\n"); - return -1; - } - if (addr < 0 || addr + len > 0x00FFFFFF) { - msg_perr("Request to write to inaccessible memory address " + msg_perr("Request to write to an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; } @@ -1367,22 +1358,24 @@ int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - for (i = 0; i < len; i += 4) { - /* FIXME: reserved bits */ - REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); - REGWRITE32(ICH9_REG_FDATA0, *buf32); + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = ich_fill_data(buf, len, ICH9_REG_FDATA0); + if (block_len < 0) + return block_len; hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ - hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= ((block_len - 1) << HSFC_FDBC_OFF); /* set byte count */ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, 4)) - return 1; - addr += 4; - buf32++; + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; } return 0; } -- 1.7.1

1 0

[PATCH 7/8] ichspi:c add support for Intel Hardware Sequencing
by Stefan Tauner 28 Jun '11

28 Jun '11

todo: - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values Tested-by: David Hendricks <dhendrix(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ichspi.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 5 files changed, 354 insertions(+), 12 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 865ba2f..5d2b6a8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8507,7 +8507,27 @@ const struct flashchip flashchips[] = { .write = write_jedec_1, .read = read_memmapped, }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8640,6 +8660,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index 3b2b94f..6b8d574 100644 --- a/flashchips.h +++ b/flashchips.h @@ -340,6 +340,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ichspi.c b/ichspi.c index 45151d7..361006d 100644 --- a/ichspi.c +++ b/ichspi.c @@ -35,10 +35,11 @@ * */ -#if defined(__i386__) || defined(__x86_64__) +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) #include <string.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1091,6 +1092,301 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static uint32_t ich_hwseq_get_flash_boundary(void) +{ + return (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR); + msg_perr("Timeout error between offset 0x%06x and " + "0x%06x + %d (=0x%06x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR); + msg_perr("Transaction error between offset 0x%06x and " + "0x%06x + %d (=0x%06x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + extern struct flash_descriptor fdbar; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + + msg_cdbg("met.\n"); + total_size = (getFCBA_component_density(0) + + getFCBA_component_density(1)); + msg_cdbg("Found %d attached SPI flash chip", fdbar.NC + 1); + if (fdbar.NC) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = ich_hwseq_get_flash_boundary(); + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr < 0 || addr + len > 0x00FFFFFF) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint32_t *buf32 = (uint32_t *)buf; + uint16_t hsfc; + uint16_t timeout = 100 * 60; + int i; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (len % 4 != 0) { + msg_perr("Read size has to be a multiple of 4 for this " + "implementation of hardware sequencing mode.\n"); + return -1; + } + + if (addr < 0 || addr + len > 0x00FFFFFF) { + msg_perr("Request to read from inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + for (i = 0; i < len; i += 4) { + /* FIXME: reserved bits */ + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, 4)) + return 1; + *buf32++ = REGREAD32(ICH9_REG_FDATA0); + addr += 4; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint32_t *buf32 = (uint32_t *)buf; + uint16_t hsfc; + uint16_t timeout = 100 * 60; + int i; + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if ((len % 4 != 0)) { + msg_perr("Write size has to be a multiple of 4 for this " + "implementation of hardware sequencing mode\n"); + return -1; + } + + if (addr < 0 || addr + len > 0x00FFFFFF) { + msg_perr("Request to write to inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + for (i = 0; i < len; i += 4) { + /* FIXME: reserved bits */ + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + REGWRITE32(ICH9_REG_FDATA0, *buf32); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, 4)) + return 1; + addr += 4; + buf32++; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1209,6 +1505,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1217,20 +1523,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint16_t spibar_offset, tmp2; uint32_t tmp; int ichspi_desc = 0; + /* used for hw sequencing detection */ + extern struct flash_descriptor fdbar; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1241,8 +1546,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1278,9 +1583,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1357,10 +1666,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, read_ich_descriptors_from_fdo(ich_spibar); prettyprint_ich_descriptors(); } - ich_init_opcodes(); - break; - default: - /* Nothing */ + + if (ichspi_lock || fdbar.NC != 0) + register_spi_programmer(&spi_programmer_ich_hwseq); + else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); + } break; } diff --git a/programmer.h b/programmer.h index cd82dcb..2c71754 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

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[PATCH 6/8] add ICH/PCH flash descriptor decoding
by Stefan Tauner 28 Jun '11

28 Jun '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds... - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers) - a new tool to the util directory that is able to decode all flash descriptors stored in a flash dump file. it also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the prettyprinting function is used by the descriptor code too: the properties of flash chips supported by the ME are stored in the same format in a descriptor table. this is also the reason why the pp function and the register bit macros are not defined in ichspi.c but ich_descriptors.h TODO: - is endianess important? and other questions related to the struct/union pattern used. - how to detect the chipset used for the strap descriptors which differ a lot between chipset versions? when called from flashrom this is easy (1. because we know the chipset and 2. we don't need to know currently, because we can't read it via registers anyway. do we wanna try to read the descriptor block from flash for this?). there is afaics no way to deduce the chipset from image files so we should introduce a parameter for that in the tool...? - file naming and partitioning was not discussed. we may want a ichspi.h. and/or rename ichspi.c to ich_spi.c or similar... Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 3 +- ich_descriptors.c | 490 ++++++++++++++++++++++ ich_descriptors.h | 447 ++++++++++++++++++++ ichspi.c | 35 ++- util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 ++++++++++ 7 files changed, 1243 insertions(+), 5 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/Makefile b/Makefile index 456c6ae..bee664f 100644 --- a/Makefile +++ b/Makefile @@ -223,7 +223,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o NEED_PCI := yes endif diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..1b7dc36 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,490 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "ich_descriptors.h" + +#if defined(__i386__) || defined(__x86_64__) + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#define msg_perr printf +#include <stdio.h> + +struct flash_strap fisba; +struct flash_upper_map flumap; + +#else + +#include "flash.h" /* for msg_* */ + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +struct flash_descriptor fdbar = { 0 }; +struct flash_component fcba = { {0} }; +struct flash_region frba = { {0} }; +struct flash_master fmba = { {0} }; + +uint32_t getFCBA(void) +{ + return (fdbar.FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA(void) +{ + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA(void) +{ + return (fdbar.FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA(void) +{ + return (fdbar.FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA(void) +{ + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; +} + +/** Returns the integer representation of the component density with index +comp in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t comp) +{ + uint8_t size_enc; + const int dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(comp) { + case 0: + size_enc = fcba.comp1_density; + break; + case 1: + if (fdbar.NC == 0) + return 0; + size_enc = fcba.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d illegal or " + "unsupported. Encoded density is 0x%x.\n", comp, + size_enc); + return 0; + } + return dec_mem[size_enc]; +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA(void) +{ /* The bits in FLUMAP1 describe bits 4-11 out of 24 in total; + * others are 0. */ + return (flumap.FLUMAP1 << 4) & 0x0ff0; +} +#endif + +const struct flash_descriptor_addresses desc_addr = { + .FCBA = getFCBA, + .FRBA = getFRBA, + .FMBA = getFMBA, + .FMSBA = getFMSBA, + .FISBA = getFISBA, + .FLREG_limit = getFLREG_limit, + .FLREG_base = getFLREG_base, +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + .VTBA = getVTBA, +#endif +}; + +void prettyprint_ich_descriptors(void) +{ + prettyprint_ich_descriptor_map(); + prettyprint_ich_descriptor_component(); + prettyprint_ich_descriptor_region(); + prettyprint_ich_descriptor_master(); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + prettyprint_ich_descriptor_upper_map(); + /* FIXME: detect chipset correctly */ + prettyprint_ich_descriptor_straps(CHIPSET_SERIES_5_IBEX_PEAK); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + msg_pdbg("\n"); +} + +void prettyprint_ich_descriptor_map(void) +{ + msg_pdbg("=== FDBAR ===\n"); + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); + msg_pdbg("\n"); + msg_pdbg("--- FDBAR details ---\n"); + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); +} + +void prettyprint_ich_descriptor_component(void) +{ + const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved/illegal", /* 010 */ + "reserved/illegal", /* 011 */ + "50 MHz", /* 100 */ + "reserved/illegal", /* 101 */ + "reserved/illegal", /* 110 */ + "reserved/illegal" /* 111 */ + }; + const char * const str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "undocumented/illegal", + "reserved/illegal" + }; + + msg_pdbg("\n"); + msg_pdbg("=== FCBA ===\n"); + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); + msg_pdbg("\n"); + msg_pdbg("--- FCBA details ---\n"); + msg_pdbg("0x%2.2x freq_read_id %s\n", + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); + msg_pdbg("0x%2.2x freq_write %s\n", + fcba.freq_write , str_freq[fcba.freq_write ]); + msg_pdbg("0x%2.2x freq_fastread %s\n", + fcba.freq_fastread, str_freq[fcba.freq_fastread]); + msg_pdbg("0x%2.2x fastread %ssupported\n", + fcba.fastread, fcba.fastread ? "" : "not "); + msg_pdbg("0x%2.2x freq_read %s\n", + fcba.freq_read, str_freq[fcba.freq_read ]); + msg_pdbg("0x%2.2x comp 1 density %s\n", + fcba.comp1_density, str_mem[fcba.comp1_density]); + if (fdbar.NC) + msg_pdbg("0x%2.2x comp 2 density %s\n", + fcba.comp2_density, str_mem[fcba.comp2_density]); + else + msg_pdbg("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", + fcba.comp2_density); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); +} + +void prettyprint_ich_descriptor_region(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FRBA ===\n"); + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); + msg_pdbg("\n"); + msg_pdbg("--- FRBA details ---\n"); + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); +} + +void prettyprint_ich_descriptor_master(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FMBA ===\n"); + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); + + msg_pdbg("\n"); + msg_pdbg("--- FMBA details ---\n"); + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); +} + +void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, BES, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void prettyprint_ich_descriptor_straps_ich8(void) +{ + const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg("\n"); + msg_pdbg("=== FISBA ===\n"); + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); + + msg_pdbg("\n"); + msg_pdbg("--- FISBA details ---\n"); + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg("\n"); + msg_pdbg("=== FMSBA ===\n"); + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); + + msg_pdbg("\n"); + msg_pdbg("--- FMSBA details ---\n"); + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); +} + +void prettyprint_ich_descriptor_straps_ibex(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FPSBA ===\n"); + for(i = 0; i <= 15; i++) + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); +} + +void prettyprint_ich_descriptor_straps(enum chipset cs) +{ + switch (cs) { + case CHIPSET_ICH8: + prettyprint_ich_descriptor_straps_ich8(); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + prettyprint_ich_descriptor_straps_ibex(); + break; + default: + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FLUMAP ===\n"); + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); + + msg_pdbg("\n"); + msg_pdbg("--- FLUMAP details ---\n"); + msg_pdbg("VTL (length) = %d\n", flumap.VTL); + msg_pdbg("VTBA (base address) = 0x%6.6x\n", desc_addr.VTBA()); + msg_pdbg("\n"); + + for (i=0; i < flumap.VTL/2; i++) + { + uint32_t jid = flumap.vscc_table[i].JID; + uint32_t vscc = flumap.vscc_table[i].VSCC; + msg_pdbg(" JID%d = 0x%8.8x\n", i, jid); + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, vscc); + msg_pdbg(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg(" "); /* indention */ + prettyprint_ich9_reg_vscc(vscc); + } +} + +int read_ich_descriptors_from_dump(uint32_t *dump) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; + + /* region */ + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; + + /* master */ + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; + + /* upper map */ + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < flumap.VTL; i++) + { + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; + } + /* straps */ + /* FIXME: detect chipset correctly */ + switch (CHIPSET_SERIES_5_IBEX_PEAK) { + case CHIPSET_ICH8: + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_from_fdo(void *spibar) +{ + msg_pdbg("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* descriptor map section */ + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); + fcba.FLILL = read_descriptor_reg(1, 1, spibar); + fcba.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* strap section and upper map */ + /* impossible via FDOC/FDOD(?) */ + msg_pdbg(" done\n"); +} + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..627852d --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,447 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +/* should probably be in ichspi.h */ +#define msg_pdbg2 msg_pspew + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +void prettyprint_ich9_reg_vscc(uint32_t reg_val); + +enum chipset { + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_descriptor_addresses { + uint32_t (*FCBA)(void); + uint32_t (*FRBA)(void); + uint32_t (*FMBA)(void); + uint32_t (*FMSBA)(void); + uint32_t (*FLREG_limit)(uint32_t flreg); + uint32_t (*FLREG_base)(uint32_t flreg); + uint32_t (*FISBA)(void); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t (*VTBA)(void); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +}; + +struct flash_descriptor { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint8_t FCBA :8; + uint8_t NC :2; + unsigned :6; + uint8_t FRBA :8; + uint8_t NR :3; + unsigned :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint8_t FMBA :8; + uint8_t NM :3; + unsigned :5; + union { + uint8_t FISBA :8; + uint8_t FPSBA :8; + }; + uint8_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint8_t FMSBA :8; + uint8_t MSL :8; + unsigned :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint8_t comp1_density :3; + uint8_t comp2_density :3; + unsigned :11; + uint8_t freq_read :3; + uint8_t fastread :1; + uint8_t freq_fastread :3; + uint8_t freq_write :3; + uint8_t freq_read_id :3; + unsigned :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint8_t invalid_instr0; + uint8_t invalid_instr1; + uint8_t invalid_instr2; + uint8_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint16_t FPBA :13; + unsigned :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint16_t reg0_base :13; + unsigned :3; + uint16_t reg0_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint16_t reg1_base :13; + unsigned :3; + uint16_t reg1_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint16_t reg2_base :13; + unsigned :3; + uint16_t reg2_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint16_t reg3_base :13; + unsigned :3; + uint16_t reg3_limit :13; + unsigned :3; + }; + }; +} frba; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint16_t BIOS_req_ID :16; + uint8_t BIOS_descr_read :1; + uint8_t BIOS_BIOS_read :1; + uint8_t BIOS_ME_read :1; + uint8_t BIOS_GbE_read :1; + uint8_t BIOS_plat_read :1; + unsigned :3; + uint8_t BIOS_descr_write :1; + uint8_t BIOS_BIOS_write :1; + uint8_t BIOS_ME_write :1; + uint8_t BIOS_GbE_write :1; + uint8_t BIOS_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint16_t ME_req_ID :16; + uint8_t ME_descr_read :1; + uint8_t ME_BIOS_read :1; + uint8_t ME_ME_read :1; + uint8_t ME_GbE_read :1; + uint8_t ME_plat_read :1; + unsigned :3; + uint8_t ME_descr_write :1; + uint8_t ME_BIOS_write :1; + uint8_t ME_ME_write :1; + uint8_t ME_GbE_write :1; + uint8_t ME_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint16_t GbE_req_ID :16; + uint8_t GbE_descr_read :1; + uint8_t GbE_BIOS_read :1; + uint8_t GbE_ME_read :1; + uint8_t GbE_GbE_read :1; + uint8_t GbE_plat_read :1; + unsigned :3; + uint8_t GbE_descr_write :1; + uint8_t GbE_BIOS_write :1; + uint8_t GbE_ME_write :1; + uint8_t GbE_GbE_write :1; + uint8_t GbE_plat_write :1; + unsigned :3; + }; + }; +}; + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + struct { + union { + uint32_t STRP0; + struct { + uint8_t ME_DISABLE :1; + unsigned :6; + uint8_t TCOMODE :1; + uint8_t ASD :7; + uint8_t BMCMODE :1; + unsigned :3; + uint8_t GLAN_PCIE_SEL :1; + uint8_t GPIO12_SEL :2; + uint8_t SPICS1_LANPHYPC_SEL :1; + uint8_t MESM2SEL :1; + unsigned :1; + uint8_t ASD2 :7; + }; + }; + union { + uint32_t STRP1; + struct { + uint8_t ME_disable_B :1; + unsigned :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + union { + uint32_t STRP0; + struct { + unsigned :1; + uint8_t cs_ss2 :1; + unsigned :5; + uint8_t SMB_EN :1; + uint8_t SML0_EN :1; + uint8_t SML1_EN :1; + uint8_t SML1FRQ :2; + uint8_t SMB0FRQ :2; + uint8_t SML0FRQ :2; + unsigned :4; + uint8_t LANPHYPC_GP12_SEL :1; + uint8_t cs_ss1 :1; + unsigned :2; + uint8_t DMI_REQID_DIS :1; + unsigned :4; + uint8_t BBBS :2; + unsigned :1; + }; + }; + union { + uint32_t STRP1; + struct { + }; + }; + union { + uint32_t STRP2; + struct { + }; + }; + union { + uint32_t STRP3; + struct { + }; + }; + union { + uint32_t STRP4; + struct { + }; + }; + union { + uint32_t STRP5; + struct { + }; + }; + union { + uint32_t STRP6; + struct { + }; + }; + union { + uint32_t STRP7; + struct { + }; + }; + union { + uint32_t STRP8; + struct { + }; + }; + union { + uint32_t STRP9; + struct { + }; + }; + union { + uint32_t STRP10; + struct { + }; + }; + union { + uint32_t STRP11; + struct { + }; + }; + union { + uint32_t STRP12; + struct { + }; + }; + union { + uint32_t STRP13; + struct { + }; + }; + union { + uint32_t STRP14; + struct { + }; + }; + union { + uint32_t STRP15; + struct { + }; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint8_t VTBA :8; + uint8_t VTL :8; + unsigned :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + unsigned :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint8_t ubes :2; + uint8_t uwg :1; + uint8_t uwsr :1; + uint8_t uwews :1; + unsigned :3; + uint8_t ueo :8; + uint8_t lbes :2; + uint8_t lwg :1; + uint8_t lwsr :1; + uint8_t lwews :1; + unsigned :3; + uint16_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptors(void); + +void prettyprint_ich_descriptor_map(void); +void prettyprint_ich_descriptor_component(void); +void prettyprint_ich_descriptor_region(void); +void prettyprint_ich_descriptor_master(void); + +int getFCBA_component_density(uint8_t comp); + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptor_upper_map(void); +void prettyprint_ich_descriptor_straps(enum chipset cs); +int read_ich_descriptors_from_dump(uint32_t *dump); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void read_ich_descriptors_from_fdo(void *spibar); + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 26522a5..45151d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,6 +42,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -131,6 +133,14 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same fields are also used in the + * flash descriptors to define the properties of the different flash chips + * supported by the BIOS image. These descriptors are also the source for the + * registers above. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -293,7 +303,7 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -313,8 +323,6 @@ static void pretty_print_opcodes(OPCODES *ops) } } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) - static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -676,7 +684,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -1208,6 +1216,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1279,6 +1288,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1327,9 +1338,25 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); + if (ichspi_desc) { + read_ich_descriptors_from_fdo(ich_spibar); + prettyprint_ich_descriptors(); + } ich_init_opcodes(); break; default: diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..0592b67 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain dump arrays +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to NOT share object files with flashrom, +# which would lead to unexpected results otherwise (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..6c6aa03 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,226 @@ +/* + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + * + * */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "flash.h" +#include "ich_descriptors.h" + +extern struct flash_descriptor fdbar; +extern struct flash_component fcba; +extern struct flash_region frba; +extern struct flash_master fmba; +extern struct flash_strap fisba; +extern struct flash_upper_map flumap; +extern struct flash_descriptor_addresses desc_addr; + +static int f; /* file descriptor to flash file */ +static int fs; /* file size */ +static uint32_t *fm; /* mmap'd file */ + +void dump_file_descriptor(char * fn) +{ + char * n = malloc(strlen(fn) + 11); + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); + if (ret != frba.reg0_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_BIOS(char * fn) +{ + char * n = malloc(strlen(fn) + 10); + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); + if (ret != frba.reg1_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_ME(char * fn) +{ + char * n = malloc(strlen(fn) + 8); + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); + if (ret != frba.reg2_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_GbE(char * fn) +{ + char * n = malloc(strlen(fn) + 9); + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); + if (ret != frba.reg3_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + + close(fh); +} + +void dump_files(char * n) +{ + printf("=== dumping section files ===\n"); + if (frba.reg0_limit) + dump_file_descriptor(n); + if (frba.reg1_limit) + dump_file_BIOS(n); + if (frba.reg2_limit) + dump_file_ME(n); + if (frba.reg3_limit) + dump_file_GbE(n); +} + +void usage(char ** argv, char* error) +{ + printf("%s\n", error); + printf("\n"); + printf("usage: '%s <bios image file> [-d]'\n", argv[0]); + printf("\n"); + printf("\twhere <bios image file> isn't actually a BIOS image, but the SPI flash\n"); + printf("\tcontents of the SPI connected to your intel chipset.\n"); + printf("\tIn case that image is really in descriptor mode (a.k.a soft-strap)\n"); + printf("\t%s will pretty print all relevant information.\n", argv[0]); + printf("\tIf '-d' is specified as the second parameter some sections such as\n"); + printf("\tthe real BIOS image as seen by the CPU or a GbE blob that is\n"); + printf("\trequired to initialize your ICH GbE are also dumped to files.\n"); + exit(1); +} + +int main(int argc, char **argv) +{ + if (argc < 2) + usage(argv, "Need at least one parameter"); + f = open(argv[1], O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + if (argc >= 3 && (strcmp("-d", argv[2]) == 0)) + usage(argv, "Bogus second argument"); + + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) + { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image is %d [0x%x] bytes\n", fs, fs); + close(f); + + if(read_ich_descriptors_from_dump(fm)){ + printf("not in descriptor mode\n"); + exit(1); + } + + prettyprint_ich_descriptors(); + + if (argc >= 3) + dump_files(argv[1]); + + return 0; +} + -- 1.7.1

1 0

[PATCH 5/8] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 28 Jun '11

28 Jun '11

- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions NB: this changes the semantic of the *run_opcode functions a bit: previously they could trash the chipset registers following the data registers because there was no (explicit) length check (it was and is checked by the dispatching run_opcode method). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 116 ++++++++++++++++++++++++++++++-------------------------------- 1 files changed, 56 insertions(+), 60 deletions(-) diff --git a/ichspi.c b/ichspi.c index 19e52d2..26522a5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -592,6 +592,55 @@ static void ich_set_bbar(uint32_t min_addr) msg_perr("Setting BBAR failed!\n"); } +/* Reads up to len byte from the fdata/spid register into the data array. + * The amount actually read is limited by the maximum read size of the + * chipset. */ + static void ich_read_data(uint8_t *data, uint8_t len, int reg0_off) + { + int a; + uint32_t temp32 = 0; + + if (len > spi_programmer->max_data_read) + len = spi_programmer->max_data_read; + + for (a = 0; a < len; a++) { + if ((a % 4) == 0) + temp32 = REGREAD32(reg0_off + (a)); + + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) + >> ((a % 4) * 8); + } +} + +/* Fills up to len bytes from the data array into the fdata/spid registers. + * The amount actually written is limited by the maximum write size of the + * chipset and is returned by the function on success. Negative values indicate + * an error. */ +static uint8_t ich_fill_data(const uint8_t *data, uint8_t len, int reg0_off) +{ + uint32_t temp32 = 0; + int a; + + if (len > spi_programmer->max_data_write) + len = spi_programmer->max_data_write; + + for (a = 0; a < len; a++) { + if ((a % 4) == 0) { + temp32 = 0; + } + + temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); + + if ((a % 4) == 3) { + REGWRITE32(reg0_off + (a - (a % 4)), temp32); + } + } + if (((a - 1) % 4) != 3) { + REGWRITE32(reg0_off + ((a - 1) - ((a - 1) % 4)), temp32); + } + return len; +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -638,9 +687,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +712,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -765,15 +795,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, } if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } + ich_read_data(data, datalength, ICH7_REG_SPID0); } return 0; @@ -785,7 +807,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +831,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -917,15 +921,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } + ich_read_data(data, datalength, ICH9_REG_FDATA0); } return 0; -- 1.7.1

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[PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Stefan Tauner 28 Jun '11

28 Jun '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/ichspi.c b/ichspi.c index f35ea37..19e52d2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -659,10 +659,11 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into SPIA while preserving reserved bits. */ + temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; + REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); - /* Program data into FDATA0 to N */ + /* Program data into SPID0 to N */ if (write_cmd && (datalength != 0)) { temp32 = 0; for (a = 0; a < datalength; a++) { @@ -803,8 +804,10 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, return 1; } - /* Programm Offset in Flash into FADDR */ - REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ + /* Program offset in flash into FADDR while preserve the reserved bits + * and clearing the 25. address bit which is only useable in hwseq. */ + temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ if (write_cmd && (datalength != 0)) { -- 1.7.1

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[PATCH 3/8] ichspi.c: add FPB (Flash Partition Boundary) macros and init printing
by Stefan Tauner 28 Jun '11

28 Jun '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 7e777f1..f35ea37 100644 --- a/ichspi.c +++ b/ichspi.c @@ -131,6 +131,10 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ +#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ +#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -1324,6 +1328,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 2/8] ichspi.c: simplify ich_set_bbar
by Stefan Tauner 28 Jun '11

28 Jun '11

less code, documenting better what the differences are (i.e. offset of BBAR only). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 +++++++++++++++++++++--------------------------- 1 files changed, 21 insertions(+), 27 deletions(-) diff --git a/ichspi.c b/ichspi.c index a78034a..7e777f1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -555,43 +555,37 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(uint32_t min_addr) { - minaddr &= BBAR_MASK; + int bbar_off; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0x50); - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = 0x50; break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; - if (ichspi_bbar) - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_off = ICH9_REG_BBAR; break; default: msg_perr("Unknown chipset for BBAR setting!\n"); - break; + return; + } + + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; + if (ichspi_bbar) { + msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", + ichspi_bbar); } + min_addr &= BBAR_MASK; + ichspi_bbar |= min_addr; + rmmio_writel(ichspi_bbar, ich_spibar + bbar_off); + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK; + + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ + if (ichspi_bbar != min_addr) + msg_perr("Setting BBAR failed!\n"); } /* This function generates OPCODES from or programs OPCODES to ICH according to -- 1.7.1

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[PATCH 1/8] ichspi.c: make REGWRITE* macros safer
by Stefan Tauner 28 Jun '11

28 Jun '11

'+' does have a quite high precedence so "calling" those macros with a term including weaker operators in the off parameter may have unexpected consequences Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ichspi.c b/ichspi.c index b4eb236..a78034a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -216,9 +216,9 @@ static uint16_t REGREAD8(int X) return mmio_readb(ich_spibar + X); } -#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off) -#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off) -#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off) +#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off)) +#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off)) +#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off)) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); -- 1.7.1

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[PATCH 0/8] ichspi 6.0
by Stefan Tauner 28 Jun '11

28 Jun '11

hwseq does use all data registers now with the help of new refactored read/write functions which are also used for swseq in all versions. main problem remains descriptor decoding (not new changes in this set). dhendrix: i was pretty tired so i fear that the quality of the previous one could be maintained, beware ;) Stefan Tauner (8): ichspi.c: make REGWRITE* macros safer ichspi.c: simplify ich_set_bbar ichspi.c: add FPB (Flash Partition Boundary) macros and init printing ichspi.c: preserve reserved bits in address registers ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding ichspi:c add support for Intel Hardware Sequencing squash! ichspi:c add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 490 +++++++++++++++++++ ich_descriptors.h | 447 +++++++++++++++++ ichspi.c | 552 +++++++++++++++++----- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 +++++++++ 11 files changed, 1685 insertions(+), 112 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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