- flashrom - mail.coreboot.org

FlashRom and Intel C204 chipset.
by Andrey V. Bondarenko 12 Oct '11

12 Oct '11

Hello, Verbose output is in the attachment file for chipset Intel C204. I sent this e-mail because it was suggested to send report. # ./flashrom --read ./P8B-E-4L-ASUS-0602.ROM flashrom v0.9.4-r1395 on Linux 2.6.18-274.3.1.el5.028stab094.3 (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-51), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel C204". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. Found Winbond flash chip "W25Q64" (8192 kB, SPI) at physical address 0xff800000. Reading flash... Transaction error! Read operation failed! FAILED.

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Re: [flashrom] Add timeout check to SPI bitbang bus request
by GatoLoko 11 Oct '11

11 Oct '11

-------- Mensaje original -------- Asunto: Re: [flashrom] Add timeout check to SPI bitbang bus request Fecha: Tue, 11 Oct 2011 16:22:17 +0200 De: GatoLoko <GatoLoko(a)gmail.com> Para: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> El 11/10/11 14:42, Carl-Daniel Hailfinger escribió: > Here is an updated timeout patch (no functional changes for > nicintel_spi). A year has passed, and I'm still trying to find someone > who can test and ack it. > > GatoLoko: This new patch also addresses the SB600 timeout issue you were > seeing. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested it, and seems to work, but the timeout feels a little too long. It took half an hour to complete a pass where no chip was found. The chip is a MX25L4005APC-12G. There was a few "strange" messages, don't know if they are related. The messages are: "Not unmapping zero size at 0xffffffffffffffff" and: """ Probing for ST M25P40-old, 512 kB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 Writing: SB600 FIFO pointer is 0, wanted 0 Executing: SB600: execute_command timeout! sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 Writing: [00][00][00] SB600 FIFO pointer corruption! Pointer is 0, wanted 3 Something else is accessing the flash chip and causes random corruption. Please stop all applications and drivers and IPMI which access the flash chip. sb600_spi_send_command, cmd=ab, writecnt=3, readcnt=1 Writing: [00][00][00] SB600 FIFO pointer corruption! Pointer is 0, wanted 3 Something else is accessing the flash chip and causes random corruption. Please stop all applications and drivers and IPMI which access the flash chip. """ Attached is a full pass log. -- GatoLoko

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Re: [flashrom] Problem with coreboot and flashrom
by Bernd Blaauw 10 Oct '11

10 Oct '11

Op 10-10-2011 17:57, Николай Пономарев schreef: > I was flashed bios with coreboot and after that network card, usb, > video card not working. flashrom not working too, it start flash bios > and stop at probing chip. Can anybody help me? > Mother board: http://www.gigabyte.ru/products/page/mb/ga-ma78gm-s2h_11 You're likely best off flashing back to vendor BIOS and/or replacing the BIOS flash chip (eeprom) by another one containing the motherboard manufacturer's BIOS. Alternatively a 2nd machine might help in performing a so-called hotswap. I've got no usage experience with CoreBoot (only reading their mailinglist archives), don't know if your board is supported at all (and if not, hopefully you've got a BIOS backup chip), and you're likely best off asking the Coreboot mailing list. Flashrom can often write Coreboot firmware, but also motherboard vendor firmware (bios/uefi). That might be one of the reasons that it's not that related/integrated to the Coreboot project anymore as it once was. Goodluck unbricking your BIOS. Some experimenting inside of QEMU might work, pity there's no ready-to-run 'coreboot-linux' harddisk image file (or virtual machine) available for download, to run directly under QEMU.

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Problem with coreboot and flashrom
by Николай Пономарев 10 Oct '11

10 Oct '11

I was flashed bios with coreboot and after that network card, usb, video card not working. flashrom not working too, it start flash bios and stop at probing chip. Can anybody help me? Mother board: http://www.gigabyte.ru/products/page/mb/ga-ma78gm-s2h_11

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M2N-X
by Mladen Pejaković 09 Oct '11

09 Oct '11

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Re: [flashrom] flashrom -V on Zotac MAG Ion
by Stefan Tauner 07 Oct '11

07 Oct '11

On Fri, 7 Oct 2011 12:47:40 +0100 Aidan Samuel <aidan.samuel(a)gmail.com> wrote: > Oh ok. That's just the version I got using apt-get on ubuntu. > hi yes, that's outdated... there will be 0.9.4 in the upcoming ubuntu 11.10. you can probably use the package from that with your current installation by installing it by hand (dpkg -i ...deb) or using apt pinning. http://packages.ubuntu.com/oneiric/flashrom -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] flashrom -V on Zotac MAG Ion
by Stefan Tauner 07 Oct '11

07 Oct '11

On Fri, 7 Oct 2011 10:35:09 +0100 Aidan Samuel <aidan.samuel(a)gmail.com> wrote: > Running on a Zotac MAG Ion: > > flashrom v0.9.1-r946 hi that's over two years old, please try at least 0.9.4 (or current subversion HEAD). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom -V on Zotac MAG Ion
by Aidan Samuel 07 Oct '11

07 Oct '11

Running on a Zotac MAG Ion: flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "To be filled by O.E.M." DMI string baseboard-product-name: "To be filled by O.E.M." DMI string baseboard-version: "To be filled by O.E.M." DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xfae80000, after clearing low bits BAR is at 0xfae80000 Mapping MCP67 SPI at 0xfae80000, unaligned size 0x544. SPI control is 0xc05a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 799M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

Re: [flashrom] Intel DQ67SW report
by Stefan Tauner 07 Oct '11

07 Oct '11

On Thu, 6 Oct 2011 13:51:03 +0300 Dima Tisnek <dimaqq(a)gmail.com> wrote: > root@quilt ~ # flashrom -Vr test.fw > flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci > […] > 0x54: 0x00000000 (FREG0: Flash Descriptor) > 0x00000000-0x00000fff is read-only > 0x58: 0x07ff0580 (FREG1: BIOS) > 0x00580000-0x007fffff is read-write > 0x5C: 0x057f0003 (FREG2: Management Engine) > 0x00003000-0x0057ffff is locked > 0x60: 0x00020001 (FREG3: Gigabit Ethernet) > 0x00001000-0x00002fff is read-write > 0x64: 0x00001fff (FREG4: Platform Data) > Platform Data region is unused. > […] > > Reading flash... Transaction error! > SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 > SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=4 > Running OPCODE 0x03 failed at address 0x003000 (payload length was 64). > Read operation failed! > FAILED. hello dima and thanks for your report! a part of the flash is locked by the chipset and we are not able to unlock it (yet). in case you want to update the firmware please use the tools from intel, sorry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

XFX MI-9300-7AS9
by j b 07 Oct '11

07 Oct '11

flashrom v0.9.2-r1141 on Linux 2.6.38-11-generic (x86_64), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2992M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 10020 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "XFX" DMI string system-product-name: "MI-9300-7AS9" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "XFX" DMI string baseboard-product-name: "MI-9300-7AS9" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8720 Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aac, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 MCP SPI BAR is at 0xfae80000 SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x13 No operations were specified.

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Re: [flashrom] Results of -rV on an Asus A8V-E SE running Asus Bios 001
by Stefan Tauner 06 Oct '11

06 Oct '11

On Tue, 27 Sep 2011 17:16:19 -0400 David Pascoe-Deslauriers <dpascoed(a)csiuo.com> wrote: > flashrom v0.9.1-r946 hello david and thanks for your report. the version you have used is 2 years old and your mainboard as well as the flash chip was already reported to be fully supported with newer versions. also, please do not post any bios images to the mailing list again. they potentially contain copyrighted material (the instructions themselves) and neither you nor we are allowed to distribute it, which could theoretically get us in legal trouble. we usually do not need them and they are usually available on the web somewhere anyway (e.g. vendor website). posting a link to it is of course allowed and appreciated. thanks again! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Intel DQ67SW report
by Dima Tisnek 06 Oct '11

06 Oct '11

root@quilt ~ # flashrom -Vr test.fw flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1995M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10004 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ67SW" DMI string baseboard-version: "AAG12527-309" DMI string chassis-type: "Desktop" Found chipset "Intel Q67" with PCI ID 8086:1c4e. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 Root Complex Register Block address = 0xfed1c000 GCS = 0xc25: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00003000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x07ff0580 (FREG1: BIOS) 0x00580000-0x007fffff is read-write 0x5C: 0x057f0003 (FREG2: Management Engine) 0x00003000-0x0057ffff is locked 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xfc0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=4 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Reading OPCODES... done preop0=0x06, preop1=0x00 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 0 op[5]=0x01, 1, 0 op[6]=0x00, 0, 0 op[7]=0x00, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF040A.RES, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x5d, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x5d, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Chip status register is 00 Found Winbond flash chip "W25Q64" (8192 kB, SPI) at physical address 0xff800000. Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x39, id2 0x44, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=4 Running OPCODE 0x03 failed at address 0x003000 (payload length was 64). Read operation failed! FAILED. Restoring PCI config space for 00:1f:0 reg 0xdc root@quilt ~ #

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[PATCH 6/6] Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 06 Oct '11

06 Oct '11

additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities Intel thinks this information should be confidential for ICH9 and up, but references some tidbits in their public documentation. This patch includes the human-readable information for ICH8, Ibex Peak (5 series) and Cougar Point (6 series); the latter two were obtained from leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9 and 10 is unknown to us yet. It can probably found in: "Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide" Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 532 ++++++++++++++++++++++ ich_descriptors.h | 327 +++++++++++++ util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++++ 5 files changed, 1132 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index 125077c..3fd731f 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,9 +22,33 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +#include <stdio.h> +#define msg_perr printf +#define msg_pdbg printf +#define msg_pdbg2 printf +#define msg_pspew printf +#define print(t, ...) printf(__VA_ARGS__) +#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a +/* The upper map is located in the word before the 256B-long OEM section at the + * end of the 4kB-long flash descriptor. + */ +#define UPPER_MAP_OFFSET (4096 - 256 - 4) +#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0) + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + #include "flash.h" /* for msg_* */ #include "programmer.h" +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + +#ifndef min +#define min(a, b) (a < b) ? a : b +#endif + void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); @@ -47,6 +71,12 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descripto prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, desc); + } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ } void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) @@ -213,6 +243,507 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc) +{ + static const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + + msg_pdbg2("--- MCH details ---\n"); + msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en"); + msg_pdbg2("\n"); + + msg_pdbg2("--- ICH details ---\n"); + msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD); + msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2); + msg_pdbg2("ME SMBus Controller is connected to the %s.\n", + desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s.\n", + desc->south.ich8.SPICS1_LANPHYPC_SEL ? + "LAN PHY Power Control Function" : + "SPI Chip Select"); + msg_pdbg2("GPIO12 is used as %s.\n", + str_GPIO12[desc->south.ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s.\n", + desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express"); + msg_pdbg2("%sn BMC Mode: " + "Intel AMT SMBus Controller 1 is connected to %s.\n", + desc->south.ich8.BMCMODE ? "I" : "Not i", + desc->south.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO is in %s Mode.\n", + desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible"); + msg_pdbg2("ME A is %sabled.\n", + desc->south.ich8.ME_DISABLE ? "dis" : "en"); + msg_pdbg2("\n"); +} + +static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t off) +{ + msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); + + off *= 4; + switch(conf){ + case 0: + msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); + break; + case 1: + msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), " + "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off); + break; + case 2: + msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports " + "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off); + break; + case 3: + msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)", + 1+off, 2+off, 4+off); + break; + } + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_pchstraps45678_56(const struct ich_desc_south_strap *s) +{ + /* PCHSTRP4 */ + msg_pdbg2("Intel PHY is %s.\n", + (s->ibex.PHYCON == 2) ? "connected" : + (s->ibex.PHYCON == 0) ? "disconnected" : "reserved"); + msg_pdbg2("GbE MAC SMBus address is %sabled.\n", + s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis"); + msg_pdbg2("GbE MAC SMBus address: 0x%02x\n", + s->ibex.GBEMAC_SMBUS_ADDR); + msg_pdbg2("GbE PHY SMBus address: 0x%02x\n", + s->ibex.GBEPHY_SMBUS_ADDR); + + /* PCHSTRP5 */ + /* PCHSTRP6 */ + /* PCHSTRP7 */ + msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + + /* PCHSTRP8 */ +} + +void prettyprint_ich_descriptor_pchstraps111213_56(const struct ich_desc_south_strap *s) +{ + /* PCHSTRP11 */ + msg_pdbg2("SMLink1 GP Address is %sabled.\n", + s->ibex.SML1GPAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n", + s->ibex.SML1GPA); + msg_pdbg2("SMLink1 I2C Target address is %sabled.\n", + s->ibex.SML1I2CAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n", + s->ibex.SML1I2CA); + + /* PCHSTRP12 */ + /* PCHSTRP13 */ +} + +void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s) +{ + static const uint8_t const dec_t209min[4] = { + 100, + 50, + 5, + 1 + }; + + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP0 */ + msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->ibex.cs_ss1); + msg_pdbg2("DMI RequesterID Checks are %sabled.\n", + s->ibex.DMI_REQID_DIS ? "en" : "dis"); + msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n", + 1 << (6 + s->ibex.BBBS)); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + + /* PCHSTRP2 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP3 */ + prettyprint_ich_descriptor_pchstraps45678_56(s); + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5); + msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n", + s->ibex.VE_EN ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n", + s->ibex.MMDDE ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n", + s->ibex.MMADDR); + msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7); + msg_pdbg2("Integrated Clocking Configuration is %d.\n", + (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + + prettyprint_ich_descriptor_pchstraps111213_56(s); + + /* PCHSTRP14 */ + msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n", + s->ibex.VE_EN2 ? "en" : "dis"); + msg_pdbg2("Virtualization Engine will boot from %sflash.\n", + s->ibex.VE_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Braidwood SSD functionality is %sabled.\n", + s->ibex.BW_SSD ? "en" : "dis"); + msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n", + s->ibex.NVMHCI_EN ? "en" : "dis"); + + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6); + msg_pdbg2("Integrated wired LAN Solution is %sabled.\n", + s->ibex.IWL_EN ? "en" : "dis"); + msg_pdbg2("t209 min Timing: %d ms\n", + dec_t209min[s->ibex.t209min]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_cougar(const struct ich_desc_south_strap *s) +{ + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP0 */ + msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->cougar.cs_ss1); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + msg_pdbg2("LinkSec is %sabled.\n", + s->cougar.LINKSEC_DIS ? "en" : "dis"); + msg_pdbg2("DMI RequesterID Checks are %sabled.\n", + s->ibex.DMI_REQID_DIS ? "en" : "dis"); + msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n", + 1 << (6 + s->ibex.BBBS)); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + msg_pdbg2("Chipset configuration Softstrap 2: 0x%x\n", s->ibex.cs_ss2); + + /* PCHSTRP2 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus MCTP Address is %sabled.\n", + s->cougar.MESMMCTPAEN ? "en" : "dis"); + msg_pdbg2("ME SMBus MCTP target address: 0x%02x\n", + s->cougar.MESMMCTPA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP3 */ + prettyprint_ich_descriptor_pchstraps45678_56(s); + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("ME Debug status writes over SMBUS are %sabled.\n", + s->cougar.MDSMBE_EN ? "en" : "dis"); + msg_pdbg2("ME Debug SMBus Emergency Mode address: 0x%02x (raw)\n", + s->cougar.MDSMBE_ADD); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + msg_pdbg2("PCIe ports Subtractive Decode Agent is %sabled.\n", + s->cougar.SUB_DECODE_EN ? "en" : "dis"); + msg_pdbg2("GPIO74 is used as %s.\n", s->cougar.PCHHOT_SML1ALERT_SEL ? + "PCHHOT#" : "SML1ALERT#"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + + msg_pdbg2("ME Debug SMBus Emergency Mode is %sabled.\n", + s->cougar.MDSMBE_EN ? "en" : "dis"); + msg_pdbg2("ME Debug SMBus Emergency Mode Address: 0x%02x\n", + s->cougar.MDSMBE_ADD); + + msg_pdbg2("Integrated Clocking Configuration used: %d\n", + s->cougar.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + msg_pdbg2("ICC Profile is selected by %s.\n", + s->cougar.ICC_PRO_SEL ? "Softstraps" : "BIOS"); + msg_pdbg2("Deep SX is %ssupported on the platform.\n", + s->cougar.Deep_SX_EN ? "not " : ""); + msg_pdbg2("ME Debug LAN Emergency Mode is %sabled.\n", + s->cougar.ME_DBG_LAN ? "en" : "dis"); + + prettyprint_ich_descriptor_pchstraps111213_56(s); + + /* PCHSTRP14 */ + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->cougar.cs_ss6); + msg_pdbg2("Integrated wired LAN is %sabled.\n", + s->cougar.IWL_EN ? "en" : "dis"); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->cougar.cs_ss5); + msg_pdbg2("SMLink1 provides temperature from %s.\n", + s->cougar.SMLINK1_THERM_SEL ? + "PCH only" : "the CPU, PCH and DIMMs"); + msg_pdbg2("GPIO29 is used as %s.\n", s->cougar.SLP_LAN_GP29_SEL ? + "general purpose output" : "SLP_LAN#"); + + /* PCHSTRP16 */ + /* PCHSTRP17 */ + msg_pdbg2("Integrated Clock: %s Clock Mode\n", + s->cougar.ICML ? "Buffered Through" : "Full Integrated "); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + unsigned int i, max; + msg_pdbg2("=== Softstraps ===\n"); + + if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { + max = sizeof(desc->north.STRPs) / 4 + 1; + msg_pdbg2("MSL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.MSL, max + 1); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.MSL; + + msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max); + for (i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); + msg_pdbg2("\n"); + + if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { + max = sizeof(desc->south.STRPs) / 4; + msg_pdbg2("ISL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.ISL, max); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.ISL; + + msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max); + for (i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]); + msg_pdbg2("\n"); + + switch (cs) { + case CHIPSET_ICH8: + if (sizeof(desc->north.ich8) / 4 != desc->content.MSL) + msg_pdbg2("Detailed North/MCH/PROC information is " + "probably not reliable, printing anyway.\n"); + if (sizeof(desc->south.ich8) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ich8(desc); + break; + case CHIPSET_5_SERIES_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + if (sizeof(desc->south.ibex) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ibex(&desc->south); + break; + case CHIPSET_6_SERIES_COUGAR_POINT: + /* PCH straps only. PROCSTRP0 is "reserved". */ + if (sizeof(desc->south.cougar) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_cougar(&desc->south); + break; + case CHIPSET_ICH_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown " + "yet.\n\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap) +{ + int i; + msg_pdbg2("=== Upper Map Section ===\n"); + msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2); + for (i = 0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%08x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich_reg_vscc(vscc, 0); + } + msg_pdbg2("\n"); +} + +/* len is the length of dump in bytes */ +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc) +{ + unsigned int i, max; + uint8_t pch_bug_offset = 0; + + if (dump == NULL || desc == NULL) + return ICH_RET_PARAM; + + if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) { + if (dump[4] == DESCRIPTOR_MODE_SIGNATURE) + pch_bug_offset = 4; + else + return ICH_RET_ERR; + } + + /* map */ + if (len < (4 + pch_bug_offset) * 4 - 1) + return ICH_RET_OOB; + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + return ICH_RET_OOB; + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + return ICH_RET_OOB; + desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; + desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + + /* master */ + if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + return ICH_RET_OOB; + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; + + /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide: + * "Identifies the 1s based number of DWORDS contained in the VSCC + * Table. Each SPI component entry in the table is 2 DWORDS long." So + * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A + * check ensures that the maximum offset actually accessed is available. + */ + if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + return ICH_RET_OOB; + + for (i = 0; i < desc->upper.VTL/2; i++) { + desc->upper.vscc_table[i].JID = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + + /* MCH/PROC (aka. North) straps */ + if (len < getFMSBA(&desc->content) + desc->content.MSL * 4) + return ICH_RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + for (i = 0; i < max; i++) + desc->north.STRPs[i] = + dump[(getFMSBA(&desc->content) >> 2) + i]; + + /* ICH/PCH (aka. South) straps */ + if (len < getFISBA(&desc->content) + desc->content.ISL * 4) + return ICH_RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + for (i = 0; i < max; i++) + desc->south.STRPs[i] = + dump[(getFISBA(&desc->content) >> 2) + i]; + + return ICH_RET_OK; +} + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + /** Returns the integer representation of the component density with index idx in bytes or 0 if a correct size can not be determined. */ int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) @@ -313,4 +844,5 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) msg_pdbg2(" done.\n"); return ICH_RET_OK; } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h index 4e2ad0a..e3e9b6f 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -240,11 +240,329 @@ struct ich_desc_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_DUMP +struct ich_desc_north_strap { + union { + uint32_t STRPs[1]; /* current maximum: ich8 */ + struct { /* ich8 */ + struct { /* STRP2 (in the datasheet) */ + uint32_t MDB :1, + :31; + }; + } ich8; + }; +}; + +struct ich_desc_south_strap { + union { + uint32_t STRPs[16]; /* current maximum: ibex peak */ + struct { /* ich8 */ + struct { /* STRP1 */ + uint32_t ME_DISABLE :1, + :6, + TCOMODE :1, + ASD :7, + BMCMODE :1, + :3, + GLAN_PCIE_SEL :1, + GPIO12_SEL :2, + SPICS1_LANPHYPC_SEL :1, + MESM2SEL :1, + :1, + ASD2 :7; + }; + } ich8; + struct { /* ibex peak */ + struct { /* STRP0 */ + uint32_t :1, + cs_ss2 :1, + :5, + SMB_EN :1, + SML0_EN :1, + SML1_EN :1, + SML1FRQ :2, + SMB0FRQ :2, + SML0FRQ :2, + :4, + LANPHYPC_GP12_SEL :1, + cs_ss1 :1, + :2, + DMI_REQID_DIS :1, + :4, + BBBS :2, + :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4, + :28; + }; + struct { /* STRP2 */ + uint32_t :8, + MESMASDEN :1, + MESMASDA :7, + :8, + MESMI2CEN :1, + MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2, + :6, + GBEMAC_SMBUS_ADDR_EN :1, + GBEMAC_SMBUS_ADDR :7, + :1, + GBEPHY_SMBUS_ADDR :7, + :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16, + MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2, + PCIEPCS2 :2, + PCIELR1 :1, + PCIELR2 :1, + DMILR :1, + :1, + PHY_PCIEPORTSEL :3, + PHY_PCIE_EN :1, + :20; + }; + struct { /* STRP10 */ + uint32_t :1, + ME_BOOT_FLASH :1, + cs_ss5 :1, + VE_EN :1, + :4, + MMDDE :1, + MMADDR :7, + cs_ss7 :1, + :1, + ICC_SEL :3, + MER_CL1 :1, + :10; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1, + SML1GPA :7, + :16, + SML1I2CAEN :1, + SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :8, + VE_EN2 :1, + :5, + VE_BOOT_FLASH :1, + :1, + BW_SSD :1, + NVMHCI_EN :1, + :14; + }; + struct { /* STRP15 */ + uint32_t :3, + cs_ss6 :2, + :1, + IWL_EN :1, + :1, + t209min :2, + :22; + }; + } ibex; + struct { /* cougar point */ + struct { /* STRP0 */ + uint32_t :1, + cs_ss1 :1, + :5, + SMB_EN :1, + SML0_EN :1, + SML1_EN :1, + SML1FRQ :2, + SMB0FRQ :2, + SML0FRQ :2, + :4, + LANPHYPC_GP12_SEL :1, + LINKSEC_DIS :1, + :2, + DMI_REQID_DIS :1, + :4, + BBBS :2, + :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4, + :4, + cs_ss2 :1, + :28; + }; + struct { /* STRP2 */ + uint32_t :8, + MESMASDEN :1, + MESMASDA :7, + MESMMCTPAEN :1, + MESMMCTPA :7, + MESMI2CEN :1, + MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2, + :6, + GBEMAC_SMBUS_ADDR_EN :1, + GBEMAC_SMBUS_ADDR :7, + :1, + GBEPHY_SMBUS_ADDR :7, + :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16, + MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2, + PCIEPCS2 :2, + PCIELR1 :1, + PCIELR2 :1, + DMILR :1, + cs_ss4 :1, + PHY_PCIEPORTSEL :3, + PHY_PCIE_EN :1, + :2, + SUB_DECODE_EN :1, + :7, + PCHHOT_SML1ALERT_SEL :1, + :9; + }; + struct { /* STRP10 */ + uint32_t :1, + ME_BOOT_FLASH :1, + :6, + MDSMBE_EN :1, + MDSMBE_ADD :7, + :2, + ICC_SEL :3, + MER_CL1 :1, + ICC_PRO_SEL :1, + Deep_SX_EN :1, + ME_DBG_LAN :1, + :7; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1, + SML1GPA :7, + :16, + SML1I2CAEN :1, + SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :32; + }; + struct { /* STRP15 */ + uint32_t cs_ss6 :6, + IWL_EN :1, + cs_ss5 :2, + :4, + SMLINK1_THERM_SEL :1, + SLP_LAN_GP29_SEL :1, + :16; + }; + struct { /* STRP16 */ + uint32_t :32; + }; + struct { /* STRP17 */ + uint32_t ICML :1, + cs_ss7 :1, + :30; + }; + } cougar; + }; +}; + +struct ich_desc_upper_map { + union { + uint32_t FLUMAP1; /* Flash Upper Map 1 */ + struct { + uint32_t VTBA :8, /* ME VSCC Table Base Address */ + VTL :8, /* ME VSCC Table Length */ + :16; + }; + }; + struct { + union { /* JEDEC-ID Register */ + uint32_t JID; + struct { + uint32_t vid :8, /* Vendor ID */ + cid0 :8, /* Component ID 0 */ + cid1 :8, /* Component ID 1 */ + :8; + }; + }; + union { /* Vendor Specific Component Capabilities */ + uint32_t VSCC; + struct { + uint32_t ubes :2, /* Upper Block/Sector Erase Size */ + uwg :1, /* Upper Write Granularity */ + uwsr :1, /* Upper Write Status Required */ + uwews :1, /* Upper Write Enable on Write Status */ + :3, + ueo :8, /* Upper Erase Opcode */ + lbes :2, /* Lower Block/Sector Erase Size */ + lwg :1, /* Lower Write Granularity */ + lwsr :1, /* Lower Write Status Required */ + lwews :1, /* Lower Write Enable on Write Status */ + :3, + leo :16; /* Lower Erase Opcode */ + }; + }; + } vscc_table[128]; +}; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + struct ich_descriptors { struct ich_desc_content content; struct ich_desc_component component; struct ich_desc_region region; struct ich_desc_master master; +#ifdef ICH_DESCRIPTORS_FROM_DUMP + struct ich_desc_north_strap north; + struct ich_desc_south_strap south; + struct ich_desc_upper_map upper; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ }; void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); @@ -254,8 +572,17 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc); + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..1af90ce --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS += -Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..03701bf --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,6 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly +- little endian only diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..da580da --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *basename, const uint32_t *dump, unsigned int len, struct ich_desc_region *reg, unsigned int i) +{ + int ret; + char *fn; + const char *reg_name; + uint32_t file_len; + const char *const region_names[5] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform" + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + + reg_name = region_names[i]; + if (base > limit) { + printf("The %s region is unused and thus not dumped.\n", + reg_name); + return; + } + + limit = limit | 0x0fff; + file_len = limit + 1 - base; + if (base + file_len > len) { + printf("The %s region is spanning 0x%08x-0x%08x, but it is " + "not (fully) included in the image (0-0x%08x), thus not " + "dumped.\n", reg_name, base, limit, len - 1); + return; + } + + fn = malloc(strlen(basename) + strlen(reg_name) + strlen(".bin") + 2); + if (!fn) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(fn, strlen(basename) + strlen(reg_name) + strlen(".bin") + 2, + "%s.%s.bin", basename, reg_name); + printf("Dumping %u bytes of the %s region from 0x%08x-0x%08x to %s... ", + file_len, region_names[i], base, limit, fn); + int fh = open(fn, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(fn); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", fn, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[base >> 2], file_len); + if (ret != file_len) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *buf, unsigned int len, struct ich_desc_region *reg) +{ + unsigned int i; + printf("=== Dumping region files ===\n"); + for (i = 0; i < 5; i++) + dump_file(n, buf, len, reg, i); + printf("\n"); +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd; /* file descriptor to flash file */ + int len; /* file/buffer size in bytes */ + uint32_t *buf; /* mmap'd file */ + + int opt; + int ret; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; + struct ich_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + fd = open(fn, O_RDONLY); + if (fd < 0) + usage(argv, "No such file"); + len = lseek(fd, 0, SEEK_END); + if (len < 0) + usage(argv, "Seeking to the end of the file failed"); + + buf = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + buf = malloc(len); + if (!buf) + usage(argv, "Could not allocate memory"); + lseek(fd, 0, SEEK_SET); + ret = read(fd, buf, len); + if (ret != len) + usage(argv, "Seeking to the end of the file failed"); + } + printf("The flash image has a size of %d [0x%x] bytes.\n", len, len); + close(fd); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_5_SERIES_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_6_SERIES_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_7_SERIES_PANTHER_POINT; + } + + ret = read_ich_descriptors_from_dump(buf, len, cs, &desc); + switch (ret) { + case ICH_RET_OK: + break; + case ICH_RET_ERR: + printf("Image not in descriptor mode.\n"); + exit(1); + case ICH_RET_OOB: + printf("Tried to access a location out of bounds of the image. " + "- Corrupt image?\n"); + exit(1); + default: + printf("Unhandled return value at %s:%u, please report this.\n", + __FILE__, __LINE__); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + //uint8_t *pMAC = (uint8_t *) &buf[r->reg3_base >> 2]; + //printf("The MAC-address might be: %02x:%02x:%02x:%02x:%02x:%02x\n", + //pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); + + if (dump == 1) + dump_files(fn, buf, len, &desc.region); + + return 0; +} + -- 1.7.1

1 0

[PATCH 5/6] ichspi: warn if regions defined by FREGs do not cover the whole flash space
by Stefan Tauner 06 Oct '11

06 Oct '11

the chipset will deny any access to addresses outside the defined regions and these registers are RO even if the configuration is not locked down. this usually indicates a broken BIOS/flash descriptor and can only mitigated by not accessing addresses outside the regions with a layout file. the implementation is not for merge. most of the routines should probably be moved to layout.c or similar and integrated with a generic layout entry data structure (think of a struct that is able to hold all information needed to define one line of a (future) layout file i.e. address range, name, access rights, lock status etc.). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 136 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index fd42ba3..896ac5e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1446,6 +1446,118 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) +struct range { + uint32_t offset; + uint32_t size; + struct range *next; +}; + +static void prettyprint_range_list(struct range *cur) +{ + unsigned int i = 0; + while (cur != NULL) { + msg_pspew("#%d: offset=0x%08x, size=0x%08x\n", + i++, cur->offset, cur->size); + cur = cur->next; + } +} + +/* Frees every element in the list */ +static void free_range_list(struct range *cur) +{ + struct range *next; + while (cur != NULL) { + next = cur->next; + free(cur); + cur = next; + } +} + +/* Unifies a *sorted* list of ranges. This means that overlapping regions are + * combined to a single region. The given list r is modifed and returned. + */ +static struct range *unify_range_list(struct range *const r) +{ + struct range *cur = r; + struct range *next; + while (cur != NULL && cur->next != NULL) { + next = cur->next; + if (cur->offset + cur->size >= next->offset) { + cur->size = next->offset + next->size - cur->offset; + cur->next = next->next; + free(next); + } else + cur = cur->next; + } + return r; +} + +/* Unifies two *sorted* lists of ranges into a third one. + * Returns the newly allocated third list, or NULL if inputs are empty lists or + * an error occurred. + */ +static struct range *unify_range_lists(struct range *const r1, struct range *const r2) +{ + struct range *cur = NULL; + struct range *new = NULL; + struct range *cur1 = r1; + struct range *cur2 = r2; + + /* first, iterate over all entries from the first range. + * compare them to the lowest, unprocessed element of the second one + * and copy the one with the smaller offset over to the new list. + * this ensures that the new list is sorted all the time. + */ + while (cur1 != NULL) { + /* first element of the new list handled as special case */ + if (cur == NULL) { + cur = malloc(sizeof(struct range)); + new = cur; + } else { + cur->next = malloc(sizeof(struct range)); + cur = cur->next; + } + if (cur == NULL) { + free_range_list(new); + return NULL; + } + cur->next = NULL; + if (cur2 == NULL || cur1->offset < cur2->offset) { + cur->offset = cur1->offset; + cur->size = cur1->size; + cur1 = cur1->next; + } else { + cur->offset = cur2->offset; + cur->size = cur2->size; + cur2 = cur2->next; + } + } + + /* then copy over the remaining elements from the second list */ + while (cur2 != NULL) { + /* first element of the new list handled as special case */ + if (cur == NULL) { + cur = malloc(sizeof(struct range)); + new = cur; + } else { + cur->next = malloc(sizeof(struct range)); + cur = cur->next; + } + if (cur == NULL) { + free_range_list(new); + return NULL; + } + cur->next = NULL; + cur->offset = cur2->offset; + cur->size = cur2->size; + cur2 = cur2->next; + } + + return unify_range_list(new); +} + +static struct range *ich_ranges = NULL; + static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1456,6 +1568,7 @@ static void do_ich9_spi_frap(uint32_t frap, int i) "Gigabit Ethernet", "Platform Data" }; uint32_t base, limit; + struct range cur; int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | (((ICH_BRRA(frap) >> i) & 1) << 0); int offset = ICH9_REG_FREG0 + i * 4; @@ -1472,6 +1585,11 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } + cur.size = (limit | 0x0fff) + 1 - base; + cur.offset = base; + cur.next = NULL; + + ich_ranges = unify_range_lists(ich_ranges, &cur); msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), access_names[rwperms]); } @@ -1675,6 +1793,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Decode and print FREGx and FRAP registers */ for (i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); + prettyprint_range_list(ich_ranges); } /* try to disable PR locks before printing them */ @@ -1732,6 +1851,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); { /* to be able to declare variables here */ struct ich_descriptors desc = {{ 0 }}; + uint32_t flash_size; if (desc_valid) { if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) @@ -1758,11 +1878,27 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } hwseq.size_comp0 = getFCBA_component_density(&desc, 0); hwseq.size_comp1 = getFCBA_component_density(&desc, 1); + flash_size = hwseq.size_comp0 + hwseq.size_comp1; register_spi_programmer(&spi_programmer_ich_hwseq); } else { + flash_size = getFCBA_component_density(&desc, 0); register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); } + if (ich_ranges != NULL) + if (ich_ranges->next != NULL || + ich_ranges->offset != 0 || + ich_ranges->size != flash_size) + msg_pinfo("WARNING: The regions defined by the " + "FREG registers do not cover the " + "whole flash\naddress space. The " + "chipset will deny access to any " + "address outside the defined\n" + "regions. Please use a layout file " + "to mitigate this and send us a log " + "with maximum\nverbosity (-VVV) to " + "flashrom(a)flashrom.org, thanks!\n\n"); + } ich_init_opcodes(); break; -- 1.7.1

1 0

[PATCH 4/6] ichspi: print flash descriptor dependent information only when it is valid
by Stefan Tauner 06 Oct '11

06 Oct '11

also, fix some coding style issues Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 61 ++++++++++++++++++++++++++++++++++--------------------------- 1 files changed, 34 insertions(+), 27 deletions(-) diff --git a/ichspi.c b/ichspi.c index 88042d1..fd42ba3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1074,7 +1074,7 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { int i; msg_pspew("The data was:\n"); - for(i=0; i<count; i++){ + for (i = 0; i < count; i++){ msg_pspew("%3d: 0x%02x\n", i, data[i]); } } @@ -1655,28 +1655,33 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, "effect. Please note that Protected\n" "Range (PR) restrictions still apply.\n"); - tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); - msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); - prettyprint_ich9_reg_hsfc(tmp2); + if (desc_valid) { + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); + } tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); - tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); + if (desc_valid) { + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* Decode and print FREGx and FRAP registers */ + for (i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + } /* try to disable PR locks before printing them */ if (!ichspi_lock) - for(i = 0; i < 5; i++) + for (i = 0; i < 5; i++) ich9_set_pr(i, 0, 0); - for(i = 0; i < 5; i++) + for (i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i); tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); @@ -1697,7 +1702,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - if (ich_generation == 8) { + if (ich_generation == 8 && desc_valid) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); @@ -1706,20 +1711,22 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + ich_set_bbar(ich_generation, 0); - tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); - msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); - msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + if (desc_valid) { + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); - tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); - msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); - msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); - ich_set_bbar(ich_generation, 0); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } } msg_pdbg("\n"); -- 1.7.1

1 0

[PATCH 3/6] compile fix for hwseq due to reverting the "unsignify" patch
by Stefan Tauner 06 Oct '11

06 Oct '11

separated because i hope we can unsignify soonish :P Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 4 ++-- ichspi.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 03ff3e6..9865022 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -89,9 +89,9 @@ int unlock_lh28f008bjt(struct flashchip *flash); /* ichspi.c */ int ich_hwseq_probe(struct flashchip *flash); -int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* jedec.c */ uint8_t oddparity(uint8_t val); diff --git a/ichspi.c b/ichspi.c index 5db5b83..88042d1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1293,7 +1293,7 @@ int ich_hwseq_block_erase(struct flashchip *flash, return 0; } -int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int addr, unsigned int len) +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; @@ -1337,7 +1337,7 @@ int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int addr, uns return 0; } -int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, unsigned int addr, unsigned int len) +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) { uint16_t hsfc; uint16_t timeout = 100 * 60; -- 1.7.1

1 0

[PATCH 2/6] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 06 Oct '11

06 Oct '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 ++ flashchips.c | 23 +++++- flashchips.h | 2 + ichspi.c | 281 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- programmer.h | 1 + 5 files changed, 309 insertions(+), 4 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 958c59a..03ff3e6 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -87,6 +87,12 @@ int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); int unlock_lh28f008bjt(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index d520a1c..054e25a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8872,7 +8872,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -9005,6 +9025,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index 2c939e4..eb66ab9 100644 --- a/flashchips.h +++ b/flashchips.h @@ -348,6 +348,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ichspi.c b/ichspi.c index 08d73db..5db5b83 100644 --- a/ichspi.c +++ b/ichspi.c @@ -28,6 +28,8 @@ #include <string.h> #include <stdlib.h> #include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include "ich_descriptors.h" @@ -1081,7 +1083,11 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -#if 0 +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { @@ -1150,7 +1156,231 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } return 0; } -#endif + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} static int ich_spi_send_multicommand(struct spi_command *cmds) { @@ -1315,6 +1545,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1322,7 +1562,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int desc_valid = 0; + int hwseq_en = 0; switch (ich_generation) { case 7: @@ -1389,6 +1631,14 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case 9: case 10: default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1473,15 +1723,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } msg_pdbg("\n"); + { /* to be able to declare variables here */ + struct ich_descriptors desc = {{ 0 }}; if (desc_valid) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + hwseq_en = 1; + } + } + + + if (hwseq_en) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return 1; + } + hwseq.size_comp0 = getFCBA_component_density(&desc, 0); + hwseq.size_comp1 = getFCBA_component_density(&desc, 1); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); } + } ich_init_opcodes(); break; } diff --git a/programmer.h b/programmer.h index 73b94c1..67a9cdc 100644 --- a/programmer.h +++ b/programmer.h @@ -520,6 +520,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 1/6] ichspi: add (partially) dead support code for Intel Hardware Sequencing
by Stefan Tauner 06 Oct '11

06 Oct '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 28 +++++++++++++++ ich_descriptors.h | 1 + ichspi.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 114 insertions(+), 13 deletions(-) diff --git a/ich_descriptors.c b/ich_descriptors.c index da1326e..125077c 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -213,6 +213,34 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) +{ + uint8_t size_enc; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only ICH SPI component index 0 or 1 are supported " + "yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of ICH SPI component with index %d is " + "invalid. Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return (1 << (19 + size_enc)); +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; diff --git a/ich_descriptors.h b/ich_descriptors.h index 886fc7c..4e2ad0a 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -255,6 +255,7 @@ void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index e30c267..08d73db 100644 --- a/ichspi.c +++ b/ichspi.c @@ -26,6 +26,7 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" #include "programmer.h" #include "spi.h" @@ -1080,6 +1081,77 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +#if 0 +/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. May return nonsense if the address is + * not valid. The erase block size for a specific address depends on the flash + * partition layout as specified by FPB and the partition properties as defined + * by UVSCC and LVSCC respectively. An alternative to implement this method + * would be by querying FPB and the respective VSCC register directly. + */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout >>= 3; /* equals /= 8; scale timeout duration to counter */ + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(8); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} +#endif + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1250,21 +1322,18 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; - int ichspi_desc = 0; + int desc_valid = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1275,8 +1344,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1313,9 +1382,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } ich_set_bbar(ich_generation, 0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1324,8 +1397,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } if (tmp2 & HSFS_FDV) - ichspi_desc = 1; - if (!(tmp2 & HSFS_FDOPSS) && ichspi_desc) + desc_valid = 1; + if (!(tmp2 & HSFS_FDOPSS) && desc_valid) msg_pinfo("The Flash Descriptor Security Override " "Strap-Pin is set. Restrictions implied\n" "by the FRAP and FREG registers are NOT in " @@ -1400,18 +1473,17 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } msg_pdbg("\n"); - if (ichspi_desc) { + if (desc_valid) { struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); } ich_init_opcodes(); break; - default: - /* Nothing */ - break; } old = pci_read_byte(dev, 0xdc); -- 1.7.1

1 0

[PATCH 0/6] ichspi 9.0
by Stefan Tauner 06 Oct '11

06 Oct '11

hwseq is split and hopefully i have addressed all triaged problems. there are some open questions in my last mail (201109181517.p8IFHdlp027261(a)mail2.student.tuwien.ac.at) though. 4/6 is new and cuts down unnecessary output in the case of non-descriptor mode boards. 5/6 is also new, but not finished, see specific commit log for details please. there were long periods between edits and the major part of the changes were made with quite some headache, be aware please. :) Stefan Tauner (6): ichspi: add (partially) dead support code for Intel Hardware Sequencing ichspi: add support for Intel Hardware Sequencing compile fix for hwseq due to reverting the "unsignify" patch ichspi: print flash descriptor dependent information only when it is valid ichspi: warn if regions defined by FREGs do not cover the whole flash space Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 560 +++++++++++++++++++++ ich_descriptors.h | 328 +++++++++++++ ichspi.c | 572 ++++++++++++++++++++-- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++++ 10 files changed, 1723 insertions(+), 42 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

Fujitsu Esprimo P9900 (locked ME region)
by Stefan Tauner 04 Oct '11

04 Oct '11

hi there regarding your question on IRC and this log: http://paste.flashrom.org/view.php?id=840 your board (vendor) has locked a region of the flash, which we can not unlock. intel does not provide the necessary information to us, but only hardware vendors and bios programmers. can you please elaborate what you want to accomplish exactly? if the Management Engine region is not important to you, i have a few patches that would allow you to read the other regions. you can read a bit about the problem here: http://blogs.coreboot.org/blog/2011/08/17/gsoc-2011-flashrom-part-5-–-dear-… and on our email archive: http://www.flashrom.org/pipermail/flashrom/ please note that this mail is also addressed to our mailing list, and your reply will (probably) also be sent there. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Parted Magic 6.7
by Heino Goldenstein 04 Oct '11

04 Oct '11

Hello, Parted Magic 6.7 is available. http://partedmagic.com/doku.php?id=changelog root@PartedMagic:~# flashrom flashrom v0.9.4-r1394 on Linux 3.0.4-pmagic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian Tjuess Heino

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Intel SCH Poulsbo
by MONDON Daniel 04 Oct '11

04 Oct '11

Hi! Flashrom V0.9.4-r1395 results: Found chipset « Intel SCH Poulsbo” Found SST flash chip “SST49LF008A” (1024kB, FWM) @ 0xfff00000 I am under TCL (TinyCore Linux). Flashing Bios is OK, but erasing flash need many loops to erase all flash (from 0x1000 to 0xFF000 = 256 loops). But sometimes, it is ok in one time. What can I do to increase erasing speed (times) … or is there any known bug … perhaps increasing timeout … or ? Thanks Daniel. Daniel MONDON Ingénieur d'applications LPG SYSTEMS 30, rue du Docteur Abel BP 35 26902 VALENCE Cedex 9 Tel: +33475786881 Fax: +33475786953 http://www.lpgsystems.fr  Merci de penser à l'environnement avant d'imprimer ce message

3 2

flashrom -V : MSI 890GXM-G65
by Steven Ballagh 03 Oct '11

03 Oct '11

Please see attached output file

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Re: [flashrom] FAILED: GeForce6100PM-M2
by Stefan Tauner 02 Oct '11

02 Oct '11

this was fixed by retry (or so :), see below for the log of the IRC conversation. * cupantae (~mark@*) has joined #flashrom <cupantae> I tried to update my bios but now even the writing the backup gives an error. What can I do? <cupantae> I have emailed flashrom(a)flashrom.org with the report <idwer> first thing to not do is reboot, second thing is to upload the whole output to http://paste.flashrom.org <cupantae> ok. done <cupantae> i'm not sure if this is helpful, but at the "VERIFY FAILED", it gave a different reason each time <cupantae> first it was at 0x000acd00! Expected=0x23, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0xfe <cupantae> then at 0x00029400! Expected=0x12, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0x1fc <cupantae> then at 0x00067700! Expected=0x2f, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0x4ea <cupantae> oh wait, but always 0xff <agaran> what machine it is <cupantae> it's there in http://paste.flashrom.org <cupantae> it's a geforce6100pm-m2 <agaran> video card? <cupantae> no that's the name of the motherboard <cupantae> named after the onboard graphics, it would seem <agaran> hmm, i never tried upgrading bios on such combo board, but if on internal programmer you get changing reads its *WEIRD* <agaran> cupantae: can you dump few times actual flash content to new file each time (and not overwriting first backup), then calc md5 over those and show us? <cupantae> you mean with flashrom -r? <agaran> yes <cupantae> ok <agaran> but please do not overwrite backup <cupantae> ok. i'm starting "dump1" <cupantae> without flashing the rom in between, the md5 stayed the same <cupantae> 625ad915d91e7b134b48aef0105a640b <cupantae> currently flashing again with the updated version of the bios <agaran> so it fails on write but in different things <agaran> so now it worked? <cupantae> well, attempting to flash, i suppose i should say <agaran> ok, so verification now against backup passes? <cupantae> oh my god, it verified this time <cupantae> i didn't change anything, so is it reasonable to be nervous about rebooting? <agaran> so if you did backup and assuming read is always correct then i should its quite safe <agaran> but still i would be somewhat uncertain why it failed at different addresses each time on verify <cupantae> it does seem strange. that said, i'm not at all familiar with this stuff :-) <agaran> it is strange <cupantae> the output is the same before the verifying stage, btw <cupantae> between the working and failing attempts <cupantae> anyway, i suppose i don't need your help any more! thanks for your time <cupantae> so will i reboot and tell you if it worked? * cupantae has quit (Quit: rebooting) * cupantae (~mark@*) has joined #flashrom <cupantae> agaran: back on post-reboot. <cupantae> seems like a fairly shitty "upgrade" but what harm :-P <cupantae> thanks for all the support! * cupantae has quit (Client Quit) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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FAILED: GeForce6100PM-M2
by Mark O'Neill 02 Oct '11

02 Oct '11

Output of # flashrom -V: **************************** flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1001M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1006 us, 10000 myus = 10017 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "GeForce6100PM-M2" DMI string system-version: "2.0" DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "GeForce6100PM-M2" DMI string baseboard-version: "2.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Super I/O ID 0x8726 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x13 No operations were specified. *************************************************************** And then the output of # flashrom -w 61M23526.ROM: *************************************************************** flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFY FAILED at 0x000acd00! Expected=0x23, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0xfe Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! ******************************************************************************************** I had made a backup, but the same happened upon attempting to reinstate this: ******************************************************************************************** flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found Winbond flash chip "W25X80" (1024 kB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFY FAILED at 0x00029400! Expected=0x12, Read=0xff, failed byte count from 0x00000000-0x000fffff: 0x1fc Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! ************** Help please! Mark

1 0

Zotac Fusion350-A (ZOTAC Fusion ITX WiFi)
by Arve Seljebu 01 Oct '11

01 Oct '11

Works. Attached output from -V -Vr and -Vw.

2 1

Re: [flashrom] My first question...
by Bernd Blaauw 01 Oct '11

01 Oct '11

Op 30-9-2011 19:09, Marcos Felipe Rasia de Mello schreef: >> I get differences with the previous one. I haven't enter in the bios or change >> anything... I was expecting no differences between them. Am I missing >> anything? >> >> Regards >> Jorge > > http://flashrom.org/Random_notes#Bios_content_changes_between_reboots It might be usefull if Flashrom gets a percentage counter: 'file savebios.bin is 99.3% identical to EEPROM contents, continue at your own risk. It's also 50.0 % identical to file asusbios.bin' instead of something along the lines of 'verification failed, file is corrupt'. Above example would also require a way to reference a 2nd file to verify against. Let's say that 2nd file is an internet-downloaded original motherboard vendor's BIOS instead of a flashrom dumped file. After all, people might want to check if flashrom works correctly before writing anything. What better way than dump current bios, compare dumped file to bios but also compare to vendor bios file. All 3 should be (near-)identical.

3 2

Re: [flashrom] ECS P4VXMS (V1.0A) - OK
by Stefan Tauner 30 Sep '11

30 Sep '11

On Mon, 19 Sep 2011 18:23:00 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > The flash chip is a Winbond W49F002U-12B. > > BIOS "vxmsv12c.BIN" from: > http://www.ecs.com.tw/ECSWebSite/Downloads/Downloads_Driver_Detail.aspx?det… > > Attached the verbose logs and lspci output. > > Marcos Hello Marcos, Thanks for your report! I have marked the chipset as OK and added the ECS P4VXMS (V1.0A) to the list of supported boards. I will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] My first question...
by Marcos Felipe Rasia de Mello 30 Sep '11

30 Sep '11

2011/9/30 Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> > > Hi, > > I'm using flashrom to save the bios from my system to a file. > I've seen an unexpected behaviour and I would like to know if it's ok. > > If I run: > > # flashrom --read bios_1st.bin > # flashrom --read bios_2nd.bin > > comparing both files I can't find any difference, but If I reboot the system and > then: > > # flashrom --read bios_3rd.bin > > I get differences with the previous one. I haven't enter in the bios or change > anything... I was expecting no differences between them. Am I missing > anything? > > Regards > Jorge http://flashrom.org/Random_notes#Bios_content_changes_between_reboots Marcos

1 0

ASRock ALiveNF5-eSATA2+: flashrom -V
by James 30 Sep '11

30 Sep '11

$ sudo flashrom -V flashrom v0.9.4-r1395 on Linux 3.0.4 (x86_64), built with libpci 3.1.7, GCC 4.5.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 649M loops per second, delay more than 10% too short (got 52% of expected delay), recalculating... 842M loops per second, delay more than 10% too short (got 66% of expected delay), recalculating... 597M loops per second, delay more than 10% too short (got 62% of expected delay), recalculating... 749M loops per second, delay more than 10% too short (got 74% of expected delay), recalculating... 822M loops per second, delay loop is unreliable, trying to continue 10 myus = 8 us, 100 myus = 64 us, 1000 myus = 646 us, 10000 myus = 6992 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "ALiveNF5-eSATA2+ " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP65" with PCI ID 10de:0441. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Found Winbond flash chip "W39V040B" (512 kB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

1 0

My first question...
by Jorge Fernandez Monteagudo 30 Sep '11

30 Sep '11

Hi, I'm using flashrom to save the bios from my system to a file. I've seen an unexpected behaviour and I would like to know if it's ok. If I run: # flashrom --read bios_1st.bin # flashrom --read bios_2nd.bin comparing both files I can't find any difference, but If I reboot the system and then: # flashrom --read bios_3rd.bin I get differences with the previous one. I haven't enter in the bios or change anything... I was expecting no differences between them. Am I missing anything? Regards Jorge Este mensaje se dirige exclusivamente a su destinatario y puede contener información privilegiada o CONFIDENCIAL. Si no es vd. el destinatario indicado, queda notificado de que la utilización, divulgación y/o copia sin autorización está prohibida en virtud de la legislación vigente. Si ha recibido este mensaje por error, le rogamos que nos lo comunique inmediatamente por esta misma vía y proceda a su destrucción. This message is intended exclusively for its addressee and may contain information that is CONFIDENTIAL and protected by professional privilege. If you are not the intended recipient you are hereby notified that any dissemination, copy or disclosure of this communication is strictly prohibited by law. If this message has been received in error, please immediately notify us via e-mail and delete it.

1 0

[patch] OSX universal binaries
by Mark Pustjens 29 Sep '11

29 Sep '11

Hi List, The included patch will cause flashrom to be built as a universal binary on osx. Included architectures are i386 and x86_64. Greetings/Groetjes Mark Pustjens -- Index: Makefile =================================================================== --- Makefile (revision 1450) +++ Makefile (working copy) @@ -43,9 +43,9 @@ STRIP_ARGS = -s endif ifeq ($(OS_ARCH), Darwin) -CPPFLAGS += -I/opt/local/include -I/opt/local/include -I/usr/local/include +CPPFLAGS += -arch i386 -arch x86_64 -I/opt/local/include -I/usr/local/include # DirectHW framework can be found in the DirectHW library. -LDFLAGS += -framework IOKit -framework DirectHW -L/opt/local/lib -L/usr/local/lib +LDFLAGS += -framework IOKit -framework DirectHW -L/usr/local/lib -arch i386 -arch x86_64 endif ifeq ($(OS_ARCH), FreeBSD) CPPFLAGS += -I/usr/local/include @@ -530,7 +530,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom.

1 0

Re: [flashrom] Results of -rV on an Asus A8V-E SE running Asus Bios 001
by Bernd Blaauw 28 Sep '11

28 Sep '11

Op 27-9-2011 23:16, David Pascoe-Deslauriers schreef: > This is from a Asus A8V-E SE running Asus Bios -01. > > root@valhalla:~# uname -a > Linux valhalla 2.6.32-33-generic #72-Ubuntu SMP Fri Jul 29 21:07:13 UTC > 2011 x86_64 GNU/Linux > > root@valhalla:~# flashrom -r current-mb-bios.bin -V > flashrom v0.9.1-r946 If you're willing/able to test your board against already released version 0.9.4 or latest trunk revision, you might get lucky enough if your board was added meanwhile. Thanks for the report, hopefully developers can use it :)

1 0

bitfield checker
by Carl-Daniel Hailfinger 26 Sep '11

26 Sep '11

Not a patch, and unfinished... I'd be interested in results of non-gcc compilers and/or non-i386 platforms. Will rework this once I have some more spare time. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

NVidia MCP73
by Koen Rousseau 24 Sep '11

24 Sep '11

1 0

Re: [flashrom] Macronix MX25L6445E
by Stefan Tauner 22 Sep '11

22 Sep '11

On Thu, 22 Sep 2011 09:40:22 +0200 "Wagner, Helge (GE Germany)" <Helge.Wagner(a)ge.com> wrote: > Hi all, > > did I miss your answer or didn't you write one yet? hello helge! our patch queue[1] is quite long and my summer work for flashrom made it even longer. your patch wont get lost, but it might take a while for it to be reviewed further and merged eventually, sorry. 1: http://patchwork.coreboot.org/project/flashrom/list/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] Macronix MX25L6445E
by Wagner, Helge (GE Germany) 22 Sep '11

22 Sep '11

Hi all, did I miss your answer or didn't you write one yet? Regards, Helge -----Original Message----- From: flashrom-bounces(a)flashrom.org [mailto:flashrom-bounces@flashrom.org] On Behalf Of Wagner, Helge (GE Germany) Sent: Dienstag, 19. Juli 2011 10:57 To: Stefan Reinauer; Carl-Daniel Hailfinger Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Macronix MX25L6445E Stefan, Did you use my latest patch (at http://www.flashrom.org/pipermail/flashrom/2011-June/007013.html )? Carl-Daniel, > >> To be sure that the spi_block_erase_20 works for both the MX25L6405 > >> and the MX25L6445E, we could change the block erase size from 64K > >> to 4K. This should work even for the MX25L6405, but with the side > >> effect of the erase taking longer than needed. This was the comment for my first try. > Sorry, but AFAICS this will cause chip corruption. To be exact, > specifying a too small eraseblock size (4 kB instead of 64 kB) means > that flashrom will walk the device in 4 kB blocks, erase each block > and write to it. Now if the actual erase block size is bigger than the > specified block size, you'll get this: And exactly because of that I have reworked the patch (see above). Regards, Helge -----Original Message----- From: Stefan Reinauer [mailto:stefan.reinauer@coreboot.org] Sent: Montag, 18. Juli 2011 23:49 To: Carl-Daniel Hailfinger Cc: Wagner, Helge (GE Germany); flashrom(a)flashrom.org Subject: Re: [flashrom] Macronix MX25L6445E * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> [110718 23:44]: > Am 18.07.2011 19:07 schrieb Stefan Reinauer: > > * Wagner, Helge (GE Intelligent Platforms) <Helge.Wagner(a)ge.com> [110527 15:46]: > > > >> To be sure that the spi_block_erase_20 works for both the MX25L6405 > >> and the MX25L6445E, we could change the block erase size from 64K > >> to 4K. This should work even for the MX25L6405, but with the side > >> effect of the erase taking longer than needed. > >> > >> > >> > >> Any comments? > >> > > > > works great for me! > > > > > >> Please find my patches included. > >> > >> Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> > >> > > Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> > > > > Sorry, but AFAICS this will cause chip corruption. To be exact, > specifying a too small eraseblock size (4 kB instead of 64 kB) means > that flashrom will walk the device in 4 kB blocks, erase each block > and write to it. Now if the actual erase block size is bigger than the > specified block size, you'll get this: Yes, I agree that changing the block erase size is risky. Good thing the patch does not change it, so it should be save to apply, plus it solves the problem. Stefan _______________________________________________ flashrom mailing list flashrom(a)flashrom.org http://www.flashrom.org/mailman/listinfo/flashrom

1 0

summary from EPoX EP-8KRAI-X
by Ben Taylor 22 Sep '11

22 Sep '11

Hello, stefanct requested I send this summary. My motherboard is a EPoX EP-8KRAI-X with a Winbond W49F002UP12B bios chip (with sticker "DP1"). http://paste.flashrom.org/view.php?id=834 As you can see, my eeprom is not detected. My goal is to update my bios with EPoX's latest version. I could provide that rom and EpoX's manual pdf if that would help you. Thanks, Ben Taylor (MacGuges)

2 1

Re: [flashrom] ReportFlashrom
by Stefan Tauner 20 Sep '11

20 Sep '11

On Wed, 14 Sep 2011 21:48:57 +0800 Boris Klimenko <bdostuk(a)gmail.com> wrote: > DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string system-product-name: "P67A-UD3P" > DMI string system-version: " " > DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string baseboard-product-name: "P67A-UD3P" > DMI string baseboard-version: "x.x" > DMI string chassis-type: "Desktop" > Found ITE Super I/O, ID 0x8728 on port 0x2e > Found chipset "Intel P67" with PCI ID 8086:1c46. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! Hello Boris, Thanks for your report! I have marked the chipset and mainboard as tested and will commit that later. There are two almost identical revisions of the mainboard (1.0 and 1.1). Just for the record... do you happen to know which version you got? Thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

ECS P4VXMS (V1.0A) - OK
by Marcos Felipe Rasia de Mello 19 Sep '11

19 Sep '11

The flash chip is a Winbond W49F002U-12B. BIOS "vxmsv12c.BIN" from: http://www.ecs.com.tw/ECSWebSite/Downloads/Downloads_Driver_Detail.aspx?det… Attached the verbose logs and lspci output. Marcos

1 0

Re: [flashrom] [PATCH] Unsignify lengths and addresses in chip functions and structs
by Carl-Daniel Hailfinger 19 Sep '11

19 Sep '11

Am 23.08.2011 17:12 schrieb Stefan Tauner: > compile tested with gcc 4.4.5 and clang 2.8 I agree with the idea and support it. However, I don't know how supportable this is on 16 bit platforms with 16 bit int. We need at least 24 bits to handle flash addresses, and we could either create a new typedef chipoffset_t or specify uint32_t explicitly. I favor a new typedef because it will make auditing easier if we ever run on 16 bit programmers. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> A comment about the typedef idea would be appreciated. Anyway, this is (even if you reject the explicit type idea) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

[commit] r1450 - trunk
by repository service 19 Sep '11

19 Sep '11

Author: stefanct Date: Mon Sep 19 00:42:18 2011 New Revision: 1450 URL: http://flashrom.org/trac/flashrom/changeset/1450 Log: Revert "Unsignify lengths and addresses in chip functions and structs" - probe_timing was changed to unsigned although we use negative values for special cases - some code was not changed along hence did no longer compile: * dediprog's read and write functions * linux_spi's read and write functions - it introduced a number of new sign conversion warnings (http://paste.flashrom.org/view.php?id=832) To be safe this patch reverts all changes made in r1448, a corrected patch will follow later. Thanks to idwer for pointing out the problem first! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/82802ab.c trunk/chipdrivers.h trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/it87spi.c trunk/jedec.c trunk/m29f400bt.c trunk/programmer.h trunk/serprog.c trunk/spi.c trunk/spi25.c trunk/sst28sf040.c trunk/wbsio_spi.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/82802ab.c Mon Sep 19 00:42:18 2011 (r1450) @@ -141,7 +141,7 @@ } /* chunksize is 1 */ -int write_82802ab(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) +int write_82802ab(struct flashchip *flash, uint8_t *src, int start, int len) { int i; chipaddr dst = flash->virtual_memory + start; Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/chipdrivers.h Mon Sep 19 00:42:18 2011 (r1450) @@ -41,9 +41,9 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_write_status_register(struct flashchip *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); @@ -51,12 +51,12 @@ void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashchip *flash); int spi_disable_blockprotect(struct flashchip *flash); -int spi_byte_program(unsigned int addr, uint8_t databyte); -int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len); -int spi_nbyte_read(unsigned int addr, uint8_t *bytes, unsigned int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int spi_byte_program(int addr, uint8_t databyte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); @@ -81,7 +81,7 @@ uint8_t wait_82802ab(struct flashchip *flash); int probe_82802ab(struct flashchip *flash); int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int write_82802ab(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_82802ab(struct flashchip *flash, uint8_t *buf, int start, int len); void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); @@ -94,8 +94,8 @@ int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); -int write_jedec_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_jedec_1(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); @@ -104,7 +104,7 @@ int probe_m29f400bt(struct flashchip *flash); int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); void protect_m29f400bt(chipaddr bios); /* pm49fl00x.c */ @@ -114,7 +114,7 @@ /* sst28sf040.c */ int erase_chip_28sf040(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_28sf040(struct flashchip *flash, uint8_t *buf, int start, int len); int unprotect_28sf040(struct flashchip *flash); int protect_28sf040(struct flashchip *flash); Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/dummyflasher.c Mon Sep 19 00:42:18 2011 (r1450) @@ -63,7 +63,7 @@ static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len); + int start, int len); static const struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, @@ -528,7 +528,7 @@ } static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len) + int start, int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/flash.h Mon Sep 19 00:42:18 2011 (r1450) @@ -108,9 +108,9 @@ uint32_t model_id; /* Total chip size in kilobytes */ - unsigned int total_size; + int total_size; /* Chip page size in bytes */ - unsigned int page_size; + int page_size; int feature_bits; /* @@ -122,7 +122,7 @@ int (*probe) (struct flashchip *flash); /* Delay after "enter/exit ID mode" commands in microseconds. */ - unsigned int probe_timing; + int probe_timing; /* * Erase blocks and associated erase function. Any chip erase function @@ -143,8 +143,8 @@ int (*printlock) (struct flashchip *flash); int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); - int (*read) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); struct { uint16_t min; uint16_t max; @@ -202,7 +202,7 @@ extern const char flashrom_version[]; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, const char *filename); @@ -210,7 +210,7 @@ int max(int a, int b); void tolower_string(char *str); char *extract_param(char **haystack, const char *needle, const char *delim); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/flashrom.c Mon Sep 19 00:42:18 2011 (r1450) @@ -564,7 +564,7 @@ flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } -int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) +int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) { chip_readn(buf, flash->virtual_memory + start, len); @@ -710,7 +710,7 @@ * @message string to print in the "FAILED" message * @return 0 for success, -1 for failure */ -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message) { int i; Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/it87spi.c Mon Sep 19 00:42:18 2011 (r1450) @@ -106,9 +106,9 @@ static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len); + int start, int len); static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len); + int start, int len); static const struct spi_programmer spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, @@ -340,7 +340,7 @@ * Need to read this big flash using firmware cycles 3 byte at a time. */ static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len) + int start, int len) { fast_spi = 0; @@ -358,7 +358,7 @@ } static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - unsigned int start, unsigned int len) + int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/jedec.c Mon Sep 19 00:42:18 2011 (r1450) @@ -355,7 +355,7 @@ } /* chunksize is 1 */ -int write_jedec_1(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) +int write_jedec_1(struct flashchip *flash, uint8_t *src, int start, int len) { int i, failed = 0; chipaddr dst = flash->virtual_memory + start; @@ -376,7 +376,7 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int page_size) +int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size) { int i, tried = 0, failed; uint8_t *s = src; @@ -424,7 +424,7 @@ * This function is a slightly modified copy of spi_write_chunked. * Each page is written separately in chunks with a maximum size of chunksize. */ -int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) +int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len) { int i, starthere, lenhere; /* FIXME: page_size is the wrong variable. We need max_writechunk_size Modified: trunk/m29f400bt.c ============================================================================== --- trunk/m29f400bt.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/m29f400bt.c Mon Sep 19 00:42:18 2011 (r1450) @@ -28,7 +28,7 @@ functions. */ /* chunksize is 1 */ -int write_m29f400bt(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) +int write_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/programmer.h Mon Sep 19 00:42:18 2011 (r1450) @@ -556,23 +556,23 @@ #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { enum spi_controller type; - unsigned int max_data_read; - unsigned int max_data_write; + int max_data_read; + int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ @@ -610,7 +610,7 @@ void serprog_delay(int delay); int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/serprog.c Mon Sep 19 00:42:18 2011 (r1450) @@ -795,7 +795,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int i; int cur_len; Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/spi.c Mon Sep 19 00:42:18 2011 (r1450) @@ -97,9 +97,9 @@ return result; } -int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - unsigned int max_data = spi_programmer->max_data_read; + int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -109,9 +109,9 @@ return spi_read_chunked(flash, buf, start, len, max_data); } -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - unsigned int max_data = spi_programmer->max_data_write; + int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -121,7 +121,7 @@ return spi_write_chunked(flash, buf, start, len, max_data); } -int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; if (!spi_programmer->read) { @@ -160,7 +160,7 @@ * .write_256 = spi_chip_write_1 */ /* real chunksize is up to 256, logical chunksize is 256 */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/spi25.c Mon Sep 19 00:42:18 2011 (r1450) @@ -844,7 +844,7 @@ return ret; } -int spi_byte_program(unsigned int addr, uint8_t databyte) +int spi_byte_program(int addr, uint8_t databyte) { int result; struct spi_command cmds[] = { @@ -879,7 +879,7 @@ return result; } -int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len) +int spi_nbyte_program(int addr, uint8_t *bytes, int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ @@ -954,7 +954,7 @@ return 0; } -int spi_nbyte_read(unsigned int address, uint8_t *bytes, unsigned int len) +int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -972,7 +972,7 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) { int rc = 0; int i, j, starthere, lenhere; @@ -1012,7 +1012,7 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) { int rc = 0; int i, j, starthere, lenhere; @@ -1061,7 +1061,7 @@ * (e.g. due to size constraints in IT87* for over 512 kB) */ /* real chunksize is 1, logical chunksize is 1 */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) { int i, result = 0; @@ -1076,7 +1076,7 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) { uint32_t pos = start; int result; Modified: trunk/sst28sf040.c ============================================================================== --- trunk/sst28sf040.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/sst28sf040.c Mon Sep 19 00:42:18 2011 (r1450) @@ -76,7 +76,7 @@ } /* chunksize is 1 */ -int write_28sf040(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) +int write_28sf040(struct flashchip *flash, uint8_t *src, int start, int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Sun Sep 18 17:15:31 2011 (r1449) +++ trunk/wbsio_spi.c Mon Sep 19 00:42:18 2011 (r1450) @@ -62,7 +62,7 @@ static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); static const struct spi_programmer spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, @@ -194,7 +194,7 @@ return 0; } -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); }

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Re: [flashrom] [PATCH 5/8] ichspi: add support for Intel Hardware Sequencing
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > todo: > - revise hwseq activation: when should hwseq be used, when swseq? > in the current version i have added a programmer parameter to tell flashrom when one > wants to use hwseq _if it is available_ (i.e. descriptor valid), example: > flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV > this needs to be documented in the man page if it gets merged like that. > - commit message (is a link to my blog post a good idea (additionally)?) We have no limits for the commit message size, but maybe we should start to package additional documentation with flashrom? > - revise (levels of) prints > - revise timeout values (for optimal performance) > - build upon the upcoming opaque interface framework instead I see all those TODOs, and most of them should be addressed before enabling the code. That's why I'd like to get most of this patch merged really soon except for the few places where the new code is hooked up. That way we get a much smaller remaining patch and the discussion about user interfaces and infrastructure are not attached to a megapatch, but rather to a small "hook up hwseq" patch. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > chipdrivers.h | 6 + > flashchips.c | 23 ++++- > flashchips.h | 2 + > ich_descriptors.c | 35 +++++ > ich_descriptors.h | 3 +- > ichspi.c | 357 +++++++++++++++++++++++++++++++++++++++++++++++++++-- > programmer.h | 1 + > 7 files changed, 414 insertions(+), 13 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 3f5b503..f3781ae 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -86,6 +86,12 @@ void print_status_82802ab(uint8_t status); > int unlock_82802ab(struct flashchip *flash); > int unlock_28f004s5(struct flashchip *flash); > > +/* ichspi.c */ > +int ich_hwseq_probe(struct flashchip *flash); > +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); > +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); Postpone this hunk for the hookup patch. > + > /* jedec.c */ > uint8_t oddparity(uint8_t val); > void toggle_ready_jedec(chipaddr dst); > diff --git a/flashchips.c b/flashchips.c > index 4d741a0..20f7197 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -8782,7 +8782,27 @@ const struct flashchip flashchips[] = { > .read = read_memmapped, > .voltage = {3000, 3600}, /* Also has 12V fast program */ > }, > - > +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > + { > + .vendor = "Intel", > + .name = "Hardware Sequencing", > + .bustype = BUS_SPI, > + .manufacture_id = INTEL_ID, > + .model_id = INTEL_HWSEQ, > + .total_size = 0, > + .page_size = 256, > + .tested = TEST_OK_PREW, > + .probe = ich_hwseq_probe, > + .block_erasers = > + { > + { /* erase blocks will be set by the probing function */ > + .block_erase = ich_hwseq_block_erase, > + } > + }, > + .write = ich_hwseq_write_256, > + .read = ich_hwseq_read, > + }, > +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) Postpone this hunk for the hookup patch. > { > .vendor = "AMIC", > .name = "unknown AMIC SPI chip", > @@ -8915,6 +8935,7 @@ const struct flashchip flashchips[] = { > .probe = probe_spi_rdid, > .write = NULL, > }, > + > { > .vendor = "Generic", > .name = "unknown SPI chip (REMS)", > diff --git a/flashchips.h b/flashchips.h > index ff49d31..1374b2f 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -346,6 +346,8 @@ > #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ > #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ > > +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ Postpone... > + > #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ > > /* > diff --git a/ich_descriptors.c b/ich_descriptors.c > index ce40d9f..8076b09 100644 > --- a/ich_descriptors.c > +++ b/ich_descriptors.c > @@ -214,6 +214,41 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) > msg_pdbg2("\n"); > } > > +/** Returns the integer representation of the component density with index > +idx in bytes or 0 if a correct size can not be determined. */ > +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) I'd prefer to have the order (desc, idx) for the parameters here. > +{ > + uint8_t size_enc; > + static const int const dec_mem[6] = { > + 512 * 1024, > + 1 * 1024 * 1024, > + 2 * 1024 * 1024, > + 4 * 1024 * 1024, > + 8 * 1024 * 1024, > + 16 * 1024 * 1024, > + }; Kill dec_mem and replace dec_mem[size_enc] with (1<<(19+size_enc)). > + > + switch(idx) { > + case 0: > + size_enc = desc->component.comp1_density; > + break; > + case 1: > + if (desc->content.NC == 0) If NC is shorthand for "not connected", this looks like inverted logic. > + return 0; > + size_enc = desc->component.comp2_density; > + break; > + default: > + msg_perr("Only component index 0 or 1 are supported yet.\n"); More specific error message: "Only ICH SPI component..." > + return 0; > + } > + if (size_enc > 5) { > + msg_perr("Density of component with index %d is invalid. " Same error message change here. > + "Encoded density is 0x%x.\n", idx, size_enc); > + return 0; > + } > + return dec_mem[size_enc]; > +} > + > static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > { > uint32_t control = 0; > diff --git a/ich_descriptors.h b/ich_descriptors.h > index b1da914..8ab798f 100644 > --- a/ich_descriptors.h > +++ b/ich_descriptors.h > @@ -255,7 +255,8 @@ void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > > int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > - > +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); > + > #endif /* BITFIELDS == 1 */ > #endif /* __ICH_DESCRIPTORS_H__ */ > #endif /* defined(__i386__) || defined(__x86_64__) */ > diff --git a/ichspi.c b/ichspi.c > index 2e25d34..61c0825 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -26,7 +26,10 @@ > #if defined(__i386__) || defined(__x86_64__) > > #include <string.h> > +#include <stdlib.h> > #include "flash.h" > +#include "flashchips.h" > +#include "chipdrivers.h" Including flashchips.h or chipdrivers.h from a programmer driver is a sign that something went wrong during the design phase. > #include "programmer.h" > #include "spi.h" > #include "ich_descriptors.h" > @@ -1084,6 +1087,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return result; > } > > +static struct hwseq { > + uint32_t size_comp0; > + uint32_t size_comp1; > +} hwseq; > + > +static void ich_hwseq_set_addr(uint32_t addr) > +{ > + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; > + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); Can this write fail somehow? > +} > + > +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes > + * of the block containing this address. */ Is it really possible to encode per-region block sizes in a descriptor? > +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) > +{ > + uint8_t enc_berase; > + static const uint32_t const dec_berase[4] = { decode_ instead of dec_. dec_ sounds too much like decrement. Or you pick a completely different name, e.g. eraseblock_sizes. > + 256, > + 4 * 1024, > + 8 * 1024, > + 64 * 1024 > + }; > + > + ich_hwseq_set_addr(addr); > + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE only has two adjacent bits set, correct? > + HSFS_BERASE_OFF; > + return dec_berase[enc_berase]; > +} > + > +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. Not something to be addressed in this patch, but we should really think about exponential backoff with maximum wait for such wait-for-hardware calls. > + Resets all error flags in HSFS. > + Returns 0 if the cycle completes successfully without errors within > + timeout us, 1 on errors. */ > +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, Can we specify the timeout in usecs instead and use programmer_delay(8) to avoid division overhead (use shift instead)? > + unsigned int len) > +{ > + uint16_t hsfs; > + uint32_t addr; > + > + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & > + (HSFS_FDONE | HSFS_FCERR)) == 0) && Can we really ignore AEL here? > + --timeout) { > + programmer_delay(10); > + } > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); This clears all errors. OK. > + if (!timeout) { > + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; > + msg_perr("Timeout error between offset 0x%08x and " > + "0x%08x + %d (=0x%08x)!\n", Please don't mix hex and decimal encoding. > + addr, addr, len - 1, addr + len - 1); > + prettyprint_ich9_reg_hsfs(hsfs); > + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); > + return 1; > + } > + > + if (hsfs & HSFS_FCERR) { > + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; > + msg_perr("Transaction error between offset 0x%08x and " > + "0x%08x (=0x%08x + %d)!\n", hex/decimal mixture. > + addr, addr + len - 1, addr, len - 1); > + prettyprint_ich9_reg_hsfs(hsfs); > + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); > + return 1; > + } > + return 0; > +} > + ich_hwseq_probe, ich_hwseq_send_command, ich_hwseq_block_erase, ich_hwseq_read and ich_hwseq_write256 use an interface which does not fit well with flashrom. Could you cut out those functions and post them separately, preferably as part of the hookup patch I mentioned above? > +int ich_hwseq_probe(struct flashchip *flash) > +{ > + uint32_t total_size, boundary; > + uint32_t erase_size_low, size_low, erase_size_high, size_high; > + struct block_eraser *eraser; > + > + if (flash->manufacture_id != INTEL_ID || > + flash->model_id != INTEL_HWSEQ) { > + msg_cerr("This chip (%s) is not supported in hardware" > + "sequencing mode and should never have been probed.\n", > + flash->name); > + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", > + __func__); > + return 0; > + } > + > + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); > + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { > + msg_cdbg("not met.\n"); > + return 0; > + } > + msg_cdbg("met.\n"); > + > + total_size = hwseq.size_comp0 + hwseq.size_comp1; > + msg_cdbg("Found %d attached SPI flash chip", > + (hwseq.size_comp1 != 0) ? 2 : 1); > + if (hwseq.size_comp1 != 0) > + msg_cdbg("s with a combined"); > + else > + msg_cdbg(" with a"); > + msg_cdbg(" density of %d kB.\n", total_size / 1024); > + flash->total_size = total_size / 1024; > + > + eraser = &(flash->block_erasers[0]); > + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; > + size_high = total_size - boundary; > + erase_size_high = ich_hwseq_get_erase_block_size(boundary); > + > + if (boundary == 0) { > + msg_cdbg("There is only one partition containing the whole " > + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); > + eraser->eraseblocks[0].size = erase_size_high; > + eraser->eraseblocks[0].count = size_high / erase_size_high; > + msg_cdbg("There are %d erase blocks with %d B each.\n", > + size_high / erase_size_high, erase_size_high); > + } else { > + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " > + "at address 0x%06x in two partitions.\n", > + 0, size_high-1, boundary); > + size_low = total_size - size_high; > + erase_size_low = ich_hwseq_get_erase_block_size(0); > + > + eraser->eraseblocks[0].size = erase_size_low; > + eraser->eraseblocks[0].count = size_low / erase_size_low; > + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", > + 0, size_low-1); > + msg_cdbg("In that range are %d erase blocks with %d B each.\n", > + size_low / erase_size_low, erase_size_low); > + > + eraser->eraseblocks[1].size = erase_size_high; > + eraser->eraseblocks[1].count = size_high / erase_size_high; > + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", > + boundary, size_high-1); > + msg_cdbg("In that range are %d erase blocks with %d B each.\n", > + size_high / erase_size_high, erase_size_high); > + } > + return 1; > +} > + > +static int ich_hwseq_send_command(unsigned int writecnt, > + unsigned int readcnt, > + const unsigned char *writearr, > + unsigned char *readarr) > +{ > + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " > + "arbitrary commands."); > + return -1; > +} > + > +int ich_hwseq_block_erase(struct flashchip *flash, > + unsigned int addr, > + unsigned int len) > +{ > + uint32_t erase_block; > + uint16_t hsfc; > + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ > + > + if (flash->manufacture_id != INTEL_ID || > + flash->model_id != INTEL_HWSEQ) { > + msg_perr("This chip (%s) is not supported in hardware" > + "sequencing mode\n", flash->name); > + return -1; > + } > + > + erase_block = ich_hwseq_get_erase_block_size(addr); > + if (len != erase_block) { > + msg_cerr("Erase block size for address 0x%06x is %d B, " > + "but requested erase block size is %d B. " > + "Not erasing anything.\n", addr, erase_block, len); > + return -1; > + } > + > + /* Although the hardware supports this (it would erase the whole block > + * containing the address) we play safe here. */ > + if (addr % erase_block != 0) { > + msg_cerr("Erase address 0x%06x is not aligned to the erase " > + "block boundary (any multiple of %d). " > + "Not erasing anything.\n", addr, erase_block); > + return -1; > + } > + > + if (addr + len > flash->total_size * 1024) { > + msg_perr("Request to erase some inaccessible memory address(es)" > + " (addr=0x%x, len=%d). " > + "Not erasing anything.\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); > + > + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* clear operation */ > + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ > + hsfc |= HSFC_FGO; /* start */ > + msg_pdbg("HSFC used for block erasing: "); > + prettyprint_ich9_reg_hsfc(hsfc); > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) > + return -1; > + return 0; > +} > + > +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) > +{ > + uint16_t hsfc; > + uint16_t timeout = 100 * 60; > + uint8_t block_len; > + > + if (flash->manufacture_id != INTEL_ID || > + flash->model_id != INTEL_HWSEQ) { > + msg_perr("This chip (%s) is not supported in hardware" > + "sequencing mode.\n", flash->name); > + return -1; > + } > + > + if (addr < 0 || addr + len > flash->total_size * 1024) { > + msg_perr("Request to read from an inaccessible memory address " > + "(addr=0x%x, len=%d).\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); > + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + while (len > 0) { > + block_len = min(len, spi_programmer->max_data_read); > + ich_hwseq_set_addr(addr); > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* set read operation */ > + hsfc &= ~HSFC_FDBC; /* clear byte count */ > + /* set byte count */ > + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); > + hsfc |= HSFC_FGO; /* start */ > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) > + return 1; > + ich_read_data(buf, block_len, ICH9_REG_FDATA0); > + addr += block_len; > + buf += block_len; > + len -= block_len; > + } > + return 0; > +} > + > +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) > +{ > + uint16_t hsfc; > + uint16_t timeout = 100 * 60; > + uint8_t block_len; > + > + if (flash->manufacture_id != INTEL_ID || > + flash->model_id != INTEL_HWSEQ) { > + msg_perr("This chip (%s) is not supported in hardware" > + "sequencing mode\n", flash->name); > + return -1; > + } > + > + if (addr < 0 || addr + len > flash->total_size * 1024) { > + msg_perr("Request to write to an inaccessible memory address " > + "(addr=0x%x, len=%d).\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); > + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + while (len > 0) { > + ich_hwseq_set_addr(addr); > + block_len = min(len, spi_programmer->max_data_write); > + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* clear operation */ > + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ > + hsfc &= ~HSFC_FDBC; /* clear byte count */ > + /* set byte count */ > + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); > + hsfc |= HSFC_FGO; /* start */ > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) > + return -1; > + addr += block_len; > + buf += block_len; > + len -= block_len; > + } > + return 0; > +} > + > static int ich_spi_send_multicommand(struct spi_command *cmds) > { > int ret = 0; > @@ -1207,6 +1502,16 @@ static const struct spi_programmer spi_programmer_ich9 = { > .write_256 = default_spi_write_256, > }; > > +static const struct spi_programmer spi_programmer_ich_hwseq = { > + .type = SPI_CONTROLLER_ICH_HWSEQ, > + .max_data_read = 64, > + .max_data_write = 64, > + .command = ich_hwseq_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = ich_hwseq_read, > + .write_256 = ich_hwseq_write_256, > +}; Move the hunk above to the hookup patch as well. > + > int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > int ich_generation) > { > @@ -1214,21 +1519,20 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + char *arg; > int ichspi_desc = 0; > + int hwseq_en = 0; > > switch (ich_generation) { > case 7: > - register_spi_programmer(&spi_programmer_ich7); > spibar_offset = 0x3020; > break; > case 8: > - register_spi_programmer(&spi_programmer_ich9); > spibar_offset = 0x3020; > break; > case 9: > case 10: > default: /* Future version might behave the same */ > - register_spi_programmer(&spi_programmer_ich9); > spibar_offset = 0x3800; > break; > } > @@ -1239,8 +1543,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > > - switch (spi_programmer->type) { > - case SPI_CONTROLLER_ICH7: > + switch (ich_generation) { > + case 7: Please make sure the VIA driver doesn't explode with this. > msg_pdbg("0x00: 0x%04x (SPIS)\n", > mmio_readw(ich_spibar + 0)); > msg_pdbg("0x02: 0x%04x (SPIC)\n", > @@ -1277,9 +1581,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_lock = 1; > } > ich_set_bbar(ich_generation, 0); > + register_spi_programmer(&spi_programmer_ich7); > ich_init_opcodes(); > break; > - case SPI_CONTROLLER_ICH9: > + case 8: > + case 9: > + case 10: > + default: /* Future version might behave the same */ OK until here. > + arg = extract_programmer_param("hwseq"); > + if (arg && !strcmp(arg, "yes")) > + hwseq_en = 1; > + else if (arg && !strlen(arg)) > + msg_pinfo("Missing argument for hwseq.\n"); > + else if (arg) > + msg_pinfo("Unknown argument for hwseq: %s\n", arg); > + free(arg); Please move the programmer parameter evaluation to the hookup patch. > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); > msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > prettyprint_ich9_reg_hsfs(tmp2); > @@ -1363,18 +1679,37 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > msg_pdbg("\n"); > #if BITFIELDS == 1 #if BITFIELDS needs to die. > + { /* to be able to declare desc here and avoid another > + * "#if BITFIELDS == 1" on top > + */ > + struct ich_descriptors desc = {{ 0 }}; > if (ichspi_desc) { Maybe rename ichspi_desc to ichspi_desc_active or ichspi_desc_enabled. > - struct ich_descriptors desc = {{ 0 }}; > if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > RET_OK) > prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > &desc); > + /* If the descriptor is valid and indicates multiple > + * flash devices we need to use hwseq to be able to > + * access the second flash device. > + */ > + if (desc.content.NC != 0) > + hwseq_en = 1; > + } else > + hwseq_en = 0; /* disable it even if the user said yes */ This case needs at least a msg_pinfo, maybe even msg_perr. We act contrary to the wishes of the user. > + > + if (hwseq_en > 0) { > + hwseq.size_comp0 = getFCBA_component_density(0, &desc); > + hwseq.size_comp1 = getFCBA_component_density(1, &desc); > + register_spi_programmer(&spi_programmer_ich_hwseq); Please move register_spi_programmer to the hookup patch. The rest of the code of this hunk should stay in this patch. > + } else { > + register_spi_programmer(&spi_programmer_ich9); > + ich_init_opcodes(); > } > -#endif /* BITFIELDS == 1 */ > + } > +#else /* BITFIELDS == 1 */ Once you remove the #ifdef, the hunk below will probably die completely. > + register_spi_programmer(&spi_programmer_ich9); > ich_init_opcodes(); > - break; > - default: > - /* Nothing */ > +#endif /* BITFIELDS == 1 */ > break; > } > > diff --git a/programmer.h b/programmer.h > index 6a28dbe..6e316d1 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -517,6 +517,7 @@ enum spi_controller { > #if defined(__i386__) || defined(__x86_64__) > SPI_CONTROLLER_ICH7, > SPI_CONTROLLER_ICH9, > + SPI_CONTROLLER_ICH_HWSEQ, Please move this to the hookup patch. > SPI_CONTROLLER_IT85XX, > SPI_CONTROLLER_IT87XX, > SPI_CONTROLLER_SB600, Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] ichspi: inform the user about the consequences of the security override strap
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 18.09.2011 03:24 schrieb Stefan Tauner: > Ibex Peak SPI Programming Guide: > The PCH has a mechanism to set up to 5 address ranges from HOST access. These are > defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT > unlocked by assertion of Flash descriptor Override. > > Also, the datasheets mention the bit in their description of FRAP but not PR[N]. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1449 - trunk
by repository service 18 Sep '11

18 Sep '11

Author: stefanct Date: Sun Sep 18 17:15:31 2011 New Revision: 1449 URL: http://flashrom.org/trac/flashrom/changeset/1449 Log: ichspi: inform the user about the consequences of the security override strap Ibex Peak SPI Programming Guide: The PCH has a mechanism to set up to 5 address ranges from HOST access. These are defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT unlocked by assertion of Flash descriptor Override. Also, the datasheets mention the bit in their description of FRAP but not PR[N]. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sun Sep 18 02:41:33 2011 (r1448) +++ trunk/ichspi.c Sun Sep 18 17:15:31 2011 (r1449) @@ -1325,6 +1325,12 @@ } if (tmp2 & HSFS_FDV) ichspi_desc = 1; + if (!(tmp2 & HSFS_FDOPSS) && ichspi_desc) + msg_pinfo("The Flash Descriptor Security Override " + "Strap-Pin is set. Restrictions implied\n" + "by the FRAP and FREG registers are NOT in " + "effect. Please note that Protected\n" + "Range (PR) restrictions still apply.\n"); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);

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[PATCH] ichspi: inform the user about the consequences of the security override strap
by Stefan Tauner 18 Sep '11

18 Sep '11

Ibex Peak SPI Programming Guide: The PCH has a mechanism to set up to 5 address ranges from HOST access. These are defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT unlocked by assertion of Flash descriptor Override. Also, the datasheets mention the bit in their description of FRAP but not PR[N]. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index e3a2d75..e30c267 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1325,6 +1325,12 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } if (tmp2 & HSFS_FDV) ichspi_desc = 1; + if (!(tmp2 & HSFS_FDOPSS) && ichspi_desc) + msg_pinfo("The Flash Descriptor Security Override " + "Strap-Pin is set. Restrictions implied\n" + "by the FRAP and FREG registers are NOT in " + "effect. Please note that Protected\n" + "Range (PR) restrictions still apply.\n"); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); -- 1.7.1

1 0

[commit] r1448 - trunk
by repository service 18 Sep '11

18 Sep '11

Author: stefanct Date: Sun Sep 18 02:41:33 2011 New Revision: 1448 URL: http://flashrom.org/trac/flashrom/changeset/1448 Log: Unsignify lengths and addresses in chip functions and structs Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/82802ab.c trunk/chipdrivers.h trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/it87spi.c trunk/jedec.c trunk/m29f400bt.c trunk/programmer.h trunk/serprog.c trunk/spi.c trunk/spi25.c trunk/sst28sf040.c trunk/wbsio_spi.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/82802ab.c Sun Sep 18 02:41:33 2011 (r1448) @@ -141,7 +141,7 @@ } /* chunksize is 1 */ -int write_82802ab(struct flashchip *flash, uint8_t *src, int start, int len) +int write_82802ab(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr dst = flash->virtual_memory + start; Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/chipdrivers.h Sun Sep 18 02:41:33 2011 (r1448) @@ -41,9 +41,9 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len); uint8_t spi_read_status_register(void); int spi_write_status_register(struct flashchip *flash, int status); void spi_prettyprint_status_register_bit(uint8_t status, int bit); @@ -51,12 +51,12 @@ void spi_prettyprint_status_register_welwip(uint8_t status); int spi_prettyprint_status_register(struct flashchip *flash); int spi_disable_blockprotect(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_byte_program(unsigned int addr, uint8_t databyte); +int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read(unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); @@ -81,7 +81,7 @@ uint8_t wait_82802ab(struct flashchip *flash); int probe_82802ab(struct flashchip *flash); int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int write_82802ab(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_82802ab(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); @@ -94,8 +94,8 @@ int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len); -int write_jedec_1(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int write_jedec_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); @@ -104,7 +104,7 @@ int probe_m29f400bt(struct flashchip *flash); int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_m29f400bt(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void protect_m29f400bt(chipaddr bios); /* pm49fl00x.c */ @@ -114,7 +114,7 @@ /* sst28sf040.c */ int erase_chip_28sf040(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_28sf040(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int unprotect_28sf040(struct flashchip *flash); int protect_28sf040(struct flashchip *flash); Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/dummyflasher.c Sun Sep 18 02:41:33 2011 (r1448) @@ -63,7 +63,7 @@ static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, @@ -528,7 +528,7 @@ } static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/flash.h Sun Sep 18 02:41:33 2011 (r1448) @@ -108,9 +108,9 @@ uint32_t model_id; /* Total chip size in kilobytes */ - int total_size; + unsigned int total_size; /* Chip page size in bytes */ - int page_size; + unsigned int page_size; int feature_bits; /* @@ -122,7 +122,7 @@ int (*probe) (struct flashchip *flash); /* Delay after "enter/exit ID mode" commands in microseconds. */ - int probe_timing; + unsigned int probe_timing; /* * Erase blocks and associated erase function. Any chip erase function @@ -143,8 +143,8 @@ int (*printlock) (struct flashchip *flash); int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*read) (struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); struct { uint16_t min; uint16_t max; @@ -202,7 +202,7 @@ extern const char flashrom_version[]; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); +int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashchip *flash); int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, const char *filename); @@ -210,7 +210,7 @@ int max(int a, int b); void tolower_string(char *str); char *extract_param(char **haystack, const char *needle, const char *delim); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message); +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); char *strcat_realloc(char *dest, const char *src); void print_version(void); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/flashrom.c Sun Sep 18 02:41:33 2011 (r1448) @@ -564,7 +564,7 @@ flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) +int read_memmapped(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) { chip_readn(buf, flash->virtual_memory + start, len); @@ -710,7 +710,7 @@ * @message string to print in the "FAILED" message * @return 0 for success, -1 for failure */ -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, +int verify_range(struct flashchip *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message) { int i; Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/it87spi.c Sun Sep 18 02:41:33 2011 (r1448) @@ -106,9 +106,9 @@ static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len); + unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, @@ -340,7 +340,7 @@ * Need to read this big flash using firmware cycles 3 byte at a time. */ static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { fast_spi = 0; @@ -358,7 +358,7 @@ } static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, - int start, int len) + unsigned int start, unsigned int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/jedec.c Sun Sep 18 02:41:33 2011 (r1448) @@ -355,7 +355,7 @@ } /* chunksize is 1 */ -int write_jedec_1(struct flashchip *flash, uint8_t *src, int start, int len) +int write_jedec_1(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i, failed = 0; chipaddr dst = flash->virtual_memory + start; @@ -376,7 +376,7 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size) +int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int page_size) { int i, tried = 0, failed; uint8_t *s = src; @@ -424,7 +424,7 @@ * This function is a slightly modified copy of spi_write_chunked. * Each page is written separately in chunks with a maximum size of chunksize. */ -int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len) +int write_jedec(struct flashchip *flash, uint8_t *buf, unsigned int start, int unsigned len) { int i, starthere, lenhere; /* FIXME: page_size is the wrong variable. We need max_writechunk_size Modified: trunk/m29f400bt.c ============================================================================== --- trunk/m29f400bt.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/m29f400bt.c Sun Sep 18 02:41:33 2011 (r1448) @@ -28,7 +28,7 @@ functions. */ /* chunksize is 1 */ -int write_m29f400bt(struct flashchip *flash, uint8_t *src, int start, int len) +int write_m29f400bt(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/programmer.h Sun Sep 18 02:41:33 2011 (r1448) @@ -556,23 +556,23 @@ #define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { enum spi_controller type; - int max_data_read; - int max_data_write; + unsigned int max_data_read; + unsigned int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); + int (*read)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); + int (*write_256)(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); }; extern const struct spi_programmer *spi_programmer; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); void register_spi_programmer(const struct spi_programmer *programmer); /* ichspi.c */ @@ -610,7 +610,7 @@ void serprog_delay(int delay); int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); #endif /* serial.c */ Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/serprog.c Sun Sep 18 02:41:33 2011 (r1448) @@ -795,7 +795,7 @@ * the advantage that it is much faster for most chips, but breaks those with * non-contiguous address space (like AT45DB161D). When spi_read_chunked is * fixed this method can be removed. */ -int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { int i; int cur_len; Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/spi.c Sun Sep 18 02:41:33 2011 (r1448) @@ -97,9 +97,9 @@ return result; } -int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int max_data = spi_programmer->max_data_read; + unsigned int max_data = spi_programmer->max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -109,9 +109,9 @@ return spi_read_chunked(flash, buf, start, len, max_data); } -int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int max_data = spi_programmer->max_data_write; + unsigned int max_data = spi_programmer->max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -121,7 +121,7 @@ return spi_write_chunked(flash, buf, start, len, max_data); } -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { int addrbase = 0; if (!spi_programmer->read) { @@ -160,7 +160,7 @@ * .write_256 = spi_chip_write_1 */ /* real chunksize is up to 256, logical chunksize is 256 */ -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/spi25.c Sun Sep 18 02:41:33 2011 (r1448) @@ -844,7 +844,7 @@ return ret; } -int spi_byte_program(int addr, uint8_t databyte) +int spi_byte_program(unsigned int addr, uint8_t databyte) { int result; struct spi_command cmds[] = { @@ -879,7 +879,7 @@ return result; } -int spi_nbyte_program(int addr, uint8_t *bytes, int len) +int spi_nbyte_program(unsigned int addr, uint8_t *bytes, unsigned int len) { int result; /* FIXME: Switch to malloc based on len unless that kills speed. */ @@ -954,7 +954,7 @@ return 0; } -int spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(unsigned int address, uint8_t *bytes, unsigned int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -972,7 +972,7 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is read separately in chunks with a maximum size of chunksize. */ -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) { int rc = 0; int i, j, starthere, lenhere; @@ -1012,7 +1012,7 @@ * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. */ -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) { int rc = 0; int i, j, starthere, lenhere; @@ -1061,7 +1061,7 @@ * (e.g. due to size constraints in IT87* for over 512 kB) */ /* real chunksize is 1, logical chunksize is 1 */ -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { int i, result = 0; @@ -1076,7 +1076,7 @@ return 0; } -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_aai_write(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { uint32_t pos = start; int result; Modified: trunk/sst28sf040.c ============================================================================== --- trunk/sst28sf040.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/sst28sf040.c Sun Sep 18 02:41:33 2011 (r1448) @@ -76,7 +76,7 @@ } /* chunksize is 1 */ -int write_28sf040(struct flashchip *flash, uint8_t *src, int start, int len) +int write_28sf040(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len) { int i; chipaddr bios = flash->virtual_memory; Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Sun Sep 18 00:21:55 2011 (r1447) +++ trunk/wbsio_spi.c Sun Sep 18 02:41:33 2011 (r1448) @@ -62,7 +62,7 @@ static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len); static const struct spi_programmer spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, @@ -194,7 +194,7 @@ return 0; } -static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len) { return read_memmapped(flash, buf, start, len); }

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Re: [flashrom] [PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > There is no sign of BBAR (BIOS Base Address Configuration Register) > in the public datasheet (or specification update) of the ICH8. Also, > the offset of that register has changed between ICH7 (SPIBAR + 50h) > and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on > ICH8. Better don't try to touch it at all and assume/hope it is 0. Just a short comment about this: Can we create a TODO.txt or UNKNOWN.txt file in the flashrom source which lists all such questions and similar assumptions? That way we know which questions we can ask Intel if one of their engineers talks to us. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 7/8] ichspi: unlock PR register restrictions if not locked down
by Carl-Daniel Hailfinger 18 Sep '11

18 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with comments. > diff --git a/ichspi.c b/ichspi.c > index c38fbfc..a9327de 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1507,6 +1507,24 @@ static void prettyprint_ich9_reg_pr(int i) > msg_pdbg(", unused)\n"); > } > > +/* Set the read and write protection enable bits of PR register @i according to Change "Set" to "Set/clear". > + * @read_prot and @write_prot. */ > +static void ich8_set_pr(int i, int read_prot, int write_prot) > +{ > + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); > + uint32_t pr = mmio_readl(addr); > + > + msg_gspew("PR%u is 0x%08x, ", i, pr); > + pr &= ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); > + if (read_prot) > + pr |= (1 << PR_RP_OFF); > + if (write_prot) > + pr |= (1 << PR_WP_OFF); Having some logic which eliminated unnecessary changes of pr would be nice. You could even print "unchanged\n" for that case. > + msg_gspew("trying to set it to 0x%08x ", pr); > + mmio_writel(pr, addr); Really not rmmio_writel? We want to undo all non-permanent config changes on shutdown. > + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); > +} > + > static const struct spi_programmer spi_programmer_ich7 = { > .type = SPI_CONTROLLER_ICH7, > .max_data_read = 64, > @@ -1648,6 +1666,10 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > for(i = 0; i < 5; i++) > do_ich9_spi_frap(tmp, i); > > + /* try to disable PR locks before printing them */ > + if (!ichspi_lock) > + for(i = 0; i < 5; i++) > + ich8_set_pr(i, 0, 0); ich8_ is an unusual prefix. Most other names use either ich7_ or ich9_ prefixes even if the functionality is present in ICH8. > for(i = 0; i < 5; i++) > prettyprint_ich9_reg_pr(i); > -- http://www.hailfinger.org/

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[commit] r1447 - trunk
by repository service 18 Sep '11

18 Sep '11

Author: stefanct Date: Sun Sep 18 00:21:55 2011 New Revision: 1447 URL: http://flashrom.org/trac/flashrom/changeset/1447 Log: ichspi: unlock PR register restrictions on ICH8+ if not locked down Tested-by: Shailendra Sodhi (predecessor/proof of concept patch) http://www.flashrom.org/pipermail/flashrom/2011-August/007717.html Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Sep 17 23:21:48 2011 (r1446) +++ trunk/ichspi.c Sun Sep 18 00:21:55 2011 (r1447) @@ -1200,6 +1200,29 @@ msg_pdbg2(", unused)\n"); } +/* Set/Clear the read and write protection enable bits of PR register @i + * according to @read_prot and @write_prot. */ +static void ich9_set_pr(int i, int read_prot, int write_prot) +{ + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + uint32_t old = mmio_readl(addr); + uint32_t new; + + msg_gspew("PR%u is 0x%08x", i, old); + new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); + if (read_prot) + new |= (1 << PR_RP_OFF); + if (write_prot) + new |= (1 << PR_WP_OFF); + if (old == new) { + msg_gspew(" already.\n"); + return; + } + msg_gspew(", trying to set it to 0x%08x ", new); + rmmio_writel(new, addr); + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1320,6 +1343,10 @@ for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); + /* try to disable PR locks before printing them */ + if (!ichspi_lock) + for(i = 0; i < 5; i++) + ich9_set_pr(i, 0, 0); for(i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i);

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