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Re: [flashrom] [PATCH 3/5] ichspi: print flash descriptor dependent information only when it is valid
by Stefan Tauner 08 Nov '11

08 Nov '11

On Fri, 21 Oct 2011 00:39:07 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Also, fix some coding style issues. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> now that hwseq is merged the way is free for this. committed in r1462. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1462 - trunk
by repository service 08 Nov '11

08 Nov '11

Author: stefanct Date: Tue Nov 8 12:55:24 2011 New Revision: 1462 URL: http://flashrom.org/trac/flashrom/changeset/1462 Log: ichspi: print flash descriptor dependent information only when it is valid Also, fix some coding style issues. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Nov 8 11:55:54 2011 (r1461) +++ trunk/ichspi.c Tue Nov 8 12:55:24 2011 (r1462) @@ -1092,7 +1092,7 @@ (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { int i; msg_pspew("The data was:\n"); - for(i=0; i<count; i++){ + for (i = 0; i < count; i++){ msg_pspew("%3d: 0x%02x\n", i, data[i]); } } @@ -1644,28 +1644,33 @@ "effect. Please note that Protected\n" "Range (PR) restrictions still apply.\n"); - tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); - msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); - prettyprint_ich9_reg_hsfc(tmp2); + if (desc_valid) { + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); + } tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); - tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); + + if (desc_valid) { + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* Decode and print FREGx and FRAP registers */ + for (i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + } /* try to disable PR locks before printing them */ if (!ichspi_lock) - for(i = 0; i < 5; i++) + for (i = 0; i < 5; i++) ich9_set_pr(i, 0, 0); - for(i = 0; i < 5; i++) + for (i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i); tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); @@ -1686,7 +1691,7 @@ mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - if (ich_generation == CHIPSET_ICH8) { + if (ich_generation == CHIPSET_ICH8 && desc_valid) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); @@ -1696,18 +1701,20 @@ msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); - msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); - msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + if (desc_valid) { + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); - tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); - msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); - msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); - - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } ich_set_bbar(0); }

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[commit] r1461 - trunk
by repository service 08 Nov '11

08 Nov '11

Author: stefanct Date: Tue Nov 8 11:55:54 2011 New Revision: 1461 URL: http://flashrom.org/trac/flashrom/changeset/1461 Log: ichspi: add support for Intel Hardware Sequencing Based on the new opaque programmer framework this patch adds support for Intel Hardware Sequencing on ICH8 and its successors. By default (or when setting the ich_spi_mode option to auto) the module tries to use swseq and only activates hwseq if need be: - if important opcodes are inaccessible due to lockdown - if more than one flash chip is attached. The other options (swseq, hwseq) select the respective mode (if possible). A general description of Hardware Sequencing can be found in this blog entry: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ Besides adding hwseq this patch also introduces these unrelated changes: - Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi. The whole error handling looks a bit odd to me, so this patch does change very little. Also, it does not touch the tunnelcreek method, which should be refactored anyway. - Add null-pointer guards to find_opcode and find_preop to matches the other opcode methods better: curopcodes == NULL has some meaning and is actively used/checked in other functions. TODO: adding real documentation when we have a directory for it Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/flashrom.8 trunk/ichspi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/chipset_enable.c Tue Nov 8 11:55:54 2011 (r1461) @@ -491,7 +491,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { - int ret; + int ret, ret_spi; uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; @@ -569,10 +569,12 @@ } /* This adds BUS_SPI */ - if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) { - if (!ret) - ret = ERROR_NONFATAL; - } + ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation); + if (ret_spi == ERROR_FATAL) + return ret_spi; + + if (ret || ret_spi) + ret = ERROR_NONFATAL; return ret; } Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/flashrom.8 Tue Nov 8 11:55:54 2011 (r1461) @@ -303,6 +303,26 @@ flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash +attached, and if a valid descriptor was written to it (e.g. by the vendor), the +chipset provides an alternative way to access the flash chip(s) named +.BR "Hardware Sequencing" . +It is much simpler than the normal access method (called +.BR "Software Sequencing" ")," +but does not allow the software to choose the SPI commands to be sent. +You can use the +.sp +.B " flashrom \-p internal:ich_spi_mode=value" +.sp +syntax where value can be +.BR auto ", " swseq " or " hwseq . +By default +.RB "(or when setting " ich_spi_mode=auto ) +the module tries to use swseq and only activates hwseq if need be (e.g. if +important opcodes are inaccessible due to lockdown; or if more than one flash +chip is attached). The other options (swseq, hwseq) select the respective mode +(if possible). +.sp If you have an Intel chipset with an ICH6 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Nov 7 00:51:09 2011 (r1460) +++ trunk/ichspi.c Tue Nov 8 11:55:54 2011 (r1461) @@ -423,6 +423,11 @@ { int a; + if (op == NULL) { + msg_perr("\n%s: null OPCODES pointer!\n", __func__); + return -1; + } + for (a = 0; a < 8; a++) { if (op->opcode[a].opcode == opcode) return a; @@ -435,6 +440,11 @@ { int a; + if (op == NULL) { + msg_perr("\n%s: null OPCODES pointer!\n", __func__); + return -1; + } + for (a = 0; a < 2; a++) { if (op->preop[a] == preop) return a; @@ -561,6 +571,31 @@ } /* + * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise. + * FIXME: this should also check for + * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) + * - at least one erasing opcode (lots.) + * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) + * - necessary preops? (EWSR, WREN, ...?) + */ +static int ich_missing_opcodes() +{ + uint8_t ops[] = { + JEDEC_READ, + JEDEC_RDSR, + 0 + }; + int i = 0; + while (ops[i] != 0) { + msg_pspew("checking for opcode 0x%02x\n", ops[i]); + if (find_opcode(curopcodes, ops[i]) == -1) + return -1; + i++; + } + return 0; +} + +/* * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ @@ -1066,7 +1101,11 @@ return result; } -#if 0 +static struct hwseq_data { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq_data; + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { @@ -1117,8 +1156,8 @@ if (!timeout) { addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; msg_perr("Timeout error between offset 0x%08x and " - "0x%08x + %d (=0x%08x)!\n", - addr, addr, len - 1, addr + len - 1); + "0x%08x (= 0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); return 1; @@ -1127,7 +1166,7 @@ if (hsfs & HSFS_FCERR) { addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; msg_perr("Transaction error between offset 0x%08x and " - "0x%08x (=0x%08x + %d)!\n", + "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); @@ -1135,7 +1174,184 @@ } return 0; } -#endif + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq_data.size_comp1 != 0) ? 2 : 1); + if (hwseq_data.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + flash->tested = TEST_OK_PREW; + return 1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, opaque_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, opaque_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} static int ich_spi_send_multicommand(struct spi_command *cmds) { @@ -1300,6 +1516,15 @@ .write_256 = default_spi_write_256, }; +static const struct opaque_programmer opaque_programmer_ich_hwseq = { + .max_data_read = 64, + .max_data_write = 64, + .probe = ich_hwseq_probe, + .read = ich_hwseq_read, + .write = ich_hwseq_write, + .erase = ich_hwseq_block_erase, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, enum ich_chipset ich_gen) { @@ -1307,13 +1532,20 @@ uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int desc_valid = 0; + struct ich_descriptors desc = {{ 0 }}; + enum ich_spi_mode { + ich_auto, + ich_hwseq, + ich_swseq + } ich_spi_mode = ich_auto; ich_generation = ich_gen; switch (ich_generation) { case CHIPSET_ICH_UNKNOWN: - return -1; + return ERROR_FATAL; case CHIPSET_ICH7: case CHIPSET_ICH8: spibar_offset = 0x3020; @@ -1330,6 +1562,8 @@ /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; + ich_init_opcodes(); + switch (ich_generation) { case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", @@ -1369,10 +1603,31 @@ } ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); - ich_init_opcodes(); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for ich_spi_mode.\n"); + free(arg); + return ERROR_FATAL; + } else if (arg) { + msg_perr("Unknown argument for ich_spi_mode: %s\n", + arg); + free(arg); + return ERROR_FATAL; + } + free(arg); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1458,14 +1713,41 @@ msg_pdbg("\n"); if (desc_valid) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + ich_missing_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcode is locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); + hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + register_opaque_programmer(&opaque_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); } - register_spi_programmer(&spi_programmer_ich9); - ich_init_opcodes(); break; }

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Re: [flashrom] PMC Flash Pm29F002T-90PC - Write OK
by Stefan Tauner 08 Nov '11

08 Nov '11

On Mon, 31 Oct 2011 20:24:17 -0200 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > It was tested in an Asus TUV4X (the original flash is a Winbond W49F002U-12B). > > Unfortunately this board uses the infamous AS99127F: > http://www.flashrom.org/pipermail/flashrom/2010-February/002339.html > > After "modprobe i2c-dev; i2cset 0 0x48 0x80 0x80" flashrom works > normally and update both chips without problems. > (didn't need to unload w83781d because I don't have lm-sensors installed here) > > Log attached. Hello Marcos, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. I won't touch anything else till someone answers my previous question(s) regarding the VIA chipset enables. Also, i have no idea about the needed i2c integration or if any progress have been made so far. The TUV4X should probably be added to our list with an appropriate note. Also, the A7V133 is already on the list although it probably does not work out of the box either(?) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Addition to working hardware Asus Z8PE-D12
by Kevin Shepherd 07 Nov '11

07 Nov '11

I would like to report complete success in upgrading my motherboard BIOS, and to thank the developers for their hard work. My motherboard is not yet listed in your working hardware lists. Motherboard: Asus Z8PE-D12 OS: Ubuntu 11.04 amd64 Please find attached my verbose log of the erase/write (flashrom-asus-z8pe-d12.log), as well as the three requested logs from your board testing page. Here is the command run: flashrom -V -w Z8PE-D12X-ASUS-1103.ROM - Kevin Shepherd

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report_flashrom_H55_chipset
by gregina 07 Nov '11

07 Nov '11

su Passwort: [root@gregina2 gl]# flashrom -V -r /home/gl/msibackup.bin flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1534M loops per second, 10 myus = 10 us, 100 myus = 105 us, 1000 myus = 1008 us, 10000 myus = 10514 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7635" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "H55M-ED55 (MS-7635) " DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "Intel H55" with PCI ID 8086:3b06. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0xc64: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00001000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x07ff0600 (FREG1: BIOS) 0x00600000-0x007fffff is read-write 0x5C: 0x05ff0001 (FREG2: Management Engine) 0x00001000-0x005fffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x543b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0006019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching enabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Chip status register is 00 Found Winbond flash chip "W25Q64" (8192 kB, SPI) at physical address 0xff800000. Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x16 Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7f5a264068a0 Restoring MMIO space at 0x7f5a2640689c Restoring MMIO space at 0x7f5a26406898 Restoring MMIO space at 0x7f5a26406896 Restoring MMIO space at 0x7f5a26406894 Restoring PCI config space for 00:1f:0 reg 0xdc [root@gregina2 gl]# Many thangs for your work!! Best regards Greg

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Re: [flashrom] [PATCH] ichspi: use a variable to distinguish ich generations instead of spi_programmer->type
by Carl-Daniel Hailfinger 07 Nov '11

07 Nov '11

Am 03.11.2011 01:58 schrieb Stefan Tauner: > The type member is enough most of the time to derive the wanted > information, but > - not always (e.g. ich_set_bbar), > - only available after registration, which we want to delay till the > end of init, and > - we really want to distinguish between chipset version-grained > attributes which are not reflected by the registered programmer. > > Hence this patch introduces a new static variable which is set up > early by the init functions and allows us to get rid of all "switch > (spi_programmer->type)" in ichspi.c. We reuse the enum introduced > for descriptor mode for the type of the new variable. > > Previously magic numbers were passed by chipset_enable wrappers. Now > they use the enumeration items too. To get this working the enum > definition had to be moved to programmer.h, which was fixed on the > way by adding necessary includes. > > Another noteworthy detail: previously we have checked for a valid > programmer/ich generation all over the place. I have removed those > checks and added one single check in the init method. Calling any > function of a programmer without executing the init method first, is > undefined behavior. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Excellent. > On Wed, 02 Nov 2011 02:44:17 +0100 > Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >>> i think it might be a good idea to get rid of the whole >>> switch(spi_programmer->type) >>> pattern and create a file-scope static ich_generation variable instead >>> of using the type member and the ich_generation parameters everywhere. >> Absolutely agreed. >> The only possible generic problem with that approach would be the >> registration of multiple ICH-style SPI programmers, but unless we see >> boards with two active ICH-style southbridges I think we can assume the >> static variable handles it well. (Note that boards with multiple MCP55 >> southbridges exist, but only one southbridge has an attached flash chip.) > and even then they would have to be from different incompatible generations... > i think we are quite safe ;) > >> There might be an issue for those who want to use flashrom as a >> standalone tool (e.g. on top of libpayload) where heap allocations for >> static variables are unwanted, but that's a huge can of worms and I'd >> rather ignore that issue until either static variables work well in that >> environment or until someone hacks a way around static variables being a >> problem there. >> >>> the type member is enough most of the time to derive the wanted >>> information, but >>> - not always (e.g. ich_set_bbar) >>> - only available after registration, which we want to delay till the end >>> of init. >>> - we really want to distinguish between chipset version-grained >>> attributes which are not reflected by the registered programmer. >> Indeed. So if you could rework the patch to use your static variable >> suggestion, it would reduce patch size and make the code more readable. > you may want to evaluate that "patch size" argument again... *sigh* Heh. > i have added the first applicable chipset to each default case for > documentation purposes. Good idea. Please go ahead. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1460 - trunk
by repository service 07 Nov '11

07 Nov '11

Author: stefanct Date: Mon Nov 7 00:51:09 2011 New Revision: 1460 URL: http://flashrom.org/trac/flashrom/changeset/1460 Log: ichspi: use a variable to distinguish ich generations instead of spi_programmer->type The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/ich_descriptors.h trunk/ichspi.c trunk/programmer.h Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/chipset_enable.c Mon Nov 7 00:51:09 2011 (r1460) @@ -489,7 +489,7 @@ } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, - int ich_generation) + enum ich_chipset ich_generation) { int ret; uint8_t bbs, buc; @@ -504,7 +504,7 @@ static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: /* EP80579 may need further changes, but this is the least * intrusive way to get correct BOOT Strap printing without * changing the rest of its code path). */ @@ -513,13 +513,13 @@ else straps_names = straps_names_ich7_nm10; break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: straps_names = straps_names_ich8910; break; - case 11: - case 12: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: straps_names = straps_names_pch56; break; default: @@ -557,7 +557,7 @@ * on ICH7 when the southbridge is strapped to LPC */ buses_supported = BUS_FWH; - if (ich_generation == 7) { + if (ich_generation == CHIPSET_ICH7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is * required. */ @@ -579,34 +579,34 @@ static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 7); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 8); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 9); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 10); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 11); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, 12); + return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); } static int via_no_byte_merge(struct pci_dev *dev, const char *name) Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/ich_descriptors.h Mon Nov 7 00:51:09 2011 (r1460) @@ -24,6 +24,7 @@ #define __ICH_DESCRIPTORS_H__ 1 #include <stdint.h> +#include "programmer.h" /* for enum ich_chipset */ /* FIXME: Replace with generic return codes */ #define ICH_RET_OK 0 @@ -63,20 +64,6 @@ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) #define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) -/* Used to select the right descriptor printing function. - * Currently only ICH8 and Ibex Peak are supported. - */ -enum ich_chipset { - CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH7 = 7, - CHIPSET_ICH8, - CHIPSET_ICH9, - CHIPSET_ICH10, - CHIPSET_5_SERIES_IBEX_PEAK, - CHIPSET_6_SERIES_COUGAR_POINT, - CHIPSET_7_SERIES_PANTHER_POINT -}; - void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); struct ich_desc_content { Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/ichspi.c Mon Nov 7 00:51:09 2011 (r1460) @@ -172,6 +172,7 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN; uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -454,23 +455,20 @@ return -1; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ preop = REGREAD16(ICH9_REG_PREOP); optype = REGREAD16(ICH9_REG_OPTYPE); opmenu[0] = REGREAD32(ICH9_REG_OPMENU); opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } op->preop[0] = (uint8_t) preop; @@ -529,9 +527,8 @@ } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case CHIPSET_ICH7: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -544,7 +541,8 @@ mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH9_REG_PREOP); @@ -557,9 +555,6 @@ mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } return 0; @@ -569,16 +564,17 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(int ich_generation, uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr) { int bbar_off; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: bbar_off = 0x50; break; - case 8: + case CHIPSET_ICH8: msg_perr("BBAR offset is unknown on ICH8!\n"); return; + case CHIPSET_ICH9: default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; @@ -943,15 +939,12 @@ return SPI_INVALID_LENGTH; } - switch (spi_programmer->type) { - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case CHIPSET_ICH7: return ich7_run_opcode(op, offset, datalength, data, maxlength); - case SPI_CONTROLLER_ICH9: + case CHIPSET_ICH8: + default: /* Future version might behave the same */ return ich9_run_opcode(op, offset, datalength, data); - default: - /* If we ever get here, something really weird happened */ - return -1; } } @@ -1022,19 +1015,11 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_ICH9: - if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); - return SPI_INVALID_ADDRESS; - } - break; - default: - break; + if (addr < ichspi_bbar) { + msg_perr("%s: Address 0x%06x below allowed " + "range 0x%06x-0xffffff\n", __func__, + addr, ichspi_bbar); + return SPI_INVALID_ADDRESS; } } @@ -1316,7 +1301,7 @@ }; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation) + enum ich_chipset ich_gen) { int i; uint8_t old, new; @@ -1324,15 +1309,16 @@ uint32_t tmp; int desc_valid = 0; + ich_generation = ich_gen; + switch (ich_generation) { - case 7: - spibar_offset = 0x3020; - break; - case 8: + case CHIPSET_ICH_UNKNOWN: + return -1; + case CHIPSET_ICH7: + case CHIPSET_ICH8: spibar_offset = 0x3020; break; - case 9: - case 10: + case CHIPSET_ICH9: default: /* Future version might behave the same */ spibar_offset = 0x3800; break; @@ -1345,7 +1331,7 @@ ich_spibar = rcrb + spibar_offset; switch (ich_generation) { - case 7: + case CHIPSET_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1381,13 +1367,11 @@ msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case 8: - case 9: - case 10: + case CHIPSET_ICH8: default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); @@ -1447,7 +1431,7 @@ mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - if (ich_generation == 8) { + if (ich_generation == CHIPSET_ICH8) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); @@ -1469,7 +1453,7 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); - ich_set_bbar(ich_generation, 0); + ich_set_bbar(0); } msg_pdbg("\n"); @@ -1524,6 +1508,7 @@ /* Not sure if it speaks all these bus protocols. */ buses_supported = BUS_LPC | BUS_FWH; + ich_generation = CHIPSET_ICH7; register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -1556,7 +1541,7 @@ ichspi_lock = 1; } - ich_set_bbar(7, 0); + ich_set_bbar(0); ich_init_opcodes(); return 0; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Nov 4 22:35:26 2011 (r1459) +++ trunk/programmer.h Mon Nov 7 00:51:09 2011 (r1460) @@ -579,9 +579,20 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation); + enum ich_chipset ich_generation); int via_init_spi(struct pci_dev *dev); /* it85spi.c */

1 0

(no subject)
by yarpr＠pochta.ru 05 Nov '11

05 Nov '11

 _ Pr.om_ot.ions on weeke_nds 

2 1

Re: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure.
by Michael Karcher 04 Nov '11

04 Nov '11

Am Freitag, den 21.10.2011, 00:39 +0200 schrieb Stefan Tauner: > diff --git a/flash.h b/flash.h > index 535c1b8..8ad2845 100644 > --- a/flash.h > +++ b/flash.h > @@ -62,8 +62,9 @@ enum chipbustype { > BUS_LPC = 1 << 1, > BUS_FWH = 1 << 2, > BUS_SPI = 1 << 3, > + BUS_PROG = 1 << 4, > BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, > - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, > + BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI | BUS_PROG, We don't need BUS_UNKNOWN. It is referenced only in flashbuses_to_text. Having a programmer being both opaque and non-opaque seems to be as useless as defining that a chip "might also be accessed through an opaque interface". In the case of opaque interfaces, we don't care about the chip type - so I don't see any use case for BUS_UNKNOWN, even more after adding BUS_PROG. > }; > +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > + { > + .vendor = "Programmer", > + .name = "Opaque flash chip", > + .bustype = BUS_PROG, > + .manufacture_id = PROGMANUF_ID, > + .model_id = PROGDEV_ID, > + .total_size = 0, > + .page_size = 256, > + /* probe is assumed to work, rest will be filled in by probe */ > + .tested = TEST_OK_PROBE, > + .probe = probe_opaque, > + /* eraseblock sizes will be set by the probing function */ > + .block_erasers = > + { > + { > + .block_erase = erase_opaque, > + } > + }, > + .write = write_opaque, > + .read = read_opaque, > + }, > +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) Why do we need any prerequisite for the opaque programmer? It should work outside of x86(-64), too, depending on which opaque backend is used. I guess this #if is there because at the moment, the only opaque programmer is the ICH9 stuff, but wouldn't a define NEED_OPAQUE that is set in the include file as soon as any programmer based on the opaque programmer is selected be more sensible? > @@ -9005,6 +9027,7 @@ const struct flashchip flashchips[] = { > .probe = probe_spi_rdid, > .write = NULL, > }, > + > { > .vendor = "Generic", > .name = "unknown SPI chip (REMS)", Unrelated change - you might have it in accidentally. > +/* > + * Contains the opaque programmer framework. > + * An opaque programmer is a programmer which does not provide direct access > + * to the flash chip and which abstracts all flash chip properties into a > + * programmer specific interface. > + */ > + > +#include <strings.h> > +#include <string.h> > +#include "flash.h" > +#include "flashchips.h" > +#include "chipdrivers.h" > +#include "programmer.h" > + > +const struct opaque_programmer opaque_programmer_none = { > + .max_data_read = MAX_DATA_UNSPECIFIED, > + .max_data_write = MAX_DATA_UNSPECIFIED, > + .probe = NULL, > + .read = NULL, You are missing ".erase = NULL" here. > + .write = NULL, > +}; > + > +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; > + > +int probe_opaque(struct flashchip *flash) > +{ > + if (!opaque_programmer->probe) { > + msg_perr("%s called, but this is not an opaque programmer. " > + "Please report a bug at flashrom(a)flashrom.org\n", > + __func__); I don't really like the error message, I would prefer "%s called without register_opaque" or something like that. > +void register_opaque_programmer(const struct opaque_programmer *pgm) > +{ > + opaque_programmer = pgm; > + buses_supported |= BUS_PROG; > +} You might want to check that the function pointers in pgm are not NULL, to make the suggested error message "without register_opaque" more apt. Otherwise, the patch looks good to me. This is Acked-By: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> If you feel confident you didn't mess up anything, feel free to re-use the ack after minor edits. Regards, Michael Karcher

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[commit] r1459 - trunk
by repository service 04 Nov '11

04 Nov '11

Author: hailfinger Date: Fri Nov 4 22:35:26 2011 New Revision: 1459 URL: http://flashrom.org/trac/flashrom/changeset/1459 Log: Add opaque programmer registration infrastructure An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Added: trunk/opaque.c Modified: trunk/Makefile trunk/chipdrivers.h trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/print.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/Makefile Fri Nov 4 22:35:26 2011 (r1459) @@ -242,7 +242,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o + a25.o at25.o opaque.o LIB_OBJS = layout.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/chipdrivers.h Fri Nov 4 22:35:26 2011 (r1459) @@ -58,6 +58,12 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +/* opaque.c */ +int probe_opaque(struct flashchip *flash); +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flash.h Fri Nov 4 22:35:26 2011 (r1459) @@ -62,8 +62,8 @@ BUS_LPC = 1 << 1, BUS_FWH = 1 << 2, BUS_SPI = 1 << 3, + BUS_PROG = 1 << 4, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, }; /* Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flashchips.c Fri Nov 4 22:35:26 2011 (r1459) @@ -8874,6 +8874,28 @@ }, { + .vendor = "Programmer", + .name = "Opaque flash chip", + .bustype = BUS_PROG, + .manufacture_id = PROGMANUF_ID, + .model_id = PROGDEV_ID, + .total_size = 0, + .page_size = 256, + /* probe is assumed to work, rest will be filled in by probe */ + .tested = TEST_OK_PROBE, + .probe = probe_opaque, + /* eraseblock sizes will be set by the probing function */ + .block_erasers = + { + { + .block_erase = erase_opaque, + } + }, + .write = write_opaque, + .read = read_opaque, + }, + + { .vendor = "AMIC", .name = "unknown AMIC SPI chip", .bustype = BUS_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/flashchips.h Fri Nov 4 22:35:26 2011 (r1459) @@ -646,4 +646,7 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 +#define PROGMANUF_ID 0xFFFE /* dummy ID for opaque chips behind a programmer */ +#define PROGDEV_ID 0x01 /* dummy ID for opaque chips behind a programmer */ + #endif /* !FLASHCHIPS_H */ Added: trunk/opaque.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/opaque.c Fri Nov 4 22:35:26 2011 (r1459) @@ -0,0 +1,99 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the opaque programmer framework. + * An opaque programmer is a programmer which does not provide direct access + * to the flash chip and which abstracts all flash chip properties into a + * programmer specific interface. + */ + +#include <stdint.h> +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "programmer.h" + +const struct opaque_programmer opaque_programmer_none = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .probe = NULL, + .read = NULL, + .write = NULL, + .erase = NULL, +}; + +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; + +int probe_opaque(struct flashchip *flash) +{ + if (!opaque_programmer->probe) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + return opaque_programmer->probe(flash); +} + +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->read) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->read(flash, buf, start, len); +} + +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->write) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->write(flash, buf, start, len); +} + +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +{ + if (!opaque_programmer->erase) { + msg_perr("%s called before register_opaque_programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->erase(flash, blockaddr, blocklen); +} + +void register_opaque_programmer(const struct opaque_programmer *pgm) +{ + if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { + msg_perr("%s called with one of probe/read/write/erase being " + "NULL. Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return; + } + opaque_programmer = pgm; + buses_supported |= BUS_PROG; +} Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/print.c Fri Nov 4 22:35:26 2011 (r1459) @@ -32,13 +32,11 @@ char *flashbuses_to_text(enum chipbustype bustype) { char *ret = calloc(1, 1); - if (bustype == BUS_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown, "); /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ - } else if (bustype == BUS_NONSPI) { + if (bustype == BUS_NONSPI) { ret = strcat_realloc(ret, "Non-SPI, "); } else { if (bustype & BUS_PARALLEL) @@ -49,6 +47,8 @@ ret = strcat_realloc(ret, "FWH, "); if (bustype & BUS_SPI) ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); if (bustype == BUS_NONE) ret = strcat_realloc(ret, "None, "); } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Nov 2 15:31:18 2011 (r1458) +++ trunk/programmer.h Fri Nov 4 22:35:26 2011 (r1459) @@ -24,6 +24,8 @@ #ifndef __PROGRAMMER_H__ #define __PROGRAMMER_H__ 1 +#include "flash.h" /* for chipaddr and flashchip */ + enum programmer { #if CONFIG_INTERNAL == 1 PROGRAMMER_INTERNAL, @@ -601,6 +603,19 @@ int wbsio_check_for_spi(void); #endif +/* opaque.c */ +struct opaque_programmer { + int max_data_read; + int max_data_write; + /* Specific functions for this programmer */ + int (*probe) (struct flashchip *flash); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +}; +extern const struct opaque_programmer *opaque_programmer; +void register_opaque_programmer(const struct opaque_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void);

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Re: [flashrom] Flashing FM28V100 through satasii
by Rudolf Marek 03 Nov '11

03 Nov '11

The message is some test from the chip which is telling if some chip is connected or not. Try to override that or check the datasheet to see what it really does. Thanks Rudolf

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SST49LF080A - ERASE FAILED at 0x000a3d28!
by Rudolf Marek 03 Nov '11

03 Nov '11

Hi all, It worked with this chip some time ago (a year). Erasing with -E also fails but the next one will succeed. If I write back content again and do it all again I can reproduce this. It seems like a timing issue. Log attached. Changing probe_timing to 10000 is not helping. Tried with latest flashrom, older ended with SIGSEGV. Any clue? Thanks Rudolf

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Re: [flashrom] [PATCH 1/2] ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes
by Carl-Daniel Hailfinger 03 Nov '11

03 Nov '11

Am 26.10.2011 15:35 schrieb Stefan Tauner: > This allows them to be called before programmer registration. > --- > i think it might be a good idea to get rid of the whole > switch(spi_programmer->type) > pattern and create a file-scope static ich_generation variable instead > of using the type member and the ich_generation parameters everywhere. Absolutely agreed. The only possible generic problem with that approach would be the registration of multiple ICH-style SPI programmers, but unless we see boards with two active ICH-style southbridges I think we can assume the static variable handles it well. (Note that boards with multiple MCP55 southbridges exist, but only one southbridge has an attached flash chip.) There might be an issue for those who want to use flashrom as a standalone tool (e.g. on top of libpayload) where heap allocations for static variables are unwanted, but that's a huge can of worms and I'd rather ignore that issue until either static variables work well in that environment or until someone hacks a way around static variables being a problem there. > the type member is enough most of the time to derive the wanted > information, but > - not always (e.g. ich_set_bbar) > - only available after registration, which we want to delay till the end > of init. > - we really want to distinguish between chipset version-grained > attributes which are not reflected by the registered programmer. Indeed. So if you could rework the patch to use your static variable suggestion, it would reduce patch size and make the code more readable. Regards, Carl-Daniel > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 44 +++++++++++++++++++++++++++----------------- > 1 files changed, 27 insertions(+), 17 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index afa420b..bc03554 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -225,8 +225,8 @@ static uint16_t REGREAD8(int X) > /* Common SPI functions */ > static int find_opcode(OPCODES *op, uint8_t opcode); > static int find_preop(OPCODES *op, uint8_t preop); > -static int generate_opcodes(OPCODES * op); > -static int program_opcodes(OPCODES *op, int enable_undo); > +static int generate_opcodes(int ich_generation, OPCODES * op); > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo); > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data); > > @@ -410,7 +410,18 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un > int oppos=2; // use original JEDEC_BE_D8 offset > curopcodes->opcode[oppos].opcode = opcode; > curopcodes->opcode[oppos].spi_type = spi_type; > - program_opcodes(curopcodes, 0); > + switch (spi_programmer->type) { > + case SPI_CONTROLLER_ICH7: > + case SPI_CONTROLLER_VIA: > + program_opcodes(7, curopcodes, 0); > + break; > + case SPI_CONTROLLER_ICH9: > + program_opcodes(9, curopcodes, 0); > + break; > + default: > + msg_perr("%s: unsupported chipset\n", __func__); > + return -1; > + } > oppos = find_opcode(curopcodes, opcode); > msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); > return oppos; > @@ -443,7 +454,7 @@ static int find_preop(OPCODES *op, uint8_t preop) > } > > /* Create a struct OPCODES based on what we find in the locked down chipset. */ > -static int generate_opcodes(OPCODES * op) > +static int generate_opcodes(int ich_generation, OPCODES * op) > { > int a; > uint16_t preop, optype; > @@ -498,7 +509,7 @@ static int generate_opcodes(OPCODES * op) > return 0; > } > > -static int program_opcodes(OPCODES *op, int enable_undo) > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) > { > uint8_t a; > uint16_t preop, optype; > @@ -529,9 +540,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_programmer->type) { > - case SPI_CONTROLLER_ICH7: > - case SPI_CONTROLLER_VIA: > + switch (ich_generation) { > + case 7: > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH7_REG_PREOP); > @@ -544,7 +554,10 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); > break; > - case SPI_CONTROLLER_ICH9: > + case 8: > + case 9: > + case 10: > + default: /* Future version might behave the same */ > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH9_REG_PREOP); > @@ -557,9 +570,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); > break; > - default: > - msg_perr("%s: unsupported chipset\n", __func__); > - return -1; > } > > return 0; > @@ -652,7 +662,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) > * > * It should be called before ICH sends any spi command. > */ > -static int ich_init_opcodes(void) > +static int ich_init_opcodes(int ich_generation) > { > int rc = 0; > OPCODES *curopcodes_done; > @@ -663,11 +673,11 @@ static int ich_init_opcodes(void) > if (ichspi_lock) { > msg_pdbg("Reading OPCODES... "); > curopcodes_done = &O_EXISTING; > - rc = generate_opcodes(curopcodes_done); > + rc = generate_opcodes(ich_generation, curopcodes_done); > } else { > msg_pdbg("Programming OPCODES... "); > curopcodes_done = &O_ST_M25P; > - rc = program_opcodes(curopcodes_done, 1); > + rc = program_opcodes(ich_generation, curopcodes_done, 1); > } > > if (rc) { > @@ -1343,6 +1353,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > + ich_init_opcodes(ich_generation); > > switch (ich_generation) { > case 7: > @@ -1383,7 +1394,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > } > ich_set_bbar(ich_generation, 0); > register_spi_programmer(&spi_programmer_ich7); > - ich_init_opcodes(); > break; > case 8: > case 9: > @@ -1557,7 +1567,7 @@ int via_init_spi(struct pci_dev *dev) > } > > ich_set_bbar(7, 0); > - ich_init_opcodes(); > + ich_init_opcodes(7); > > return 0; > } -- http://www.hailfinger.org/

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Re: [flashrom] Successful test on Asus P5K-VM
by Stefan Tauner 02 Nov '11

02 Nov '11

On Mon, 31 Oct 2011 20:11:54 +0100 Grischa Ebinger <grischa.ebinger(a)gmail.com> wrote: > Hello, > > I was able to successfully reflash the BIOS of a P5K-VM motherboard > with flashrom-0.9.4. It recognized 2 different flash chips (AT25DF081A > and AT26DF081A) at the same address. I selected the first of the two > chipsets. > > I wasn't sure if flashrom did support my hardware. According to your > wiki it wasn't tested before. Luckily, it did its job without a > hiccup. Thank you a lot for providing such a useful tool, I hope I can > help you by sending you this new data. Hello Grischa, Thanks for your report! I have marked the mainboard as supported and will commit that later together with other small changes. > […] > Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT25DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 > Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT26DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Sequential Program Mode Status (SPM) is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > […] > Multiple flash chips were detected: "AT25DF081A", "AT26DF081A" the chips are not found "at the same address", but report the same ID when queried. atmel did no give them distinct IDs so we can not distinguish them on our own, hence your help was required*, sorry. * i have not looked at the respective datesheets. it is possible that the other definition would work equally. > […] > > $ lspci -nnvvxxx > […] not needed in this case. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Flashrom fails to write - Sun Ultra 40 M2
by Stefan Tauner 02 Nov '11

02 Nov '11

On Tue, 25 Oct 2011 11:29:45 -0700 Nick <nochristrequired(a)gmail.com> wrote: > DMI string system-manufacturer: "Sun Microsystems" > DMI string system-product-name: "Sun Ultra 40 M2 Workstation" > DMI string system-version: "11" > DMI string baseboard-manufacturer: "Sun Microsystems" > DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" > DMI string baseboard-version: "50" > > nForce Pro 3600 / MCP55, SMSC SuperIO > > Verbose output when flashing coreboot - > http://paste.flashrom.org/view.php?id=880 > Verbose output when flashing original Sun BIOS image - > http://paste.flashrom.org/view.php?id=881 > > lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 > superiotool -deV output - http://paste.flashrom.org/view.php?id=884 > > Original Sun Ultra 40 M2 BIOS image - > http://paste.flashrom.org/view.php?id=882 hey there, as you know we have a patch to get this working. i have committed it to our repository moments ago so that board will be supported from now (r1458) on. gl with coreboot ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add board enable for Sun Ultra 40 M2
by Joshua Roys 02 Nov '11

02 Nov '11

On 11/02/2011 10:15 AM, Stefan Tauner wrote: > Success report: > http://paste.flashrom.org/view.php?id=889 > Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Stefan, feel free to sign-off also, if you want. > Acked-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > board_enable.c | 33 +++++++++++++++++++++++++++++++++ > print.c | 1 + > 2 files changed, 34 insertions(+), 0 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 1874459..fe2f021 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) > > /* > * Suited for: > + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 > + */ > +static int board_sun_ultra_40_m2(void) > +{ > + int ret; > + uint8_t reg; > + uint16_t base; > + struct pci_dev *dev; > + > + ret = nvidia_mcp_gpio4_lower(); > + if (ret) > + return ret; > + > + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ > + if (!dev) { > + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); > + return -1; > + } > + > + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ > + if (!base) > + return -1; > + > + reg = INB(base + 0x4b); > + reg |= 0x10; > + OUTB(reg, base + 0x4b); > + > + return 0; > +} > + > +/* > + * Suited for: > * - Artec Group DBE61 and DBE62 > */ > static int board_artecgroup_dbe6x(void) > @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { > {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, > {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, > + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, > {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, > {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, > diff --git a/print.c b/print.c > index 05eee9f..91288ee 100644 > --- a/print.c > +++ b/print.c > @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { > B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), > B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), > B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), > + B("Sun", "Ultra 40 M2", 1, NULL, NULL), > B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), > B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), > B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL),

2 1

[commit] r1458 - trunk
by repository service 02 Nov '11

02 Nov '11

Author: stefanct Date: Wed Nov 2 15:31:18 2011 New Revision: 1458 URL: http://flashrom.org/trac/flashrom/changeset/1458 Log: Add board enable for Sun Ultra 40 M2 Failure report with logs: http://www.flashrom.org/pipermail/flashrom/2011-October/008158.html Success report: http://paste.flashrom.org/view.php?id=889 Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/board_enable.c Wed Nov 2 15:31:18 2011 (r1458) @@ -1051,6 +1051,38 @@ /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/print.c Wed Nov 2 15:31:18 2011 (r1458) @@ -846,6 +846,7 @@ B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, "http://download.oracle.com/docs/cd/E19127-01/ultra40.ws/820-0123-13/intro.h…", NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL),

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[PATCH] Add board enable for Sun Ultra 40 M2
by Stefan Tauner 02 Nov '11

02 Nov '11

Success report: http://paste.flashrom.org/view.php?id=889 (mostly) written by Joshua Roy (please add your signed-off tag) and Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 33 +++++++++++++++++++++++++++++++++ print.c | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 1874459..fe2f021 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, diff --git a/print.c b/print.c index 05eee9f..91288ee 100644 --- a/print.c +++ b/print.c @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, NULL, NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), -- 1.7.1

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Re: [flashrom] Programming an A25L40 EEPROM
by Idwer Vollering 02 Nov '11

02 Nov '11

2011/10/27 Arup Basak <arup(a)circuitsdiy.com>: > I have the 512KB bios file, and was trying to program it with flashrom and > buspirate. > Looks like one version of flashrom says "missing libftdi.dll" while another > version says programmer buspirate_spi not supported. Can you find out which version/build showed those messages? > Can you give me link of any latest version. I have tried to copy the > libftdi.dll into the flashrom directory, also tried 'regsrv32 libftdi.dll' > in a command-box (where regsrv32 looks to be absent in Windows 7) This 7z file has (should have) the required dependencies: http://ra.openbios.org/~idwer/flashrom/flashrom_v0.9.4-r1457_mingw_win32_li… If that does not work, install libusb-win32: http://www.libusb.org/wiki/libusb-win32 > > One more thing, when I hooked up the SPI chip to buspirate, if I use > terminal mode of buspirate and set correct mode, then if I try to read some > block using CS enables, I get 0x00 and if I keep CS disabled I get 0xFF. > I've tried to write anything with both CS enabled and disabled. But values > are read as above. > Maybe I've settled up wrong mode while trying to access EEPROM from > buspirate terminal mode. . I've worked with mode 5 spi, 125khz, Clock > polarity:Idle low , Output clock edge:Active to idle, Input sample > phase:middle, Output mode: Normal (H=3.3V, L=GND), W(power supplies on). > I didn't need to do so because for flashing my BIOS chip, I am trying to use > flashrom. > This is the fresh chip I bought for recovery. > http://in.rsdelivers.com/product/amic-technology/a25l040m-f/spi-flash-4mb-s… > Note: The BIOS chips is of my tablet, and not PC, so no problem if it takes > few days to resolve issues and program it. It isn't much serious case when > someone corrupts motherboard's BIOS. I know flashrom's support is free and > takes few hours to get reply. It's not an issue in my case. > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

1 0

Re: [flashrom] Flashrom report
by Stefan Tauner 02 Nov '11

02 Nov '11

On Thu, 27 Oct 2011 11:27:57 +0200 Piotr Czepek <piotr.czepek(a)gmail.com> wrote: > Found chipset "VIA VT8601/VT8601A" with PCI ID 1106:0601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8601T" with PCI ID 1106:8601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8231" with PCI ID 1106:8231. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! can someone please shed some light onto this VIA stuff? i see how this is done in source, but not why. just because we need to write one register in the northbridge(s) to disable "byte merging"? should i just mark all of them as tested? or should i leave the northbridges marked as untested because we did not enter the "if (byte merge enabled)" branch? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

(no subject)
by yarpr＠pochta.ru 02 Nov '11

02 Nov '11

 _ Only here you can find ha.ppiness in personal r_elationships 

1 0

[PATCH] Register opaque and parallel/LPC/FWH programmers
by Carl-Daniel Hailfinger 02 Nov '11

02 Nov '11

Just to show how it should look like once all type-specific programmer registration patches are applied. The generic programmer registration patch will live on top of this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-register_all_programmers/flash.h =================================================================== --- flashrom-register_all_programmers/flash.h (Revision 1457) +++ flashrom-register_all_programmers/flash.h (Arbeitskopie) @@ -62,8 +62,9 @@ BUS_LPC = 1 << 1, BUS_FWH = 1 << 2, BUS_SPI = 1 << 3, + BUS_PROG = 1 << 4, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, - BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI, + BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI | BUS_PROG, }; /* Index: flashrom-register_all_programmers/drkaiser.c =================================================================== --- flashrom-register_all_programmers/drkaiser.c (Revision 1457) +++ flashrom-register_all_programmers/drkaiser.c (Arbeitskopie) @@ -39,6 +39,19 @@ static uint8_t *drkaiser_bar; +static const struct par_programmer par_programmer_drkaiser = { + .chip_readb = drkaiser_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = drkaiser_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); @@ -64,7 +77,8 @@ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + max_rom_decode.parallel = 131072; if (register_shutdown(drkaiser_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/it87spi.c =================================================================== --- flashrom-register_all_programmers/it87spi.c (Revision 1457) +++ flashrom-register_all_programmers/it87spi.c (Arbeitskopie) @@ -192,7 +192,7 @@ free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; - if (buses_supported & BUS_SPI) + if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ register_spi_programmer(&spi_programmer_it87xx); Index: flashrom-register_all_programmers/gfxnvidia.c =================================================================== --- flashrom-register_all_programmers/gfxnvidia.c (Revision 1457) +++ flashrom-register_all_programmers/gfxnvidia.c (Arbeitskopie) @@ -61,6 +61,19 @@ {}, }; +static const struct par_programmer par_programmer_gfxnvidia = { + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); @@ -94,7 +107,7 @@ reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); /* Write/erase doesn't work. */ programmer_may_write = 0; Index: flashrom-register_all_programmers/serprog.c =================================================================== --- flashrom-register_all_programmers/serprog.c (Revision 1457) +++ flashrom-register_all_programmers/serprog.c (Arbeitskopie) @@ -309,6 +309,21 @@ .write_256 = default_spi_write_256, }; +static const struct par_programmer par_programmer_serprog = { + .chip_readb = serprog_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = serprog_chip_readn, + .chip_writeb = serprog_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + +static enum chipbustype serprog_buses_supported = BUS_NONE; + int serprog_init(void) { uint16_t iface; @@ -400,11 +415,13 @@ if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { msg_perr("Error: NAK to query interface version\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (iface != 1) { msg_perr("Error: Unknown interface version: %d\n", iface); + // FIXME: Clean up and return an error instead. exit(1); } @@ -412,28 +429,34 @@ if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { msg_perr("Error: query command map not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } sp_check_avail_automatic = 1; - + /* FIXME: This assumes that serprog device bustypes are always + * identical with flashrom bustype enums and that they all fit + * in a single byte. + */ if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { msg_perr("Warning: NAK to query supported buses\n"); c = BUS_NONSPI; /* A reasonable default for now. */ } - buses_supported = c; + serprog_buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", (c & BUS_PARALLEL) ? "on" : "off", (c & BUS_LPC) ? "on" : "off", (c & BUS_FWH) ? "on" : "off", (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ - if (buses_supported & BUS_SPI) { + if (serprog_buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); + // FIXME: Clean up and return an error instead. exit(1); } /* Success of any of these commands is optional. We don't need @@ -461,21 +484,22 @@ spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } - bt = buses_supported; + bt = serprog_buses_supported; sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); - register_spi_programmer(&spi_programmer_serprog); } - if (buses_supported & BUS_NONSPI) { + if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { msg_perr("Error: Initialize operation buffer " "not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { msg_perr("Error: Write to opbuf: " "delay not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -483,17 +507,20 @@ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { msg_perr("Error: Single byte read not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { msg_perr("Error: Read n bytes not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { msg_perr("Error: Write to opbuf: " "write byte not supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -513,6 +540,7 @@ if (!sp_write_n_buf) { msg_perr("Error: cannot allocate memory for " "Write-n buffer\n"); + // FIXME: Clean up and return an error instead. exit(1); } sp_write_n_bytes = 0; @@ -551,11 +579,13 @@ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { msg_perr("Error: Execute operation buffer not " "supported\n"); + // FIXME: Clean up and return an error instead. exit(1); } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); + // FIXME: Clean up and return an error instead. exit(1); } @@ -572,6 +602,11 @@ sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; + if (serprog_buses_supported & BUS_SPI) + register_spi_programmer(&spi_programmer_serprog); + if (serprog_buses_supported & BUS_NONSPI) + register_par_programmer(&par_programmer_serprog, + serprog_buses_supported & BUS_NONSPI); return 0; } Index: flashrom-register_all_programmers/nicrealtek.c =================================================================== --- flashrom-register_all_programmers/nicrealtek.c (Revision 1457) +++ flashrom-register_all_programmers/nicrealtek.c (Arbeitskopie) @@ -36,6 +36,19 @@ {}, }; +static const struct par_programmer par_programmer_nicrealtek = { + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ @@ -50,7 +63,7 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/satamv.c =================================================================== --- flashrom-register_all_programmers/satamv.c (Revision 1457) +++ flashrom-register_all_programmers/satamv.c (Arbeitskopie) @@ -41,6 +41,19 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static const struct par_programmer par_programmer_satamv = { + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); @@ -137,7 +150,7 @@ mv_iobar = tmp & 0xffff; msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ Index: flashrom-register_all_programmers/Makefile =================================================================== --- flashrom-register_all_programmers/Makefile (Revision 1457) +++ flashrom-register_all_programmers/Makefile (Arbeitskopie) @@ -242,7 +242,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o + a25.o at25.o opaque.o LIB_OBJS = layout.o Index: flashrom-register_all_programmers/dummyflasher.c =================================================================== --- flashrom-register_all_programmers/dummyflasher.c (Revision 1457) +++ flashrom-register_all_programmers/dummyflasher.c (Arbeitskopie) @@ -75,6 +75,21 @@ .write_256 = dummy_spi_write_256, }; +static const struct par_programmer par_programmer_dummy = { + .chip_readb = dummy_chip_readb, + .chip_readw = dummy_chip_readw, + .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, + .chip_writeb = dummy_chip_writeb, + .chip_writew = dummy_chip_writew, + .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, + .map_flash_region = dummy_map, + .unmap_flash_region = dummy_unmap, +}; + +enum chipbustype dummy_buses_supported = BUS_NONE; + static int dummy_shutdown(void *data) { msg_pspew("%s\n", __func__); @@ -108,24 +123,29 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - buses_supported = BUS_NONE; + dummy_buses_supported = BUS_NONE; if (strstr(bustext, "parallel")) { - buses_supported |= BUS_PARALLEL; + dummy_buses_supported |= BUS_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); } if (strstr(bustext, "lpc")) { - buses_supported |= BUS_LPC; + dummy_buses_supported |= BUS_LPC; msg_pdbg("Enabling support for %s flash.\n", "LPC"); } if (strstr(bustext, "fwh")) { - buses_supported |= BUS_FWH; + dummy_buses_supported |= BUS_FWH; msg_pdbg("Enabling support for %s flash.\n", "FWH"); } + if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) + register_par_programmer(&par_programmer_dummy, + dummy_buses_supported & + (BUS_PARALLEL | BUS_LPC | + BUS_FWH)); if (strstr(bustext, "spi")) { register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } - if (buses_supported == BUS_NONE) + if (dummy_buses_supported == BUS_NONE) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); Index: flashrom-register_all_programmers/cli_classic.c =================================================================== --- flashrom-register_all_programmers/cli_classic.c (Revision 1457) +++ flashrom-register_all_programmers/cli_classic.c (Arbeitskopie) @@ -443,7 +443,10 @@ ret = 1; goto out_shutdown; } + msg_pdbg("This programmer supports the following protocols: %s.\n", + flashbuses_to_text(buses_supported)); + for (i = 0; i < ARRAY_SIZE(flashes); i++) { startchip = probe_flash(startchip, &flashes[i], 0); if (startchip == -1) Index: flashrom-register_all_programmers/internal.c =================================================================== --- flashrom-register_all_programmers/internal.c (Revision 1457) +++ flashrom-register_all_programmers/internal.c (Arbeitskopie) @@ -127,6 +127,21 @@ int is_laptop = 0; int laptop_ok = 0; +static const struct par_programmer par_programmer_internal = { + .chip_readb = internal_chip_readb, + .chip_readw = internal_chip_readw, + .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, + .chip_writeb = internal_chip_writeb, + .chip_writew = internal_chip_writew, + .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = physmap, + .unmap_flash_region = physunmap, +}; + +enum chipbustype internal_buses_supported = BUS_NONE; + static int internal_shutdown(void *data) { release_io_perms(); @@ -191,9 +206,10 @@ return 1; /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. + * is found, the host controller init routine sets the + * internal_buses_supported bitfield. */ - buses_supported = BUS_NONSPI; + internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ @@ -287,6 +303,7 @@ * Besides that, we don't check the board enable return code either. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) + register_par_programmer(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-register_all_programmers/ichspi.c =================================================================== --- flashrom-register_all_programmers/ichspi.c (Revision 1457) +++ flashrom-register_all_programmers/ichspi.c (Arbeitskopie) @@ -1523,7 +1523,7 @@ ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); /* Not sure if it speaks all these bus protocols. */ - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; register_spi_programmer(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); Index: flashrom-register_all_programmers/opaque.c =================================================================== --- flashrom-register_all_programmers/opaque.c (Revision 0) +++ flashrom-register_all_programmers/opaque.c (Revision 0) @@ -0,0 +1,93 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the opaque programmer framework. + * An opaque programmer is a programmer which does not provide direct access + * to the flash chip and which abstracts all flash chip properties into a + * programmer specific interface. + */ + +#include <strings.h> +#include <string.h> +#include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "programmer.h" + +const struct opaque_programmer opaque_programmer_none = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .probe = NULL, + .read = NULL, + .write = NULL, +}; + +const struct opaque_programmer *opaque_programmer = &opaque_programmer_none; + +int probe_opaque(struct flashchip *flash) +{ + if (!opaque_programmer->probe) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + return opaque_programmer->probe(flash); +} + +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->read) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->read(flash, buf, start, len); +} + +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (!opaque_programmer->write) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->write(flash, buf, start, len); +} + +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +{ + if (!opaque_programmer->erase) { + msg_perr("%s called, but this is not an opaque programmer. " + "Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 1; + } + return opaque_programmer->erase(flash, blockaddr, blocklen); +} + +void register_opaque_programmer(const struct opaque_programmer *pgm) +{ + opaque_programmer = pgm; + buses_supported |= BUS_PROG; +} Index: flashrom-register_all_programmers/nicnatsemi.c =================================================================== --- flashrom-register_all_programmers/nicnatsemi.c (Revision 1457) +++ flashrom-register_all_programmers/nicnatsemi.c (Arbeitskopie) @@ -35,6 +35,19 @@ {}, }; +static const struct par_programmer par_programmer_nicnatsemi = { + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicnatsemi_shutdown(void *data) { pci_cleanup(pacc); @@ -48,7 +61,7 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket Index: flashrom-register_all_programmers/it85spi.c =================================================================== --- flashrom-register_all_programmers/it85spi.c (Revision 1457) +++ flashrom-register_all_programmers/it85spi.c (Arbeitskopie) @@ -257,8 +257,10 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("it85 communication", - 0xFFFFF000, 0x1000); + /* FIXME: We should block accessing that region for anything else. + * Major TODO here, and it will be a lot of work. + */ + base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ @@ -285,18 +287,26 @@ { int ret; - if (!(buses_supported & BUS_FWH)) { + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; } ret = it85xx_spi_common_init(s); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); if (!ret) { - msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, - buses_supported); - if (buses_supported & BUS_FWH) - msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); - /* Really leave FWH enabled? */ + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ /* Set this as SPI controller. */ register_spi_programmer(&spi_programmer_it85xx); } Index: flashrom-register_all_programmers/atahpt.c =================================================================== --- flashrom-register_all_programmers/atahpt.c (Revision 1457) +++ flashrom-register_all_programmers/atahpt.c (Arbeitskopie) @@ -40,6 +40,19 @@ {}, }; +static const struct par_programmer par_programmer_atahpt = { + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int atahpt_shutdown(void *data) { /* Flash access is disabled automatically by PCI restore. */ @@ -61,7 +74,7 @@ reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); if (register_shutdown(atahpt_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/flashchips.c =================================================================== --- flashrom-register_all_programmers/flashchips.c (Revision 1457) +++ flashrom-register_all_programmers/flashchips.c (Arbeitskopie) @@ -8872,8 +8872,30 @@ .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { + .vendor = "Programmer", + .name = "Opaque flash chip", + .bustype = BUS_PROG, + .manufacture_id = PROGMANUF_ID, + .model_id = PROGDEV_ID, + .total_size = 0, + .page_size = 256, + /* probe is assumed to work, rest will be filled in by probe */ + .tested = TEST_OK_PROBE, + .probe = probe_opaque, + /* eraseblock sizes will be set by the probing function */ + .block_erasers = + { + { + .block_erase = erase_opaque, + } + }, + .write = write_opaque, + .read = read_opaque, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { .vendor = "AMIC", .name = "unknown AMIC SPI chip", .bustype = BUS_SPI, @@ -9005,6 +9027,7 @@ .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", Index: flashrom-register_all_programmers/flashchips.h =================================================================== --- flashrom-register_all_programmers/flashchips.h (Revision 1457) +++ flashrom-register_all_programmers/flashchips.h (Arbeitskopie) @@ -646,4 +646,7 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 +#define PROGMANUF_ID 0xFFFE /* dummy ID for opaque chips behind a programmer */ +#define PROGDEV_ID 0x01 /* dummy ID for opaque chips behind a programmer */ + #endif /* !FLASHCHIPS_H */ Index: flashrom-register_all_programmers/nic3com.c =================================================================== --- flashrom-register_all_programmers/nic3com.c (Revision 1457) +++ flashrom-register_all_programmers/nic3com.c (Arbeitskopie) @@ -55,6 +55,19 @@ {}, }; +static const struct par_programmer par_programmer_nic3com = { + .chip_readb = nic3com_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nic3com_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nic3com_shutdown(void *data) { /* 3COM 3C90xB cards need a special fixup. */ @@ -96,8 +109,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - buses_supported = BUS_PARALLEL; max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); if (register_shutdown(nic3com_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/satasii.c =================================================================== --- flashrom-register_all_programmers/satasii.c (Revision 1457) +++ flashrom-register_all_programmers/satasii.c (Arbeitskopie) @@ -42,6 +42,19 @@ {}, }; +static const struct par_programmer par_programmer_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); @@ -76,7 +89,7 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - buses_supported = BUS_PARALLEL; + register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); if (register_shutdown(satasii_shutdown, NULL)) return 1; Index: flashrom-register_all_programmers/chipset_enable.c =================================================================== --- flashrom-register_all_programmers/chipset_enable.c (Revision 1457) +++ flashrom-register_all_programmers/chipset_enable.c (Arbeitskopie) @@ -213,7 +213,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; old = pci_read_word(dev, xbcs); @@ -303,7 +303,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -412,9 +412,9 @@ msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override - * buses_supported anyway. + * internal_buses_supported anyway. */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -434,7 +434,7 @@ if (new != old) rpci_write_byte(dev, 0xd9, new); - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } @@ -468,12 +468,11 @@ bnt = mmio_readl(rcrb + 0x3410); if (bnt & 0x02) { /* If strapped to LPC, no SPI initialization is required */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; return 0; } /* This adds BUS_SPI */ - buses_supported = BUS_SPI; if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { if (!ret) ret = ERROR_NONFATAL; @@ -556,7 +555,7 @@ * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; + internal_buses_supported = BUS_FWH; if (ich_generation == 7) { if (bbs == 0x03) { /* If strapped to LPC, no further SPI initialization is @@ -564,7 +563,7 @@ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ - buses_supported = 0; + internal_buses_supported = BUS_NONE; } } @@ -667,7 +666,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -820,7 +819,7 @@ (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); } - buses_supported = BUS_LPC | BUS_FWH; + internal_buses_supported = BUS_LPC | BUS_FWH; ret = sb600_probe_spi(dev); @@ -914,7 +913,7 @@ { uint8_t tmp; - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -1014,7 +1013,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(dev, name); - buses_supported = BUS_LPC; + internal_buses_supported = BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -1022,7 +1021,7 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); msg_pinfo("SPI on this chipset is WIP. Please report any " "success or failure by mailing us the verbose " @@ -1030,7 +1029,7 @@ break; default: /* Should not happen. */ - buses_supported = BUS_NONE; + internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is unknown (none)\n"); msg_pinfo("Something went wrong with bus type detection.\n"); goto out_msg; @@ -1323,7 +1322,6 @@ struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ int i; - char *s; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { @@ -1375,9 +1373,5 @@ } } - s = flashbuses_to_text(buses_supported); - msg_pinfo("This chipset supports the following protocols: %s.\n", s); - free(s); - return ret; } Index: flashrom-register_all_programmers/nicintel.c =================================================================== --- flashrom-register_all_programmers/nicintel.c (Revision 1457) +++ flashrom-register_all_programmers/nicintel.c (Arbeitskopie) @@ -43,6 +43,19 @@ #define CSR_FCR 0x0c +static const struct par_programmer par_programmer_nicintel = { + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); @@ -93,9 +106,8 @@ */ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); - buses_supported = BUS_PARALLEL; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-register_all_programmers/flashrom.c =================================================================== --- flashrom-register_all_programmers/flashrom.c (Revision 1457) +++ flashrom-register_all_programmers/flashrom.c (Arbeitskopie) @@ -66,16 +66,6 @@ { .name = "internal", .init = internal_init, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, - .chip_readb = internal_chip_readb, - .chip_readw = internal_chip_readw, - .chip_readl = internal_chip_readl, - .chip_readn = internal_chip_readn, - .chip_writeb = internal_chip_writeb, - .chip_writew = internal_chip_writew, - .chip_writel = internal_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -84,16 +74,6 @@ { .name = "dummy", .init = dummy_init, - .map_flash_region = dummy_map, - .unmap_flash_region = dummy_unmap, - .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, - .chip_readn = dummy_chip_readn, - .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, - .chip_writen = dummy_chip_writen, .delay = internal_delay, }, #endif @@ -102,16 +82,6 @@ { .name = "nic3com", .init = nic3com_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nic3com_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nic3com_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -122,16 +92,6 @@ .name = "nicrealtek", //.name = "nicsmc1211", .init = nicrealtek_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -140,16 +100,6 @@ { .name = "nicnatsemi", .init = nicnatsemi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -158,16 +108,6 @@ { .name = "gfxnvidia", .init = gfxnvidia_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = gfxnvidia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = gfxnvidia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -176,16 +116,6 @@ { .name = "drkaiser", .init = drkaiser_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = drkaiser_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = drkaiser_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -194,16 +124,6 @@ { .name = "satasii", .init = satasii_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -212,16 +132,6 @@ { .name = "atahpt", .init = atahpt_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = atahpt_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atahpt_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -230,16 +140,6 @@ { .name = "ft2232_spi", .init = ft2232_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -248,16 +148,6 @@ { .name = "serprog", .init = serprog_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = serprog_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = serprog_chip_readn, - .chip_writeb = serprog_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = serprog_delay, }, #endif @@ -266,16 +156,6 @@ { .name = "buspirate_spi", .init = buspirate_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -284,16 +164,6 @@ { .name = "dediprog", .init = dediprog_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -302,16 +172,6 @@ { .name = "rayer_spi", .init = rayer_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -320,16 +180,6 @@ { .name = "nicintel", .init = nicintel_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = nicintel_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicintel_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -338,16 +188,6 @@ { .name = "nicintel_spi", .init = nicintel_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -356,16 +196,6 @@ { .name = "ogp_spi", .init = ogp_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -374,16 +204,6 @@ { .name = "satamv", .init = satamv_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = satamv_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satamv_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -392,16 +212,6 @@ { .name = "linux_spi", .init = linux_spi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -502,53 +312,52 @@ void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len) { - return programmer_table[programmer].map_flash_region(descr, - phys_addr, len); + return par_programmer->map_flash_region(descr, phys_addr, len); } void programmer_unmap_flash_region(void *virt_addr, size_t len) { - programmer_table[programmer].unmap_flash_region(virt_addr, len); + par_programmer->unmap_flash_region(virt_addr, len); } void chip_writeb(uint8_t val, chipaddr addr) { - programmer_table[programmer].chip_writeb(val, addr); + par_programmer->chip_writeb(val, addr); } void chip_writew(uint16_t val, chipaddr addr) { - programmer_table[programmer].chip_writew(val, addr); + par_programmer->chip_writew(val, addr); } void chip_writel(uint32_t val, chipaddr addr) { - programmer_table[programmer].chip_writel(val, addr); + par_programmer->chip_writel(val, addr); } void chip_writen(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_writen(buf, addr, len); + par_programmer->chip_writen(buf, addr, len); } uint8_t chip_readb(const chipaddr addr) { - return programmer_table[programmer].chip_readb(addr); + return par_programmer->chip_readb(addr); } uint16_t chip_readw(const chipaddr addr) { - return programmer_table[programmer].chip_readw(addr); + return par_programmer->chip_readw(addr); } uint32_t chip_readl(const chipaddr addr) { - return programmer_table[programmer].chip_readl(addr); + return par_programmer->chip_readl(addr); } void chip_readn(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_readn(buf, addr, len); + par_programmer->chip_readn(buf, addr, len); } void programmer_delay(int usecs) @@ -1156,7 +965,7 @@ return -1; #if CONFIG_INTERNAL == 1 - if (programmer_table[programmer].map_flash_region == physmap) + if (par_programmer->map_flash_region == physmap) snprintf(location, sizeof(location), "at physical address 0x%lx", base); else #endif Index: flashrom-register_all_programmers/programmer.c =================================================================== --- flashrom-register_all_programmers/programmer.c (Revision 1457) +++ flashrom-register_all_programmers/programmer.c (Arbeitskopie) @@ -19,7 +19,23 @@ */ #include "flash.h" +#include "programmer.h" +static const struct par_programmer par_programmer_none = { + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, +}; + +const struct par_programmer *par_programmer = &par_programmer_none; + /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) { @@ -96,3 +112,9 @@ buf[i] = chip_readb(addr + i); return; } + +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) +{ + par_programmer = pgm; + buses_supported |= buses; +} Index: flashrom-register_all_programmers/programmer.h =================================================================== --- flashrom-register_all_programmers/programmer.h (Revision 1457) +++ flashrom-register_all_programmers/programmer.h (Arbeitskopie) @@ -91,18 +91,6 @@ int (*init) (void); - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); - void (*unmap_flash_region) (void *virt_addr, size_t len); - - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -304,6 +292,7 @@ extern int force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); +extern enum chipbustype internal_buses_supported; int internal_init(void); void internal_chip_writeb(uint8_t val, chipaddr addr); void internal_chip_writew(uint16_t val, chipaddr addr); @@ -358,7 +347,23 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); + void *(*map_flash_region) (const char *descr, unsigned long phys_addr, + size_t len); + void (*unmap_flash_region) (void *virt_addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); + /* dummyflasher.c */ #if CONFIG_DUMMY == 1 int dummy_init(void); @@ -601,6 +606,19 @@ int wbsio_check_for_spi(void); #endif +/* opaque.c */ +struct opaque_programmer { + int max_data_read; + int max_data_write; + /* Specific functions for this programmer */ + int (*probe) (struct flashchip *flash); + int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); +}; +extern const struct opaque_programmer *opaque_programmer; +void register_opaque_programmer(const struct opaque_programmer *pgm); + /* serprog.c */ #if CONFIG_SERPROG == 1 int serprog_init(void); Index: flashrom-register_all_programmers/chipdrivers.h =================================================================== --- flashrom-register_all_programmers/chipdrivers.h (Revision 1457) +++ flashrom-register_all_programmers/chipdrivers.h (Arbeitskopie) @@ -58,6 +58,12 @@ int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +/* opaque.c */ +int probe_opaque(struct flashchip *flash); +int read_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int write_opaque(struct flashchip *flash, uint8_t *buf, int start, int len); +int erase_opaque(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); + /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); Index: flashrom-register_all_programmers/print.c =================================================================== --- flashrom-register_all_programmers/print.c (Revision 1457) +++ flashrom-register_all_programmers/print.c (Arbeitskopie) @@ -49,6 +49,8 @@ ret = strcat_realloc(ret, "FWH, "); if (bustype & BUS_SPI) ret = strcat_realloc(ret, "SPI, "); + if (bustype & BUS_PROG) + ret = strcat_realloc(ret, "Programmer-specific, "); if (bustype == BUS_NONE) ret = strcat_realloc(ret, "None, "); } Index: flashrom-register_all_programmers/board_enable.c =================================================================== --- flashrom-register_all_programmers/board_enable.c (Revision 1457) +++ flashrom-register_all_programmers/board_enable.c (Arbeitskopie) @@ -425,7 +425,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - buses_supported = BUS_PARALLEL; + internal_buses_supported = BUS_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); -- http://www.hailfinger.org/

1 0

PMC Flash Pm29F002T-90PC - Write OK
by Marcos Felipe Rasia de Mello 31 Oct '11

31 Oct '11

It was tested in an Asus TUV4X (the original flash is a Winbond W49F002U-12B). Unfortunately this board uses the infamous AS99127F: http://www.flashrom.org/pipermail/flashrom/2010-February/002339.html After "modprobe i2c-dev; i2cset 0 0x48 0x80 0x80" flashrom works normally and update both chips without problems. (didn't need to unload w83781d because I don't have lm-sensors installed here) Log attached. Regards, Marcos

1 0

Successful test on Asus P5K-VM
by Grischa Ebinger 31 Oct '11

31 Oct '11

Hello, I was able to successfully reflash the BIOS of a P5K-VM motherboard with flashrom-0.9.4. It recognized 2 different flash chips (AT25DF081A and AT26DF081A) at the same address. I selected the first of the two chipsets. I wasn't sure if flashrom did support my hardware. According to your wiki it wasn't tested before. Luckily, it did its job without a hiccup. Thank you a lot for providing such a useful tool, I hope I can help you by sending you this new data. greetings, greb Here the requested debug data: $ flashrom -V flashrom v0.9.4-r1395 on Linux 3.0.6-gentoo (x86_64), built with libpci 3.1.7, GCC 4.5.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1996M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10000 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "P5K-VM" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5K-VM" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found chipset "Intel ICH9" with PCI ID 8086:2918. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=0, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000202 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x02, BRRA 0x02 0x54: 0x00001fff (FREG0: Flash Descriptor) Flash Descriptor region is unused. 0x58: 0x00001fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x00001fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0xd43b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x3906019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Chip status register is 00 Found Atmel flash chip "AT25DF081A" (1024 kB, SPI) at physical address 0xfff00000. Ignoring security lockdown (if present) Ignoring status register byte 2 Chip status register is 00 Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is asserted Chip status register: Software Protection Status (SWP): no sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Chip status register is 00 Found Atmel flash chip "AT26DF081A" (1024 kB, SPI) at physical address 0xfff00000. Chip status register is 00 Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Sequential Program Mode Status (SPM) is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is asserted Chip status register: Software Protection Status (SWP): no sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x35, id2 0xc6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0xff, id2 0xff Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x35, id2 0xc6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x51, id2 0x39, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x35, id2 0xc6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x35, id2 0xc6, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff Multiple flash chips were detected: "AT25DF081A", "AT26DF081A" Please specify which chip to use with the -c <chipname> option. Restoring MMIO space at 0x7f1d122d58a0 Restoring MMIO space at 0x7f1d122d589c Restoring MMIO space at 0x7f1d122d5898 Restoring MMIO space at 0x7f1d122d5896 Restoring MMIO space at 0x7f1d122d5894 Restoring PCI config space for 00:1f:0 reg 0xdc $ lspci -nnvvxxx 00:00.0 Host bridge [0600]: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller [8086:29c0] (rev 02) Subsystem: ASUSTeK Computer Inc. Device [1043:8276] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0b <?> Kernel driver in use: agpgart-intel 00: 86 80 c0 29 06 00 90 a0 02 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 76 82 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d1 fe 01 00 00 00 01 00 6b 7f 00 00 00 00 50: 00 00 30 01 09 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 01 00 00 33 33 00 ff 03 00 00 00 1a 38 00 a0: 20 00 00 08 00 00 80 7f 00 00 70 7f 00 00 70 7f b0: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 49 00 00 00 00 00 00 00 e0: 09 00 0b 01 20 00 25 09 47 0c 06 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 90 0f 03 00 00 00 00 00 00:02.0 VGA compatible controller [0300]: Intel Corporation 82G33/G31 Express Integrated Graphics Controller [8086:29c2] (rev 02) (prog-if 00 [VGA controller]) Subsystem: ASUSTeK Computer Inc. Device [1043:8276] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fe980000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at bc00 [size=8] Region 2: Memory at d0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at fe800000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: i915 00: 86 80 c2 29 07 00 90 00 02 00 00 03 00 00 00 00 10: 00 00 98 fe 01 bc 00 00 08 00 00 d0 00 00 80 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 76 82 30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 40: 09 00 0b 01 20 00 25 09 47 0c 06 00 00 00 00 00 50: 00 00 30 01 09 00 00 00 00 00 00 00 00 00 80 7f 60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 05 d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 11 11 00 00 00 00 06 03 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 01 02 00 e0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 f0: 12 00 03 00 00 00 00 00 90 0f 03 00 f4 e0 68 7f 00:1a.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at b480 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 37 29 05 00 90 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 b4 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1a.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at b800 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 38 29 05 00 90 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 b8 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1a.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at b880 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 39 29 05 00 90 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 b8 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1a.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 0: Memory at fe97bc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] Vendor Specific Information: Len=06 <?> Kernel driver in use: ehci_hcd 00: 86 80 3c 29 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 bc 97 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 cf 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 09 00 06 20 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 02 00 06 17 02 20 00:1b.0 Audio device [0403]: Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] (rev 02) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 22 Region 0: Memory at fe974000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=1 ArbSelect=Fixed TC/VC=80 Status: NegoPending- InProgress- Capabilities: [130 v1] Root Complex Link Desc: PortNumber=0f ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c000 Kernel driver in use: HDA Intel 00: 86 80 3e 29 06 00 10 00 02 00 03 04 08 00 00 00 10: 04 40 97 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 00 00 40: 01 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 91 00 00 00 00 10 00 08 10 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 04 00 01 00 00 00 00 31 00 a3 02 00 00 00 00 d0: 61 00 a3 02 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.0 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 [8086:2940] (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: 7fd00000-800fffff Prefetchable memory behind bridge: 00000000fdf00000-00000000fdffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=01 ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c000 Kernel driver in use: pcieport 00: 86 80 40 29 07 01 10 00 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 10 10 00 00 20: d0 7f 00 80 f1 fd f1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 41 4c 11 01 50: 00 00 01 10 60 05 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 43 10 77 82 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.4 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 [8086:2948] (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: 7f900000-7fafffff Prefetchable memory behind bridge: 000000007fb00000-000000007fcfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=05 ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c000 Kernel driver in use: pcieport 00: 86 80 48 29 07 01 10 00 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 d0 d0 00 00 20: 90 7f a0 7f b1 7f c1 7f 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 05 50: 40 00 11 30 60 05 00 00 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 43 10 77 82 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1c.5 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 [8086:294a] (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: fea00000-feafffff Prefetchable memory behind bridge: 000000007f700000-000000007f8fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #6, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed+ WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: [180 v1] Root Complex Link Desc: PortNumber=06 ComponentID=00 EltType=Config Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ Addr: 00000000fed1c000 Kernel driver in use: pcieport 00: 86 80 4a 29 07 01 10 00 02 00 04 06 08 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 c0 c0 00 00 20: a0 fe a0 fe 71 7f 81 7f 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 06 50: 40 00 11 30 60 05 00 00 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 43 10 77 82 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 00 c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 4: I/O ports at b000 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 34 29 05 00 90 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 b0 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 0e 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at b080 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 35 29 05 00 90 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 b0 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] (rev 02) (prog-if 00 [UHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at b400 [size=32] Capabilities: [50] Vendor Specific Information: Len=06 <?> Kernel driver in use: uhci_hcd 00: 86 80 36 29 05 00 90 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 b4 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] (rev 02) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at fe97b800 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] Vendor Specific Information: Len=06 <?> Kernel driver in use: ehci_hcd 00: 86 80 3a 29 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 b8 97 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 50 00 00 00 00 00 00 00 0e 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 df 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 09 00 06 20 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 02 00 06 17 02 20 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 92) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=32 I/O behind bridge: 0000e000-0000efff Memory behind bridge: feb00000-febfffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR+ BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: ASUSTeK Computer Inc. Device [1043:8277] 00: 86 80 4e 24 07 01 10 00 92 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 20 e0 e0 80 a2 20: b0 fe b0 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 02 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 50: 0d 00 00 00 43 10 77 82 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.0 ISA bridge [0601]: Intel Corporation 82801IB (ICH9) LPC Interface Controller [8086:2918] (rev 02) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0c <?> 00: 86 80 18 29 07 00 10 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 80 00 00 00 81 04 00 00 10 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 8b 8a 85 8b d0 00 00 00 8a 83 8f 8e f8 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 0f 14 95 02 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 28 06 00 00 39 00 00 00 13 00 00 00 00 03 00 00 b0: 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 e0: 09 00 0c 10 20 00 24 0a 60 00 00 00 00 00 00 00 f0: 01 c0 d1 fe 03 79 0e 00 86 0f 02 00 00 00 00 00 00:1f.2 IDE interface [0101]: Intel Corporation 82801IB (ICH9) 2 port SATA IDE Controller [8086:2921] (rev 02) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 22 Region 0: I/O ports at 9c00 [size=8] Region 1: I/O ports at 9880 [size=4] Region 2: I/O ports at 9800 [size=8] Region 3: I/O ports at 9480 [size=4] Region 4: I/O ports at 9400 [size=16] Region 5: I/O ports at 9080 [size=16] Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Vendor Specific Information: Len=06 <?> Kernel driver in use: ata_piix 00: 86 80 21 29 07 00 b0 02 02 8f 01 01 00 00 00 00 10: 01 9c 00 00 81 98 00 00 01 98 00 00 81 94 00 00 20: 01 94 00 00 81 90 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 70 00 00 00 00 00 00 00 0f 02 00 00 40: 07 a3 03 a3 00 00 00 00 05 00 01 01 00 00 00 00 50: 00 00 00 00 f0 50 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 b0 03 00 08 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 03 83 93 01 00 00 00 00 00 00 01 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] (rev 02) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 18 Region 0: Memory at fe97b400 (64-bit, non-prefetchable) [size=256] Region 4: I/O ports at 0400 [size=32] Kernel driver in use: i801_smbus 00: 86 80 30 29 03 00 80 02 02 00 05 0c 00 00 00 00 10: 04 b4 97 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 03 04 04 00 00 00 08 08 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 00:1f.5 IDE interface [0101]: Intel Corporation 82801I (ICH9 Family) 2 port SATA IDE Controller [8086:2926] (rev 02) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. Device [1043:8277] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 22 Region 0: I/O ports at ac00 [size=8] Region 1: I/O ports at a880 [size=4] Region 2: I/O ports at a800 [size=8] Region 3: I/O ports at a480 [size=4] Region 4: I/O ports at a400 [size=16] Region 5: I/O ports at a080 [size=16] Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Vendor Specific Information: Len=06 <?> Kernel driver in use: ata_piix 00: 86 80 26 29 07 00 b0 02 02 85 01 01 00 00 00 00 10: 01 ac 00 00 81 a8 00 00 01 a8 00 00 81 a4 00 00 20: 01 a4 00 00 81 a0 00 00 00 00 00 00 43 10 77 82 30: 00 00 00 00 70 00 00 00 00 00 00 00 0f 02 00 00 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 b0 03 00 08 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 01:00.0 Ethernet controller [0200]: Marvell Technology Group Ltd. 88E8056 PCI-E Gigabit Ethernet Controller [11ab:4364] (rev 12) Subsystem: ASUSTeK Computer Inc. Device [1043:81f8] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at feafc000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at c800 [size=256] Expansion ROM at feac0000 [disabled] [size=128K] Capabilities: [48] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Marvell Yukon 88E8056 Gigabit Ethernet Controller Read-only fields: [PN] Part number: Yukon 88E8056 [EC] Engineering changes: Rev. 1.2 [MN] Manufacture ID: 4d 61 72 76 65 6c 6c [SN] Serial number: AbCdEfGDA0F5F [CP] Extended capability: 01 10 cc 03 [RV] Reserved: checksum good, 9 byte(s) reserved Read/write fields: [RW] Read-write area: 121 byte(s) free End Capabilities: [5c] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [e0] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 1f, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: sky2 00: ab 11 64 43 07 00 10 00 12 00 00 02 08 00 00 00 10: 04 c0 af fe 00 00 00 00 01 c8 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 f8 81 30: 00 00 ac fe 48 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 f0 01 00 80 a0 01 01 50 03 fe 00 20 00 13 50: 03 5c fc 80 00 00 00 78 00 00 00 01 05 e0 80 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 70 00 00 00 00 00 00 82 a8 e8 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 10 00 11 00 c0 8f 28 00 00 20 19 00 11 ac 07 00 f0: 48 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 IDE interface [0101]: JMicron Technology Corp. JMB368 IDE controller [197b:2368] (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. Device [1043:827e] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at dc00 [size=8] Region 1: I/O ports at d880 [size=4] Region 2: I/O ports at d800 [size=8] Region 3: I/O ports at d480 [size=4] Region 4: I/O ports at d400 [size=16] Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Express (v1) Legacy Endpoint, MSI 01 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 00: 7b 19 68 23 07 00 10 00 00 85 01 01 08 00 00 00 10: 01 dc 00 00 81 d8 00 00 01 d8 00 00 81 d4 00 00 20: 01 d4 00 00 00 00 00 00 00 00 00 00 43 10 7e 82 30: 00 00 00 00 68 00 00 00 00 00 00 00 0b 01 00 00 40: bd 00 c0 00 08 08 80 e0 00 00 00 00 00 00 00 00 50: 10 00 11 02 00 00 00 00 00 20 08 00 11 44 02 01 60: 40 00 11 10 00 00 00 00 01 50 02 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 a0 01 00 00 0f 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 31 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 c0: c3 8b 38 70 03 45 02 00 00 00 00 00 00 00 00 00 d0: 18 00 00 80 00 00 00 10 00 00 eb 00 00 00 00 01 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:02.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] (rev c0) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. M4A series motherboard [1043:81fe] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (8000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at febff800 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at ec00 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: firewire_ohci 00: 06 11 44 30 17 00 10 02 c0 10 00 0c 08 40 00 00 10: 00 f8 bf fe 01 ec 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 fe 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 20 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 02 e4 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

Flashing FM28V100 through satasii
by Alexei Gladkikh 31 Oct '11

31 Oct '11

Hi, I'm tried to flash memory FM28V100-TG using flashrom software, but flashrom didn't find it ("Flash seems unconnected"). Could this memory IC be added to supported IC's list? I'm use it because it's only type of IC that I could find now (I have to wait for long standard flash chips). I've read datasheet on this IC and know that isn't standard flash memory, but it has parallel interface and it compatible with JEDEC pinout. -- regards, Alexei mailto:GladkikhAlexei@gmail.com

1 0

Report log
by La cigale 28 Oct '11

28 Oct '11

Hi, if I can help you finish support for your chipset... :) I Have the motherboard ASUS M2N68-AM PLUS. Good luck...

1 0

Re: [flashrom] Programming an A25L40 EEPROM
by Arup Basak 27 Oct '11

27 Oct '11

I have the 512KB bios file, and was trying to program it with flashrom and buspirate. Looks like one version of flashrom says "missing libftdi.dll" while another version says programmer buspirate_spi not supported. Can you give me link of any latest version. I have tried to copy the libftdi.dll into the flashrom directory, also tried 'regsrv32 libftdi.dll' in a command-box (where regsrv32 looks to be absent in Windows 7) One more thing, when I hooked up the SPI chip to buspirate, if I use terminal mode of buspirate and set correct mode, then if I try to read some block using CS enables, I get 0x00 and if I keep CS disabled I get 0xFF. I've tried to write anything with both CS enabled and disabled. But values are read as above. Maybe I've settled up wrong mode while trying to access EEPROM from buspirate terminal mode. . I've worked with mode 5 spi, 125khz, Clock polarity:Idle low , Output clock edge:Active to idle, Input sample phase:middle, Output mode: Normal (H=3.3V, L=GND), W(power supplies on). I didn't need to do so because for flashing my BIOS chip, I am trying to use flashrom. This is the fresh chip I bought for recovery. http://in.rsdelivers.com/product/amic-technology/a25l040m-f/spi-flash-4mb-s… Note: The BIOS chips is of my tablet, and not PC, so no problem if it takes few days to resolve issues and program it. It isn't much serious case when someone corrupts motherboard's BIOS. I know flashrom's support is free and takes few hours to get reply. It's not an issue in my case.

1 0

Re: [flashrom] Flashrom report
by Stefan Tauner 27 Oct '11

27 Oct '11

On Thu, 27 Oct 2011 09:17:23 +0200 Piotr Czepek <piotr.czepek(a)gmail.com> wrote: > Hello, > I tried to re-flash VIA Epia mb with flashrom. > Chipset is marked as untested, so I attached report for you. > > Just for test - I read flash image to file and I wrote it back. > After reboot system is alive, so I think flasrom works fine with this mb ;) > Hello Piotr, Thanks for your effort! If you look at the end of your write log you will see a lot of address ranges followed by an 'S'. This indicates that flashrom has detected that the current content already matches the data to write and *S*kips that range. Naturally in your case it skips the whole image and hence the log is no proof of erase + write working correctly. If you have means to recover a failed write (or an UPS and some patience) or if you are brave enough you can try to first erase the chip with -E and write the backup image afterwards like you did already. I have no experience with the VIA chips you have, so i can't say if it is fairly safe or not (i guess so). If that would be my productive machine i would not try it... some glitch can always occur... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Flashrom report
by Piotr Czepek 27 Oct '11

27 Oct '11

Hello, I tried to re-flash VIA Epia mb with flashrom. Chipset is marked as untested, so I attached report for you. Just for test - I read flash image to file and I wrote it back. After reboot system is alive, so I think flasrom works fine with this mb ;) -- best regards piotr czepek

1 0

[PATCH/bios_extract] Add support for Phoenix FFV layouts
by Joshua Roys 26 Oct '11

26 Oct '11

Hello, This patch was developed through some guesswork and by examining the debug output of "official" tools. Expected output looks like: Using file "../882.bin" (1024kB) Found Phoenix BIOS "PhoenixBIOS 4.0 Release 6.1 " Version "DEVEL972", created on 07/07/08 at 15:37:46. BCPSYS module offset is NULL. FFV modules: 5 [ 0]: (00000000-00080000) FED91FBA-D37B-4EEA-8729-2EF29FB37A78 _R00 (00000000-0000819A) 0000819A 00 02 oprom_00.rom _R01 (0000819A-0000FA31) 00007897 00 02 oprom_01.rom _H00 (0000FA31-00014EC3) 00005492 00 02 tcpa_H_00.rom _Q00 (00014EC3-000193B3) 000044F0 00 02 tcpa_Q_00.rom _A00 (000193B3-0001B034) 00001C81 00 02 acpi_00.rom _C00 (0001B038-0001C860) 00001828 02 01 update_00.rom _B05 (0001C860-00027F12) 0000B6B2 00 02 bioscode_05.rom _B02 (00027F12-00031351) 0000943F 00 02 bioscode_02.rom _B03 (00031351-00039238) 00007EE7 00 02 bioscode_03.rom _B00 (00039238-0003E135) 00004EFD 00 02 bioscode_00.rom _K00 (0003E135-00042B33) 000049FE 00 02 tcpa_K_00.rom _T00 (00042B33-000471A2) 0000466F 00 02 template_00.rom _E00 (000471A2-0004B1F0) 0000404E 00 02 setup_00.rom _S00 (0004B1F0-0004EE85) 00003C95 00 02 strings_00.rom _L01 (0004EE85-0005212D) 000032A8 00 02 logo_01.rom _B04 (0005212D-00054DDE) 00002CB1 00 02 bioscode_04.rom _B06 (00054DDE-00057826) 00002A48 00 02 bioscode_06.rom _B01 (00057826-000598EE) 000020C8 00 02 bioscode_01.rom _M00 (000598EE-0005AC93) 000013A5 00 02 miser_00.rom _D00 (0005AC93-0005B82E) 00000B9B 00 02 display_00.rom _Y00 (0005B82E-0005C1E2) 000009B4 00 02 _Y00.rom _L00 (0005C1E2-0005CAA3) 000008C1 00 02 logo_00.rom _G00 (0005CAA3-0005CF07) 00000464 00 02 decompcode_00.rom _A01 (0005CF07-0005CF7F) 00000078 00 02 acpi_01.rom _A02 (0005CF7F-0005CFD1) 00000052 00 02 acpi_02.rom volumeinfo.bin (0005CFD1-0005D031) 00000060 00 01 volumeinfo.bin GAP (0005D031-00080000) 00022FCF 00 F0 [ 1]: (00080000-00082000) FD21E8FD-2525-4A95-BB90-47EC5763FF9E ESCD [ 2]: (00082000-00090000) F6AE0F63-5F8C-4316-A2EA-76B9AF762756 Hole (raw code) [ 3]: (00090000-000F7000) FED91FBA-D37B-4EEA-8729-2EF29FB37A78 volumedir.bin2 (00090008-00090190) 00000188 42 01 volumedir.bin2 volumeinfo.bin (00090190-000901F0) 00000060 00 01 volumeinfo.bin GAP (000901F0-000DFFE8) 0004FDF8 00 F0 _$00 (000DFFE8-000E0004) 0000001C 40 01 _$00.rom _X01 (000E0008-000E9750) 00009748 40 01 romexec_01.rom GAP (000E9750-000ED6E8) 00003F98 00 F0 _X00 (000ED6E8-000F6000) 00008918 40 01 romexec_00.rom GAP (000F6000-000F7000) 00001000 00 F0 [ 4]: (000F7000-00100000) F6AE0F63-5F8C-4316-A2EA-76B9AF762756 Hole (raw code) Note that many newer Phoenix BIOSes have a trailer containing flash enable information, etc. which must be stripped off for this code to work. ESCD seems to be "Extended System Configuration Data" (dumped to ESCD.bin) and all holes are dumped to hole_%02x.bin. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com>

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[PATCH 2/2] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 26 Oct '11

26 Oct '11

Based on the new opaque programmer framework this patch adds support for Intel Hardware Sequencing on ICH8 and its successors. By default (or when setting the ich_spi_mode option to auto) the module tries to use swseq and only activates hwseq if need be: - if important opcodes are inaccessible due to lockdown - if more than one flash chip is attached. The other options (swseq, hwseq) select the respective mode (if possible). A general description of Hardware Sequencing can be found in this blog entry: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ TODO: adding real documentation when we have a directory for it Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 20 +++++ ichspi.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 283 insertions(+), 5 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index a8f4660..66cde4f 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -303,6 +303,26 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash +attached, and if a valid descriptor was written to it (e.g. by the vendor), the +chipset provides an alternative way to access the flash chip(s) named +.BR "Hardware Sequencing" . +It is much simpler than the normal access method (called +.BR "Software Sequencing" ")," +but does not allow the software to choose the SPI commands to be sent. +You can use the +.sp +.B " flashrom \-p internal:ich_spi_mode=value" +.sp +syntax where value can be +.BR auto ", " swseq " or " hwseq . +By default +.RB "(or when setting " ich_spi_mode=auto ) +the module tries to use swseq and only activates hwseq if need be (e.g. if +important opcodes are inaccessible due to lockdown; or if more than one flash +chip is attached). The other options (swseq, hwseq) select the respective mode +(if possible). +.sp If you have an Intel chipset with an ICH6 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the diff --git a/ichspi.c b/ichspi.c index bc03554..1d5dd34 100644 --- a/ichspi.c +++ b/ichspi.c @@ -575,6 +575,25 @@ static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) return 0; } +/* Returns true if the most important opcodes are accessible. */ +static int ich_check_opcodes() +{ + uint8_t ops[] = { + JEDEC_READ, + JEDEC_BYTE_PROGRAM, + JEDEC_RDSR, + 0 + }; + int i = 0; + while (ops[i] != 0) { + msg_pspew("checking for opcode 0x%02x\n", ops[i]); + if (find_opcode(curopcodes, ops[i]) == -1) + return 0; + i++; + } + return 1; +} + /* * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. @@ -1091,7 +1110,11 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -#if 0 +static struct hwseq_data { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq_data; + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { @@ -1160,7 +1183,184 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } return 0; } -#endif + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq_data.size_comp1 != 0) ? 2 : 1); + if (hwseq_data.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + flash->tested = TEST_OK_PREW; + return 1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, opaque_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, opaque_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} static int ich_spi_send_multicommand(struct spi_command *cmds) { @@ -1325,6 +1525,14 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct opaque_programmer opaque_programmer_ich_hwseq = { + .max_data_read = 64, + .max_data_write = 64, + .probe = ich_hwseq_probe, + .read = ich_hwseq_read, + .write = ich_hwseq_write, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1332,7 +1540,14 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int desc_valid = 0; + struct ich_descriptors desc = {{ 0 }}; + enum ich_spi_mode { + ich_auto, + ich_hwseq, + ich_swseq + } ich_spi_mode = ich_auto; switch (ich_generation) { case 7: @@ -1399,6 +1614,22 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case 9: case 10: default: /* Future version might behave the same */ + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for ich_spi_mode.\n"); + else if (arg) + msg_pinfo("Unknown argument for ich_spi_mode: %s\n", arg); + free(arg); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1484,14 +1715,41 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); if (desc_valid) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + !ich_check_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcodes are locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return 1; + } + hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); + hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + register_opaque_programmer(&opaque_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); } - register_spi_programmer(&spi_programmer_ich9); - ich_init_opcodes(); break; } -- 1.7.1

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[PATCH 1/2] ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes
by Stefan Tauner 26 Oct '11

26 Oct '11

This allows them to be called before programmer registration. --- i think it might be a good idea to get rid of the whole switch(spi_programmer->type) pattern and create a file-scope static ich_generation variable instead of using the type member and the ich_generation parameters everywhere. the type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar) - only available after registration, which we want to delay till the end of init. - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 44 +++++++++++++++++++++++++++----------------- 1 files changed, 27 insertions(+), 17 deletions(-) diff --git a/ichspi.c b/ichspi.c index afa420b..bc03554 100644 --- a/ichspi.c +++ b/ichspi.c @@ -225,8 +225,8 @@ static uint16_t REGREAD8(int X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); static int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(OPCODES * op); -static int program_opcodes(OPCODES *op, int enable_undo); +static int generate_opcodes(int ich_generation, OPCODES * op); +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); @@ -410,7 +410,18 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un int oppos=2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0); + switch (spi_programmer->type) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_VIA: + program_opcodes(7, curopcodes, 0); + break; + case SPI_CONTROLLER_ICH9: + program_opcodes(9, curopcodes, 0); + break; + default: + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } oppos = find_opcode(curopcodes, opcode); msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -443,7 +454,7 @@ static int find_preop(OPCODES *op, uint8_t preop) } /* Create a struct OPCODES based on what we find in the locked down chipset. */ -static int generate_opcodes(OPCODES * op) +static int generate_opcodes(int ich_generation, OPCODES * op) { int a; uint16_t preop, optype; @@ -498,7 +509,7 @@ static int generate_opcodes(OPCODES * op) return 0; } -static int program_opcodes(OPCODES *op, int enable_undo) +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) { uint8_t a; uint16_t preop, optype; @@ -529,9 +540,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case 7: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -544,7 +554,10 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH9_REG_PREOP); @@ -557,9 +570,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } return 0; @@ -652,7 +662,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) * * It should be called before ICH sends any spi command. */ -static int ich_init_opcodes(void) +static int ich_init_opcodes(int ich_generation) { int rc = 0; OPCODES *curopcodes_done; @@ -663,11 +673,11 @@ static int ich_init_opcodes(void) if (ichspi_lock) { msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(curopcodes_done); + rc = generate_opcodes(ich_generation, curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; - rc = program_opcodes(curopcodes_done, 1); + rc = program_opcodes(ich_generation, curopcodes_done, 1); } if (rc) { @@ -1343,6 +1353,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; + ich_init_opcodes(ich_generation); switch (ich_generation) { case 7: @@ -1383,7 +1394,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } ich_set_bbar(ich_generation, 0); register_spi_programmer(&spi_programmer_ich7); - ich_init_opcodes(); break; case 8: case 9: @@ -1557,7 +1567,7 @@ int via_init_spi(struct pci_dev *dev) } ich_set_bbar(7, 0); - ich_init_opcodes(); + ich_init_opcodes(7); return 0; } -- 1.7.1

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[PATCH 0/2] ichspi 9.2
by Stefan Tauner 26 Oct '11

26 Oct '11

this requires the opaque programmer framework. i have also left out further but unchanged patches. please see the first patch for some discussion. Stefan Tauner (2): ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes ichspi: add support for Intel Hardware Sequencing flashrom.8 | 20 ++++ ichspi.c | 312 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 310 insertions(+), 22 deletions(-)

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Flashrom fails to write - Sun Ultra 40 M2
by Nick 25 Oct '11

25 Oct '11

DMI string system-manufacturer: "Sun Microsystems" DMI string system-product-name: "Sun Ultra 40 M2 Workstation" DMI string system-version: "11" DMI string baseboard-manufacturer: "Sun Microsystems" DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" DMI string baseboard-version: "50" nForce Pro 3600 / MCP55, SMSC SuperIO Verbose output when flashing coreboot - http://paste.flashrom.org/view.php?id=880 Verbose output when flashing original Sun BIOS image - http://paste.flashrom.org/view.php?id=881 lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 superiotool -deV output - http://paste.flashrom.org/view.php?id=884 Original Sun Ultra 40 M2 BIOS image - http://paste.flashrom.org/view.php?id=882

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Re: [flashrom] flashrom on NVIDIA MCP61 chipset
by Stefan Tauner 24 Oct '11

24 Oct '11

On Mon, 24 Oct 2011 21:57:07 +0700 Nurul Ikhsan <nurixx(a)gmail.com> wrote: > Dear Flashrom developer, > > I got messages that my chipset is untested, but I'm successfully > upgrade my BIOS using flashrom. > Thank you for your hardwork and this great tool. I really appreciate it. > Within this email I also attach Verbose output. > Hello, Thanks for your report! I have marked the abit NF-M2S as supported and will commit that later together with other small changes. I am not entirely sure about the chipset so i left it alone for now... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] `flashrom -V' for ASUS M5A99X EVO
by Stefan Tauner 24 Oct '11

24 Oct '11

On Sun, 23 Oct 2011 19:27:13 +0200 Bernhard Urban <lewurm(a)gmail.com> wrote: > Hi, > > I successfully upgraded the firmware of my ASUS M5A99X EVO board [1] > to version 0705 with flashrom. > > > Thanks, > Bernhard > > [1]: http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ Hello Bernhard, Thanks for your report! I have marked the board as support and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom on NVIDIA MCP61 chipset
by Nurul Ikhsan 24 Oct '11

24 Oct '11

Dear Flashrom developer, I got messages that my chipset is untested, but I'm successfully upgrade my BIOS using flashrom. Thank you for your hardwork and this great tool. I really appreciate it. Within this email I also attach Verbose output. Thanks, Regards, Ikhsan.

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Re: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure.
by Carl-Daniel Hailfinger 23 Oct '11

23 Oct '11

Am 21.10.2011 00:39 schrieb Stefan Tauner: > An opaque programmer does not allow direct flash access and only > offers abstract probe/read/erase/write methods. > Examples are ICH Hardware Sequencing and direct firmware uploads. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Thanks to Stefan for posting this while I had no mail access. This is indeed my patch, and I hereby confirm authorship. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 2/5] ichspi: add support for Intel Hardware Sequencing
by Carl-Daniel Hailfinger 23 Oct '11

23 Oct '11

Am 21.10.2011 00:39 schrieb Stefan Tauner: > Based on the new opaque programmer framework this patch adds support > for Intel Hardware Sequencing on ICH8 and its successors. > > If the flash descriptor is valid, one can activate Hardware > Sequencing by using the hwseq option of the internal programmer, > example: flashrom -p internal:hwseq=yes > > A general description of Hardware Sequencing can be found in this blog entry: > http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ > > todo: > - man page > - adding real documentation when we have a directory for it > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> I really like the paranoid sanity checks everywhere in the code. There is one small comment near the end of the patch, but it is informational and not holding back your patch at all. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> I am so glad we can finally merge this code. A big THANK YOU to Stefan Tauner. This is probably the most reworked patch which ever hit our tree, and in the process flashrom got a lot more extensible as well. > --- > ichspi.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- > 1 files changed, 226 insertions(+), 5 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index afa420b..ce1fff9 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1081,7 +1081,11 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return result; > } > > -#if 0 > +static struct hwseq { > + uint32_t size_comp0; > + uint32_t size_comp1; > +} hwseq; > + > /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ > static void ich_hwseq_set_addr(uint32_t addr) > { > @@ -1150,7 +1154,184 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, > } > return 0; > } > -#endif > + > +int ich_hwseq_probe(struct flashchip *flash) > +{ > + uint32_t total_size, boundary; > + uint32_t erase_size_low, size_low, erase_size_high, size_high; > + struct block_eraser *eraser; > + > + total_size = hwseq.size_comp0 + hwseq.size_comp1; > + msg_cdbg("Found %d attached SPI flash chip", > + (hwseq.size_comp1 != 0) ? 2 : 1); > + if (hwseq.size_comp1 != 0) > + msg_cdbg("s with a combined"); > + else > + msg_cdbg(" with a"); > + msg_cdbg(" density of %d kB.\n", total_size / 1024); > + flash->total_size = total_size / 1024; > + > + eraser = &(flash->block_erasers[0]); > + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; > + size_high = total_size - boundary; > + erase_size_high = ich_hwseq_get_erase_block_size(boundary); > + > + if (boundary == 0) { > + msg_cdbg("There is only one partition containing the whole " > + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); > + eraser->eraseblocks[0].size = erase_size_high; > + eraser->eraseblocks[0].count = size_high / erase_size_high; > + msg_cdbg("There are %d erase blocks with %d B each.\n", > + size_high / erase_size_high, erase_size_high); > + } else { > + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " > + "at address 0x%06x in two partitions.\n", > + 0, size_high-1, boundary); > + size_low = total_size - size_high; > + erase_size_low = ich_hwseq_get_erase_block_size(0); > + > + eraser->eraseblocks[0].size = erase_size_low; > + eraser->eraseblocks[0].count = size_low / erase_size_low; > + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", > + 0, size_low-1); > + msg_cdbg("In that range are %d erase blocks with %d B each.\n", > + size_low / erase_size_low, erase_size_low); > + > + eraser->eraseblocks[1].size = erase_size_high; > + eraser->eraseblocks[1].count = size_high / erase_size_high; > + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", > + boundary, size_high-1); > + msg_cdbg("In that range are %d erase blocks with %d B each.\n", > + size_high / erase_size_high, erase_size_high); > + } > + flash->tested = TEST_OK_PREW; > + return 1; > +} > + > +int ich_hwseq_block_erase(struct flashchip *flash, > + unsigned int addr, > + unsigned int len) > +{ > + uint32_t erase_block; > + uint16_t hsfc; > + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ > + > + erase_block = ich_hwseq_get_erase_block_size(addr); > + if (len != erase_block) { > + msg_cerr("Erase block size for address 0x%06x is %d B, " > + "but requested erase block size is %d B. " > + "Not erasing anything.\n", addr, erase_block, len); > + return -1; > + } > + > + /* Although the hardware supports this (it would erase the whole block > + * containing the address) we play safe here. */ > + if (addr % erase_block != 0) { > + msg_cerr("Erase address 0x%06x is not aligned to the erase " > + "block boundary (any multiple of %d). " > + "Not erasing anything.\n", addr, erase_block); > + return -1; > + } > + > + if (addr + len > flash->total_size * 1024) { > + msg_perr("Request to erase some inaccessible memory address(es)" > + " (addr=0x%x, len=%d). " > + "Not erasing anything.\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); > + > + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* clear operation */ > + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ > + hsfc |= HSFC_FGO; /* start */ > + msg_pdbg("HSFC used for block erasing: "); > + prettyprint_ich9_reg_hsfc(hsfc); > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) > + return -1; > + return 0; > +} > + > +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) > +{ > + uint16_t hsfc; > + uint16_t timeout = 100 * 60; > + uint8_t block_len; > + > + if (addr < 0 || addr + len > flash->total_size * 1024) { > + msg_perr("Request to read from an inaccessible memory address " > + "(addr=0x%x, len=%d).\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); > + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + while (len > 0) { > + block_len = min(len, opaque_programmer->max_data_read); > + ich_hwseq_set_addr(addr); > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* set read operation */ > + hsfc &= ~HSFC_FDBC; /* clear byte count */ > + /* set byte count */ > + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); > + hsfc |= HSFC_FGO; /* start */ > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) > + return 1; > + ich_read_data(buf, block_len, ICH9_REG_FDATA0); > + addr += block_len; > + buf += block_len; > + len -= block_len; > + } > + return 0; > +} > + > +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) > +{ > + uint16_t hsfc; > + uint16_t timeout = 100 * 60; > + uint8_t block_len; > + > + if (addr < 0 || addr + len > flash->total_size * 1024) { > + msg_perr("Request to write to an inaccessible memory address " > + "(addr=0x%x, len=%d).\n", addr, len); > + return -1; > + } > + > + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); > + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ > + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); > + > + while (len > 0) { > + ich_hwseq_set_addr(addr); > + block_len = min(len, opaque_programmer->max_data_write); > + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); > + hsfc = REGREAD16(ICH9_REG_HSFC); > + hsfc &= ~HSFC_FCYCLE; /* clear operation */ > + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ > + hsfc &= ~HSFC_FDBC; /* clear byte count */ > + /* set byte count */ > + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); > + hsfc |= HSFC_FGO; /* start */ > + REGWRITE16(ICH9_REG_HSFC, hsfc); > + > + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) > + return -1; > + addr += block_len; > + buf += block_len; > + len -= block_len; > + } > + return 0; > +} > > static int ich_spi_send_multicommand(struct spi_command *cmds) > { > @@ -1315,6 +1496,14 @@ static const struct spi_programmer spi_programmer_ich9 = { > .write_256 = default_spi_write_256, > }; > > +static const struct opaque_programmer opaque_programmer_ich_hwseq = { > + .max_data_read = 64, > + .max_data_write = 64, > + .probe = ich_hwseq_probe, > + .read = ich_hwseq_read, > + .write = ich_hwseq_write, > +}; > + > int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > int ich_generation) > { > @@ -1322,7 +1511,10 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + char *arg; > int desc_valid = 0; > + int hwseq_en = 0; > + struct ich_descriptors desc = {{ 0 }}; > > switch (ich_generation) { > case 7: > @@ -1389,6 +1581,14 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > case 9: > case 10: > default: /* Future version might behave the same */ > + arg = extract_programmer_param("hwseq"); > + if (arg && !strcmp(arg, "yes")) > + hwseq_en = 1; > + else if (arg && !strlen(arg)) > + msg_pinfo("Missing argument for hwseq.\n"); > + else if (arg) > + msg_pinfo("Unknown argument for hwseq: %s\n", arg); > + free(arg); > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); > msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > prettyprint_ich9_reg_hsfs(tmp2); > @@ -1474,14 +1674,35 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > msg_pdbg("\n"); > if (desc_valid) { > - struct ich_descriptors desc = {{ 0 }}; > if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > ICH_RET_OK) > prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > &desc); > + /* If the descriptor is valid and indicates multiple > + * flash devices we need to use hwseq to be able to > + * access the second flash device. > + */ > + if (desc.content.NC != 0) { > + msg_pinfo("Enabling hardware sequencing due to " > + "multiple flash chips detected.\n"); > + hwseq_en = 1; > + } > } > - register_spi_programmer(&spi_programmer_ich9); > - ich_init_opcodes(); > + > + if (hwseq_en) { > + if (!desc_valid) { > + msg_perr("Hardware sequencing was requested " > + "but the flash descriptor is not " > + "valid. Aborting.\n"); > + return 1; > + } > + hwseq.size_comp0 = getFCBA_component_density(&desc, 0); > + hwseq.size_comp1 = getFCBA_component_density(&desc, 1); > + register_opaque_programmer(&opaque_programmer_ich_hwseq); This is a big question. Should we only register hwseq, or should we register hwseq in addition to swseq? Both solutions make sense, and I'm not yet sure which one is better. There's the user interface issue for non-experts which would benefit from having only one (virtual) chip visible, and there's the desire to access at least one flash chip with swseq even if multiple chips are present. This question should not block a merge of this patch, but we need to address it eventually. > + } else { > + register_spi_programmer(&spi_programmer_ich9); > + ich_init_opcodes(); > + } > break; > } > -- http://www.hailfinger.org/

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`flashrom -V' for ASUS M5A99X EVO
by Bernhard Urban 23 Oct '11

23 Oct '11

Hi, I successfully upgraded the firmware of my ASUS M5A99X EVO board [1] to version 0705 with flashrom. Thanks, Bernhard [1]: http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ # flashrom -V flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1098M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1011 us, 10000 myus = 9968 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To be filled by O.E.M." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M5A99X EVO" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8721 on port 0x2e Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 16.5 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. Super I/O ID 0x8721 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000. Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xc8, id2 0xd8, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xc8, id2 0xd8, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xc8, id2 0xd8, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xc8, id2 0xd8, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x6f, id2 0x63, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x15 No operations were specified.

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[PATCH] Fintek SPI driver, based off it87spi
by Sean Nelson 23 Oct '11

23 Oct '11

I've been extremely busy with preparing for the US Air Force, which I leave for Basic on November 2nd. But... Fintek SPI Flashrom Driver: * based off of it87spi.c * untested * should be good for F71882 and F71889 Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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Re: [flashrom] [PATCH] Fix all ASUS P5GD* board enables
by Stefan Tauner 23 Oct '11

23 Oct '11

On Fri, 12 Aug 2011 22:38:21 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > adding tested board enable with exact matches for identified and > tested boards and NT board enables for potentially compatible boards > should be the scheme to be used in the future for all mainboard > families instead of adding an uncertain generic board enable or none > at all (just because the user does not reply). The policy should be > to add board enables as soon as they become available or at least no > longer than a week after posting it, even without success reports. > > Rationale: This scheme guarantees that we get success reports for > untested boards which allows us to combine them later when we are > sure (enough). OTOH it allows users to easily test the yet > unsupported boards without recompiling by forcing the generic board > enables. And it keeps the patch queue short. > > Investigating all of the above was certainly not worth it on its own > and id suggest to avoid similar efforts in the future by following > the scheme :) this was way too much work to let it bit-rot and has a small impact overall, so it was Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> and committed in r1457. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1457 - trunk
by repository service 23 Oct '11

23 Oct '11

Author: stefanct Date: Sun Oct 23 00:01:09 2011 New Revision: 1457 URL: http://flashrom.org/trac/flashrom/changeset/1457 Log: Fix all ASUS P5GD* board enables Changes related to P5GD1 variants: - Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable - Add an untested "P5GD1(-VM)" board enable and add an entry to print.c - Add P5GD1-VM/S variant as reported by "Limer" Changes related to P5GD(2/C) variants: - Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and print.c entry. NB: there is no "P5GDC-V" board. - Add a generic match for P5GD(2/C)* boards with a not tested tag. This are the potential targets for this according to the asus ftp: ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/ Unsupported variants of the P5GD2: P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X (P5GD2 Premium is already tested) (there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to asus :) Unsupported variants of the P5GDC: P5GDC Pro, P5GDC-MX (P5GDC Deluxe and P5GDC-V Deluxe are already tested) References: P5GD1 PRO (dmi "P5GD1 PRO") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e* http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html P5GD1 (dmi "P5GD1") The non-pro version seems to match the pro pci pattern, but could be distinguished by the SATA ID of 1043:2604 vs. 1043:2601: https://launchpadlibrarian.net/62167576/Lspci.txt or a DMI pattern of course. P5GD1-VM (dmi "P5GD1-VM") This does also match the current PCI IDs. https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379 - P5GD2 Premium (dmi "P5GD2-Premium") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html - P5GDC-V Deluxe (dmi "P5GDC-V") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html - P5GDC Deluxe (dmi "P5GDC") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html - P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2 no useful logs found - P5GD2-Deluxe (dmi "P5GD2-Deluxe") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514 - P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI") smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7* https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> and due to the tremendous interest... ;) Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Oct 22 23:45:27 2011 (r1456) +++ trunk/board_enable.c Sun Oct 23 00:01:09 2011 (r1457) @@ -2041,9 +2041,13 @@ {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Oct 22 23:45:27 2011 (r1456) +++ trunk/print.c Sun Oct 23 00:01:09 2011 (r1457) @@ -647,15 +647,19 @@ B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), + B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), + B("ASUS", "P5GD1-VM/S", 1, NULL, "This is an OEM board from FSC. Although flashrom supports it and can probably not distinguish it from the P5GD1-VM, please note that the P5GD1-VM BIOS does not support the FSC variants completely."), + B("ASUS", "P5GD1(-VM)", 0, NULL, "Untested board enable."), B("ASUS", "P5GD2 Premium", 1, "http://www.asus.it/product.aspx?P_ID=lRKaz1Rb6Xb0OFM7", NULL), B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), + B("ASUS", "P5GDC-V Deluxe", 1, NULL, NULL), + B("ASUS", "P5GD2/C variants", 0, NULL, "Untested board enable."), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), B("ASUS", "P5LP-LE (Lithium-UL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP."), B("ASUS", "P5LP-LE (Epson OEM)", 1, NULL, "This is an OEM board from Epson (e.g. Endeavor MT7700)."), B("ASUS", "P5LP-LE", 0, NULL, "This designation is used for OEM boards from HP, Epson and maybe others. The HP names vary and not all of them have been tested yet. Please report any success or failure, thanks."), - B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL),

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Re: [flashrom] [PATCH 2/3] serprog: small improvements
by Uwe Hermann 22 Oct '11

22 Oct '11

On Thu, Sep 08, 2011 at 12:56:22AM +0200, Stefan Tauner wrote: > @@ -220,32 +220,27 @@ static int sp_check_commandavail(uint8_t command) > static int sp_automatic_cmdcheck(uint8_t cmd) > { > if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { > - msg_pdbg("Warning: Automatic command availability check" > - " failed for cmd %d - wont execute cmd\n",cmd); > + msg_pdbg("Warning: Automatic command availability check failed " > + "for cmd 0x%x - wont execute cmd\n", cmd); won't > + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", > + (c & CHIP_BUSTYPE_PARALLEL) ? "on" : "off", > + (c & CHIP_BUSTYPE_LPC) ? "on" : "off", > + (c & CHIP_BUSTYPE_FWH) ? "on" : "off", > + (c & CHIP_BUSTYPE_SPI) ? "on" : "off"); Hm, I was thinking multiple times now that maybe we should change PARALLEL to PAR in all the code, it makes places like this where LPC/FWH/SPI cases are handles align pretty nicely (same length). That's for another patch, though. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1456 - trunk
by repository service 22 Oct '11

22 Oct '11

Author: stefanct Date: Sat Oct 22 23:45:27 2011 New Revision: 1456 URL: http://flashrom.org/trac/flashrom/changeset/1456 Log: serprog: small improvements - rename serprog_delay parameter to usecs - fix code style, (output) formatting issues and comments - sp_docommand: remove unnecessary malloc+memcpy and fix formatting Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/programmer.h trunk/serprog-protocol.txt trunk/serprog.c Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Oct 21 15:20:11 2011 (r1455) +++ trunk/programmer.h Sat Oct 22 23:45:27 2011 (r1456) @@ -607,9 +607,10 @@ void serprog_chip_writeb(uint8_t val, chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void serprog_delay(int delay); +void serprog_delay(int usecs); int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); + const unsigned char *writearr, + unsigned char *readarr); int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif Modified: trunk/serprog-protocol.txt ============================================================================== --- trunk/serprog-protocol.txt Fri Oct 21 15:20:11 2011 (r1455) +++ trunk/serprog-protocol.txt Sat Oct 22 23:45:27 2011 (r1456) @@ -19,7 +19,7 @@ 0x05 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK 0x06 Query connected address lines none ACK + 8bit line count / NAK 0x07 Query operation buffer size none ACK + 16bit size / NAK -0x08 Query write-n maximum data len none ACK + 24bit maximum length / NAK +0x08 Query maximum write-n length none ACK + 24bit length (0==2^24) / NAK 0x09 Read byte 24-bit addr ACK + BYTE / NAK 0x0A Read n bytes 24-bit addr + 24-bit length ACK + length bytes / NAK 0x0B Initialize operation buffer none ACK / NAK Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Fri Oct 21 15:20:11 2011 (r1455) +++ trunk/serprog.c Sat Oct 22 23:45:27 2011 (r1456) @@ -38,7 +38,7 @@ #include "programmer.h" #include "chipdrivers.h" -#define MSGHEADER "serprog:" +#define MSGHEADER "serprog: " /* * FIXME: This prototype was added to help reduce diffs for the shutdown @@ -204,7 +204,7 @@ return; } } - msg_perr("Error: cannot synchronize protocol\n" + msg_perr("Error: cannot synchronize protocol " "- check communications and reset device?\n"); exit(1); } @@ -220,32 +220,27 @@ static int sp_automatic_cmdcheck(uint8_t cmd) { if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { - msg_pdbg("Warning: Automatic command availability check" - " failed for cmd %d - wont execute cmd\n",cmd); + msg_pdbg("Warning: Automatic command availability check failed " + "for cmd 0x%x - won't execute cmd\n", cmd); return 1; } return 0; } static int sp_docommand(uint8_t command, uint32_t parmlen, - uint8_t * params, uint32_t retlen, void *retparms) + uint8_t *params, uint32_t retlen, void *retparms) { - unsigned char *sendpacket; unsigned char c; if (sp_automatic_cmdcheck(command)) return 1; - sendpacket = malloc(1 + parmlen); - if (!sendpacket) - sp_die("Error: cannot malloc command buffer"); - sendpacket[0] = command; - memcpy(&(sendpacket[1]), params, parmlen); - if (write(sp_fd, sendpacket, 1 + parmlen) != (1 + parmlen)) { - sp_die("Error: cannot write command"); - } - free(sendpacket); + if (write(sp_fd, &command, 1) != 1) + sp_die("Error: cannot write op code"); + if (write(sp_fd, params, parmlen) != (parmlen)) + sp_die("Error: cannot write parameters"); if (read(sp_fd, &c, 1) != 1) sp_die("Error: cannot read from device"); - if (c == S_NAK) return 1; + if (c == S_NAK) + return 1; if (c != S_ACK) { msg_perr("Error: invalid response 0x%02X from device\n",c); exit(1); @@ -256,8 +251,8 @@ int r; r = read(sp_fd, retparms + rd_bytes, retlen - rd_bytes); - if (r <= 0) sp_die - ("Error: cannot read return parameters"); + if (r <= 0) + sp_die("Error: cannot read return parameters"); rd_bytes += r; } while (rd_bytes != retlen); } @@ -404,12 +399,12 @@ msg_pdbg(MSGHEADER "Synchronized\n"); if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { - msg_perr("Error: NAK to Query Interface version\n"); + msg_perr("Error: NAK to query interface version\n"); exit(1); } if (iface != 1) { - msg_perr("Error: Unknown interface version %d\n", iface); + msg_perr("Error: Unknown interface version: %d\n", iface); exit(1); } @@ -428,6 +423,11 @@ c = BUS_NONSPI; /* A reasonable default for now. */ } buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", + (c & BUS_PARALLEL) ? "on" : "off", + (c & BUS_LPC) ? "on" : "off", + (c & BUS_FWH) ? "on" : "off", + (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ if (buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; @@ -538,12 +538,12 @@ strcpy((char *)pgmname, "(unknown)"); } pgmname[16] = 0; - msg_pinfo(MSGHEADER "Programmer name \"%s\"\n", pgmname); + msg_pinfo(MSGHEADER "Programmer name is \"%s\"\n", pgmname); if (sp_docommand(S_CMD_Q_SERBUF, 0, NULL, 2, &sp_device_serbuf_size)) { msg_perr("Warning: NAK to query serial buffer size\n"); } - msg_pdbg(MSGHEADER "serial buffer size %d\n", + msg_pdbg(MSGHEADER "Serial buffer size is %d\n", sp_device_serbuf_size); if (sp_check_commandavail(S_CMD_O_INIT)) { @@ -564,7 +564,7 @@ msg_perr("Warning: NAK to query operation buffer " "size\n"); } - msg_pdbg(MSGHEADER "operation buffer size %d\n", + msg_pdbg(MSGHEADER "operation buffer size is %d\n", sp_device_opbuf_size); } @@ -581,7 +581,7 @@ { unsigned char header[7]; msg_pspew(MSGHEADER "Passing write-n bytes=%d addr=0x%x\n", - sp_write_n_bytes, sp_write_n_addr); + sp_write_n_bytes, sp_write_n_addr); if (sp_streamed_transmit_bytes >= (7 + sp_write_n_bytes + sp_device_serbuf_size)) sp_flush_stream(); @@ -735,31 +735,32 @@ { size_t lenm = len; chipaddr addrm = addr; - while ((sp_max_read_n)&&(lenm > sp_max_read_n)) { - sp_do_read_n(&(buf[addrm-addr]),addrm,sp_max_read_n); + while ((sp_max_read_n != 0) && (lenm > sp_max_read_n)) { + sp_do_read_n(&(buf[addrm-addr]), addrm, sp_max_read_n); addrm += sp_max_read_n; lenm -= sp_max_read_n; } - if (lenm) sp_do_read_n(&(buf[addrm-addr]),addrm,lenm); + if (lenm) + sp_do_read_n(&(buf[addrm-addr]), addrm, lenm); } -void serprog_delay(int delay) +void serprog_delay(int usecs) { unsigned char buf[4]; - msg_pspew("%s\n", __func__); + msg_pspew("%s usecs=%d\n", __func__, usecs); if (!sp_check_commandavail(S_CMD_O_DELAY)) { - internal_delay(delay); msg_pdbg("Note: serprog_delay used, but the programmer doesn't " "support delay\n"); + internal_delay(usecs); return; } if ((sp_max_write_n) && (sp_write_n_bytes)) sp_pass_writen(); sp_check_opbuf_usage(5); - buf[0] = ((delay >> 0) & 0xFF); - buf[1] = ((delay >> 8) & 0xFF); - buf[2] = ((delay >> 16) & 0xFF); - buf[3] = ((delay >> 24) & 0xFF); + buf[0] = ((usecs >> 0) & 0xFF); + buf[1] = ((usecs >> 8) & 0xFF); + buf[2] = ((usecs >> 16) & 0xFF); + buf[3] = ((usecs >> 24) & 0xFF); sp_stream_buffer_op(S_CMD_O_DELAY, 4, buf); sp_opbuf_usage += 5; sp_prev_was_write = 0;

1 0

donation?
by Chris 22 Oct '11

22 Oct '11

Hi, I couldn't find where to send my donation to on the website ( http://www.flashrom.org/Flashrom )? Regards, Chris

2 1

Trac is down
by Marcos Felipe Rasia de Mello 22 Oct '11

22 Oct '11

Hi, Trac is down. Timeline is empty, "Missing "youngest_rev" in cache metadata" when browse source, "ValueError: year is out of range" in roadmap... http://www.flashrom.org/trac/flashrom Marcos

1 0

flashrom log
by cjt2007 22 Oct '11

22 Oct '11

Hi flashrom people, I tried to use your tool for the ASUS M2N-MX board but failed to upgrade. Please find the verbose output attached. I hope this helps to improve your great tool. Thank you and best regards Christoph

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Re: [flashrom] ASUS
by Stefan Tauner 22 Oct '11

22 Oct '11

On Fri, 21 Oct 2011 22:03:40 +0200 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2011/10/21 mindzeebeez <mindzeebeez(a)mac.com>: > > ...so I just add > > > > -p internal:laptop=force_I_want_a_brick > > > > ...after the normal command to install the new bios? > > If you are using the stable/release version: yes, if you are using a > build based on subversion code you can use "-p > internal:this_is_not_a_laptop". idwer: -p internal:this_is_not_a_laptop is wrong. it should be -p internal:laptop=this_is_not_a_laptop imo. chris: -p internal:laptop=force_I_want_a_brick should work in any case, so please use that one. if you are using the parameter correctly it should show: > […] > You have been warned. > ======================================================================== > Proceeding anyway because user forced us to. > […] if not you are doing it wrong and should post the exact command you are executing please. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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