- flashrom - mail.coreboot.org

[PATCH] IT87* SPI unallocated port recovery
by Carl-Daniel Hailfinger 16 Jul '09

16 Jul '09

For Ward Vandewege. IT87* SPI unallocated port recovery. Some coreboot versions forget to set the correct SPI flash port. This in turn causes the port range to stay unallocated and thus not passed through to the device. Since the serial port at 0x3f8 is always enabled, disable the serial port, set its address to zero, then allow the user to set the SPI flash port to 0x3f8. Not intended for merging yet, we need a proper user interface for this How to use this: Boot a kernel with modular serial port, load the serial module and test it with minicom/whatever, run # lspci -nnvvvxxxx >lspci_loaded.txt # superiotool -d >superiotool_loaded.txt Unload the serial module, then run # lspci -nnvvvxxxx >lspci_unloaded.txt # superiotool -d >superiotool_unloaded.txt # flashrom -p it87spi=port=0x3f8 # lspci -nnvvvxxxx >lspci_modified.txt # superiotool -d >superiotool_modified.txt The above sequence needs to happen right after a cold boot and after testing the serial port. The flashrom step will alter some registers until the next cold boot, so running it twice will not yield useful results. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it87spi_emergency_serial_replacement/it87spi.c =================================================================== --- flashrom-it87spi_emergency_serial_replacement/it87spi.c (Revision 653) +++ flashrom-it87spi_emergency_serial_replacement/it87spi.c (Arbeitskopie) @@ -90,7 +90,7 @@ sio_write(port, 0x24, tmp); } printf("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); - /* LDN 0x7, reg 0x64/0x65 */ + /* LDN 0x7 */ sio_write(port, 0x07, 0x7); flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); @@ -102,6 +102,16 @@ if (it87opts && (portpos = strstr(it87opts, "port="))) { portpos += 5; flashport = strtol(portpos, (char **)NULL, 0); + tmp = sio_read(port, 0x2b); + printf("Logical block lock is %02x\n", tmp); + printf("Disabling serial port\n"); + /* LDN 0x1 */ + sio_write(port, 0x07, 0x1); + sio_write(port, 0x30, 0x00); + sio_write(port, 0x60, 0x00); + sio_write(port, 0x61, 0x00); + /* LDN 0x7 */ + sio_write(port, 0x07, 0x7); printf("Forcing serial flash port 0x%04x\n", flashport); sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); -- http://www.hailfinger.org/

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Re: [flashrom] FW: Asus A7V8X needs a board enable.
by Luc Verhaegen 15 Jul '09

15 Jul '09

On Wed, Jul 15, 2009 at 02:02:17AM +0000, Glenn Mueller wrote: > > Sure I can try but is my board or chipset supported at all by your program? Chipset; should be ok. Board; try and find out, but in general, very little boards actually need a board enable. And the board enable usually is the more tangible of issues we can fix :) Our big question here is, can we really support the flash part. And if we can, why didn't it work in the asus a7v8x? Luc Verhaegen.

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Asus A7V8X needs a board enable.
by Luc Verhaegen 14 Jul '09

14 Jul '09

Output from flashrom (from the .rar Glenn provided in a previous mail): Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. Found chip "SST SST49LF040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! Verifying flash... FAILED at 0x00000000! Expected=0x95, Read=0x49 Output from lspci -vnnxxx attached. Suggested ids: Host Bridge KT400: 0x1106, 0x3189, 0x1043, 0x807F ISA Bridge VT8235: 0x1106, 0x3177, 0x1043, 0x808C Board enable requires two things: io(0x370) &= ~0x02; io(PM_IO_Base + 0x2C) |= 0x01; The second scarily translates to: "Enable SMI generation". The first is (according to carldani) most likely an io range for the super io. The superio is probably an it8712, but we do not know for sure, but there is a good chance that this is about dropping a gpio line. We might then get lucky and might not need SMI at all. Glenn, please attach the output of superio -Vd, we cannot proceed without that. Luc Verhaegen.

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[PATCH] Use a distinct return code for invalid SPI command length
by Carl-Daniel Hailfinger 14 Jul '09

14 Jul '09

Use a distinct return code for SPI commands with unsupported/invalid length. Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_commandlength/it87spi.c =================================================================== --- flashrom-spi_commandlength/it87spi.c (Revision 652) +++ flashrom-spi_commandlength/it87spi.c (Arbeitskopie) @@ -170,7 +170,7 @@ if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", __FUNCTION__, readcnt); - return 1; + return SPI_INVALID_LENGTH; } switch (writecnt) { case 1: @@ -200,7 +200,7 @@ default: printf("%s called with unsupported writecnt %i.\n", __FUNCTION__, writecnt); - return 1; + return SPI_INVALID_LENGTH; } /* * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. Index: flashrom-spi_commandlength/ft2232_spi.c =================================================================== --- flashrom-spi_commandlength/ft2232_spi.c (Revision 652) +++ flashrom-spi_commandlength/ft2232_spi.c (Arbeitskopie) @@ -201,6 +201,9 @@ unsigned char port_val = 0; int i, ret = 0; + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + buf = realloc(buf, writecnt + readcnt + 100); if (!buf) { fprintf(stderr, "Out of memory!\n"); Index: flashrom-spi_commandlength/wbsio_spi.c =================================================================== --- flashrom-spi_commandlength/wbsio_spi.c (Revision 652) +++ flashrom-spi_commandlength/wbsio_spi.c (Arbeitskopie) @@ -154,7 +154,8 @@ if (!mode) { fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n", __func__, writecnt, readcnt); - return 1; + /* Command type refers to the number of bytes read/written. */ + return SPI_INVALID_LENGTH; } OUTB(writearr[0], wbsio_spibase); Index: flashrom-spi_commandlength/spi.h =================================================================== --- flashrom-spi_commandlength/spi.h (Revision 652) +++ flashrom-spi_commandlength/spi.h (Arbeitskopie) @@ -108,5 +108,6 @@ /* Error codes */ #define SPI_INVALID_OPCODE -2 #define SPI_INVALID_ADDRESS -3 +#define SPI_INVALID_LENGTH -4 #endif /* !__SPI_H__ */ Index: flashrom-spi_commandlength/sb600spi.c =================================================================== --- flashrom-spi_commandlength/sb600spi.c (Revision 652) +++ flashrom-spi_commandlength/sb600spi.c (Arbeitskopie) @@ -114,14 +114,14 @@ if (readcnt > 8) { printf("%s, SB600 SPI controller can not receive %d bytes, " - "which is limited with 8 bytes\n", __func__, readcnt); - return 1; + "it is limited to 8 bytes\n", __func__, readcnt); + return SPI_INVALID_LENGTH; } if (writecnt > 8) { - printf("%s, SB600 SPI controller can not sent %d bytes, " - "which is limited with 8 bytes\n", __func__, writecnt); - return 1; + printf("%s, SB600 SPI controller can not send %d bytes, " + "it is limited to 8 bytes\n", __func__, writecnt); + return SPI_INVALID_LENGTH; } mmio_writeb(cmd, sb600_spibar + 0); Index: flashrom-spi_commandlength/ichspi.c =================================================================== --- flashrom-spi_commandlength/ichspi.c (Revision 652) +++ flashrom-spi_commandlength/ichspi.c (Arbeitskopie) @@ -599,10 +599,16 @@ { switch (spi_controller) { case SPI_CONTROLLER_VIA: + if (datalength > 16) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich9_run_opcode(op, offset, datalength, data); default: printf_debug("%s: unsupported chipset\n", __FUNCTION__); @@ -686,6 +692,7 @@ const unsigned char *writearr, unsigned char *readarr) { int a; + int result; int opcode_index = -1; const unsigned char cmd = *writearr; OPCODE *opcode; @@ -728,10 +735,10 @@ count = readcnt; } - if (run_opcode(*opcode, addr, count, data) != 0) { + result = run_opcode(*opcode, addr, count, data); + if (result) { printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); - return 1; } - return 0; + return result; } -- http://www.hailfinger.org/

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[commit] r653 - trunk
by svn＠flashrom.org 14 Jul '09

14 Jul '09

Author: hailfinger Date: 2009-07-14 12:26:56 +0200 (Tue, 14 Jul 2009) New Revision: 653 Modified: trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.h trunk/wbsio_spi.c Log: Use a distinct return code for SPI commands with unsupported/invalid length. Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/ft2232_spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -201,6 +201,9 @@ unsigned char port_val = 0; int i, ret = 0; + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + buf = realloc(buf, writecnt + readcnt + 100); if (!buf) { fprintf(stderr, "Out of memory!\n"); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/ichspi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -599,10 +599,16 @@ { switch (spi_controller) { case SPI_CONTROLLER_VIA: + if (datalength > 16) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: + if (datalength > 64) + return SPI_INVALID_LENGTH; return ich9_run_opcode(op, offset, datalength, data); default: printf_debug("%s: unsupported chipset\n", __FUNCTION__); @@ -686,6 +692,7 @@ const unsigned char *writearr, unsigned char *readarr) { int a; + int result; int opcode_index = -1; const unsigned char cmd = *writearr; OPCODE *opcode; @@ -728,10 +735,10 @@ count = readcnt; } - if (run_opcode(*opcode, addr, count, data) != 0) { + result = run_opcode(*opcode, addr, count, data); + if (result) { printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); - return 1; } - return 0; + return result; } Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/it87spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -170,7 +170,7 @@ if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", __FUNCTION__, readcnt); - return 1; + return SPI_INVALID_LENGTH; } switch (writecnt) { case 1: @@ -200,7 +200,7 @@ default: printf("%s called with unsupported writecnt %i.\n", __FUNCTION__, writecnt); - return 1; + return SPI_INVALID_LENGTH; } /* * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/sb600spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -114,14 +114,14 @@ if (readcnt > 8) { printf("%s, SB600 SPI controller can not receive %d bytes, " - "which is limited with 8 bytes\n", __func__, readcnt); - return 1; + "it is limited to 8 bytes\n", __func__, readcnt); + return SPI_INVALID_LENGTH; } if (writecnt > 8) { - printf("%s, SB600 SPI controller can not sent %d bytes, " - "which is limited with 8 bytes\n", __func__, writecnt); - return 1; + printf("%s, SB600 SPI controller can not send %d bytes, " + "it is limited to 8 bytes\n", __func__, writecnt); + return SPI_INVALID_LENGTH; } mmio_writeb(cmd, sb600_spibar + 0); Modified: trunk/spi.h =================================================================== --- trunk/spi.h 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/spi.h 2009-07-14 10:26:56 UTC (rev 653) @@ -108,5 +108,6 @@ /* Error codes */ #define SPI_INVALID_OPCODE -2 #define SPI_INVALID_ADDRESS -3 +#define SPI_INVALID_LENGTH -4 #endif /* !__SPI_H__ */ Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-13 12:40:17 UTC (rev 652) +++ trunk/wbsio_spi.c 2009-07-14 10:26:56 UTC (rev 653) @@ -154,7 +154,8 @@ if (!mode) { fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n", __func__, writecnt, readcnt); - return 1; + /* Command type refers to the number of bytes read/written. */ + return SPI_INVALID_LENGTH; } OUTB(writearr[0], wbsio_spibase);

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[commit] r652 - trunk
by svn＠flashrom.org 13 Jul '09

13 Jul '09

Author: libv Date: 2009-07-13 14:40:17 +0200 (Mon, 13 Jul 2009) New Revision: 652 Modified: trunk/board_enable.c Log: Board enable for Asus A7V8X. GP51 is attached to both WP# and TBL#. Made possible by the quick response of ITE when asked for information, and the tenacious testing of Glenn Mueller. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Glenn Mueller <mechwarrior5(a)hotmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-12 12:06:18 UTC (rev 651) +++ trunk/board_enable.c 2009-07-13 12:40:17 UTC (rev 652) @@ -832,6 +832,44 @@ } /** + * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A + */ +static int board_asus_a7v8x(const char *name) +{ + uint16_t id, base; + uint8_t tmp; + + /* find the IT8703F */ + w836xx_ext_enter(0x2E); + id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); + w836xx_ext_leave(0x2E); + + if (id != 0x8701) { + fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n"); + return -1; + } + + /* Get the GP567 IO base */ + w836xx_ext_enter(0x2E); + sio_write(0x2E, 0x07, 0x0C); + base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + w836xx_ext_leave(0x2E); + + if (!base) { + fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO" + " Base.\n"); + return -1; + } + + /* Raise GP51. */ + tmp = INB(base); + tmp |= 0x02; + OUTB(tmp, base); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -860,6 +898,7 @@ {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, + {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},

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[PATCH] Convert SPI byte program to multicommand
by Carl-Daniel Hailfinger 12 Jul '09

12 Jul '09

Convert SPI byte program to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_byteprogram/flash.h =================================================================== --- flashrom-spi_multicommand_byteprogram/flash.h (Revision 650) +++ flashrom-spi_multicommand_byteprogram/flash.h (Arbeitskopie) @@ -446,9 +446,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); -void spi_byte_program(int address, uint8_t byte); -int spi_nbyte_program(int address, uint8_t *bytes, int len); -int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Index: flashrom-spi_multicommand_byteprogram/it87spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/it87spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/it87spi.c (Arbeitskopie) @@ -232,6 +232,7 @@ result = spi_write_enable(); if (result) return result; + /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { @@ -262,10 +263,7 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Index: flashrom-spi_multicommand_byteprogram/spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/spi.c (Arbeitskopie) @@ -154,21 +154,7 @@ result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -736,39 +722,80 @@ return spi_send_command(sizeof(cmd), 0, cmd, NULL); } -void spi_byte_program(int address, uint8_t byte) +int spi_byte_program(int addr, uint8_t byte) { - const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { - JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - byte - }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send Byte-Program */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_nbyte_program(int address, uint8_t *bytes, int len) { + int result; + /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, (address >> 16) & 0xff, (address >> 8) & 0xff, (address >> 0) & 0xff, }; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + if (!len) { + printf_debug ("%s called for zero-length write\n", __func__); + return 1; + } if (len > 256) { - printf_debug ("%s called for too long a write\n", - __FUNCTION__); + printf_debug ("%s called for too long a write\n", __func__); return 1; } memcpy(&cmd[4], bytes, len); - /* Send Byte-Program */ - return spi_send_command(4 + len, 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_disable_blockprotect(void) @@ -883,7 +910,6 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); Index: flashrom-spi_multicommand_byteprogram/ft2232_spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/ft2232_spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/ft2232_spi.c (Arbeitskopie) @@ -276,7 +276,6 @@ else l = total_size - i; - spi_write_enable(); if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); // spi_write_disable(); chip does this for us Index: flashrom-spi_multicommand_byteprogram/wbsio_spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/wbsio_spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/wbsio_spi.c (Arbeitskopie) @@ -200,11 +200,8 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } - result = spi_write_enable(); - if (result) - return result; for (pos = 0; pos < size; pos++) { - spi_byte_program(pos, buf[pos]); + result = spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Index: flashrom-spi_multicommand_byteprogram/sb600spi.c =================================================================== --- flashrom-spi_multicommand_byteprogram/sb600spi.c (Revision 650) +++ flashrom-spi_multicommand_byteprogram/sb600spi.c (Arbeitskopie) @@ -73,10 +73,7 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { spi_disable_blockprotect(); - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, *buf); + result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) printf("."); -- http://www.hailfinger.org/

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[commit] r651 - trunk
by svn＠flashrom.org 12 Jul '09

12 Jul '09

Author: hailfinger Date: 2009-07-12 14:06:18 +0200 (Sun, 12 Jul 2009) New Revision: 651 Modified: trunk/flash.h trunk/ft2232_spi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Convert SPI byte program to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested it on Epia-m700 worked okay. Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/flash.h 2009-07-12 12:06:18 UTC (rev 651) @@ -446,9 +446,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); -void spi_byte_program(int address, uint8_t byte); -int spi_nbyte_program(int address, uint8_t *bytes, int len); -int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/ft2232_spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -276,7 +276,6 @@ else l = total_size - i; - spi_write_enable(); if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); // spi_write_disable(); chip does this for us Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/it87spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -232,6 +232,7 @@ result = spi_write_enable(); if (result) return result; + /* FIXME: The command below seems to be redundant or wrong. */ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { @@ -262,10 +263,7 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); } Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/sb600spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -73,10 +73,7 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { spi_disable_blockprotect(); - result = spi_write_enable(); - if (result) - return result; - spi_byte_program(i, *buf); + result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) printf("."); Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -154,21 +154,7 @@ result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -736,39 +722,80 @@ return spi_send_command(sizeof(cmd), 0, cmd, NULL); } -void spi_byte_program(int address, uint8_t byte) +int spi_byte_program(int addr, uint8_t byte) { - const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = { - JEDEC_BYTE_PROGRAM, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - byte - }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send Byte-Program */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_nbyte_program(int address, uint8_t *bytes, int len) { + int result; + /* FIXME: Switch to malloc based on len unless that kills speed. */ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { JEDEC_BYTE_PROGRAM, (address >> 16) & 0xff, (address >> 8) & 0xff, (address >> 0) & 0xff, }; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + if (!len) { + printf_debug ("%s called for zero-length write\n", __func__); + return 1; + } if (len > 256) { - printf_debug ("%s called for too long a write\n", - __FUNCTION__); + printf_debug ("%s called for too long a write\n", __func__); return 1; } memcpy(&cmd[4], bytes, len); - /* Send Byte-Program */ - return spi_send_command(4 + len, 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + return result; + } + return result; } int spi_disable_blockprotect(void) @@ -883,7 +910,6 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-11 22:26:52 UTC (rev 650) +++ trunk/wbsio_spi.c 2009-07-12 12:06:18 UTC (rev 651) @@ -200,11 +200,8 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } - result = spi_write_enable(); - if (result) - return result; for (pos = 0; pos < size; pos++) { - spi_byte_program(pos, buf[pos]); + result = spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); }

1 0

[PATCH] Convert SPI block erase to multicommand
by Carl-Daniel Hailfinger 12 Jul '09

12 Jul '09

Convert SPI block erase to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_blockerase/spi.c =================================================================== --- flashrom-spi_multicommand_blockerase/spi.c (Revision 648) +++ flashrom-spi_multicommand_blockerase/spi.c (Arbeitskopie) @@ -536,17 +536,30 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -566,17 +579,30 @@ */ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -615,18 +641,30 @@ /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE, }; int result; - - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_SE, (addr & 0x00ff0000) >> 16, (addr & 0x0000ff00) >> 8, (addr & 0x000000ff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send SE (Sector Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ -- http://www.hailfinger.org/

2 3

[commit] r650 - trunk
by svn＠flashrom.org 12 Jul '09

12 Jul '09

Author: hailfinger Date: 2009-07-12 00:26:52 +0200 (Sun, 12 Jul 2009) New Revision: 650 Modified: trunk/spi.c Log: Convert SPI block erase to use the multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Jakob writes: Tested it on my EPIA-m700 and it worked nice. Also double checked that one of the changed functions actually ran. Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 22:17:28 UTC (rev 649) +++ trunk/spi.c 2009-07-11 22:26:52 UTC (rev 650) @@ -536,17 +536,30 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -566,17 +579,30 @@ */ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8, }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send BE (Block Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -615,18 +641,30 @@ /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE, }; int result; - - cmd[1] = (addr & 0x00ff0000) >> 16; - cmd[2] = (addr & 0x0000ff00) >> 8; - cmd[3] = (addr & 0x000000ff); + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - result = spi_write_enable(); - if (result) + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); return result; - /* Send SE (Sector Erase) */ - spi_send_command(sizeof(cmd), 0, cmd, NULL); + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */

1 0

[commit] r649 - trunk
by svn＠flashrom.org 12 Jul '09

12 Jul '09

Author: uwe Date: 2009-07-12 00:17:28 +0200 (Sun, 12 Jul 2009) New Revision: 649 Modified: trunk/flashrom.8 Log: Fix incorrect manpage (trivial). The flashrom manpage currently says "-w, --write: Write file into flash ROM (default when <file> is specified)". This is no longer true for recent flashrom versions, which only write if you explicitly use the -w option. Proof: $ flashrom coreboot.rom flashrom v0.9.0-r631 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found board "Kontron 986LCD-M", enabling flash write... OK. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. No operations were specified. Thus, fix manpage accordingly. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-07-11 19:39:11 UTC (rev 648) +++ trunk/flashrom.8 2009-07-11 22:17:28 UTC (rev 649) @@ -33,9 +33,7 @@ .BR <file> . .TP .B "\-w, \-\-write <file>" -Write file into flash ROM (default when -.B <file> -is specified). +Write file into flash ROM. .TP .B "\-n, \-\-noverify" Do

1 0

[PATCH] Add Winbond W25X16
by Hector Martin 11 Jul '09

11 Jul '09

Tested probing and reading only. The chip ID was already in flashchips.h. Signed-off-by: Hector Martin <hector(a)marcansoft.com> --- flashrom/flashchips.c (revision 645) +++ flashrom/flashchips.c (working copy) @@ -2795,6 +2795,22 @@ { .vendor = "Winbond", + .name = "W25x16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25X16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W29C011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, -- Hector Martin (hector(a)marcansoft.com) Public Key: http://www.marcansoft.com/marcan.asc

2 1

[commit] r648 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 21:39:11 +0200 (Sat, 11 Jul 2009) New Revision: 648 Modified: trunk/flashchips.c Log: Add Winbond W25X16. Tested probing and reading only. The chip ID was already in flashchips.h. Signed-off-by: Hector Martin <hector(a)marcansoft.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-11 19:28:36 UTC (rev 647) +++ trunk/flashchips.c 2009-07-11 19:39:11 UTC (rev 648) @@ -2795,6 +2795,22 @@ { .vendor = "Winbond", + .name = "W25x16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = W_25X16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W29C011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID,

1 0

[PATCH] Convert SPI chip erase to multicommand
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

Convert SPI chip erase to use the multicommand infrastructure. This breaks ICH/VIA SPI. The good news is that once VIA/SPI are converted to multicommand, a lot of hacks can disappear. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_chiperase/spi.c =================================================================== --- flashrom-spi_multicommand_chiperase/spi.c (Revision 645) +++ flashrom-spi_multicommand_chiperase/spi.c (Arbeitskopie) @@ -417,21 +417,34 @@ int spi_chip_erase_60(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_60_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_60 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -449,21 +462,34 @@ int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_C7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. -- http://www.hailfinger.org/

2 4

[commit] r647 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 21:28:36 +0200 (Sat, 11 Jul 2009) New Revision: 647 Modified: trunk/spi.c Log: Convert SPI chip erase to use the multicommand infrastructure. Once the ICH/VIA SPI driver is converted to multicommand, a lot of hacks can disappear. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-11 18:05:42 UTC (rev 646) +++ trunk/spi.c 2009-07-11 19:28:36 UTC (rev 647) @@ -61,12 +61,30 @@ int spi_send_multicommand(struct spi_command *spicommands) { - int res = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !res) { - res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + int ret = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !ret) { + ret = spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); + /* This awful hack needs to be replaced with a multicommand + * capable ICH/VIA SPI driver. + */ + if ((ret == SPI_INVALID_OPCODE) && + ((spicommands->writearr[0] == JEDEC_WREN) || + (spicommands->writearr[0] == JEDEC_EWSR))) { + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_ICH9: + case SPI_CONTROLLER_VIA: + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + ret = 0; + default: + break; + } + } + spicommands++; } - return res; + return ret; } static int spi_rdid(unsigned char *readarr, int bytes) @@ -417,21 +435,34 @@ int spi_chip_erase_60(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_60_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_60 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -449,21 +480,34 @@ int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_CE_C7_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } - result = spi_write_enable(); - if (result) - return result; - /* Send CE (Chip Erase) */ - result = spi_send_command(sizeof(cmd), 0, cmd, NULL); + + result = spi_send_multicommand(spicommands); if (result) { - printf_debug("spi_chip_erase_60 failed sending erase\n"); + printf_debug("%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared.

1 0

test
by Carl-Daniel Hailfinger 11 Jul '09

11 Jul '09

test the list configuration

1 0

[commit] r646 - trunk
by svn＠flashrom.org 11 Jul '09

11 Jul '09

Author: hailfinger Date: 2009-07-11 20:05:42 +0200 (Sat, 11 Jul 2009) New Revision: 646 Modified: trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/it87spi.c Log: Add an optional flash port parameter for IT87* SPI controllers in standalone programmer mode. If the parameter is set, the IT87* SPI driver will set the I/O base port of the IT87* SPI controller interface to the port specified in the parameter. Usage: flashrom -p it87spi=port=0x820 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flash.h 2009-07-11 18:05:42 UTC (rev 646) @@ -479,6 +479,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); /* it87spi.c */ +extern char *it87opts; extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flashrom.8 2009-07-11 18:05:42 UTC (rev 646) @@ -184,6 +184,14 @@ .BR nic3com , .BR satasii . .sp +The it87spi has an optional parameter which will set the I/O base port of the +IT87* SPI controller interface to the port specified in the parameter. +For that you have to use the +.B "flashrom -p it87spi=port=portnum" +syntax where +.B portnum +is an I/O port number which must be a multiple of 8. +.sp The ft2232spi has an optional parameter specifying the controller type and interface/port it should support. For that you have to use the .B "flashrom -p ft2232spi=model,port=interface" Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/flashrom.c 2009-07-11 18:05:42 UTC (rev 646) @@ -647,6 +647,8 @@ pcidev_bdf = strdup(optarg + 8); } else if (strncmp(optarg, "it87spi", 7) == 0) { programmer = PROGRAMMER_IT87SPI; + if (optarg[7] == '=') + it87opts = strdup(optarg + 8); } else if (strncmp(optarg, "ft2232spi", 9) == 0) { programmer = PROGRAMMER_FT2232SPI; if (optarg[9] == '=') Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-10 21:08:55 UTC (rev 645) +++ trunk/it87spi.c 2009-07-11 18:05:42 UTC (rev 646) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> * Copyright (C) 2008 coresystems GmbH * @@ -24,12 +24,14 @@ */ #include <string.h> +#include <stdlib.h> #include "flash.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +char *it87opts = NULL; uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; @@ -56,6 +58,7 @@ static uint16_t find_ite_spi_flash_port(uint16_t port) { uint8_t tmp = 0; + char *portpos = NULL; uint16_t id, flashport = 0; enter_conf_mode_ite(port); @@ -77,6 +80,9 @@ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); printf("LPC write to serial flash %sabled\n", (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ /* If any serial flash segment is enabled, enable writing. */ if ((tmp & 0xe) && (!(tmp & 1 << 4))) { printf("Enabling LPC write to serial flash\n"); @@ -89,6 +95,17 @@ flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); printf("Serial flash port 0x%04x\n", flashport); + if (it87opts && !strlen(it87opts)) { + free(it87opts); + it87opts = NULL; + } + if (it87opts && (portpos = strstr(it87opts, "port="))) { + portpos += 5; + flashport = strtol(portpos, (char **)NULL, 0); + printf("Forcing serial flash port 0x%04x\n", flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } } exit_conf_mode_ite(port); return flashport; @@ -206,10 +223,11 @@ } /* Page size is usually 256 bytes */ -static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) +static int it8716f_spi_page_program(struct flashchip *flash, int block, uint8_t *buf) { int i; int result; + chipaddr bios = flash->virtual_memory; result = spi_write_enable(); if (result) @@ -217,7 +235,7 @@ OUTB(0x06, it8716f_flashport + 1); OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { - bios[256 * block + i] = buf[256 * block + i]; + chip_writeb(buf[256 * block + i], bios + 256 * block + i); } OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. @@ -288,8 +306,7 @@ it8716f_spi_chip_write_1(flash, buf); } else { for (i = 0; i < total_size / 256; i++) { - it8716f_spi_page_program(i, buf, - (uint8_t *)flash->virtual_memory); + it8716f_spi_page_program(flash, i, buf); } }

1 0

[PATCH] Add SPI multicommand infrastructure
by Carl-Daniel Hailfinger 10 Jul '09

10 Jul '09

Add SPI multicommand infrastructure. Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand/flash.h =================================================================== --- flashrom-spi_multicommand/flash.h (Revision 643) +++ flashrom-spi_multicommand/flash.h (Arbeitskopie) @@ -350,7 +350,7 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* nic3com.c */ @@ -372,7 +372,7 @@ #define FTDI_FT4232H 0x6011 extern char *ft2232spi_param; int ft2232_spi_init(void); -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -414,14 +414,22 @@ SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, }; +struct spi_command { + unsigned int writecnt; + unsigned int readcnt; + const unsigned char *writearr; + unsigned char *readarr; +}; + extern enum spi_controller spi_controller; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(struct spi_command *spicommands); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -465,7 +473,7 @@ /* ichspi.c */ int ich_init_opcodes(void); -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); @@ -476,14 +484,14 @@ void exit_conf_mode_ite(uint16_t port); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); @@ -582,7 +590,7 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); Index: flashrom-spi_multicommand/it87spi.c =================================================================== --- flashrom-spi_multicommand/it87spi.c (Revision 643) +++ flashrom-spi_multicommand/it87spi.c (Arbeitskopie) @@ -141,7 +141,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; Index: flashrom-spi_multicommand/spi.c =================================================================== --- flashrom-spi_multicommand/spi.c (Revision 643) +++ flashrom-spi_multicommand/spi.c (Arbeitskopie) @@ -32,25 +32,25 @@ void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { switch (spi_controller) { case SPI_CONTROLLER_IT87XX: - return it8716f_spi_command(writecnt, readcnt, writearr, + return it8716f_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_SB600: - return sb600_spi_command(writecnt, readcnt, writearr, readarr); + return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_WBSIO: - return wbsio_spi_command(writecnt, readcnt, writearr, readarr); + return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_FT2232: - return ft2232_spi_command(writecnt, readcnt, writearr, readarr); + return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_DUMMY: - return dummy_spi_command(writecnt, readcnt, writearr, readarr); + return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -59,13 +59,23 @@ return 1; } +int spi_send_multicommand(struct spi_command *spicommands) +{ + int res = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !res) { + res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return res; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; printf_debug("RDID returned"); @@ -81,14 +91,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -102,14 +112,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); } if (ret) return ret; @@ -123,7 +133,7 @@ int result; /* Send WREN (Write Enable) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -150,7 +160,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -292,7 +302,7 @@ /* SB600 uses a different way to read status register. */ return sb600_read_status_register(); } else { - ret = spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) printf_debug("RDSR failed!\n"); } @@ -419,7 +429,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -451,7 +461,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -492,7 +502,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -522,7 +532,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -572,7 +582,7 @@ if (result) return result; /* Send SE (Sector Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -609,7 +619,7 @@ int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -641,7 +651,7 @@ { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -655,7 +665,7 @@ }; /* Send Byte-Program */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); } int spi_nbyte_program(int address, uint8_t *bytes, int len) @@ -676,7 +686,7 @@ memcpy(&cmd[4], bytes, len); /* Send Byte-Program */ - return spi_command(4 + len, 0, cmd, NULL); + return spi_send_command(4 + len, 0, cmd, NULL); } int spi_disable_blockprotect(void) @@ -712,7 +722,7 @@ }; /* Send Read */ - return spi_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(sizeof(cmd), len, cmd, bytes); } /* @@ -855,13 +865,13 @@ result = spi_write_enable(); if (result) return result; - spi_command(6, 0, w, NULL); + spi_send_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; - spi_command(3, 0, w, NULL); + spi_send_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } Index: flashrom-spi_multicommand/ft2232_spi.c =================================================================== --- flashrom-spi_multicommand/ft2232_spi.c (Revision 643) +++ flashrom-spi_multicommand/ft2232_spi.c (Arbeitskopie) @@ -193,7 +193,7 @@ return 0; } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -298,7 +298,7 @@ exit(1); } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { fprintf(stderr, "FT2232 SPI support was not compiled in\n"); Index: flashrom-spi_multicommand/wbsio_spi.c =================================================================== --- flashrom-spi_multicommand/wbsio_spi.c (Revision 643) +++ flashrom-spi_multicommand/wbsio_spi.c (Arbeitskopie) @@ -90,7 +90,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-spi_multicommand/dummyflasher.c =================================================================== --- flashrom-spi_multicommand/dummyflasher.c (Revision 643) +++ flashrom-spi_multicommand/dummyflasher.c (Arbeitskopie) @@ -141,7 +141,7 @@ return; } -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Index: flashrom-spi_multicommand/sb600spi.c =================================================================== --- flashrom-spi_multicommand/sb600spi.c (Revision 643) +++ flashrom-spi_multicommand/sb600spi.c (Arbeitskopie) @@ -52,7 +52,7 @@ unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -103,7 +103,7 @@ ; } -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Index: flashrom-spi_multicommand/ichspi.c =================================================================== --- flashrom-spi_multicommand/ichspi.c (Revision 643) +++ flashrom-spi_multicommand/ichspi.c (Arbeitskopie) @@ -682,7 +682,7 @@ return rc; } -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int a; -- http://www.hailfinger.org/

2 2

[commit] r645 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 23:08:55 +0200 (Fri, 10 Jul 2009) New Revision: 645 Modified: trunk/dummyflasher.c trunk/flash.h trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Add SPI multicommand infrastructure. Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/dummyflasher.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ return; } -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/flash.h 2009-07-10 21:08:55 UTC (rev 645) @@ -350,7 +350,7 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* nic3com.c */ @@ -372,7 +372,7 @@ #define FTDI_FT4232H 0x6011 extern char *ft2232spi_param; int ft2232_spi_init(void); -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -414,14 +414,22 @@ SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, }; +struct spi_command { + unsigned int writecnt; + unsigned int readcnt; + const unsigned char *writearr; + unsigned char *readarr; +}; + extern enum spi_controller spi_controller; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(struct spi_command *spicommands); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -465,7 +473,7 @@ /* ichspi.c */ int ich_init_opcodes(void); -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); @@ -476,14 +484,14 @@ void exit_conf_mode_ite(uint16_t port); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); @@ -582,7 +590,7 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ft2232_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -193,7 +193,7 @@ return 0; } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -298,7 +298,7 @@ exit(1); } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { fprintf(stderr, "FT2232 SPI support was not compiled in\n"); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ichspi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -682,7 +682,7 @@ return rc; } -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int a; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/it87spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/sb600spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -52,7 +52,7 @@ unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -103,7 +103,7 @@ ; } -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -32,25 +32,25 @@ void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { switch (spi_controller) { case SPI_CONTROLLER_IT87XX: - return it8716f_spi_command(writecnt, readcnt, writearr, + return it8716f_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_SB600: - return sb600_spi_command(writecnt, readcnt, writearr, readarr); + return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_WBSIO: - return wbsio_spi_command(writecnt, readcnt, writearr, readarr); + return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_FT2232: - return ft2232_spi_command(writecnt, readcnt, writearr, readarr); + return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_DUMMY: - return dummy_spi_command(writecnt, readcnt, writearr, readarr); + return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -59,13 +59,23 @@ return 1; } +int spi_send_multicommand(struct spi_command *spicommands) +{ + int res = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !res) { + res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return res; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; printf_debug("RDID returned"); @@ -81,14 +91,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -102,14 +112,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); } if (ret) return ret; @@ -123,7 +133,7 @@ int result; /* Send WREN (Write Enable) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -150,7 +160,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -292,7 +302,7 @@ /* SB600 uses a different way to read status register. */ return sb600_read_status_register(); } else { - ret = spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) printf_debug("RDSR failed!\n"); } @@ -419,7 +429,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -451,7 +461,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -492,7 +502,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -522,7 +532,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -572,7 +582,7 @@ if (result) return result; /* Send SE (Sector Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -609,7 +619,7 @@ int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -641,7 +651,7 @@ { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -655,7 +665,7 @@ }; /* Send Byte-Program */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); } int spi_nbyte_program(int address, uint8_t *bytes, int len) @@ -676,7 +686,7 @@ memcpy(&cmd[4], bytes, len); /* Send Byte-Program */ - return spi_command(4 + len, 0, cmd, NULL); + return spi_send_command(4 + len, 0, cmd, NULL); } int spi_disable_blockprotect(void) @@ -712,7 +722,7 @@ }; /* Send Read */ - return spi_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(sizeof(cmd), len, cmd, bytes); } /* @@ -855,13 +865,13 @@ result = spi_write_enable(); if (result) return result; - spi_command(6, 0, w, NULL); + spi_send_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; - spi_command(3, 0, w, NULL); + spi_send_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/wbsio_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -90,7 +90,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i;

1 0

[commit] r644 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 22:19:48 +0200 (Fri, 10 Jul 2009) New Revision: 644 Modified: trunk/Makefile Log: Change tarball compression from gzip to bzip2. Set the user and group of all files to root for tar versions which support it. Add explanatory comments for supporting that feature with other tar versions. Use LC_ALL instead of LANG everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-07-08 14:50:36 UTC (rev 643) +++ trunk/Makefile 2009-07-10 20:19:48 UTC (rev 644) @@ -58,7 +58,7 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LANG=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) +SVNVERSION := $(shell LC_ALL=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) VERSION := 0.9.0-r$(SVNVERSION) @@ -67,10 +67,15 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") +FEATURE_CFLAGS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") -FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +FEATURE_LIBS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +# TAROPTIONS reduces information leakage from the packager's system. +# If other tar programs support command line arguments for setting uid/gid of +# stored files, they can be handled here as well. +TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") + %.o: %.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< @@ -137,9 +142,9 @@ @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ tarball: export - @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @tar cjf $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 -C $(EXPORTDIR)/ $(TAROPTIONS) flashrom-$(VERSION)/ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) - @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 .PHONY: all clean distclean dep compiler pciutils features export tarball

1 0

Re: [flashrom] [Patch] superiotool: Add IT8703F support.
by Glenn Mueller 09 Jul '09

09 Jul '09

here it is. > Date: Thu, 9 Jul 2009 18:36:59 +0200 > To: coreboot(a)coreboot.org > CC: mechwarrior5(a)hotmail.com > Subject: [Patch] superiotool: Add IT8703F support. > From: libv(a)skynet.be > > Glenn, can you run this on your Asus A7V8X and attach the output? > > Thanks, > > Luc Verhaegen. _________________________________________________________________ Lauren found her dream laptop. Find the PC that’s right for you. http://www.microsoft.com/windows/choosepc/?ocid=ftp_val_wl_290

1 0

[Patch] Flag bad read/write on W39V040B.
by Luc Verhaegen 08 Jul '09

08 Jul '09

I found an extra chip on a k8m890 board i got off of ebay which was completely fubar. If there's a taker in euroland who wants to spend time on this, just give me a holler. Luc Verhaegen.

2 2

[commit] r643 - trunk
by svn＠flashrom.org 08 Jul '09

08 Jul '09

Author: libv Date: 2009-07-08 16:50:36 +0200 (Wed, 08 Jul 2009) New Revision: 643 Modified: trunk/flashchips.c Log: W39V040B: Flag Erase/Write as bad. Chip has now been properly tested in both my Jetway J7F5M and my EPIA-SP (known good board). Erase and write fail. Mark these operations as bad until i or someone else have time to fix this. Reported by Arvid Brodin <arvidb(a)kth.se>. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> M flashchips.c Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-06 22:58:46 UTC (rev 642) +++ trunk/flashchips.c 2009-07-08 14:50:36 UTC (rev 643) @@ -2881,7 +2881,7 @@ .model_id = W_39V040B, .total_size = 512, .page_size = 64*1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR | TEST_BAD_ERASE | TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec,

1 0

Flashrom does not work with J7F5M
by Arvid Brodin 07 Jul '09

07 Jul '09

Hi. I tested flashrom on my Jetway J7F5M motherboard. # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA CX700", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. No operations were specified. So probing seems to work ok, as do reading. Writing, however, does not work - the image on the flash chip remains unchanged (had a sweaty moment after the FAILED message before I had read the chip again and diffed it against the backed-up original image!). The "Protect flash part" option in BIOS is set to Disabled (I also tried Enabled, just to be sure). Is there any hope on getting flashrom support for this card? The AWDFLASH.EXE utility recommended for flashing by Jetway is "only" some sixty thousand bytes - any hints on reverse engineering this? The computer is head-, FD- and CDR-less and runs linux, so it's a chore to flash it with the d**n DOS utility... -- Arvid

2 7

https://www.ohloh.net/p/flashrom
by Luc Verhaegen 07 Jul '09

07 Jul '09

Go claim your contributions :) Luc Verhaegen.

1 0

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