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[commit] r664 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 03:44:38 +0200 (Thu, 23 Jul 2009) New Revision: 664 Modified: trunk/flashchips.c Log: Fix erase for SST49LF020A. The chip supports multiple erase functions, but the function we use has an eraseblock size of 4k. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-23 01:42:56 UTC (rev 663) +++ trunk/flashchips.c 2009-07-23 01:44:38 UTC (rev 664) @@ -2160,7 +2160,7 @@ .manufacture_id = SST_ID, .model_id = SST_49LF020A, .total_size = 256, - .page_size = 16 * 1024, + .page_size = 4 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */

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[PATCH] Continue verifying after first error
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

Continue erase/write verification after the first error. The first error is printed in detail and all subsequent errors are listed in statistics. This allows users to check if there was just one error or if the failure was widespread. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-verify_keep_going/flashrom.c =================================================================== --- flashrom-verify_keep_going/flashrom.c (Revision 659) +++ flashrom-verify_keep_going/flashrom.c (Arbeitskopie) @@ -278,6 +278,7 @@ int i, j, starthere, lenhere, ret = 0; int page_size = flash->page_size; uint8_t *readbuf = malloc(page_size); + int failcount = 0; if (!len) goto out_free; @@ -318,15 +319,21 @@ flash->read(flash, readbuf, starthere, lenhere); for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { - fprintf(stderr, "%s FAILED at 0x%08x! " - "Expected=0x%02x, Read=0x%02x\n", - message, starthere + j, - cmpbuf[starthere - start + j], readbuf[j]); - ret = -1; - goto out_free; + /* Only print the first failure. */ + if (!failcount++) + fprintf(stderr, "%s FAILED at 0x%08x! " + "Expected=0x%02x, Read=0x%02x,", + message, starthere + j, + cmpbuf[starthere - start + j], + readbuf[j]); } } } + if (failcount) { + fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + start, start + len - 1, failcount); + ret = -1; + } out_free: free(readbuf); -- http://www.hailfinger.org/

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[commit] r663 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 03:42:56 +0200 (Thu, 23 Jul 2009) New Revision: 663 Modified: trunk/flashrom.c Log: Continue erase/write verification after the first error. The first error is printed in detail and all subsequent errors are listed in statistics. This allows users to check if there was just one error or if the failure was widespread. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-23 01:40:20 UTC (rev 662) +++ trunk/flashrom.c 2009-07-23 01:42:56 UTC (rev 663) @@ -278,6 +278,7 @@ int i, j, starthere, lenhere, ret = 0; int page_size = flash->page_size; uint8_t *readbuf = malloc(page_size); + int failcount = 0; if (!len) goto out_free; @@ -318,15 +319,21 @@ flash->read(flash, readbuf, starthere, lenhere); for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { - fprintf(stderr, "%s FAILED at 0x%08x! " - "Expected=0x%02x, Read=0x%02x\n", - message, starthere + j, - cmpbuf[starthere - start + j], readbuf[j]); - ret = -1; - goto out_free; + /* Only print the first failure. */ + if (!failcount++) + fprintf(stderr, "%s FAILED at 0x%08x! " + "Expected=0x%02x, Read=0x%02x,", + message, starthere + j, + cmpbuf[starthere - start + j], + readbuf[j]); } } } + if (failcount) { + fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + start, start + len - 1, failcount); + ret = -1; + } out_free: free(readbuf);

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[PATCH] ST M25P RES support
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

Add support for old ST M25P05/M25P10 chips which only respond to the RES command and not the RDID command. Unfortunately, either the datasheets are wrong or both chips have exactly the same ID. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst25_res/flashchips.c =================================================================== --- flashrom-sst25_res/flashchips.c (Revision 659) +++ flashrom-sst25_res/flashchips.c (Arbeitskopie) @@ -2249,8 +2249,29 @@ .read = spi_chip_read, }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the + * ST M25P05-A in RES mode, but supports only 128 byte writes instead + * of 256 byte writes. We rely heavily on the fact that probe_spi_res + * only is successful if RDID does not work. + */ { .vendor = "ST", + .name = "M25P05.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P05_RES, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P10-A", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, @@ -2265,8 +2286,25 @@ .read = spi_chip_read, }, + /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", + .name = "M25P10.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P10_RES, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P20", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, Index: flashrom-sst25_res/flashchips.h =================================================================== --- flashrom-sst25_res/flashchips.h (Revision 659) +++ flashrom-sst25_res/flashchips.h (Arbeitskopie) @@ -322,7 +322,9 @@ */ #define ST_ID 0x20 /* ST / SGS/Thomson */ #define ST_M25P05A 0x2010 +#define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 +#define ST_M25P10_RES 0x10 /* Same code as M25P05. */ #define ST_M25P20 0x2012 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 -- http://www.hailfinger.org/

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[commit] r662 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 03:40:20 +0200 (Thu, 23 Jul 2009) New Revision: 662 Modified: trunk/flashchips.c trunk/flashchips.h Log: Add support for old ST M25P05/M25P10 chips which only respond to the RES command and not the RDID command. Unfortunately, either the datasheets are wrong or both chips have exactly the same ID. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-23 01:36:08 UTC (rev 661) +++ trunk/flashchips.c 2009-07-23 01:40:20 UTC (rev 662) @@ -2249,8 +2249,29 @@ .read = spi_chip_read, }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the + * ST M25P05-A in RES mode, but supports only 128 byte writes instead + * of 256 byte writes. We rely heavily on the fact that probe_spi_res + * only is successful if RDID does not work. + */ { .vendor = "ST", + .name = "M25P05.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P05_RES, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P10-A", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, @@ -2265,8 +2286,25 @@ .read = spi_chip_read, }, + /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", + .name = "M25P10.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P10_RES, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25P20", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, Modified: trunk/flashchips.h =================================================================== --- trunk/flashchips.h 2009-07-23 01:36:08 UTC (rev 661) +++ trunk/flashchips.h 2009-07-23 01:40:20 UTC (rev 662) @@ -322,7 +322,9 @@ */ #define ST_ID 0x20 /* ST / SGS/Thomson */ #define ST_M25P05A 0x2010 +#define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 +#define ST_M25P10_RES 0x10 /* Same code as M25P05. */ #define ST_M25P20 0x2012 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12

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[PATCH] SB600 SPI off-by-one read count workaround
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

This is a workaround for a bug in SB600 and SB700. If we only send an opcode and no additional data/address, the SPI controller will read one byte too few from the chip. Basically, the last byte of the chip response is discarded and will not end up in the FIFO. It is unclear if the CS# line is set high too early as well. That hardware bug is undocumented as of now, but I'm working with AMD to add a detailed description of it to the errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory comments for unintuitive code flow. Thanks go to Uwe for testing quite a few iterations of the patch. As a side benefit, we can now kill the SB600 flash chip status register special case, which was a somewhat misguided workaround for that hardware erratum. Note for future added features in the SB600 SPI driver: It may be possible to read up to 15 bytes of command response with overlapping reads due to the ring buffer design of the FIFO if the command can be repeated without ill effects. Same for skipping up to 7 bytes between command and response. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_sb600_offbyone_workaround/chipset_enable.c =================================================================== --- flashrom-spi_sb600_offbyone_workaround/chipset_enable.c (Revision 653) +++ flashrom-spi_sb600_offbyone_workaround/chipset_enable.c (Arbeitskopie) @@ -692,25 +692,49 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); - tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) has_spi = 0; - /* Physical memory can only be mapped at page (4k) boundaries */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); - /* The low bits of the SPI base address are used as offset into the mapped page */ - sb600_spibar += tmp & 0xfff; + if (has_spi) { + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + tmp = pci_read_long(dev, 0xa0); + printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { + if (has_spi && !smbus_dev) { fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; - } else { + } + if (has_spi) { /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); Index: flashrom-spi_sb600_offbyone_workaround/sb600spi.c =================================================================== --- flashrom-spi_sb600_offbyone_workaround/sb600spi.c (Revision 653) +++ flashrom-spi_sb600_offbyone_workaround/sb600spi.c (Arbeitskopie) @@ -38,7 +38,7 @@ *}; */ -uint8_t *sb600_spibar; +uint8_t *sb600_spibar = NULL; int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -106,6 +106,7 @@ int count; /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; + unsigned int readoffby1; writecnt--; @@ -124,8 +125,15 @@ return SPI_INVALID_LENGTH; } + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + mmio_writeb((readcnt + readoffby1) << 4 | (writecnt), sb600_spibar + 1); mmio_writeb(cmd, sb600_spibar + 0); - mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1); /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); @@ -147,17 +155,24 @@ /* * After the command executed, we should find out the index of the - * received byte. Here we just reset the FIFO pointer, skip the - * writecnt, is there anyone who have anther method to replace it? + * received byte. Here we just reset the FIFO pointer and skip the + * writecnt. + * It would be possible to increase the FIFO pointer by one instead + * of reading and discarding one byte from the FIFO. + * The FIFO is implemented on top of an 8 byte ring buffer and the + * buffer is never cleared. For every byte that is shifted out after + * the opcode, the FIFO already stores the response from the chip. + * Usually, the chip will respond with 0x00 or 0xff. */ reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("The FIFO pointer after skipping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); -- http://www.hailfinger.org/

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[commit] r661 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 03:36:08 +0200 (Thu, 23 Jul 2009) New Revision: 661 Modified: trunk/chipset_enable.c trunk/flash.h trunk/sb600spi.c trunk/spi.c Log: This is a workaround for a bug in SB600 and SB700. If we only send an opcode and no additional data/address, the SPI controller will read one byte too few from the chip. Basically, the last byte of the chip response is discarded and will not end up in the FIFO. It is unclear if the CS# line is set high too early as well. That hardware bug is undocumented as of now, but I'm working with AMD to add a detailed description of it to the errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory comments for unintuitive code flow. Thanks go to Uwe for testing quite a few iterations of the patch. Kill the SB600 flash chip status register special case, which was a somewhat misguided workaround for that hardware erratum. Note for future added features in the SB600 SPI driver: It may be possible to read up to 15 bytes of command response with overlapping reads due to the ring buffer design of the FIFO if the command can be repeated without ill effects. Same for skipping up to 7 bytes between command and response. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-07-23 01:33:43 UTC (rev 660) +++ trunk/chipset_enable.c 2009-07-23 01:36:08 UTC (rev 661) @@ -692,25 +692,49 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); - tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) has_spi = 0; - /* Physical memory can only be mapped at page (4k) boundaries */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); - /* The low bits of the SPI base address are used as offset into the mapped page */ - sb600_spibar += tmp & 0xfff; + if (has_spi) { + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + tmp = pci_read_long(dev, 0xa0); + printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { + if (has_spi && !smbus_dev) { fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; - } else { + } + if (has_spi) { /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-23 01:33:43 UTC (rev 660) +++ trunk/flash.h 2009-07-23 01:36:08 UTC (rev 661) @@ -511,7 +511,6 @@ const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); -uint8_t sb600_read_status_register(void); extern uint8_t *sb600_spibar; /* jedec.c */ Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-23 01:33:43 UTC (rev 660) +++ trunk/sb600spi.c 2009-07-23 01:36:08 UTC (rev 661) @@ -38,7 +38,7 @@ *}; */ -uint8_t *sb600_spibar; +uint8_t *sb600_spibar = NULL; int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -46,16 +46,6 @@ return spi_read_chunked(flash, buf, start, len, 8); } -uint8_t sb600_read_status_register(void) -{ - const unsigned char cmd[0x02] = { JEDEC_RDSR, 0x00 }; - unsigned char readarr[JEDEC_RDSR_INSIZE]; - - /* Read Status Register */ - spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); - return readarr[0]; -} - int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { int rc = 0, i; @@ -106,6 +96,7 @@ int count; /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; + unsigned int readoffby1; writecnt--; @@ -124,8 +115,15 @@ return SPI_INVALID_LENGTH; } + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + mmio_writeb((readcnt + readoffby1) << 4 | (writecnt), sb600_spibar + 1); mmio_writeb(cmd, sb600_spibar + 0); - mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1); /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); @@ -147,17 +145,25 @@ /* * After the command executed, we should find out the index of the - * received byte. Here we just reset the FIFO pointer, skip the - * writecnt, is there anyone who have anther method to replace it? + * received byte. Here we just reset the FIFO pointer and skip the + * writecnt. + * It would be possible to increase the FIFO pointer by one instead + * of reading and discarding one byte from the FIFO. + * The FIFO is implemented on top of an 8 byte ring buffer and the + * buffer is never cleared. For every byte that is shifted out after + * the opcode, the FIFO already stores the response from the chip. + * Usually, the chip will respond with 0x00 or 0xff. */ reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("The FIFO pointer after skipping is %d.\n", + mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-23 01:33:43 UTC (rev 660) +++ trunk/spi.c 2009-07-23 01:36:08 UTC (rev 661) @@ -367,10 +367,6 @@ int ret; /* Read Status Register */ - if (spi_controller == SPI_CONTROLLER_SB600) { /* FIXME */ - /* Workaround for SB600 hardware bug. Can be killed later. */ - return sb600_read_status_register(); - } ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) fprintf(stderr, "RDSR failed!\n");

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[PATCH] Verbose probe output improvements
by Carl-Daniel Hailfinger 23 Jul '09

23 Jul '09

Verbose probe output is split across multiple lines for some probe functions. This makes visual inspection and grepping a lot harder than necessary. Remove line breaks where appropriate. Output of "flashrom -V" on various chipsets and programmers is appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-verbose_probe_oneline/jedec.c =================================================================== --- flashrom-verbose_probe_oneline/jedec.c (Revision 655) +++ flashrom-verbose_probe_oneline/jedec.c (Arbeitskopie) @@ -99,7 +99,7 @@ probe_timing_enter = probe_timing_exit = 0; } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ printf_debug("Chip lacks correct probe timing information, " - "using default 10mS/40uS\n"); + "using default 10mS/40uS. "); probe_timing_enter = 10000; probe_timing_exit = 40; } else { Index: flashrom-verbose_probe_oneline/spi.c =================================================================== --- flashrom-verbose_probe_oneline/spi.c (Revision 655) +++ flashrom-verbose_probe_oneline/spi.c (Arbeitskopie) @@ -99,7 +99,7 @@ printf_debug("RDID returned"); for (i = 0; i < bytes; i++) printf_debug(" 0x%02x", readarr[i]); - printf_debug("\n"); + printf_debug(". "); return 0; } @@ -177,12 +177,12 @@ return 0; if (!oddparity(readarr[0])) - printf_debug("RDID byte 0 parity violation.\n"); + printf_debug("RDID byte 0 parity violation. "); /* Check if this is a continuation vendor ID */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) - printf_debug("RDID byte 1 parity violation.\n"); + printf_debug("RDID byte 1 parity violation. "); id1 = (readarr[0] << 8) | readarr[1]; id2 = readarr[2]; if (bytes > 3) { -- http://www.hailfinger.org/

2 3

[commit] r660 - trunk
by svn＠flashrom.org 23 Jul '09

23 Jul '09

Author: hailfinger Date: 2009-07-23 03:33:43 +0200 (Thu, 23 Jul 2009) New Revision: 660 Modified: trunk/jedec.c trunk/spi.c trunk/w29ee011.c Log: Verbose probe output is split across multiple lines for some probe functions. This makes visual inspection and grepping a lot harder than necessary. Remove line breaks where appropriate. Some error messages should end up on stderr instead of just being displayed in verbose mode. Thanks to Maciej Pijanka for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-07-22 20:13:00 UTC (rev 659) +++ trunk/jedec.c 2009-07-23 01:33:43 UTC (rev 660) @@ -99,7 +99,7 @@ probe_timing_enter = probe_timing_exit = 0; } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ printf_debug("Chip lacks correct probe timing information, " - "using default 10mS/40uS\n"); + "using default 10mS/40uS. "); probe_timing_enter = 10000; probe_timing_exit = 40; } else { Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-22 20:13:00 UTC (rev 659) +++ trunk/spi.c 2009-07-23 01:33:43 UTC (rev 660) @@ -163,7 +163,7 @@ printf_debug("RDID returned"); for (i = 0; i < bytes; i++) printf_debug(" 0x%02x", readarr[i]); - printf_debug("\n"); + printf_debug(". "); return 0; } @@ -184,7 +184,7 @@ } if (ret) return ret; - printf_debug("REMS returned %02x %02x.\n", readarr[0], readarr[1]); + printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]); return 0; } @@ -205,7 +205,7 @@ } if (ret) return ret; - printf_debug("RES returned %02x.\n", readarr[0]); + printf_debug("RES returned %02x. ", readarr[0]); return 0; } @@ -218,7 +218,7 @@ result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) - printf_debug("%s failed\n", __func__); + fprintf(stderr, "%s failed\n", __func__); return result; } @@ -241,12 +241,12 @@ return 0; if (!oddparity(readarr[0])) - printf_debug("RDID byte 0 parity violation.\n"); + printf_debug("RDID byte 0 parity violation. "); /* Check if this is a continuation vendor ID */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) - printf_debug("RDID byte 1 parity violation.\n"); + printf_debug("RDID byte 1 parity violation. "); id1 = (readarr[0] << 8) | readarr[1]; id2 = readarr[2]; if (bytes > 3) { @@ -373,7 +373,7 @@ } ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) - printf_debug("RDSR failed!\n"); + fprintf(stderr, "RDSR failed!\n"); return readarr[0]; } @@ -506,13 +506,14 @@ result = spi_disable_blockprotect(); if (result) { - printf_debug("spi_disable_blockprotect failed\n"); + fprintf(stderr, "spi_disable_blockprotect failed\n"); return result; } result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -551,13 +552,13 @@ result = spi_disable_blockprotect(); if (result) { - printf_debug("spi_disable_blockprotect failed\n"); + fprintf(stderr, "spi_disable_blockprotect failed\n"); return result; } result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -607,7 +608,8 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -650,7 +652,7 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -678,7 +680,7 @@ for (i = 0; i < total_size / erase_size; i++) { rc = spi_block_erase_d8(flash, i * erase_size, erase_size); if (rc) { - printf("Error erasing block at 0x%x\n", i); + fprintf(stderr, "Error erasing block at 0x%x\n", i); break; } } @@ -712,7 +714,8 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); return result; } /* Wait until the Write-In-Progress bit is cleared. @@ -730,7 +733,8 @@ int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { - fprintf(stderr, "%s called with incorrect arguments\n", __func__); + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); return -1; } return spi_chip_erase_60(flash); @@ -739,7 +743,8 @@ int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { if ((addr != 0) || (blocklen != flash->total_size * 1024)) { - fprintf(stderr, "%s called with incorrect arguments\n", __func__); + fprintf(stderr, "%s called with incorrect arguments\n", + __func__); return -1; } return spi_chip_erase_c7(flash); @@ -754,7 +759,7 @@ result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) - printf_debug("%s failed\n", __func__); + fprintf(stderr, "%s failed\n", __func__); return result; } @@ -786,7 +791,8 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); } return result; } @@ -814,7 +820,8 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); } return result; } @@ -848,11 +855,11 @@ }}; if (!len) { - printf_debug ("%s called for zero-length write\n", __func__); + fprintf(stderr, "%s called for zero-length write\n", __func__); return 1; } if (len > 256) { - printf_debug ("%s called for too long a write\n", __func__); + fprintf(stderr, "%s called for too long a write\n", __func__); return 1; } @@ -860,7 +867,8 @@ result = spi_send_multicommand(spicommands); if (result) { - printf_debug("%s failed during command execution\n", __func__); + fprintf(stderr, "%s failed during command execution\n", + __func__); } return result; } @@ -876,7 +884,7 @@ printf_debug("Some block protection in effect, disabling\n"); result = spi_write_status_register(status & ~0x3c); if (result) { - printf_debug("spi_write_status_register failed\n"); + fprintf(stderr, "spi_write_status_register failed\n"); return result; } } Modified: trunk/w29ee011.c =================================================================== --- trunk/w29ee011.c 2009-07-22 20:13:00 UTC (rev 659) +++ trunk/w29ee011.c 2009-07-23 01:33:43 UTC (rev 660) @@ -28,11 +28,10 @@ extern char *chip_to_probe; if (!chip_to_probe || strcmp(chip_to_probe, "W29EE011")) { - printf_debug("\n===\n"); - printf_debug(" Probing disabled for Winbond W29EE011 because the probing sequence puts the\n"); - printf_debug(" AMIC A49LF040A in a funky state.\n"); - printf_debug(" Use 'flashrom -c W29EE011' if you have a board with this chip."); - printf_debug("\n===\n"); + printf_debug("Probing disabled for Winbond W29EE011 because " + "the probing sequence puts the AMIC A49LF040A in " + "a funky state. Use 'flashrom -c W29EE011' if you " + "have a board with this chip.\n"); return 0; }

1 0

[PATCH] Eliminate version string duplication
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Eliminate version string duplication. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-versionstring_once/flash.h =================================================================== --- flashrom-versionstring_once/flash.h (Revision 657) +++ flashrom-versionstring_once/flash.h (Arbeitskopie) @@ -379,6 +379,7 @@ /* flashrom.c */ extern int verbose; +extern const char *flashrom_version; #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); Index: flashrom-versionstring_once/flashrom.c =================================================================== --- flashrom-versionstring_once/flashrom.c (Revision 657) +++ flashrom-versionstring_once/flashrom.c (Arbeitskopie) @@ -30,6 +30,7 @@ #include "flash.h" #include "flashchips.h" +const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; int programmer = PROGRAMMER_INTERNAL; @@ -503,7 +504,7 @@ void print_version(void) { - printf("flashrom v%s\n", FLASHROM_VERSION); + printf("flashrom v%s\n", flashrom_version); } int main(int argc, char *argv[]) Index: flashrom-versionstring_once/print.c =================================================================== --- flashrom-versionstring_once/print.c (Revision 657) +++ flashrom-versionstring_once/print.c (Arbeitskopie) @@ -718,7 +718,7 @@ { time_t t = time(NULL); - printf(wiki_header, ctime(&t), FLASHROM_VERSION); + printf(wiki_header, ctime(&t), flashrom_version); print_supported_chips_wiki(); print_supported_chipsets_wiki(); print_supported_boards_wiki(); -- http://www.hailfinger.org/

2 2

[commit] r659 - trunk
by svn＠flashrom.org 22 Jul '09

22 Jul '09

Author: hailfinger Date: 2009-07-22 22:13:00 +0200 (Wed, 22 Jul 2009) New Revision: 659 Modified: trunk/flash.h trunk/flashrom.c trunk/print.c Log: Eliminate version string duplication. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-22 20:09:28 UTC (rev 658) +++ trunk/flash.h 2009-07-22 20:13:00 UTC (rev 659) @@ -379,6 +379,7 @@ /* flashrom.c */ extern int verbose; +extern const char *flashrom_version; #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-07-22 20:09:28 UTC (rev 658) +++ trunk/flashrom.c 2009-07-22 20:13:00 UTC (rev 659) @@ -30,6 +30,7 @@ #include "flash.h" #include "flashchips.h" +const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; int programmer = PROGRAMMER_INTERNAL; @@ -503,7 +504,7 @@ void print_version(void) { - printf("flashrom v%s\n", FLASHROM_VERSION); + printf("flashrom v%s\n", flashrom_version); } int main(int argc, char *argv[]) Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-07-22 20:09:28 UTC (rev 658) +++ trunk/print.c 2009-07-22 20:13:00 UTC (rev 659) @@ -718,7 +718,7 @@ { time_t t = time(NULL); - printf(wiki_header, ctime(&t), FLASHROM_VERSION); + printf(wiki_header, ctime(&t), flashrom_version); print_supported_chips_wiki(); print_supported_chipsets_wiki(); print_supported_boards_wiki();

1 0

[PATCH] Convert SPI write status register to multicommand
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Convert SPI write status register to multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_statusreg/spi.c =================================================================== --- flashrom-spi_multicommand_statusreg/spi.c (Revision 652) +++ flashrom-spi_multicommand_statusreg/spi.c (Arbeitskopie) @@ -690,21 +690,7 @@ result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -715,11 +701,30 @@ */ int spi_write_status_register(int status) { - const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = - { JEDEC_WRSR, (unsigned char)status }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_EWSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_EWSR }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send WRSR (Write Status Register) */ - return spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + } + return result; } int spi_byte_program(int addr, uint8_t byte) @@ -746,7 +751,6 @@ result = spi_send_multicommand(spicommands); if (result) { printf_debug("%s failed during command execution\n", __func__); - return result; } return result; } @@ -793,7 +797,6 @@ result = spi_send_multicommand(spicommands); if (result) { printf_debug("%s failed during command execution\n", __func__); - return result; } return result; } @@ -807,11 +810,6 @@ /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - result = spi_write_status_enable(); - if (result) { - printf_debug("spi_write_status_enable failed\n"); - return result; - } result = spi_write_status_register(status & ~0x3c); if (result) { printf_debug("spi_write_status_register failed\n"); -- http://www.hailfinger.org/

2 3

[commit] r658 - trunk
by svn＠flashrom.org 22 Jul '09

22 Jul '09

Author: hailfinger Date: 2009-07-22 22:09:28 +0200 (Wed, 22 Jul 2009) New Revision: 658 Modified: trunk/spi.c Log: Convert SPI write status register to multicommand infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-22 15:36:50 UTC (rev 657) +++ trunk/spi.c 2009-07-22 20:09:28 UTC (rev 658) @@ -754,21 +754,7 @@ result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) - printf_debug("%s failed", __func__); - if (result == SPI_INVALID_OPCODE) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - return 0; - default: - break; - } - } - if (result) - printf_debug("\n"); + printf_debug("%s failed\n", __func__); return result; } @@ -779,11 +765,30 @@ */ int spi_write_status_register(int status) { - const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = - { JEDEC_WRSR, (unsigned char)status }; + int result; + struct spi_command spicommands[] = { + { + .writecnt = JEDEC_EWSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_EWSR }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRSR_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; - /* Send WRSR (Write Status Register) */ - return spi_send_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_multicommand(spicommands); + if (result) { + printf_debug("%s failed during command execution\n", __func__); + } + return result; } int spi_byte_program(int addr, uint8_t byte) @@ -810,7 +815,6 @@ result = spi_send_multicommand(spicommands); if (result) { printf_debug("%s failed during command execution\n", __func__); - return result; } return result; } @@ -857,7 +861,6 @@ result = spi_send_multicommand(spicommands); if (result) { printf_debug("%s failed during command execution\n", __func__); - return result; } return result; } @@ -871,11 +874,6 @@ /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - result = spi_write_status_enable(); - if (result) { - printf_debug("spi_write_status_enable failed\n"); - return result; - } result = spi_write_status_register(status & ~0x3c); if (result) { printf_debug("spi_write_status_register failed\n");

1 0

Create spi programer struct
by Jakob Bornecrantz 22 Jul '09

22 Jul '09

Hi all Here is a patch that replaces most of the switch cases in the spi code with lookup on a struct instead. I have only done limited testing with the external ft2232 programmer. Cheers Jakob.

3 8

[commit] r657 - trunk
by svn＠flashrom.org 22 Jul '09

22 Jul '09

Author: hailfinger Date: 2009-07-22 17:36:50 +0200 (Wed, 22 Jul 2009) New Revision: 657 Modified: trunk/flash.h trunk/ichspi.c trunk/spi.c Log: Replace most of the switch cases in the spi code with lookup on a struct instead. This brings the SPI code in line with the generic programmer infrastructure. This patch is a reworked version of a patch by Jakob Bornecrantz. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-21 13:02:59 UTC (rev 656) +++ trunk/flash.h 2009-07-22 15:36:50 UTC (rev 657) @@ -420,8 +420,18 @@ const unsigned char *writearr; unsigned char *readarr; }; +struct spi_programmer { + int (*command)(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + int (*multicommand)(struct spi_command *spicommands); + /* Optimized functions for this programmer */ + int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); + int (*write_256)(struct flashchip *flash, uint8_t *buf); +}; + extern enum spi_controller spi_controller; +extern const struct spi_programmer spi_programmer[]; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); @@ -452,6 +462,9 @@ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); +int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int default_spi_send_multicommand(struct spi_command *spicommands); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); @@ -477,6 +490,7 @@ const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); +int ich_spi_send_multicommand(struct spi_command *spicommands); /* it87spi.c */ extern char *it87opts; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-21 13:02:59 UTC (rev 656) +++ trunk/ichspi.c 2009-07-22 15:36:50 UTC (rev 657) @@ -742,3 +742,23 @@ return result; } + +int ich_spi_send_multicommand(struct spi_command *spicommands) +{ + int ret = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !ret) { + ret = ich_spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + /* This awful hack needs to be smarter. + */ + if ((ret == SPI_INVALID_OPCODE) && + ((spicommands->writearr[0] == JEDEC_WREN) || + (spicommands->writearr[0] == JEDEC_EWSR))) { + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + ret = 0; + } + spicommands++; + } + return ret; +} Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-21 13:02:59 UTC (rev 656) +++ trunk/spi.c 2009-07-22 15:36:50 UTC (rev 657) @@ -32,61 +32,125 @@ void spi_prettyprint_status_register(struct flashchip *flash); +const struct spi_programmer spi_programmer[] = { + { /* SPI_CONTROLLER_NONE */ + .command = NULL, + .multicommand = NULL, + .read = NULL, + .write_256 = NULL, + }, + + { /* SPI_CONTROLLER_ICH7 */ + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, + }, + + { /* SPI_CONTROLLER_ICH9 */ + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, + }, + + { /* SPI_CONTROLLER_IT87XX */ + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, + }, + + { /* SPI_CONTROLLER_SB600 */ + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = sb600_spi_read, + .write_256 = sb600_spi_write_1, + }, + + { /* SPI_CONTROLLER_VIA */ + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, + }, + + { /* SPI_CONTROLLER_WBSIO */ + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = wbsio_spi_write_1, + }, + + { /* SPI_CONTROLLER_FT2232 */ + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ft2232_spi_read, + .write_256 = ft2232_spi_write_256, + }, + + { /* SPI_CONTROLLER_DUMMY */ + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = NULL, + .write_256 = NULL, + }, +}; + + int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - switch (spi_controller) { - case SPI_CONTROLLER_IT87XX: - return it8716f_spi_send_command(writecnt, readcnt, writearr, - readarr); - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - return ich_spi_send_command(writecnt, readcnt, writearr, readarr); - case SPI_CONTROLLER_SB600: - return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); - case SPI_CONTROLLER_WBSIO: - return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); - case SPI_CONTROLLER_FT2232: - return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); - case SPI_CONTROLLER_DUMMY: - return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); - default: - printf_debug - ("%s called, but no SPI chipset/strapping detected\n", - __FUNCTION__); + if (!spi_programmer[spi_controller].command) { + fprintf(stderr, "%s called, but SPI is unsupported on this " + "hardware. Please report a bug.\n", __func__); + return 1; } - return 1; + + return spi_programmer[spi_controller].command(writecnt, readcnt, + writearr, readarr); } int spi_send_multicommand(struct spi_command *spicommands) { - int ret = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !ret) { - ret = spi_send_command(spicommands->writecnt, spicommands->readcnt, - spicommands->writearr, spicommands->readarr); - /* This awful hack needs to be replaced with a multicommand - * capable ICH/VIA SPI driver. - */ - if ((ret == SPI_INVALID_OPCODE) && - ((spicommands->writearr[0] == JEDEC_WREN) || - (spicommands->writearr[0] == JEDEC_EWSR))) { - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - ret = 0; - default: - break; - } - } - spicommands++; + if (!spi_programmer[spi_controller].multicommand) { + fprintf(stderr, "%s called, but SPI is unsupported on this " + "hardware. Please report a bug.\n", __func__); + return 1; } - return ret; + + return spi_programmer[spi_controller].multicommand(spicommands); } +int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + struct spi_command cmd[] = { + { + .writecnt = writecnt, + .readcnt = readcnt, + .writearr = writearr, + .readarr = readarr, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + return spi_send_multicommand(cmd); +} + +int default_spi_send_multicommand(struct spi_command *spicommands) +{ + int result = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !result) { + result = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return result; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -298,18 +362,18 @@ uint8_t spi_read_status_register(void) { const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; + /* FIXME: No workarounds for driver/hardware bugs in generic code. */ unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ int ret; /* Read Status Register */ - if (spi_controller == SPI_CONTROLLER_SB600) { - /* SB600 uses a different way to read status register. */ + if (spi_controller == SPI_CONTROLLER_SB600) { /* FIXME */ + /* Workaround for SB600 hardware bug. Can be killed later. */ return sb600_read_status_register(); - } else { - ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); - if (ret) - printf_debug("RDSR failed!\n"); } + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) + printf_debug("RDSR failed!\n"); return readarr[0]; } @@ -875,26 +939,13 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - switch (spi_controller) { - case SPI_CONTROLLER_IT87XX: - return it8716f_spi_chip_read(flash, buf, start, len); - case SPI_CONTROLLER_SB600: - return sb600_spi_read(flash, buf, start, len); - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - return ich_spi_read(flash, buf, start, len); - case SPI_CONTROLLER_WBSIO: - return wbsio_spi_read(flash, buf, start, len); - case SPI_CONTROLLER_FT2232: - return ft2232_spi_read(flash, buf, start, len); - default: - printf_debug - ("%s called, but no SPI chipset/strapping detected\n", - __FUNCTION__); + if (!spi_programmer[spi_controller].read) { + fprintf(stderr, "%s called, but SPI read is unsupported on this" + " hardware. Please report a bug.\n", __func__); + return 1; } - return 1; + return spi_programmer[spi_controller].read(flash, buf, start, len); } /* @@ -924,26 +975,13 @@ */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { - switch (spi_controller) { - case SPI_CONTROLLER_IT87XX: - return it8716f_spi_chip_write_256(flash, buf); - case SPI_CONTROLLER_SB600: - return sb600_spi_write_1(flash, buf); - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - return ich_spi_write_256(flash, buf); - case SPI_CONTROLLER_WBSIO: - return wbsio_spi_write_1(flash, buf); - case SPI_CONTROLLER_FT2232: - return ft2232_spi_write_256(flash, buf); - default: - printf_debug - ("%s called, but no SPI chipset/strapping detected\n", - __FUNCTION__); + if (!spi_programmer[spi_controller].write_256) { + fprintf(stderr, "%s called, but SPI page write is unsupported " + " on this hardware. Please report a bug.\n", __func__); + return 1; } - return 1; + return spi_programmer[spi_controller].write_256(flash, buf); } uint32_t spi_get_valid_read_addr(void)

1 0

mailman test 1
by Carl-Daniel Hailfinger 22 Jul '09

22 Jul '09

Test for mailman bug. >From someone This should not end up in a separate mail in the archive, at least that's what I hope.

1 0

[commit] r656 - trunk
by svn＠flashrom.org 21 Jul '09

21 Jul '09

Author: hailfinger Date: 2009-07-21 15:02:59 +0200 (Tue, 21 Jul 2009) New Revision: 656 Added: trunk/serprog-protocol.txt Modified: trunk/serprog.c Log: Support for an external serial flasher protocol. Supports RS-232, USB serial converters (untested) and TCP streams. The protocol specification is in serprog-protocol.txt There will be tweaks to the code and maybe the protocol in the future, so the API is not set in stone yet. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/serprog-protocol.txt =================================================================== --- trunk/serprog-protocol.txt (rev 0) +++ trunk/serprog-protocol.txt 2009-07-21 13:02:59 UTC (rev 656) @@ -0,0 +1,101 @@ +Serial Flasher Protocol Specification - version 1 (0x01 return value == 1) + +Command And Answer Sequence - all commands give an answer. +PC: COMMAND(8bit) <parameters determined by opcode> +DEV: ACK/NAK(8bit) <OPTIONAL RETURN BYTES (only if ACK)> / nothing +Command 0x10 (SYNCNOP) has a special return of NAK+ACK for synchronization. + +ACK = 0x06 +NAK = 0x15 + +All multibyte values are little-endian. Addresses and lengths are 24-bit. + +COMMAND Description Parameters Return Value +0x00 NOP none ACK +0x01 Query programmer iface version none ACK + 16bit version (nonzero) +0x02 Query supported commands bitmap none ACK + 32 bytes (256 bits) of supported cmds flags +0x03 Query programmer name none ACK + 16 bytes string (null padding) / NAK +0x04 Query serial buffer size none ACK + 16bit size / NAK +0x05 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK +0x06 Query connected address lines none ACK + 8bit line count / NAK +0x07 Query operation buffer size none ACK + 16bit size / NAK +0x08 Query write-n maximum data len none ACK + 24bit maximum length / NAK +0x09 Read byte 24-bit addr ACK + BYTE / NAK +0x0A Read n bytes 24-bit addr + 24-bit length ACK + length bytes / NAK +0x0B Initialize operation buffer none ACK / NAK +0x0C Write to opbuf: Write byte 24-bit addr + 8-bit byte ACK / NAK (NOTE: takes 5 bytes in opbuf) +0x0D Write to opbuf: Write n 24-bit length + 24-bit addr + ACK / NAK (NOTE: takes 7+n bytes in opbuf) + + length bytes of data +0x0E Write to opbuf: delay 32-bit usecs ACK / NAK (NOTE: takes 5 bytes in opbuf) +0x0F Execute operation buffer none ACK / NAK +0x10 Sync NOP none NAK + ACK (for synchronization) +0x11 Query maximum read-n length none ACK + 24-bit length (0==2^24) / NAK +0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK +0x?? unimplemented command - invalid. + + +Additional information of the above commands: + About unimplemented commands / startup sequence: + Only commands allowed to be used without checking anything are 0x00,0x10 and 0x01 (NOP,SYNCNOP,Q_IFACE). + If 0x01 doesn't return 1, dont do anything if you dont support a newer protocol. + Then, check support for any other opcode (except 0x02) by using 0x02 (Q_CMDMAP). + 0x02 (Q_CMDMAP): + The map's bits are mapped as follows: + cmd 0 support: byte 0 bit 0 + cmd 1 support: byte 0 bit 1 + cmd 7 support: byte 0 bit 7 + cmd 8 support: byte 1 bit 0, and so on. + 0x04 (Q_SERBUF): + If the programmer has guaranteedly working flow control, + it should return a big bogus value - eg 0xFFFF. + 0x05 (Q_BUSTYPE): + The bit's are defined as follows: + bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported). + 0x06 (Q_CHIPSIZE): + Only applicable to parallel programmers. + An LPC/FHW/SPI-programmer can report this as not supported in the command bitmap. + 0x08 (Q_WRNMAXLEN): + If a programmer reports a bigger maximum write-n length than the serial buffer size, + it is assumed that the programmer can process the data fast enough to take in the + reported maximum write-n without problems. + 0x0F (O_EXEC): + Execute operation buffer will also clear it, regardless of the return value. + 0x11 (Q_RDNMAXLEN): + If this command is not supported, assume return of 0 (2^24). + 0x12 (S_BUSTYPE): + Set's the used bustype if the programmer can support more than one flash protocol. + Sending a byte with more than 1 bit set will make the programmer decide among them + on it's own. Bit values as with Q_BUSTYPE. + About mandatory commands: + The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, + but one can't really do anything with these commands. + Support for the following commands is necessary for flashrom to operate properly: + S_CMD_Q_SERBUF, S_CMD_Q_OPBUF, S_CMD_Q_WRNMAXLEN, S_CMD_R_BYTE, + S_CMD_R_NBYTES, S_CMD_O_INIT, S_CMD_O_WRITEB, S_CMD_O_WRITEN, + S_CMD_O_DELAY, S_CMD_O_EXEC. + In addition, support for these commands is recommended: + S_CMD_Q_PGMNAME, S_CMD_Q_BUSTYPE, S_CMD_Q_CHIPSIZE (if parallel). + + +This define listing should help C coders - (it's here to be the single source for copying - will be a .h someday i think) +#define S_ACK 0x06 +#define S_NAK 0x15 +#define S_CMD_NOP 0x00 /* No operation */ +#define S_CMD_Q_IFACE 0x01 /* Query interface version */ +#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ +#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ +#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ +#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ +#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ +#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum lenght */ +#define S_CMD_R_BYTE 0x09 /* Read a single byte */ +#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ +#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ +#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ +#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ +#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ +#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ +#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ +#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ +#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ Modified: trunk/serprog.c =================================================================== --- trunk/serprog.c 2009-07-21 01:44:45 UTC (rev 655) +++ trunk/serprog.c 2009-07-21 13:02:59 UTC (rev 656) @@ -39,9 +39,747 @@ char *serprog_param = NULL; -#define SERPROG_SUPPORT 0 +#define SERPROG_SUPPORT 1 + #if SERPROG_SUPPORT == 1 + +#define MSGHEADER "serprog:" + +#define S_ACK 0x06 +#define S_NAK 0x15 +#define S_CMD_NOP 0x00 /* No operation */ +#define S_CMD_Q_IFACE 0x01 /* Query interface version */ +#define S_CMD_Q_CMDMAP 0x02 /* Query supported commands bitmap */ +#define S_CMD_Q_PGMNAME 0x03 /* Query programmer name */ +#define S_CMD_Q_SERBUF 0x04 /* Query Serial Buffer Size */ +#define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ +#define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ +#define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum lenght */ +#define S_CMD_R_BYTE 0x09 /* Read a single byte */ +#define S_CMD_R_NBYTES 0x0A /* Read n bytes */ +#define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ +#define S_CMD_O_WRITEB 0x0C /* Write opbuf: Write byte with address */ +#define S_CMD_O_WRITEN 0x0D /* Write to opbuf: Write-N */ +#define S_CMD_O_DELAY 0x0E /* Write opbuf: udelay */ +#define S_CMD_O_EXEC 0x0F /* Execute operation buffer */ +#define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ +#define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ +#define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ + +static int sp_fd; + +static uint16_t sp_device_serbuf_size = 16; +static uint16_t sp_device_opbuf_size = 300; +/* Bitmap of supported commands */ +static uint8_t sp_cmdmap[32]; + +/* sp_prev_was_write used to detect writes with continouous addresses + and combine them to write-n's */ +static int sp_prev_was_write = 0; +/* sp_write_n_addr used as the starting addr of the currently + combined write-n operation */ +static uint32_t sp_write_n_addr; +/* The maximum length of an write_n operation; 0 = write-n not supported */ +static uint32_t sp_max_write_n = 0; +/* The maximum length of a read_n operation; 0 = 2^24 */ +static uint32_t sp_max_read_n = 0; + +/* A malloc'd buffer for combining the operation's data + and a counter that tells how much data is there. */ +static uint8_t *sp_write_n_buf; +static uint32_t sp_write_n_bytes = 0; + +/* sp_streamed_* used for flow control checking */ +static int sp_streamed_transmit_ops = 0; +static int sp_streamed_transmit_bytes = 0; + +/* sp_opbuf_usage used for counting the amount of + on-device operation buffer used */ +static int sp_opbuf_usage = 0; +/* if true causes sp_docommand to automatically check + whether the command is supported before doing it */ +static int sp_check_avail_automatic = 0; + +static void sp_die(char *msg) +{ + perror(msg); + exit(1); +} + +static int sp_opensocket(char *ip, unsigned int port) +{ + int flag = 1; + struct hostent *hostPtr = NULL; + struct sockaddr_in sp; + int sock; + printf_debug(MSGHEADER "IP %s port %d\n", ip, port); + sock = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP); + if (sock < 0) + sp_die("Error: serprog cannot open socket"); + hostPtr = gethostbyname(ip); + if (NULL == hostPtr) { + hostPtr = gethostbyaddr(ip, strlen(ip), AF_INET); + if (NULL == hostPtr) + sp_die("Error: cannot resolve"); + } + memset(&sp, 0, sizeof(sp)); + sp.sin_family = AF_INET; + sp.sin_port = htons(port); + (void)memcpy(&sp.sin_addr, hostPtr->h_addr, hostPtr->h_length); + if (connect(sock, (struct sockaddr *)&sp, sizeof(sp)) < 0) { + close(sock); + sp_die("Error: serprog cannot connect"); + } + /* We are latency limited, and sometimes do write-write-read * + * (write-n) - so enable TCP_NODELAY. */ + setsockopt(sock, IPPROTO_TCP, TCP_NODELAY, &flag, sizeof(int)); + return sock; +} + +struct baudentry { + int flag; + unsigned int baud; +}; + +/* I'd like if the C preprocessor could have directives in macros */ +#define BAUDENTRY(baud) { B##baud, baud }, +static const struct baudentry sp_baudtable[] = { + BAUDENTRY(9600) + BAUDENTRY(19200) + BAUDENTRY(38400) + BAUDENTRY(57600) + BAUDENTRY(115200) +#ifdef B230400 + BAUDENTRY(230400) +#endif +#ifdef B460800 + BAUDENTRY(460800) +#endif +#ifdef B500000 + BAUDENTRY(500000) +#endif +#ifdef B576000 + BAUDENTRY(576000) +#endif +#ifdef B921600 + BAUDENTRY(921600) +#endif +#ifdef B1000000 + BAUDENTRY(1000000) +#endif +#ifdef B1152000 + BAUDENTRY(1152000) +#endif +#ifdef B1500000 + BAUDENTRY(1500000) +#endif +#ifdef B2000000 + BAUDENTRY(2000000) +#endif +#ifdef B2500000 + BAUDENTRY(2500000) +#endif +#ifdef B3000000 + BAUDENTRY(3000000) +#endif +#ifdef B3500000 + BAUDENTRY(3500000) +#endif +#ifdef B4000000 + BAUDENTRY(4000000) +#endif + {0, 0} /* Terminator */ +}; + +static int sp_openserport(char *dev, unsigned int baud) +{ + struct termios options; + int fd, i; + fd = open(dev, O_RDWR | O_NOCTTY | O_NDELAY); + if (fd < 0) + sp_die("Error: cannot open serial port"); + fcntl(fd, F_SETFL, 0); + tcgetattr(fd, &options); + for (i = 0;; i++) { + if (sp_baudtable[i].baud == 0) { + close(fd); + fprintf(stderr, + "Error: cannot configure for baudrate %d\n", + baud); + exit(1); + } + if (sp_baudtable[i].baud == baud) { + cfsetispeed(&options, sp_baudtable[i].flag); + cfsetospeed(&options, sp_baudtable[i].flag); + break; + } + } + options.c_cflag &= ~PARENB; + options.c_cflag &= ~CSTOPB; + options.c_cflag &= ~CSIZE; + options.c_cflag |= CS8; + options.c_cflag &= ~CRTSCTS; + options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG); + options.c_iflag &= ~(IXON | IXOFF | IXANY | ICRNL | IGNCR | INLCR); + options.c_oflag &= ~OPOST; + options.c_cflag |= (CLOCAL | CREAD); + tcsetattr(fd, TCSANOW, &options); + return fd; +} + +static void sp_flush_incoming(void) +{ + int i; + for (i=0;i<100;i++) { /* In case the device doesnt do EAGAIN, just read 0 */ + unsigned char flush[16]; + ssize_t rv; + rv = read(sp_fd, flush, sizeof(flush)); + if ((rv == -1) && (errno == EAGAIN)) + break; + if (rv == -1) + sp_die("flush read"); + } + return; +} + +static int sp_sync_read_timeout(int loops) +{ + int i; + unsigned char c; + for (i = 0; i < loops; i++) { + ssize_t rv; + rv = read(sp_fd, &c, 1); + if (rv == 1) + return c; + if ((rv == -1) && (errno != EAGAIN)) + sp_die("read"); + usleep(10 * 1000); /* 10ms units */ + } + return -1; +} + +/* Synchronize: a bit tricky algorhytm that tries to (and in my tests has * + * always succeeded in) bring the serial protocol to known waiting-for- * + * command state - uses nonblocking read - rest of the driver uses * + * blocking read - TODO: add an alarm() timer for the rest of the app on * + * serial operations, though not such a big issue as the first thing to * + * do is synchronize (eg. check that device is alive). */ +static void sp_synchronize(void) +{ + int i; + int flags = fcntl(sp_fd, F_GETFL); + unsigned char buf[8]; + flags |= O_NONBLOCK; + fcntl(sp_fd, F_SETFL, flags); + /* First sends 8 NOPs, then flushes the return data - should cause * + * the device serial parser to get to a sane state, unless if it * + * is waiting for a real long write-n. */ + memset(buf, S_CMD_NOP, 8); + if (write(sp_fd, buf, 8) != 8) + sp_die("flush write"); + /* A second should be enough to get all the answers to the buffer */ + usleep(1000 * 1000); + sp_flush_incoming(); + + /* Then try upto 8 times to send syncnop and get the correct special * + * return of NAK+ACK. Timing note: upto 10 characters, 10*50ms = * + * upto 500ms per try, 8*0.5s = 4s; +1s (above) = upto 5s sync * + * attempt, ~1s if immediate success. */ + for (i = 0; i < 8; i++) { + int n; + unsigned char c = S_CMD_SYNCNOP; + if (write(sp_fd, &c, 1) != 1) + sp_die("sync write"); + printf_debug("."); + fflush(stdout); + for (n = 0; n < 10; n++) { + c = sp_sync_read_timeout(5); /* wait upto 50ms */ + if (c != S_NAK) + continue; + c = sp_sync_read_timeout(2); + if (c != S_ACK) + continue; + c = S_CMD_SYNCNOP; + if (write(sp_fd, &c, 1) != 1) + sp_die("sync write"); + c = sp_sync_read_timeout(50); + if (c != S_NAK) + break; /* fail */ + c = sp_sync_read_timeout(10); + if (c != S_ACK) + break; /* fail */ + /* Ok, synchronized; back to blocking reads and return. */ + flags &= ~O_NONBLOCK; + fcntl(sp_fd, F_SETFL, flags); + printf_debug("\n"); + return; + } + } + fprintf(stderr, + "Error: cannot synchronize protocol\n" + "- check communications and reset device?\n"); + exit(1); +} + +static int sp_check_commandavail(uint8_t command) +{ + int byteoffs, bitoffs; + byteoffs = command / 8; + bitoffs = command % 8; + return (sp_cmdmap[byteoffs] & (1 << bitoffs)) ? 1 : 0; +} + +static int sp_automatic_cmdcheck(uint8_t cmd) +{ + if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { + printf_debug ("Warning: Automatic command availability check" + " failed for cmd %d - wont execute cmd\n",cmd); + return 1; + } + return 0; +} + +static int sp_docommand(uint8_t command, uint32_t parmlen, + uint8_t * params, uint32_t retlen, void *retparms) +{ + unsigned char *sendpacket; + unsigned char c; + if (sp_automatic_cmdcheck(command)) + return 1; + sendpacket = malloc(1 + parmlen); + if (!sendpacket) + sp_die("Error: cannot malloc command buffer"); + sendpacket[0] = command; + memcpy(&(sendpacket[1]), params, parmlen); + if (write(sp_fd, sendpacket, 1 + parmlen) != (1 + parmlen)) { + sp_die("Error: cannot write command"); + } + free(sendpacket); + if (read(sp_fd, &c, 1) != 1) + sp_die("Error: cannot read from device"); + if (c == S_NAK) return 1; + if (c != S_ACK) { + fprintf(stderr, + "Error: invalid response 0x%02X from device\n",c); + exit(1); + } + if (retlen) { + int rd_bytes = 0; + do { + int r; + r = read(sp_fd, retparms + rd_bytes, + retlen - rd_bytes); + if (r <= 0) sp_die + ("Error: cannot read return parameters"); + rd_bytes += r; + } while (rd_bytes != retlen); + } + return 0; +} + +static void sp_flush_stream(void) +{ + if (sp_streamed_transmit_ops) + do { + unsigned char c; + if (read(sp_fd, &c, 1) != 1) { + sp_die + ("Error: cannot read from device (flushing stream)"); + } + if (c == S_NAK) { + fprintf(stderr, + "Error: NAK to a stream buffer operation\n"); + exit(1); + } + if (c != S_ACK) { + fprintf(stderr, + "Error: Invalid reply 0x%02X from device\n", + c); + exit(1); + } + } while (--sp_streamed_transmit_ops); + sp_streamed_transmit_ops = 0; + sp_streamed_transmit_bytes = 0; +} + +static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms) +{ + uint8_t *sp; + if (sp_automatic_cmdcheck(cmd)) + return 1; + sp = malloc(1 + parmlen); + if (!sp) sp_die("Error: cannot malloc command buffer"); + sp[0] = cmd; + memcpy(&(sp[1]), parms, parmlen); + if (sp_streamed_transmit_bytes >= (1 + parmlen + sp_device_serbuf_size)) + sp_flush_stream(); + if (write(sp_fd, sp, 1 + parmlen) != (1 + parmlen)) + sp_die("Error: cannot write command"); + free(sp); + sp_streamed_transmit_ops += 1; + sp_streamed_transmit_bytes += 1 + parmlen; + return 0; +} + +int serprog_init(void) +{ + uint16_t iface; + int len; + unsigned char pgmname[17]; + unsigned char rbuf[3]; + unsigned char c; + char *num; + char *dev; + printf_debug("%s\n", __func__); + /* the parameter is either of format "/dev/device:baud" or "ip:port" */ + if ((!serprog_param) || (!strlen(serprog_param))) { + nodevice: + fprintf(stderr, + "Error: No device/host given for the serial programmer driver.\n" + "Use flashrom -p serprog=/dev/device:baud or flashrom -p serprog=ip:port\n"); + exit(1); + } + num = strstr(serprog_param, ":"); + len = num - serprog_param; + if (!len) goto nodevice; + if (!num) { + fprintf(stderr, + "Error: No port or baudrate specified to serial programmer driver.\n" + "Use flashrom -p serprog=/dev/device:baud or flashrom -p serprog=ip:port\n"); + exit(1); + } + len = num - serprog_param; + dev = malloc(len + 1); + if (!dev) sp_die("Error: memory allocation failure"); + memcpy(dev, serprog_param, len); + dev[len] = 0; + num = strdup(num + 1); + if (!num) sp_die("Error: memory allocation failure"); + free(serprog_param); + serprog_param = NULL; + + if (dev[0] == '/') sp_fd = sp_openserport(dev, atoi(num)); + else sp_fd = sp_opensocket(dev, atoi(num)); + + free(dev); dev = NULL; + free(num); num = NULL; + + printf_debug(MSGHEADER "connected - attempting to synchronize\n"); + + sp_check_avail_automatic = 0; + + sp_synchronize(); + + printf_debug(MSGHEADER "Synchronized\n"); + + if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { + fprintf(stderr, "Error: NAK to Query Interface version\n"); + exit(1); + } + + if (iface != 1) { + fprintf(stderr, "Error: Unknown interface version %d\n", iface); + exit(1); + } + + printf_debug(MSGHEADER "Interface version ok.\n"); + + if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { + fprintf(stderr, "Error: query command map not supported\n"); + exit(1); + } + + sp_check_avail_automatic = 1; + + /* Check for the minimum operational set of commands */ + if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { + fprintf(stderr, "Error: Single byte read not supported\n"); + exit(1); + } + /* This could be translated to single byte reads (if missing), * + * but now we dont support that. */ + if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { + fprintf(stderr, "Error: Read n bytes not supported\n"); + exit(1); + } + /* In the future one could switch to read-only mode if these * + * are not available. */ + if (sp_check_commandavail(S_CMD_O_INIT) == 0) { + fprintf(stderr, + "Error: Initialize operation buffer not supported\n"); + exit(1); + } + if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { + fprintf(stderr, + "Error: Write to opbuf: write byte not supported\n"); + exit(1); + } + if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { + fprintf(stderr, "Error: Write to opbuf: delay not supported\n"); + exit(1); + } + if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { + fprintf(stderr, + "Error: Execute operation buffer not supported\n"); + exit(1); + } + + if (sp_docommand(S_CMD_Q_PGMNAME, 0, NULL, 16, pgmname)) { + fprintf(stderr, "Warning: NAK to query programmer name\n"); + strcpy((char *)pgmname, "(unknown)"); + } + pgmname[16] = 0; + printf(MSGHEADER "Programmer name \"%s\"\n", pgmname); + + if (sp_docommand(S_CMD_Q_SERBUF, 0, NULL, 2, &sp_device_serbuf_size)) { + fprintf(stderr, "Warning: NAK to query serial buffer size\n"); + } + printf_debug(MSGHEADER "serial buffer size %d\n", + sp_device_serbuf_size); + + if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, &sp_device_opbuf_size)) { + fprintf(stderr, + "Warning: NAK to query operation buffer size\n"); + } + printf_debug(MSGHEADER "operation buffer size %d\n", + sp_device_opbuf_size); + + if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { + fprintf(stderr, "Warning: NAK to query supported buses\n"); + c = CHIP_BUSTYPE_NONSPI; /* A reasonable default for now. */ + } + buses_supported = c; + + if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { + fprintf(stderr, "Error: NAK to initialize operation buffer\n"); + exit(1); + } + + if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { + printf_debug(MSGHEADER "Write-n not supported"); + sp_max_write_n = 0; + } else { + sp_max_write_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_write_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_write_n |= ((unsigned int)(rbuf[2]) << 16); + printf_debug(MSGHEADER "Maximum write-n length %d\n", + sp_max_write_n); + sp_write_n_buf = malloc(sp_max_write_n); + if (!sp_write_n_buf) { + fprintf(stderr, + "Error: cannot allocate memory for Write-n buffer\n"); + exit(1); + } + sp_write_n_bytes = 0; + } + + if ((sp_check_commandavail(S_CMD_Q_RDNMAXLEN)) + &&((sp_docommand(S_CMD_Q_RDNMAXLEN,0,NULL, 3, rbuf) == 0))) { + sp_max_read_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_read_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_read_n |= ((unsigned int)(rbuf[2]) << 16); + printf_debug(MSGHEADER "Maximum read-n length %d\n", + sp_max_read_n ? sp_max_read_n : (1<<24)); + } else { + printf_debug(MSGHEADER "Maximum read-n length not reported\n"); + sp_max_read_n = 0; + } + + sp_prev_was_write = 0; + sp_streamed_transmit_ops = 0; + sp_streamed_transmit_bytes = 0; + sp_opbuf_usage = 0; + return 0; +} + +/* Move an in flashrom buffer existing write-n operation to * + * the on-device operation buffer. */ +static void sp_pass_writen(void) +{ + unsigned char header[7]; + printf_debug(MSGHEADER "Passing write-n bytes=%d addr=0x%x\n", + sp_write_n_bytes, sp_write_n_addr); + if (sp_streamed_transmit_bytes >= + (7 + sp_write_n_bytes + sp_device_serbuf_size)) + sp_flush_stream(); + /* In case it's just a single byte send it as a single write. */ + if (sp_write_n_bytes == 1) { + sp_write_n_bytes = 0; + header[0] = (sp_write_n_addr >> 0) & 0xFF; + header[1] = (sp_write_n_addr >> 8) & 0xFF; + header[2] = (sp_write_n_addr >> 16) & 0xFF; + header[3] = sp_write_n_buf[0]; + sp_stream_buffer_op(S_CMD_O_WRITEB, 4, header); + sp_opbuf_usage += 5; + return; + } + header[0] = S_CMD_O_WRITEN; + header[1] = (sp_write_n_bytes >> 0) & 0xFF; + header[2] = (sp_write_n_bytes >> 8) & 0xFF; + header[3] = (sp_write_n_bytes >> 16) & 0xFF; + header[4] = (sp_write_n_addr >> 0) & 0xFF; + header[5] = (sp_write_n_addr >> 8) & 0xFF; + header[6] = (sp_write_n_addr >> 16) & 0xFF; + if (write(sp_fd, header, 7) != 7) + sp_die("Error: cannot write write-n command\n"); + if (write(sp_fd, sp_write_n_buf, sp_write_n_bytes) != + sp_write_n_bytes) + sp_die("Error: cannot write write-n data"); + sp_streamed_transmit_bytes += 7 + sp_write_n_bytes; + sp_streamed_transmit_ops += 1; + sp_opbuf_usage += 7 + sp_write_n_bytes; + sp_write_n_bytes = 0; + sp_prev_was_write = 0; +} + +static void sp_execute_opbuf_noflush(void) +{ + if ((sp_max_write_n) && (sp_write_n_bytes)) + sp_pass_writen(); + sp_stream_buffer_op(S_CMD_O_EXEC, 0, 0); + printf_debug(MSGHEADER "Executed operation buffer of %d bytes\n", + sp_opbuf_usage); + sp_opbuf_usage = 0; + sp_prev_was_write = 0; + return; +} + +static void sp_execute_opbuf(void) +{ + sp_execute_opbuf_noflush(); + sp_flush_stream(); +} + +int serprog_shutdown(void) +{ + printf_debug("%s\n", __func__); + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) + sp_execute_opbuf(); + close(sp_fd); + if (sp_max_write_n) + free(sp_write_n_buf); + return 0; +} + +static void sp_check_opbuf_usage(int bytes_to_be_added) +{ + if (sp_device_opbuf_size <= (sp_opbuf_usage + bytes_to_be_added)) { + sp_execute_opbuf(); + /* If this happens in the mid of an page load the page load * + * will propably fail. */ + printf_debug(MSGHEADER + "Warning: executed operation buffer due to size reasons\n"); + } +} + +void serprog_chip_writeb(uint8_t val, chipaddr addr) +{ + printf_debug("%s\n", __func__); + if (sp_max_write_n) { + if ((sp_prev_was_write) + && (addr == (sp_write_n_addr + sp_write_n_bytes))) { + sp_write_n_buf[sp_write_n_bytes++] = val; + } else { + if ((sp_prev_was_write) && (sp_write_n_bytes)) + sp_pass_writen(); + sp_prev_was_write = 1; + sp_write_n_addr = addr; + sp_write_n_bytes = 1; + sp_write_n_buf[0] = val; + } + sp_check_opbuf_usage(7 + sp_write_n_bytes); + if (sp_write_n_bytes >= sp_max_write_n) + sp_pass_writen(); + } else { + /* We will have to do single writeb ops. */ + unsigned char writeb_parm[4]; + sp_check_opbuf_usage(6); + writeb_parm[0] = (addr >> 0) & 0xFF; + writeb_parm[1] = (addr >> 8) & 0xFF; + writeb_parm[2] = (addr >> 16) & 0xFF; + writeb_parm[3] = val; + sp_stream_buffer_op(S_CMD_O_WRITEB, 4, writeb_parm); + sp_opbuf_usage += 5; + } +} + +uint8_t serprog_chip_readb(const chipaddr addr) +{ + unsigned char c; + unsigned char buf[3]; + /* Will stream the read operation - eg. add it to the stream buffer, * + * then flush the buffer, then read the read answer. */ + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) + sp_execute_opbuf_noflush(); + buf[0] = ((addr >> 0) & 0xFF); + buf[1] = ((addr >> 8) & 0xFF); + buf[2] = ((addr >> 16) & 0xFF); + sp_stream_buffer_op(S_CMD_R_BYTE, 3, buf); + sp_flush_stream(); + if (read(sp_fd, &c, 1) != 1) + sp_die("readb byteread"); + printf_debug("%s addr=0x%lx returning 0x%02X\n", __func__, addr, c); + return c; +} + +/* Local version that really does the job, doesnt care of max_read_n. */ +static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) +{ + int rd_bytes = 0; + unsigned char sbuf[6]; + printf_debug("%s: addr=0x%lx len=%lu\n", __func__, addr, (unsigned long)len); + /* Stream the read-n -- as above. */ + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) + sp_execute_opbuf_noflush(); + sbuf[0] = ((addr >> 0) & 0xFF); + sbuf[1] = ((addr >> 8) & 0xFF); + sbuf[2] = ((addr >> 16) & 0xFF); + sbuf[3] = ((len >> 0) & 0xFF); + sbuf[4] = ((len >> 8) & 0xFF); + sbuf[5] = ((len >> 16) & 0xFF); + sp_stream_buffer_op(S_CMD_R_NBYTES, 6, sbuf); + sp_flush_stream(); + do { + int r = read(sp_fd, buf + rd_bytes, len - rd_bytes); + if (r <= 0) + sp_die("Error: cannot read read-n data"); + rd_bytes += r; + } while (rd_bytes != len); + return; +} + +/* The externally called version that makes sure that max_read_n is obeyed. */ +void serprog_chip_readn(uint8_t * buf, const chipaddr addr, size_t len) +{ + size_t lenm = len; + chipaddr addrm = addr; + while ((sp_max_read_n)&&(lenm > sp_max_read_n)) { + sp_do_read_n(&(buf[addrm-addr]),addrm,sp_max_read_n); + addrm += sp_max_read_n; + lenm -= sp_max_read_n; + } + if (lenm) sp_do_read_n(&(buf[addrm-addr]),addrm,lenm); +} + +void serprog_delay(int delay) +{ + unsigned char buf[4]; + printf_debug("%s\n", __func__); + if ((sp_max_write_n) && (sp_write_n_bytes)) + sp_pass_writen(); + sp_check_opbuf_usage(5); + buf[0] = ((delay >> 0) & 0xFF); + buf[1] = ((delay >> 8) & 0xFF); + buf[2] = ((delay >> 16) & 0xFF); + buf[3] = ((delay >> 24) & 0xFF); + sp_stream_buffer_op(S_CMD_O_DELAY, 4, buf); + sp_opbuf_usage += 5; + sp_prev_was_write = 0; +} + #else + int serprog_init(void) { fprintf(stderr, "Serial programmer support was not compiled in\n");

1 0

motherboard results
by scott＠gnuveau.net 21 Jul '09

21 Jul '09

Hi Carldani, first board... a-open vKM400 AM-S: Calibrating delay loop... 746M loops per second. OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A25L40P, 512 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A49LF040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for AMIC Technology A29040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x3a, id2 0x5a Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI chipset detected Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x21, id2 0x31, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x75, id2 0x1 Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset detected Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset detected Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset detected Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset detected Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset detected Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset detected Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset detected Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI chipset detected Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x49, id2 0x4d Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x3a, id2 0x5a, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0x49, did 0x4d Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI chipset detected No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ------------------------------lspci output------------------------------ 00:00.0 Host bridge [0600]: VIA Technologies, Inc. VT8378 [KM400/A] Chipset Host Bridge [1106:3205] Subsystem: VIA Technologies, Inc. VT8378 [KM400/A] Chipset Host Bridge [1106:3205] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 8 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] Capabilities: [80] AGP version 3.5 Status: RQ=32 Iso- ArqSz=0 Cal=2 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3+ Rate=x4,x8 Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x8 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: agpgart-via Kernel modules: via-agp 00: 06 11 05 32 06 00 30 22 00 00 00 06 00 08 00 00 10: 08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 05 32 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 00 19 88 80 82 44 01 00 1b b9 88 80 82 44 00 00 50: 08 80 00 ca c0 85 40 40 e0 00 40 40 40 40 40 40 60: 82 aa 0a 20 ec 99 c0 13 47 2d 54 d0 b1 40 00 00 70: 02 c8 ee 01 21 0f 50 08 01 00 00 00 00 00 00 02 80: 02 c0 35 00 0b 0a 00 1f 02 03 00 00 00 00 00 00 90: 80 01 00 00 20 0f 01 00 00 00 9a 37 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 21 98 00 48 b0: 7f 00 31 00 25 46 46 02 69 84 6a 01 f0 81 2d 08 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 17 a3 6b ea 07 1c f1 19 72 ff 00 00 61 72 74 01 e0: 00 00 00 00 80 ff 01 00 a6 87 ee 00 00 96 33 40 f0: 00 01 00 a0 84 00 84 00 0f 62 20 08 00 04 00 00 00:01.0 PCI bridge [0604]: VIA Technologies, Inc. VT8237/VX700 PCI Bridge [1106:b198] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: e8000000-e80fffff Prefetchable memory behind bridge: d8000000-e7ffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: shpchp 00: 06 11 98 b1 07 01 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 d0 d0 20 22 20: 00 e8 00 e8 00 d8 f0 e7 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 08 00 40: 01 c0 88 44 34 72 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 Network controller [0280]: Intersil Corporation Prism 2.5 Wavelan chipset [1260:3873] (rev 01) Subsystem: Belkin Device [1799:0601] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at e8100000 (32-bit, prefetchable) [size=4K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: hostap_pci Kernel modules: orinoco_pci, hostap_pci 00: 60 12 73 38 07 00 90 02 01 00 80 02 08 20 00 00 10: 08 00 10 e8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 99 17 01 06 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 00 00 40: 80 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 7e e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) Subsystem: AOPEN Inc. Device [a0a0:0477] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at e000 [size=256] Region 1: Memory at e8101000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too Kernel modules: 8139cp, 8139too 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 e0 00 00 00 10 10 e8 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 a0 a0 77 04 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 RAID bus controller [0104]: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller [1106:3149] (rev 80) Subsystem: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller [1106:3149] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin B routed to IRQ 20 Region 0: I/O ports at e100 [size=8] Region 1: I/O ports at e200 [size=4] Region 2: I/O ports at e300 [size=8] Region 3: I/O ports at e400 [size=4] Region 4: I/O ports at e500 [size=16] Region 5: I/O ports at e600 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_via Kernel modules: sata_via 00: 06 11 49 31 07 00 90 02 80 00 04 01 00 20 80 00 10: 01 e1 00 00 01 e2 00 00 01 e3 00 00 01 e4 00 00 20: 01 e5 00 00 01 e6 00 00 00 00 00 00 06 11 49 31 30: 00 00 00 00 c0 00 00 00 00 00 00 00 0b 02 00 00 40: 33 03 f1 44 06 af 00 00 10 82 05 03 00 00 00 00 50: 00 00 00 00 00 00 04 04 00 10 10 00 05 00 10 00 60: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 e0 82 37 00 10 85 37 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 80 02 49 31 06 11 49 31 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.1 IDE interface [0101]: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE [1106:0571] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 20 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at e700 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: VIA_IDE Kernel modules: via82cxxx 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e7 00 00 00 00 00 00 00 00 00 00 06 11 71 05 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 01 00 00 40: 3b 02 09 05 18 8c c0 00 5d 5d 5d 20 ff 00 b6 20 50: 17 17 17 e1 0c 00 00 00 a8 a8 a8 a8 00 00 00 00 60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 70: 02 01 00 00 00 00 00 00 82 01 00 00 00 00 00 00 80: 00 30 83 37 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 06 00 71 05 06 11 71 05 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00:10.0 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 21 Region 4: I/O ports at e800 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 07 00 10 02 81 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 01 00 00 40: 40 10 03 00 00 00 00 00 00 0b a0 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.1 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 21 Region 4: I/O ports at e900 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 07 00 10 02 81 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e9 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 01 00 00 40: 40 10 03 00 00 00 00 00 00 0b a0 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.2 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at ea00 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 07 00 10 02 81 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ea 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 40: 40 10 03 00 00 00 00 00 00 0b a0 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.3 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 81) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at eb00 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 07 00 10 02 81 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 eb 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 40: 40 12 03 00 00 00 00 00 00 0b a0 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.4 USB Controller [0c03]: VIA Technologies, Inc. USB 2.0 [1106:3104] (rev 86) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 [1106:3104] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin C routed to IRQ 21 Region 0: Memory at e8102000 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00: 06 11 04 31 17 00 10 02 86 20 03 0c 10 20 80 00 10: 00 20 10 e8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31 30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 03 00 00 40: 00 00 03 00 00 00 00 00 a8 20 00 09 00 00 00 00 50: 00 5a 00 80 00 00 00 00 04 0b 88 88 03 88 88 00 60: 20 20 01 00 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 80 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 88 00 00 00 00 00 00 00 00 00 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] [1106:3227] Subsystem: VIA Technologies, Inc. DFI KT600-AL / Soltek SL-B9D-FGR Motherboard [1106:3227] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: i2c-viapro 00: 06 11 27 32 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 27 32 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 54 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 08 08 50: 80 89 09 00 00 00 00 00 42 80 00 09 00 00 00 00 60: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 70: 06 11 27 32 00 00 00 00 00 00 00 00 20 00 00 00 80: 20 84 59 00 fa 10 00 00 01 40 00 00 00 00 00 00 90: 00 84 d8 88 b0 40 0e 00 00 07 25 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 50 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00:11.5 Multimedia audio controller [0401]: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] (rev 60) Subsystem: Avance Logic Inc. Device [4005:4720] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 22 Region 0: I/O ports at ec00 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: VIA 82xx Audio Kernel modules: snd-via82xx 00: 06 11 59 30 01 00 10 02 60 00 01 04 00 00 00 00 10: 01 ec 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 05 40 20 47 30: 00 00 00 00 c0 00 00 00 00 00 00 00 0a 03 00 00 40: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV280 [Radeon 9200 PRO] [1002:5960] (rev 01) (prog-if 00 [VGA controller]) Subsystem: ATI Technologies Inc Device [1002:2002] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (2000ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at d8000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at d000 [size=256] Region 2: Memory at e8030000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at e8000000 [disabled] [size=128K] Capabilities: [58] AGP version 3.0 Status: RQ=256 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3+ Rate=x4,x8 Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x8 Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: radeonfb 00: 02 10 60 59 07 00 b0 02 01 00 00 03 08 20 80 00 10: 08 00 00 d8 01 d0 00 00 00 00 03 e8 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 02 20 30: 00 00 00 00 58 00 00 00 00 00 00 00 0c 01 08 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 02 20 50: 01 00 02 06 00 00 00 00 02 50 30 00 1b 02 00 ff 60: 02 03 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.1 Display controller [0380]: ATI Technologies Inc RV280 [Radeon 9200 PRO] (Secondary) [1002:5940] (rev 01) Subsystem: ATI Technologies Inc Device [1002:2003] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: Memory at e0000000 (32-bit, prefetchable) [disabled] [size=128M] Region 1: Memory at e8020000 (32-bit, non-prefetchable) [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 40 59 00 00 b0 02 01 00 80 03 08 20 00 00 10: 08 00 00 e0 00 00 02 e8 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 03 20 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 02 06 00 00 00 00 02 50 30 00 1b 02 00 ff 60: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -------------------------------second board--------------------------------- msi ms-6570 coming in next mail.

2 9

[commit] r655 - trunk
by svn＠flashrom.org 21 Jul '09

21 Jul '09

Author: libv Date: 2009-07-21 03:44:45 +0200 (Tue, 21 Jul 2009) New Revision: 655 Modified: trunk/board_enable.c Log: Board enable for Aopen VKM400 AM-S. This board is a VIA KM400 and VT8237 and IT8705F superio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Scott Johnson <scott(a)gnuveau.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-20 15:21:18 UTC (rev 654) +++ trunk/board_enable.c 2009-07-21 01:44:45 UTC (rev 655) @@ -636,10 +636,10 @@ /** * Suited for: - * - Biostar P4M80-M4: Intel P4 + VIA P4M800 + VT8237 - * - GIGABYTE GA-7VT600: AMD K7 + VIA KT600 + VT8237 + * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF + * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 */ -static int board_biostar_p4m80_m4(const char *name) +static int it8705_rom_write_enable(const char *name) { /* enter IT87xx conf mode */ enter_conf_mode_ite(0x2e); @@ -659,6 +659,24 @@ } /** + * Suited for A-Open vKM400 AM-S: VIA KM400 + VT8237 + IT8705F. + */ +static int board_aopen_vkm400(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); + return -1; + } + + vt823x_set_all_writes_to_lpc(dev); + + return it8705_rom_write_enable(name); +} + +/** * Winbond W83697HF Super I/O + VIA VT8235 southbridge * * Suited for: @@ -896,18 +914,19 @@ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400 AM-s", board_aopen_vkm400}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", board_biostar_p4m80_m4}, + {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, + {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},

1 0

[commit] r654 - trunk
by svn＠flashrom.org 20 Jul '09

20 Jul '09

Author: hailfinger Date: 2009-07-20 17:21:18 +0200 (Mon, 20 Jul 2009) New Revision: 654 Modified: trunk/sst49lfxxxc.c Log: Reset SST49LF016C after erase to exit the read status register mode. Without this, all reads after erase will return 0x80 instead of the real memory contents. Thanks to Michael Melcher for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Michael Melcher <Michael.Melcher82(a)googlemail.com> Modified: trunk/sst49lfxxxc.c =================================================================== --- trunk/sst49lfxxxc.c 2009-07-14 10:26:56 UTC (rev 653) +++ trunk/sst49lfxxxc.c 2009-07-20 15:21:18 UTC (rev 654) @@ -91,6 +91,7 @@ return (-1); } } while (!(status & STATUS_WSMS)); + chip_writeb(RESET, bios); if (check_erased_range(flash, address, sector_size)) { fprintf(stderr, "ERASE FAILED!\n");

1 0

Re: [flashrom] [PATCH] Reset SST49LF016C after erase
by Michael Melcher 20 Jul '09

20 Jul '09

On Mon, Jul 20, 2009 at 04:57:56PM +0200, Carl-Daniel Hailfinger wrote: > Reset SST49LF016C after erase to exit the read status register mode. > Without this, all reads after erase will return 0x80 instead of the real > memory contents. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested and verified. Acked-by Michael Melcher <Michael.Melcher82(a)googlemail.com>

1 0

Info for supermicro x7dw-n
by Michael Melcher 20 Jul '09

20 Jul '09

# ../flashrom/flashrom -w real.rom flashrom v0.9.0-r653 No coreboot table found. Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address 0xffe00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: ERASE FAILED at 0x00000000! Expected=0xff, Read=0x80 ERASE FAILED! ERASE FAILED! Verifying flash... VERIFY FAILED at 0x00000000! Expected=0xf8, Read=0x80

3 2

Re: [flashrom] bad flash ?
by Luc Verhaegen 17 Jul '09

17 Jul '09

On Fri, Jul 17, 2009 at 11:08:18PM +0200, Benjamin BELLEC wrote: > OK, it's now good, I have dl and install from the svn (flashrom > v0.9.0-r653) and it's works fine ! (Previously I used the Fedora > packages, I don't know which svn revision it was). > I'm now using the F8 BIOS ! > You can add this motherboard at the "approved" list. > > Thank you for your help. Great, Luc Verhaegen.

1 0

IBM T30: UNTESTED though READ seems to work.
by Chet Johnson 17 Jul '09

17 Jul '09

I'm going to be slow about this as I don't want to brick my very useful notebook, but the bios read seemed to work successfully. Here is the output from the read operation. This is an old IBM T30 and it pretty much does everything I need as it stands. It does need an upgraded bios to accommodate some updated wifi features. I'm really concerned about performing the write operation. <------------> #sudo flashrom -r original.rom [sudo] password for <name> Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH3-M", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading flash... done. <-------------> This created the following file -rw-r--r-- 1 root root 1048576 2009-07-16 12:52 original.rom More when I ramp up my bravery (foolishness). Chet

2 1

[RFC] More debugging for SB600/SB700 SPI
by Carl-Daniel Hailfinger 17 Jul '09

17 Jul '09

More debugging for SB600/SB700 SPI. Some of this should be conditional on SB700. Anyway, it should be harmless on SB600. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_sb600_sb700_debug/chipset_enable.c =================================================================== --- flashrom-spi_sb600_sb700_debug/chipset_enable.c (Revision 645) +++ flashrom-spi_sb600_sb700_debug/chipset_enable.c (Arbeitskopie) @@ -692,7 +692,9 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); - tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, AbortEnable=%i\n", + tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ @@ -704,6 +706,13 @@ /* The low bits of the SPI base address are used as offset into the mapped page */ sb600_spibar += tmp & 0xfff; + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); Index: flashrom-spi_sb600_sb700_debug/sb600spi.c =================================================================== --- flashrom-spi_sb600_sb700_debug/sb600spi.c (Revision 645) +++ flashrom-spi_sb600_sb700_debug/sb600spi.c (Arbeitskopie) @@ -117,13 +117,13 @@ if (readcnt > 8) { printf("%s, SB600 SPI controller can not receive %d bytes, " - "which is limited with 8 bytes\n", __func__, readcnt); + "it is limited to 8 bytes\n", __func__, readcnt); return 1; } if (writecnt > 8) { - printf("%s, SB600 SPI controller can not sent %d bytes, " - "which is limited with 8 bytes\n", __func__, writecnt); + printf("%s, SB600 SPI controller can not send %d bytes, " + "it is limited to 8 bytes\n", __func__, writecnt); return 1; } @@ -136,6 +136,7 @@ /* Send the write byte to FIFO. */ for (count = 0; count < writecnt; count++, writearr++) { printf_debug(" [%x]", *writearr); + /* FIXME: Can we rely on auto-posting these writes or do we have to issue a read afterwards? */ mmio_writeb(*writearr, sb600_spibar + 0xC); } printf_debug("\n"); @@ -153,19 +154,28 @@ * received byte. Here we just reset the FIFO pointer, skip the * writecnt, is there anyone who have anther method to replace it? */ + printf_debug("The FIFO pointer before reset is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); reset_internal_fifo_pointer(); for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the bytes we send. */ printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("The FIFO pointer after skipping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); } printf_debug("\n"); + printf_debug("The FIFO pointer after reading is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + printf_debug("Dumping everything that's left in the FIFO\n"); + for (count = 0; count < 8; count++) { + cmd = mmio_readb(sb600_spibar + 0xC); + printf_debug("[ %2x]", cmd); + } + printf_debug("The FIFO pointer after dumping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); + return 0; } -- http://www.hailfinger.org/

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