- flashrom - mail.coreboot.org

[commit] r678 - trunk
by svn＠flashrom.org 12 Aug '09

12 Aug '09

Author: hailfinger Date: 2009-08-12 13:39:29 +0200 (Wed, 12 Aug 2009) New Revision: 678 Modified: trunk/flash.h trunk/flashrom.c trunk/internal.c Log: FT2232 and IT87 programmers used functions of the dummy programmer instead of fallback functions. The dummy programmer is a "real" programmer with possible side effects and its functions should not be abused by other programmers. Make FT2232 and IT87 use official fallback functions instead. Create fallback_shutdown(). Create fallback_chip_writeb(). Convert the programmer #defines to an enum. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-08-12 09:27:45 UTC (rev 677) +++ trunk/flash.h 2009-08-12 11:39:29 UTC (rev 678) @@ -80,15 +80,18 @@ typedef unsigned long chipaddr; -extern int programmer; -#define PROGRAMMER_INTERNAL 0x00 -#define PROGRAMMER_DUMMY 0x01 -#define PROGRAMMER_NIC3COM 0x02 -#define PROGRAMMER_SATASII 0x03 -#define PROGRAMMER_IT87SPI 0x04 -#define PROGRAMMER_FT2232SPI 0x05 -#define PROGRAMMER_SERPROG 0x06 +enum programmer { + PROGRAMMER_INTERNAL, + PROGRAMMER_DUMMY, + PROGRAMMER_NIC3COM, + PROGRAMMER_SATASII, + PROGRAMMER_IT87SPI, + PROGRAMMER_FT2232SPI, + PROGRAMMER_SERPROG, +}; +extern enum programmer programmer; + struct programmer_entry { const char *vendor; const char *name; @@ -332,8 +335,10 @@ uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); void internal_delay(int usecs); +int fallback_shutdown(void); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); +void fallback_chip_writeb(uint8_t val, chipaddr addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); @@ -382,7 +387,6 @@ int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); /* flashrom.c */ Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-08-12 09:27:45 UTC (rev 677) +++ trunk/flashrom.c 2009-08-12 11:39:29 UTC (rev 678) @@ -33,7 +33,7 @@ const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; -int programmer = PROGRAMMER_INTERNAL; +enum programmer programmer = PROGRAMMER_INTERNAL; const struct programmer_entry programmer_table[] = { { @@ -102,14 +102,14 @@ { .init = it87spi_init, - .shutdown = dummy_shutdown, - .map_flash_region = dummy_map, - .unmap_flash_region = dummy_unmap, + .shutdown = fallback_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, .chip_readb = dummy_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = dummy_chip_writeb, + .chip_writeb = fallback_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, @@ -118,19 +118,20 @@ { .init = ft2232_spi_init, - .shutdown = dummy_shutdown, - .map_flash_region = dummy_map, - .unmap_flash_region = dummy_unmap, + .shutdown = fallback_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, .chip_readb = dummy_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, - .chip_writeb = dummy_chip_writeb, + .chip_writeb = fallback_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, .delay = internal_delay, }, + { .init = serprog_init, .shutdown = serprog_shutdown, Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-08-12 09:27:45 UTC (rev 677) +++ trunk/internal.c 2009-08-12 11:39:29 UTC (rev 678) @@ -218,6 +218,12 @@ } } +/* Fallback shutdown() for programmers which don't need special handling */ +int fallback_shutdown(void) +{ + return 0; +} + /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { @@ -229,6 +235,11 @@ { } +/* No-op fallback for drivers not supporting addr/data pair accesses */ +void fallback_chip_writeb(uint8_t val, chipaddr addr) +{ +} + /* Little-endian fallback for drivers not supporting 16 bit accesses */ void fallback_chip_writew(uint16_t val, chipaddr addr) {

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[commit] r677 - trunk
by svn＠flashrom.org 12 Aug '09

12 Aug '09

Author: stepan Date: 2009-08-12 11:27:45 +0200 (Wed, 12 Aug 2009) New Revision: 677 Modified: trunk/chipset_enable.c trunk/flash.h trunk/physmap.c Log: Fix up MSR handling in flashrom to support more OSes than Linux. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-11 12:15:39 UTC (rev 676) +++ trunk/chipset_enable.c 2009-08-12 09:27:45 UTC (rev 677) @@ -2,7 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2000 Silicon Integrated System Corporation - * Copyright (C) 2005-2009 coresystems GmbH <stepan(a)coresystems.de> + * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify @@ -527,92 +527,36 @@ /** * Geode systems write protect the BIOS via RCONFs (cache settings similar - * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and - * writing to MSRs, however requires instructions rdmsr/wrmsr, which are - * ring0 privileged instructions so only the kernel can do the read/write. - * This function, therefore, requires that the msr kernel module be loaded - * to access these instructions from user space using device /dev/cpu/0/msr. + * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. * - * This hard-coded location could have potential problems on SMP machines - * since it assumes cpu0, but it is safe on the Geode which is not SMP. - * * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. * To enable write to NOR Boot flash for the benefit of systems that have such * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). - * - * This is probably not portable beyond Linux. */ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { #define MSR_RCONF_DEFAULT 0x1808 #define MSR_NORF_CTL 0x51400018 - int fd_msr; - unsigned char buf[8]; + msr_t msr; - fd_msr = open("/dev/cpu/0/msr", O_RDWR); - if (fd_msr == -1) { - perror("open(/dev/cpu/0/msr)"); - printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n"); + /* Geode only has a single core */ + if (setup_cpu_msr(0)) return -1; - } - if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { - perror("lseek64"); - close(fd_msr); - return -1; + msr = rdmsr(MSR_RCONF_DEFAULT); + if ((msr.hi >> 24) != 0x22) { + msr.hi &= 0xfbffffff; + wrmsr(MSR_RCONF_DEFAULT, msr); } - if (read(fd_msr, buf, 8) != 8) { - perror("read msr"); - close(fd_msr); - return -1; - } - - if (buf[7] != 0x22) { - buf[7] &= 0xfb; - if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, - SEEK_SET) == -1) { - perror("lseek64"); - close(fd_msr); - return -1; - } - - if (write(fd_msr, buf, 8) < 0) { - perror("msr write"); - close(fd_msr); - return -1; - } - } - - if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { - perror("lseek64"); - close(fd_msr); - return -1; - } - - if (read(fd_msr, buf, 8) != 8) { - perror("read msr"); - close(fd_msr); - return -1; - } - + msr = rdmsr(MSR_NORF_CTL); /* Raise WE_CS3 bit. */ - buf[0] |= 0x08; + msr.lo |= 0x08; + wrmsr(MSR_NORF_CTL, msr); - if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { - perror("lseek64"); - close(fd_msr); - return -1; - } - if (write(fd_msr, buf, 8) < 0) { - perror("msr write"); - close(fd_msr); - return -1; - } + cleanup_cpu_msr(); - close(fd_msr); - #undef MSR_RCONF_DEFAULT #undef MSR_NORF_CTL return 0; Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-08-11 12:15:39 UTC (rev 676) +++ trunk/flash.h 2009-08-12 09:27:45 UTC (rev 677) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 Silicon Integrated System Corporation * Copyright (C) 2000 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2005-2007 coresystems GmbH <stepan(a)coresystems.de> + * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006-2009 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify @@ -301,6 +301,13 @@ /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); +int setup_cpu_msr(int cpu); +void cleanup_cpu_msr(void); +#ifndef __DARWIN__ +typedef struct { uint32_t hi, lo; } msr_t; +msr_t rdmsr(int addr); +int wrmsr(int addr, msr_t msr); +#endif /* internal.c */ struct pci_dev *pci_dev_find_filter(struct pci_filter filter); Modified: trunk/physmap.c =================================================================== --- trunk/physmap.c 2009-08-11 12:15:39 UTC (rev 676) +++ trunk/physmap.c 2009-08-12 09:27:45 UTC (rev 677) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> + * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <sys/stat.h> #include <fcntl.h> #include <stdlib.h> +#include <string.h> #include <errno.h> #include "flash.h" @@ -117,3 +119,136 @@ return virt_addr; } + +#ifdef __linux__ +/* + * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, + * which are ring0 privileged instructions so only the kernel can do the + * read/write. This function, therefore, requires that the msr kernel module + * be loaded to access these instructions from user space using device + * /dev/cpu/0/msr. + */ + +static int fd_msr = -1; + +msr_t rdmsr(int addr) +{ + uint8_t buf[8]; + msr_t msr = { 0xffffffff, 0xffffffff }; + + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { + perror("Could not lseek() to MSR"); + close(fd_msr); + exit(1); + } + + if (read(fd_msr, buf, 8) == 8) { + msr.lo = *(uint32_t *)buf; + msr.hi = *(uint32_t *)(buf + 4); + + return msr; + } + + if (errno != EIO) { + // A severe error. + perror("Could not read() MSR"); + close(fd_msr); + exit(1); + } + + return msr; +} + +int wrmsr(int addr, msr_t msr) +{ + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { + perror("Could not lseek() to MSR"); + close(fd_msr); + exit(1); + } + + if (write(fd_msr, &msr, 8) != 8 && errno != EIO) { + perror("Could not write() MSR"); + close(fd_msr); + exit(1); + } + + /* some MSRs must not be written */ + if (errno == EIO) + return -1; + + return 0; +} + +int setup_cpu_msr(int cpu) +{ + char msrfilename[64]; + memset(msrfilename, 0, 64); + sprintf(msrfilename, "/dev/cpu/%d/msr", cpu); + + if (fd_msr != -1) { + printf("MSR was already initialized\n"); + return -1; + } + + fd_msr = open(msrfilename, O_RDWR); + + if (fd_msr < 0) { + perror("Error while opening /dev/cpu/0/msr"); + printf("Did you run 'modprobe msr'?\n"); + return -1; + } + + return 0; +} + +void cleanup_cpu_msr(void) +{ + if (fd_msr == -1) { + printf("No MSR initialized.\n"); + return; + } + + close(fd_msr); + + /* Clear MSR file descriptor */ + fd_msr = -1; +} +#else +#ifdef __DARWIN__ +int setup_cpu_msr(int cpu) +{ + // Always succeed for now + return 0; +} + +void cleanup_cpu_msr(void) +{ + // Nothing, yet. +} +#else +msr_t rdmsr(int addr) +{ + msr_t ret = { 0xffffffff, 0xffffffff }; + + return ret; +} + +int wrmsr(int addr, msr_t msr) +{ + return -1; +} + +int setup_cpu_msr(int cpu) +{ + printf("No MSR support for your OS yet.\n"); + return -1; +} + +void cleanup_cpu_msr(void) +{ + // Nothing, yet. +} +#endif +#endif +

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flashrom -V output on Asus P4P800-E Deluxe
by crnibojan 12 Aug '09

12 Aug '09

Hello! Here it is output from flashrom -V on Asus P4P800-E Deluxe flashrom v0.9.0-r676 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 787M loops per second, 100 myus = 162 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x2b, id2 0xeb Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x6d, id2 0x48 Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x6d, id2 0x48 Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x6d, id2 0x48 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified. Best regards, Bojan Radakovic

1 3

MSI MS-7350 with Nvidia mcp51 but no flash chip
by Philipp Matthias Hahn 11 Aug '09

11 Aug '09

Hi, attached below if the output of "flashrom --verbose" from my MSI MS-7350 with th Nvidia mcp51 chip but not flash chip detected. Any advise on how to procees is appreciated. Thanks in advance for your nice work. flashrom v0.9.0-r674 No coreboot table found. Found chipset "NVIDIA MCP51", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 760M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x00, id2 0x00 Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x02, id2 0x1e Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x02, id2 0x1e Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x02, id2 0x1e Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x02, id2 0x1e Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0xff, id2 0xff Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x02, id2 0x1e Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x02, id2 0x1e Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x91, id2 0xe3, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x02, id2 0x1e Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x1e, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. BYtE Philipp -- / / (_)__ __ ____ __ Philipp Hahn / /__/ / _ \/ // /\ \/ / /____/_/_//_/\_,_/ /_/\_\ pmhahn(a)titan.lahn.de

1 0

[commit] r676 - trunk
by svn＠flashrom.org 11 Aug '09

11 Aug '09

Author: stepan Date: 2009-08-11 14:15:39 +0200 (Tue, 11 Aug 2009) New Revision: 676 Modified: trunk/chipset_enable.c Log: Make debug messages printf_debug(). Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-10 23:30:45 UTC (rev 675) +++ trunk/chipset_enable.c 2009-08-11 12:15:39 UTC (rev 676) @@ -2,7 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2000 Silicon Integrated System Corporation - * Copyright (C) 2005-2007 coresystems GmbH <stepan(a)coresystems.de> + * Copyright (C) 2005-2009 coresystems GmbH <stepan(a)coresystems.de> * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify @@ -98,7 +98,7 @@ } OUTB(0x24, 0x2e); - printf("2f is %#x\n", INB(0x2f)); + printf_debug("2f is %#x\n", INB(0x2f)); b = INB(0x2f) | 0xfc; OUTB(0x24, 0x2e); OUTB(b, 0x2f); @@ -146,7 +146,7 @@ pci_write_word(dev, xbcs, new); if (pci_read_word(dev, xbcs) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); return -1; } @@ -182,7 +182,7 @@ pci_write_byte(dev, bios_cntl, new); if (pci_read_byte(dev, bios_cntl) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); return -1; } @@ -487,7 +487,7 @@ pci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n", + printf("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } @@ -627,7 +627,7 @@ new = pci_read_byte(dev, 0x52); if (new != 0xee) { - printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); return -1; } @@ -647,8 +647,8 @@ newer = pci_read_byte(dev, 0x45); if (newer != new) { - printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf("Stuck at 0x%x\n", newer); + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + printf_debug("Stuck at 0x%x\n", newer); return -1; } @@ -659,8 +659,8 @@ pci_write_byte(dev, 0x40, new); newer = pci_read_byte(dev, 0x40); if (newer != new) { - printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf("Stuck at 0x%x\n", newer); + printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + printf_debug("Stuck at 0x%x\n", newer); return -1; } return 0; @@ -677,7 +677,7 @@ if (new != old) { pci_write_byte(dev, 0x43, new); if (pci_read_byte(dev, 0x43) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); } } @@ -689,7 +689,7 @@ pci_write_byte(dev, 0x40, new); if (pci_read_byte(dev, 0x40) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); return -1; } @@ -860,7 +860,7 @@ if (new != old) { pci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); } } @@ -871,7 +871,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } @@ -937,7 +937,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; }

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Re: [flashrom] ICH6-ICH10 flash decode debug, IDSEL=0 hardcode
by Carl-Daniel Hailfinger 11 Aug '09

11 Aug '09

On 07.08.2009 00:38, Chris Kinney wrote: > here is the real output, didnt recompile, mistake on my part! looks > better now. Great, it found the chip. Flashing should work fine, no forcing needed at all. > [root@k2 flashrom]# ./flashrom -V > flashrom v0.9.0-r670 > Found candidate at: 00000500-00000510 > Found coreboot table at 0x00000500. > Found candidate at: 00000c00-00001350 > Found coreboot table at 0x00000c00. > coreboot table found at 0xcf7f3c00. > coreboot header(24) checksum: 67a9 table(1872) checksum: ff43 entries: 21 > Vendor ID: KONTRON, part ID: 986LCD-M > Found chipset "Intel ICH7/ICH7R", enabling flash write... > 0xfff80000/0xffb80000 FWH IDSEL: 0x0, > 0xfff00000/0xffb00000 FWH IDSEL: 0x0, > 0xffe80000/0xffa80000 FWH IDSEL: 0x1, > 0xffe00000/0xffa00000 FWH IDSEL: 0x1, > 0xffd80000/0xff980000 FWH IDSEL: 0x2, > 0xffd00000/0xff900000 FWH IDSEL: 0x2, > 0xffc80000/0xff880000 FWH IDSEL: 0x3, > 0xffc00000/0xff800000 FWH IDSEL: 0x3, > 0xff700000/0xff300000 FWH IDSEL: 0x4, > 0xff600000/0xff200000 FWH IDSEL: 0x5, > 0xff500000/0xff100000 FWH IDSEL: 0x6, > 0xff400000/0xff000000 FWH IDSEL: 0x7, 0xfff80000/0xffb80000 FWH decode > enabled, 0xfff00000/0xffb00000 FWH decode enabled, > 0xffe80000/0xffa80000 FWH decode enabled, 0xffe00000/0xffa00000 FWH > decode enabled, 0xffd80000/0xff980000 FWH decode enabled, > 0xffd00000/0xff900000 FWH decode enabled, 0xffc80000/0xff880000 FWH > decode enabled, 0xffc00000/0xff800000 FWH decode enabled, > 0xff700000/0xff300000 FWH decode enabled, 0xff600000/0xff200000 FWH > decode enabled, 0xff500000/0xff100000 FWH decode enabled, > 0xff400000/0xff000000 FWH decode enabled, > Setting IDSEL=0 for top 8 MB > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x7a0c60: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: > 0x3 (LPC) > Top Swap : not enabled > OK. > This chipset supports the following protocols: LPC,FWH. > Disabling flash write protection for board "Kontron 986LCD-M"... > GPIOBAR=0x0480 GP_LVL: 0x0001003d > OK. > Calibrating delay loop... 282M loops per second, 100 myus = 202 us. OK. > Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMIC A25L40P, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xbf, id2 0x5c Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xbf, id2 0x5c > Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC Pm29F0002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for PMC Pm29F0002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xbf, id2 0x5c > Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xbf, id2 0x5c > Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xbf, id2 0x5c > Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xbf, id2 0x5c > Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address 0xffe00000. > Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xbf, id2 0x5c > Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x5c > Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x5c > Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x5c > Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x5c > Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xbf, id2 0x5c > Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xbf, id2 0x5c > Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xbf, id2 0x5c > Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xbf, id2 0x5c > Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xbf, id2 0x5c > Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. > Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5c > Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xbf, id2 0x5c > Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xbf, id2 0x5c > Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. > > No operations were specified. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

[commit] r675 - trunk
by svn＠flashrom.org 11 Aug '09

11 Aug '09

Author: hailfinger Date: 2009-08-11 01:30:45 +0200 (Tue, 11 Aug 2009) New Revision: 675 Modified: trunk/chipset_enable.c Log: Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode settings to the debug output. This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Chris Kinney <cmkinne(a)sandia.gov> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-10 10:14:23 UTC (rev 674) +++ trunk/chipset_enable.c 2009-08-10 23:30:45 UTC (rev 675) @@ -191,11 +191,47 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { + /* + * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and + * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and + * FB_DEC_EN2. + */ return enable_flash_ich(dev, name, 0x4e); } static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { + uint32_t fwh_conf; + int i; + + /* Ignore all legacy ranges below 1 MB. */ + /* FWH_SEL1 */ + fwh_conf = pci_read_long(dev, 0xd0); + for (i = 7; i >= 0; i--) + printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + (0x1ff8 + i) * 0x80000, + (0x1ff0 + i) * 0x80000, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, 0xd4); + for (i = 3; i >= 0; i--) + printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + (0xff4 + i) * 0x100000, + (0xff0 + i) * 0x100000, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_DEC_EN1 */ + fwh_conf = pci_read_word(dev, 0xd8); + for (i = 7; i >= 0; i--) + printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + (0x1ff8 + i) * 0x80000, + (0x1ff0 + i) * 0x80000, + (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis"); + for (i = 3; i >= 0; i--) + printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + (0xff4 + i) * 0x100000, + (0xff0 + i) * 0x100000, + (fwh_conf >> i) & 0x1 ? "en" : "dis"); + return enable_flash_ich(dev, name, 0xdc); }

1 0

[PATCH] Add IDs for 44 new flash chips
by Carl-Daniel Hailfinger 10 Aug '09

10 Aug '09

Add IDs for 25 AMD chips, 8 Sharp chips, 11 Hynix chips and their variants. AM29DL400BB AM29DL400BT AM29DL800BB AM29DL800BT AM29F004BB AM29F004BT AM29F200BB AM29F200BT AM29F400BB AM29F400BT AM29F800BB AM29F800BT AM29LV002BB AM29LV002BT AM29LV004BB AM29LV004BT AM29LV008BB AM29LV008BT AM29LV080B AM29LV200BB AM29LV200BT AM29LV400BB AM29LV400BT AM29LV800BB AM29LV800BT HY29F002 HY29F040A HY29F080 HY29F400B HY29F400T HY29F800B HY29F800T HY29LV400B HY29LV400T HY29LV800B HY29LV800T LH28F008BJxxPB LH28F008BJxxPT LH28F008SA LH28F008SC LH28F800BVxxBTL LH28F800BVxxBV LH28F800BVxxTV LHF00L02 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-newids/flashchips.h =================================================================== --- flashrom-newids/flashchips.h (Revision 667) +++ flashrom-newids/flashchips.h (Arbeitskopie) @@ -39,20 +39,44 @@ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ +#define AM_29DL400BT 0x0C +#define AM_29DL400BB 0x0F +#define AM_29DL800BT 0x4A +#define AM_29DL800BB 0xCB +#define AM_29F002BB 0x34 /* Same as Am29F002NBB */ +#define AM_29F002BT 0xB0 /* Same as Am29F002NBT */ +#define AM_29F004BB 0x7B +#define AM_29F004BT 0x77 +#define AM_29F016D 0xAD #define AM_29F010B 0x20 /* Same as Am29F010A */ -#define AM_29F002BT 0xB0 -#define AM_29F002BB 0x34 #define AM_29F040B 0xA4 #define AM_29F080B 0xD5 +#define AM_29F200BB 0x57 +#define AM_29F200BT 0x51 +#define AM_29F400BB 0xAB +#define AM_29F400BT 0x23 +#define AM_29F800BB 0x58 +#define AM_29F800BT 0xD6 +#define AM_29LV002BB 0xC2 +#define AM_29LV002BT 0x40 +#define AM_29LV004BB 0xB6 +#define AM_29LV004BT 0xB5 +#define AM_29LV008BB 0x37 +#define AM_29LV008BT 0x3E #define AM_29LV040B 0x4F -#define AM_29LV081B 0x38 -#define AM_29F016D 0xAD +#define AM_29LV080B 0x38 /* Same as Am29LV081B */ +#define AM_29LV200BB 0xBF +#define AM_29LV200BT 0x3B +#define AM_29LV800BB 0x5B /* Same as Am29LV800DB */ +#define AM_29LV400BT 0xB9 +#define AM_29LV400BB 0xBA +#define AM_29LV800BT 0xDA /* Same as Am29LV800DT */ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 #define AMIC_A29002B 0x0d -#define AMIC_A29002T 0x8c +#define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 #define AMIC_A29400T 0xB0 /* Same as 294001T */ #define AMIC_A29400U 0x31 /* Same as A294001U */ @@ -194,16 +218,29 @@ #define MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define HYUNDAI_ID 0xAD /* Hyundai */ +#define HY_29F400T 0x23 /* Same as HY_29F400AT */ +#define HY_29F800B 0x58 /* Same as HY_29F800AB */ +#define HY_29LV800B 0x5B +#define HY_29F040A 0xA4 +#define HY_29F400B 0xAB /* Same as HY_29F400AB */ +#define HY_29F002 0xB0 +#define HY_29LV400T 0xB9 +#define HY_29LV400B 0xBA +#define HY_29F080 0xD5 +#define HY_29F800T 0xD6 /* Same as HY_29F800AT */ +#define HY_29LV800T 0xDA #define IMT_ID 0x7F1F /* Integrated Memory Technologies */ #define IM_29F004B 0xAE #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ -#define I_82802AB 0xAD -#define I_82802AC 0xAC +#define I_82802AB 0xAD +#define I_82802AC 0xAC #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ +#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ @@ -287,14 +324,20 @@ #define PMC_49FL004 0x6E #define SHARP_ID 0xB0 /* Sharp */ -#define SHARP_LHF00L04 0xCF +#define SHARP_LH28F008BJxxPT 0xEC +#define SHARP_LH28F008BJxxPB 0xED +#define SHARP_LH28F800BVxxBTL 0x4B +#define SHARP_LH28F800BVxxBV 0x4D +#define SHARP_LH28F800BVxxTV 0x4C +#define SHARP_LHF00L02 0xC9 /* Same as LHF00L06/LHF00L07 */ +#define SHARP_LHF00L04 0xCF /* Same as LHF00L03/LHF00L05 */ /* * Spansion was previously a joint venture of AMD and Fujitsu. * S25 chips are SPI. The first device ID byte is memory type and * the second device ID byte is memory capacity. */ -#define SPANSION_ID 0x01 /* Spansion */ +#define SPANSION_ID 0x01 /* Spansion, same ID as AMD */ #define SPANSION_S25FL016A 0x0214 /* @@ -336,13 +379,13 @@ #define SST_29SF040 0x13 #define SST_29VF040 0x14 #define SST_39SF010 0xB5 -#define SST_39SF020 0xB6 +#define SST_39SF020 0xB6 /* Same as 39SF020A */ #define SST_39SF040 0xB7 #define SST_39VF512 0xD4 #define SST_39VF010 0xD5 -#define SST_39VF020 0xD6 -#define SST_39VF040 0xD7 -#define SST_39VF080 0xD8 /* Same as SST_39LF080/39VF080/39VF088 */ +#define SST_39VF020 0xD6 /* Same as 39LF020 */ +#define SST_39VF040 0xD7 /* Same as 39LF040 */ +#define SST_39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */ #define SST_49LF040B 0x50 #define SST_49LF040 0x51 #define SST_49LF020 0x61 @@ -351,7 +394,7 @@ #define SST_49LF080A 0x5B #define SST_49LF002A 0x57 #define SST_49LF003A 0x1B -#define SST_49LF004A 0x60 +#define SST_49LF004A 0x60 /* Same as 49LF004B */ #define SST_49LF008A 0x5A #define SST_49LF004C 0x54 #define SST_49LF008C 0x59 @@ -389,14 +432,14 @@ #define ST_M50FW080 0x2D #define ST_M50FW016 0x2E #define ST_M50LPW116 0x30 -#define ST_M29F002B 0x34 -#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */ -#define ST_M29F040B 0xE2 +#define ST_M29F002B 0x34 /* Same as M29F002BB */ +#define ST_M29F002T 0xB0 /* Same as M29F002BT/M29F002NT/M29F002BNT */ +#define ST_M29F040B 0xE2 /* Same as M29F040 */ #define ST_M29F080 0xF1 #define ST_M29F200BT 0xD3 #define ST_M29F200BB 0xD4 -#define ST_M29F400BT 0xD5 -#define ST_M29F400BB 0xD6 +#define ST_M29F400BT 0xD5 /* Same as M29F400T */ +#define ST_M29F400BB 0xD6 /* Same as M29F400B */ #define ST_M29F800DB 0x58 #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 @@ -427,8 +470,8 @@ #define W_25X32 0x3016 #define W_25X64 0x3017 #define W_29C011 0xC1 -#define W_29C020C 0x45 -#define W_29C040P 0x46 +#define W_29C020C 0x45 /* Same as W29C020 */ +#define W_29C040P 0x46 /* Same as W29C040 */ #define W_29EE011 0xC1 #define W_39L020 0xB5 #define W_39L040 0xB6 -- http://www.hailfinger.org/

2 3

[commit] r674 - trunk
by svn＠flashrom.org 10 Aug '09

10 Aug '09

Author: hailfinger Date: 2009-08-10 12:14:23 +0200 (Mon, 10 Aug 2009) New Revision: 674 Modified: trunk/flashchips.c trunk/flashchips.h Log: Add IDs for 25 AMD chips, 11 Hynix chips, 8 Sharp chips, and their variants. AM29DL400BB, AM29DL400BT, AM29DL800BB, AM29DL800BT, AM29F004BB AM29F004BT, AM29F200BB, AM29F200BT, AM29F400BB, AM29F400BT AM29F800BB, AM29F800BT, AM29LV002BB, AM29LV002BT, AM29LV004BB AM29LV004BT, AM29LV008BB, AM29LV008BT, AM29LV080B, AM29LV200BB AM29LV200BT, AM29LV400BB, AM29LV400BT, AM29LV800BB, AM29LV800BT HY29F002, HY29F040A, HY29F080, HY29F400B, HY29F400T, HY29F800B HY29F800T, HY29LV400B, HY29LV400T, HY29LV800B, HY29LV800T LH28F008BJxxPB, LH28F008BJxxPT, LH28F008SA, LH28F008SC, LH28F800BVxxBTL LH28F800BVxxBV, LH28F800BVxxTV, LHF00L02 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-08-10 02:29:21 UTC (rev 673) +++ trunk/flashchips.c 2009-08-10 10:14:23 UTC (rev 674) @@ -165,7 +165,7 @@ .name = "Am29LV081B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, - .model_id = AM_29LV081B, + .model_id = AM_29LV080B, .total_size = 1024, .page_size = 64 * 1024, .tested = TEST_UNTESTED, Modified: trunk/flashchips.h =================================================================== --- trunk/flashchips.h 2009-08-10 02:29:21 UTC (rev 673) +++ trunk/flashchips.h 2009-08-10 10:14:23 UTC (rev 674) @@ -39,20 +39,44 @@ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ +#define AM_29DL400BT 0x0C +#define AM_29DL400BB 0x0F +#define AM_29DL800BT 0x4A +#define AM_29DL800BB 0xCB +#define AM_29F002BB 0x34 /* Same as Am29F002NBB */ +#define AM_29F002BT 0xB0 /* Same as Am29F002NBT */ +#define AM_29F004BB 0x7B +#define AM_29F004BT 0x77 +#define AM_29F016D 0xAD #define AM_29F010B 0x20 /* Same as Am29F010A */ -#define AM_29F002BT 0xB0 -#define AM_29F002BB 0x34 #define AM_29F040B 0xA4 #define AM_29F080B 0xD5 +#define AM_29F200BB 0x57 +#define AM_29F200BT 0x51 +#define AM_29F400BB 0xAB +#define AM_29F400BT 0x23 +#define AM_29F800BB 0x58 +#define AM_29F800BT 0xD6 +#define AM_29LV002BB 0xC2 +#define AM_29LV002BT 0x40 +#define AM_29LV004BB 0xB6 +#define AM_29LV004BT 0xB5 +#define AM_29LV008BB 0x37 +#define AM_29LV008BT 0x3E #define AM_29LV040B 0x4F -#define AM_29LV081B 0x38 -#define AM_29F016D 0xAD +#define AM_29LV080B 0x38 /* Same as Am29LV081B */ +#define AM_29LV200BB 0xBF +#define AM_29LV200BT 0x3B +#define AM_29LV800BB 0x5B /* Same as Am29LV800DB */ +#define AM_29LV400BT 0xB9 +#define AM_29LV400BB 0xBA +#define AM_29LV800BT 0xDA /* Same as Am29LV800DT */ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define AMIC_A25L40P 0x2013 #define AMIC_A29002B 0x0d -#define AMIC_A29002T 0x8c +#define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 #define AMIC_A29400T 0xB0 /* Same as 294001T */ #define AMIC_A29400U 0x31 /* Same as A294001U */ @@ -194,16 +218,29 @@ #define MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define HYUNDAI_ID 0xAD /* Hyundai */ +#define HY_29F400T 0x23 /* Same as HY_29F400AT */ +#define HY_29F800B 0x58 /* Same as HY_29F800AB */ +#define HY_29LV800B 0x5B +#define HY_29F040A 0xA4 +#define HY_29F400B 0xAB /* Same as HY_29F400AB */ +#define HY_29F002 0xB0 +#define HY_29LV400T 0xB9 +#define HY_29LV400B 0xBA +#define HY_29F080 0xD5 +#define HY_29F800T 0xD6 /* Same as HY_29F800AT */ +#define HY_29LV800T 0xDA #define IMT_ID 0x7F1F /* Integrated Memory Technologies */ #define IM_29F004B 0xAE #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ -#define I_82802AB 0xAD -#define I_82802AC 0xAC +#define I_82802AB 0xAD +#define I_82802AC 0xAC #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ +#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ @@ -287,14 +324,20 @@ #define PMC_49FL004 0x6E #define SHARP_ID 0xB0 /* Sharp */ -#define SHARP_LHF00L04 0xCF +#define SHARP_LH28F008BJxxPT 0xEC +#define SHARP_LH28F008BJxxPB 0xED +#define SHARP_LH28F800BVxxBTL 0x4B +#define SHARP_LH28F800BVxxBV 0x4D +#define SHARP_LH28F800BVxxTV 0x4C +#define SHARP_LHF00L02 0xC9 /* Same as LHF00L06/LHF00L07 */ +#define SHARP_LHF00L04 0xCF /* Same as LHF00L03/LHF00L05 */ /* * Spansion was previously a joint venture of AMD and Fujitsu. * S25 chips are SPI. The first device ID byte is memory type and * the second device ID byte is memory capacity. */ -#define SPANSION_ID 0x01 /* Spansion */ +#define SPANSION_ID 0x01 /* Spansion, same ID as AMD */ #define SPANSION_S25FL016A 0x0214 /* @@ -336,13 +379,13 @@ #define SST_29SF040 0x13 #define SST_29VF040 0x14 #define SST_39SF010 0xB5 -#define SST_39SF020 0xB6 +#define SST_39SF020 0xB6 /* Same as 39SF020A */ #define SST_39SF040 0xB7 #define SST_39VF512 0xD4 #define SST_39VF010 0xD5 -#define SST_39VF020 0xD6 -#define SST_39VF040 0xD7 -#define SST_39VF080 0xD8 /* Same as SST_39LF080/39VF080/39VF088 */ +#define SST_39VF020 0xD6 /* Same as 39LF020 */ +#define SST_39VF040 0xD7 /* Same as 39LF040 */ +#define SST_39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */ #define SST_49LF040B 0x50 #define SST_49LF040 0x51 #define SST_49LF020 0x61 @@ -351,7 +394,7 @@ #define SST_49LF080A 0x5B #define SST_49LF002A 0x57 #define SST_49LF003A 0x1B -#define SST_49LF004A 0x60 +#define SST_49LF004A 0x60 /* Same as 49LF004B */ #define SST_49LF008A 0x5A #define SST_49LF004C 0x54 #define SST_49LF008C 0x59 @@ -389,14 +432,14 @@ #define ST_M50FW080 0x2D #define ST_M50FW016 0x2E #define ST_M50LPW116 0x30 -#define ST_M29F002B 0x34 -#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */ -#define ST_M29F040B 0xE2 +#define ST_M29F002B 0x34 /* Same as M29F002BB */ +#define ST_M29F002T 0xB0 /* Same as M29F002BT/M29F002NT/M29F002BNT */ +#define ST_M29F040B 0xE2 /* Same as M29F040 */ #define ST_M29F080 0xF1 #define ST_M29F200BT 0xD3 #define ST_M29F200BB 0xD4 -#define ST_M29F400BT 0xD5 -#define ST_M29F400BB 0xD6 +#define ST_M29F400BT 0xD5 /* Same as M29F400T */ +#define ST_M29F400BB 0xD6 /* Same as M29F400B */ #define ST_M29F800DB 0x58 #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 @@ -427,8 +470,8 @@ #define W_25X32 0x3016 #define W_25X64 0x3017 #define W_29C011 0xC1 -#define W_29C020C 0x45 -#define W_29C040P 0x46 +#define W_29C020C 0x45 /* Same as W29C020 */ +#define W_29C040P 0x46 /* Same as W29C040 */ #define W_29EE011 0xC1 #define W_39L020 0xB5 #define W_39L040 0xB6

1 0

[PATCH] SPI autoerase before write
by Carl-Daniel Hailfinger 10 Aug '09

10 Aug '09

Some SPI chip drivers and the generic 1-byte SPI chip write functions didn't include the automatic erase present in other chip drivers. Since the majority is definitely auto-erase, change the remaining explicit-erase cases to be auto-erase as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_autoerase_before_write/flash.h =================================================================== --- flashrom-spi_autoerase_before_write/flash.h (revision 672) +++ flashrom-spi_autoerase_before_write/flash.h (working copy) @@ -505,7 +505,6 @@ int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ Index: flashrom-spi_autoerase_before_write/it87spi.c =================================================================== --- flashrom-spi_autoerase_before_write/it87spi.c (revision 672) +++ flashrom-spi_autoerase_before_write/it87spi.c (working copy) @@ -248,32 +248,6 @@ } /* - * Program chip using firmware cycle byte programming. (SLOW!) - * This is for chips which can only handle one byte writes - * and for chips where memory mapped programming is impossible due to - * size constraints in IT87* (over 512 kB) - */ -int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf) -{ - int total_size = 1024 * flash->total_size; - int i; - int result; - - fast_spi = 0; - - spi_disable_blockprotect(); - for (i = 0; i < total_size; i++) { - result = spi_byte_program(i, buf[i]); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10); - } - /* resume normal ops... */ - OUTB(0x20, it8716f_flashport); - - return 0; -} - -/* * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ @@ -301,8 +275,16 @@ * mapped access. */ if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - it8716f_spi_chip_write_1(flash, buf); + spi_chip_write_1(flash, buf); } else { + spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); for (i = 0; i < total_size / 256; i++) { it8716f_spi_page_program(flash, i, buf); } Index: flashrom-spi_autoerase_before_write/spi.c =================================================================== --- flashrom-spi_autoerase_before_write/spi.c (revision 672) +++ flashrom-spi_autoerase_before_write/spi.c (working copy) @@ -963,6 +963,13 @@ int i; spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); for (i = 0; i < total_size; i++) { spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) Index: flashrom-spi_autoerase_before_write/ft2232_spi.c =================================================================== --- flashrom-spi_autoerase_before_write/ft2232_spi.c (revision 672) +++ flashrom-spi_autoerase_before_write/ft2232_spi.c (working copy) @@ -271,6 +271,14 @@ int total_size = 1024 * flash->total_size; int i; + spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); printf_debug("total_size is %d\n", total_size); for (i = 0; i < total_size; i += 256) { int l, r; @@ -281,14 +289,12 @@ if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); - // spi_write_disable(); chip does this for us return 1; } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) /* loop */; } - // spi_write_disable(); chip does this for us return 0; } Index: flashrom-spi_autoerase_before_write/wbsio_spi.c =================================================================== --- flashrom-spi_autoerase_before_write/wbsio_spi.c (revision 672) +++ flashrom-spi_autoerase_before_write/wbsio_spi.c (working copy) @@ -183,29 +183,17 @@ return 1; } - read_memmapped(flash, buf, start, len); - return 0; + return read_memmapped(flash, buf, start, len); } int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int pos, size = flash->total_size * 1024; - int result; + int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - if (flash->erase(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - for (pos = 0; pos < size; pos++) { - result = spi_byte_program(pos, buf[pos]); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10); - } - spi_write_disable(); - return 0; + return spi_chip_write_1(flash, buf); } Index: flashrom-spi_autoerase_before_write/sb600spi.c =================================================================== --- flashrom-spi_autoerase_before_write/sb600spi.c (revision 672) +++ flashrom-spi_autoerase_before_write/sb600spi.c (working copy) @@ -45,12 +45,14 @@ return spi_read_chunked(flash, buf, start, len, 8); } +/* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { int rc = 0, i; int total_size = flash->total_size * 1024; int result; + spi_disable_blockprotect(); /* Erase first */ printf("Erasing flash before programming... "); if (flash->erase(flash)) { @@ -61,7 +63,6 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { - spi_disable_blockprotect(); result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) -- http://www.hailfinger.org/

2 2

[commit] r673 - trunk
by svn＠flashrom.org 10 Aug '09

10 Aug '09

Author: hailfinger Date: 2009-08-10 04:29:21 +0200 (Mon, 10 Aug 2009) New Revision: 673 Modified: trunk/flash.h trunk/ft2232_spi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Some SPI chip drivers and the generic 1-byte SPI chip write functions didn't include the automatic erase present in other chip drivers. Since the majority is definitely auto-erase, change the remaining explicit-erase cases to be auto-erase as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carlos Arnau Perez <cemede(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/flash.h 2009-08-10 02:29:21 UTC (rev 673) @@ -505,7 +505,6 @@ int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/ft2232_spi.c 2009-08-10 02:29:21 UTC (rev 673) @@ -271,6 +271,14 @@ int total_size = 1024 * flash->total_size; int i; + spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); printf_debug("total_size is %d\n", total_size); for (i = 0; i < total_size; i += 256) { int l, r; @@ -281,14 +289,12 @@ if ((r = spi_nbyte_program(i, &buf[i], l))) { fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); - // spi_write_disable(); chip does this for us return 1; } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) /* loop */; } - // spi_write_disable(); chip does this for us return 0; } Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/it87spi.c 2009-08-10 02:29:21 UTC (rev 673) @@ -248,32 +248,6 @@ } /* - * Program chip using firmware cycle byte programming. (SLOW!) - * This is for chips which can only handle one byte writes - * and for chips where memory mapped programming is impossible due to - * size constraints in IT87* (over 512 kB) - */ -int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf) -{ - int total_size = 1024 * flash->total_size; - int i; - int result; - - fast_spi = 0; - - spi_disable_blockprotect(); - for (i = 0; i < total_size; i++) { - result = spi_byte_program(i, buf[i]); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10); - } - /* resume normal ops... */ - OUTB(0x20, it8716f_flashport); - - return 0; -} - -/* * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ @@ -301,8 +275,16 @@ * mapped access. */ if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - it8716f_spi_chip_write_1(flash, buf); + spi_chip_write_1(flash, buf); } else { + spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); for (i = 0; i < total_size / 256; i++) { it8716f_spi_page_program(flash, i, buf); } Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/sb600spi.c 2009-08-10 02:29:21 UTC (rev 673) @@ -45,12 +45,14 @@ return spi_read_chunked(flash, buf, start, len, 8); } +/* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { int rc = 0, i; int total_size = flash->total_size * 1024; int result; + spi_disable_blockprotect(); /* Erase first */ printf("Erasing flash before programming... "); if (flash->erase(flash)) { @@ -61,7 +63,6 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { - spi_disable_blockprotect(); result = spi_byte_program(i, *buf); /* wait program complete. */ if (i % 0x8000 == 0) Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/spi.c 2009-08-10 02:29:21 UTC (rev 673) @@ -963,6 +963,13 @@ int i; spi_disable_blockprotect(); + /* Erase first */ + printf("Erasing flash before programming... "); + if (flash->erase(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + printf("done.\n"); for (i = 0; i < total_size; i++) { spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-08-09 21:50:24 UTC (rev 672) +++ trunk/wbsio_spi.c 2009-08-10 02:29:21 UTC (rev 673) @@ -183,29 +183,17 @@ return 1; } - read_memmapped(flash, buf, start, len); - return 0; + return read_memmapped(flash, buf, start, len); } int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int pos, size = flash->total_size * 1024; - int result; + int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - if (flash->erase(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - for (pos = 0; pos < size; pos++) { - result = spi_byte_program(pos, buf[pos]); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(10); - } - spi_write_disable(); - return 0; + return spi_chip_write_1(flash, buf); }

1 0

[PATCH] Fix another SB600 SPI corner case
by Carl-Daniel Hailfinger 10 Aug '09

10 Aug '09

SB600 SPI has an off-by-one error during read, and that hardware issue is not documented anywhere yet. r661 tried to work around this, but the fix had unpleasant side effects. The new workaround only triggers if readcnt is nonzero, eliminating all possible interactions with write-only commands. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_sb600_offbyone_fixfix/sb600spi.c =================================================================== --- flashrom-spi_sb600_offbyone_fixfix/sb600spi.c (revision 672) +++ flashrom-spi_sb600_offbyone_fixfix/sb600spi.c (working copy) @@ -118,9 +118,13 @@ * an opcode and no additional data/address, the SPI controller will * read one byte too few from the chip. Basically, the last byte of * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. + * It is unclear if the CS# line is set high too early as well, but + * it seems CS# line timing matches the bytecounts we specify, so there + * is a mismatch between FIFO content count and CS# timing. + * Only trigger this if readcnt is nonzero on the assumption that + * reading more doesn't hurt if we already read soemthing. */ - readoffby1 = (writecnt) ? 0 : 1; + readoffby1 = (!writecnt && readcnt) ? 1 : 0; mmio_writeb((readcnt + readoffby1) << 4 | (writecnt), sb600_spibar + 1); mmio_writeb(cmd, sb600_spibar + 0); -- http://www.hailfinger.org/

1 1

[PATCH] ioperm+include cleanup
by Carl-Daniel Hailfinger 09 Aug '09

09 Aug '09

Releasing IO permissions was done by hand everywhere. Use a proper abstraction. Kill unneeded #include statements. Move #include statements for serprog inside #ifdef. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-cleanup/flash.h =================================================================== --- flashrom-cleanup/flash.h (Revision 671) +++ flashrom-cleanup/flash.h (Arbeitskopie) @@ -308,6 +308,7 @@ struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); void get_io_perms(void); +void release_io_perms(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); Index: flashrom-cleanup/serprog.c =================================================================== --- flashrom-cleanup/serprog.c (Revision 671) +++ flashrom-cleanup/serprog.c (Arbeitskopie) @@ -21,6 +21,13 @@ #include <string.h> #include <stdlib.h> +#include <stdio.h> +#include "flash.h" + +char *serprog_param = NULL; + +#if SERPROG_SUPPORT == 1 + #include <ctype.h> #include <fcntl.h> #include <sys/types.h> @@ -31,16 +38,10 @@ #include <netdb.h> #include <sys/stat.h> #include <errno.h> -#include <stdio.h> #include <unistd.h> #include <inttypes.h> #include <termios.h> -#include "flash.h" -char *serprog_param = NULL; - -#if SERPROG_SUPPORT == 1 - #define MSGHEADER "serprog:" #define S_ACK 0x06 Index: flashrom-cleanup/nic3com.c =================================================================== --- flashrom-cleanup/nic3com.c (Revision 671) +++ flashrom-cleanup/nic3com.c (Arbeitskopie) @@ -20,10 +20,7 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #define BIOS_ROM_ADDR 0x04 @@ -99,9 +96,7 @@ free(pcidev_bdf); pci_cleanup(pacc); -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; } Index: flashrom-cleanup/satasii.c =================================================================== --- flashrom-cleanup/satasii.c (Revision 671) +++ flashrom-cleanup/satasii.c (Arbeitskopie) @@ -22,10 +22,6 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> -#include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #define PCI_VENDOR_ID_SII 0x1095 @@ -77,9 +73,7 @@ { free(pcidev_bdf); pci_cleanup(pacc); -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; } Index: flashrom-cleanup/internal.c =================================================================== --- flashrom-cleanup/internal.c (Revision 671) +++ flashrom-cleanup/internal.c (Arbeitskopie) @@ -95,6 +95,13 @@ } } +void release_io_perms(void) +{ +#if defined(__FreeBSD__) || defined(__DragonFly__) + close(io_fd); +#endif +} + int internal_init(void) { int ret = 0; @@ -128,9 +135,7 @@ int internal_shutdown(void) { -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; } -- http://www.hailfinger.org/

2 4

[commit] r672 - trunk
by svn＠flashrom.org 09 Aug '09

09 Aug '09

Author: hailfinger Date: 2009-08-09 23:50:24 +0200 (Sun, 09 Aug 2009) New Revision: 672 Modified: trunk/flash.h trunk/internal.c trunk/nic3com.c trunk/satasii.c Log: Releasing IO permissions was done by hand everywhere. Use a proper abstraction. Kill unneeded #include statements. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-08-09 12:44:08 UTC (rev 671) +++ trunk/flash.h 2009-08-09 21:50:24 UTC (rev 672) @@ -308,6 +308,7 @@ struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); void get_io_perms(void); +void release_io_perms(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-08-09 12:44:08 UTC (rev 671) +++ trunk/internal.c 2009-08-09 21:50:24 UTC (rev 672) @@ -95,6 +95,13 @@ } } +void release_io_perms(void) +{ +#if defined(__FreeBSD__) || defined(__DragonFly__) + close(io_fd); +#endif +} + int internal_init(void) { int ret = 0; @@ -128,9 +135,7 @@ int internal_shutdown(void) { -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; } Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-08-09 12:44:08 UTC (rev 671) +++ trunk/nic3com.c 2009-08-09 21:50:24 UTC (rev 672) @@ -20,10 +20,7 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #define BIOS_ROM_ADDR 0x04 @@ -99,9 +96,7 @@ free(pcidev_bdf); pci_cleanup(pacc); -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; } Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-08-09 12:44:08 UTC (rev 671) +++ trunk/satasii.c 2009-08-09 21:50:24 UTC (rev 672) @@ -22,10 +22,6 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> -#include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" #define PCI_VENDOR_ID_SII 0x1095 @@ -77,9 +73,7 @@ { free(pcidev_bdf); pci_cleanup(pacc); -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif + release_io_perms(); return 0; }

1 0

some questions about flashrom in windows edition
by zhou 09 Aug '09

09 Aug '09

hello, my honor! I am very interested in the program of flashrom,especially of the edition in windows,now I had worked on it for a few months,but there is some questions I couldn't understand, I wonder if you could offer me some help.The questions are showed as below: * 1,what's the use of the source code "Board_enable.c"? It looks so strange to me that I hardly understand? How I get something helpful? * 2,In order to modify the program under GNU,how can I test it? And how to debug it in details in windows? Is there any software ? * 3,As it is a complex program, where can I find out all the datasheets suitable? Are they free? I am looking forward your answers and please reply as soon as possible . My best wishes! james

2 1

[PATCH] Clean up before Windows support merge
by Carl-Daniel Hailfinger 09 Aug '09

09 Aug '09

Stefan pointed out a few issues with the current code which have to be worked around in the Windows support patch. Fix them. Remove unnecessary #include files. Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-winprepare/pcidev.c =================================================================== --- flashrom-winprepare/pcidev.c (Revision 670) +++ flashrom-winprepare/pcidev.c (Arbeitskopie) @@ -20,10 +20,7 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" uint32_t io_base_addr; Index: flashrom-winprepare/serprog.c =================================================================== --- flashrom-winprepare/serprog.c (Revision 670) +++ flashrom-winprepare/serprog.c (Arbeitskopie) @@ -39,8 +39,6 @@ char *serprog_param = NULL; -#define SERPROG_SUPPORT 1 - #if SERPROG_SUPPORT == 1 #define MSGHEADER "serprog:" Index: flashrom-winprepare/sst49lfxxxc.c =================================================================== --- flashrom-winprepare/sst49lfxxxc.c (Revision 670) +++ flashrom-winprepare/sst49lfxxxc.c (Arbeitskopie) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <errno.h> -#include <fcntl.h> -#include <sys/mman.h> #include <stdlib.h> #include "flash.h" Index: flashrom-winprepare/Makefile =================================================================== --- flashrom-winprepare/Makefile (Revision 670) +++ flashrom-winprepare/Makefile (Arbeitskopie) @@ -68,6 +68,8 @@ $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) FEATURE_CFLAGS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") +# Always enable serprog for now. Needs to be disabled on Windows. +FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' FEATURE_LIBS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") Index: flashrom-winprepare/dummyflasher.c =================================================================== --- flashrom-winprepare/dummyflasher.c (Revision 670) +++ flashrom-winprepare/dummyflasher.c (Arbeitskopie) @@ -21,10 +21,7 @@ #include <string.h> #include <stdlib.h> #include <ctype.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" char *dummytype = NULL; Index: flashrom-winprepare/chipset_enable.c =================================================================== --- flashrom-winprepare/chipset_enable.c (Revision 670) +++ flashrom-winprepare/chipset_enable.c (Arbeitskopie) @@ -29,7 +29,6 @@ #include <string.h> #include <sys/types.h> #include <sys/stat.h> -#include <sys/mman.h> #include <fcntl.h> #include "flash.h" @@ -968,7 +967,7 @@ } /* 4. Clean up */ - munmap(mmcr, getpagesize()); + physunmap(mmcr, getpagesize()); return 0; } Index: flashrom-winprepare/sb600spi.c =================================================================== --- flashrom-winprepare/sb600spi.c (Revision 670) +++ flashrom-winprepare/sb600spi.c (Arbeitskopie) @@ -21,7 +21,6 @@ */ #include <string.h> -#include <sys/mman.h> #include "flash.h" #include "spi.h" Index: flashrom-winprepare/ichspi.c =================================================================== --- flashrom-winprepare/ichspi.c (Revision 670) +++ flashrom-winprepare/ichspi.c (Arbeitskopie) @@ -33,7 +33,6 @@ */ #include <string.h> -#include <sys/mman.h> #include "flash.h" #include "spi.h" Index: flashrom-winprepare/cbtable.c =================================================================== --- flashrom-winprepare/cbtable.c (Revision 670) +++ flashrom-winprepare/cbtable.c (Arbeitskopie) @@ -22,11 +22,8 @@ */ #include <stdlib.h> -#include <fcntl.h> #include <sys/types.h> #include <string.h> -#include <errno.h> -#include <sys/mman.h> #include "flash.h" #include "coreboot_tables.h" -- http://www.hailfinger.org/

2 2

[commit] r671 - trunk
by svn＠flashrom.org 09 Aug '09

09 Aug '09

Author: hailfinger Date: 2009-08-09 14:44:08 +0200 (Sun, 09 Aug 2009) New Revision: 671 Modified: trunk/Makefile trunk/cbtable.c trunk/chipset_enable.c trunk/dummyflasher.c trunk/ichspi.c trunk/pcidev.c trunk/sb600spi.c trunk/serprog.c trunk/sst49lfxxxc.c Log: Remove unnecessary #include files. Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/Makefile 2009-08-09 12:44:08 UTC (rev 671) @@ -68,6 +68,8 @@ $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) FEATURE_CFLAGS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") +# Always enable serprog for now. Needs to be disabled on Windows. +FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' FEATURE_LIBS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") Modified: trunk/cbtable.c =================================================================== --- trunk/cbtable.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/cbtable.c 2009-08-09 12:44:08 UTC (rev 671) @@ -22,11 +22,8 @@ */ #include <stdlib.h> -#include <fcntl.h> #include <sys/types.h> #include <string.h> -#include <errno.h> -#include <sys/mman.h> #include "flash.h" #include "coreboot_tables.h" Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/chipset_enable.c 2009-08-09 12:44:08 UTC (rev 671) @@ -29,7 +29,6 @@ #include <string.h> #include <sys/types.h> #include <sys/stat.h> -#include <sys/mman.h> #include <fcntl.h> #include "flash.h" @@ -968,7 +967,7 @@ } /* 4. Clean up */ - munmap(mmcr, getpagesize()); + physunmap(mmcr, getpagesize()); return 0; } Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/dummyflasher.c 2009-08-09 12:44:08 UTC (rev 671) @@ -21,10 +21,7 @@ #include <string.h> #include <stdlib.h> #include <ctype.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" char *dummytype = NULL; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/ichspi.c 2009-08-09 12:44:08 UTC (rev 671) @@ -33,7 +33,6 @@ */ #include <string.h> -#include <sys/mman.h> #include "flash.h" #include "spi.h" Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/pcidev.c 2009-08-09 12:44:08 UTC (rev 671) @@ -20,10 +20,7 @@ #include <stdlib.h> #include <string.h> -#include <fcntl.h> #include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> #include "flash.h" uint32_t io_base_addr; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/sb600spi.c 2009-08-09 12:44:08 UTC (rev 671) @@ -21,7 +21,6 @@ */ #include <string.h> -#include <sys/mman.h> #include "flash.h" #include "spi.h" Modified: trunk/serprog.c =================================================================== --- trunk/serprog.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/serprog.c 2009-08-09 12:44:08 UTC (rev 671) @@ -39,8 +39,6 @@ char *serprog_param = NULL; -#define SERPROG_SUPPORT 1 - #if SERPROG_SUPPORT == 1 #define MSGHEADER "serprog:" Modified: trunk/sst49lfxxxc.c =================================================================== --- trunk/sst49lfxxxc.c 2009-08-03 09:35:20 UTC (rev 670) +++ trunk/sst49lfxxxc.c 2009-08-09 12:44:08 UTC (rev 671) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <errno.h> -#include <fcntl.h> -#include <sys/mman.h> #include <stdlib.h> #include "flash.h"

1 0

GSoCs Winflashrom versus r126.
by Luc Verhaegen 09 Aug '09

09 Aug '09

3 4

AMIC A290021T-70
by Helmut Adrigan 08 Aug '09

08 Aug '09

hi i found this AMIC A290021T-70 chip in my ABIT BX133-Raid V 1.01 (Intel 440BX Chipset) Mainboard. greetz

1 0

A290021T-70
by Helmut Adrigan 08 Aug '09

08 Aug '09

hi, many thx

1 0

ICH6-ICH10 flash decode debug, IDSEL=0 hardcode
by Carl-Daniel Hailfinger 07 Aug '09

07 Aug '09

Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode settings to the debug output. This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Hardcode IDSEL=0 for the top 8 MB for now. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich6_fwh_idsel_debug/chipset_enable.c =================================================================== --- flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Revision 670) +++ flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Arbeitskopie) @@ -192,11 +192,45 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { + /* + * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and + * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and + * FB_DEC_EN2. + */ return enable_flash_ich(dev, name, 0x4e); } static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { + uint32_t fwh_conf; + int i; + + /* Ignore all legacy ranges below 1 MB. */ + /* FWH_SEL1 */ + fwh_conf = pci_read_long(dev, 0xd0); + for (i = 7; i >= 0; i--) + printf_debug("\n0xff%02x0000/0xff%02x0000 FWH IDSEL: 0x%x, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, 0xd4); + for (i = 3; i >= 0; i--) + printf_debug("\n0xff%02x0000/0xff%02x0000 FWH IDSEL: 0x%x, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_DEC_EN1 */ + fwh_conf = pci_read_word(dev, 0xd8); + for (i = 7; i >= 0; i--) + printf_debug("0xff%02x0000/0xff%02x0000 FWH decode %sabled, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis"); + for (i = 3; i >= 0; i--) + printf_debug("0xff%02x0000/0xff%02x0000 FWH decode %sabled, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> i) & 0x1 ? "en" : "dis"); + /* Gross unmergeable hack to pick IDSEL=0 for top 8 MB */ + printf("\nSetting IDSEL=0 for top 8 MB"); + pci_write_word(dev, 0xd0, 0x00000000); return enable_flash_ich(dev, name, 0xdc); } -- http://www.hailfinger.org/

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SPIPGM bug for SST25*
by Carl-Daniel Hailfinger 05 Aug '09

05 Aug '09

Hi RayeR, I found that SST25 flash only allows one-byte write and no page write. But it uses the normal page write opcode. To fix this, SPI_FLASH_PAGE_SIZE must be 1 instead of 256 for SST25 family. Regards, Carl-Daniel

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[PATCH] Fix SPI multicommand endless loop
by Carl-Daniel Hailfinger 03 Aug '09

03 Aug '09

Fix SPI multicommand endless loop in default_spi_send_multicommand. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_multicommand_loopfix/spi.c =================================================================== --- flashrom-spi_multicommand_loopfix/spi.c (Revision 669) +++ flashrom-spi_multicommand_loopfix/spi.c (Arbeitskopie) @@ -147,6 +147,7 @@ while ((spicommands->writecnt || spicommands->readcnt) && !result) { result = spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); + spicommands++; } return result; } -- http://www.hailfinger.org/

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[commit] r670 - trunk
by svn＠flashrom.org 03 Aug '09

03 Aug '09

Author: hailfinger Date: 2009-08-03 11:35:20 +0200 (Mon, 03 Aug 2009) New Revision: 670 Modified: trunk/spi.c Log: Fix SPI multicommand endless loop in default_spi_send_multicommand. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-30 13:32:26 UTC (rev 669) +++ trunk/spi.c 2009-08-03 09:35:20 UTC (rev 670) @@ -147,6 +147,7 @@ while ((spicommands->writecnt || spicommands->readcnt) && !result) { result = spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); + spicommands++; } return result; }

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[PATCH] ICH6-ICH10 flash decode debugging
by Carl-Daniel Hailfinger 30 Jul '09

30 Jul '09

Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decode settings to the debug output. This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich6_fwh_idsel_debug/chipset_enable.c =================================================================== --- flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Revision 667) +++ flashrom-ich6_fwh_idsel_debug/chipset_enable.c (Arbeitskopie) @@ -192,11 +192,43 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { + /* + * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and + * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and + * FB_DEC_EN2. + */ return enable_flash_ich(dev, name, 0x4e); } static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { + uint32_t fwh_conf; + int i; + + /* Ignore all legacy ranges below 1 MB. */ + /* FWH_SEL1 */ + fwh_conf = pci_read_long(dev, 0xd0); + for (i = 7; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH IDSEL: 0x%x, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, 0xd4); + for (i = 3; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH IDSEL: 0x%x, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> (i * 4)) & 0xf); + /* FWH_DEC_EN1 */ + fwh_conf = pci_read_word(dev, 0xd8); + for (i = 7; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH decode %sabled, ", + i * 0x8 + 0xc0, i * 0x8 + 0x80, + (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis"); + for (i = 3; i >= 0; i--) + printf_debug("0xff%02x/0xff%02x FWH decode %sabled, ", + i * 0x10 + 0x40, i * 0x10, + (fwh_conf >> i) & 0x1 ? "en" : "dis"); + printf_debug("\n"); return enable_flash_ich(dev, name, 0xdc); } -- http://www.hailfinger.org/

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