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[commit] r739 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: hailfinger Date: 2009-10-01 15:16:32 +0200 (Thu, 01 Oct 2009) New Revision: 739 Modified: trunk/sb600spi.c trunk/spi.c Log: Introduce proper error checking for SPI programming. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-10-01 13:15:01 UTC (rev 738) +++ trunk/sb600spi.c 2009-10-01 13:16:32 UTC (rev 739) @@ -48,9 +48,9 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; + int i; int total_size = flash->total_size * 1024; - int result; + int result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -63,10 +63,10 @@ printf("Programming flash"); for (i = 0; i < total_size; i++, buf++) { - result = spi_byte_program(i, *buf); + result = spi_nbyte_program(i, buf, 1); if (result) { - // spi_byte_program reported the error for us already - printf_debug("... continuing anyway.\n"); + fprintf(stderr, "Write error!\n"); + return result; } /* wait program complete. */ @@ -76,7 +76,7 @@ ; } printf(" done.\n"); - return rc; + return result; } static void reset_internal_fifo_pointer(void) Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-10-01 13:15:01 UTC (rev 738) +++ trunk/spi.c 2009-10-01 13:16:32 UTC (rev 739) @@ -970,7 +970,7 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; + int i, result = 0; spi_disable_blockprotect(); /* Erase first */ @@ -981,7 +981,9 @@ } printf("done.\n"); for (i = 0; i < total_size; i++) { - spi_byte_program(i, buf[i]); + result = spi_byte_program(i, buf[i]); + if (result) + return 1; while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(10); }

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[PATCH] eraseblocks for mx25
by Carl-Daniel Hailfinger 01 Oct '09

01 Oct '09

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> someone else please commit. Index: flashrom-eraseblocks_mx25/flashchips.c =================================================================== --- flashrom-eraseblocks_mx25/flashchips.c (Revision 719) +++ flashrom-eraseblocks_mx25/flashchips.c (Arbeitskopie) @@ -44,6 +44,11 @@ * .probe = Probe function * .probe_timing = Probe function delay * .erase = Chip erase function + * .block_erasers[] = Array of erase layouts and erase functions + * { + * .eraseblocks[] = Array of { blocksize, blockcount } + * .block_erase = Block erase function + * } * .write = Chip write function * .read = Chip read function */ @@ -1235,20 +1240,16 @@ { .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_52, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1274,16 +1275,13 @@ { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 2} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1304,6 +1302,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1320,6 +1337,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1336,6 +1372,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1352,6 +1407,25 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + }, { + .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D/MX25L1635D */ + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, Index: flashrom-eraseblocks_mx25/flashchips.h =================================================================== --- flashrom-eraseblocks_mx25/flashchips.h (Revision 719) +++ flashrom-eraseblocks_mx25/flashchips.h (Arbeitskopie) @@ -251,7 +251,7 @@ * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ +#define MX_25L512 0x2010 /* Same as MX25V512 */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 #define MX_25L4005 0x2013 /* MX25L4005{,A} */ -- http://www.hailfinger.org/

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[commit] r738 - trunk
by svn＠flashrom.org 01 Oct '09

01 Oct '09

Author: hailfinger Date: 2009-10-01 15:15:01 +0200 (Thu, 01 Oct 2009) New Revision: 738 Modified: trunk/flashchips.c trunk/flashchips.h Log: Add comments about the meaning of block erase related struct flashchip members. Cosmetics: Place curly brackets on a common line. Add MX25V512 as alias name to MX25L512. Add MX25V8005 as alias name to MX25L8005. Add erase block definitions for MX25L2005, MX25L4005, MX25L8005, MX25L1605 and change their status to TEST_OK_PRW where applicable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-30 18:29:55 UTC (rev 737) +++ trunk/flashchips.c 2009-10-01 13:15:01 UTC (rev 738) @@ -44,6 +44,11 @@ * .probe = Probe function * .probe_timing = Probe function delay * .erase = Chip erase function + * .block_erasers[] = Array of erase layouts and erase functions + * { + * .eraseblocks[] = Array of { blocksize, blockcount } + * .block_erase = Block erase function + * } * .write = Chip write function * .read = Chip read function */ @@ -1235,20 +1240,16 @@ { .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_52, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1274,16 +1275,13 @@ { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, - }, - { + }, { .eraseblocks = { {64 * 1024, 2} }, .block_erase = spi_block_erase_d8, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_60, - }, - { + }, { .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, @@ -1303,7 +1301,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1316,10 +1333,29 @@ .model_id = MX_25L4005, .total_size = 512, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1332,10 +1368,29 @@ .model_id = MX_25L8005, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -1348,10 +1403,29 @@ .model_id = MX_25L1605, .total_size = 2048, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + }, { + .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, .write = spi_chip_write_256, .read = spi_chip_read, }, Modified: trunk/flashchips.h =================================================================== --- trunk/flashchips.h 2009-09-30 18:29:55 UTC (rev 737) +++ trunk/flashchips.h 2009-10-01 13:15:01 UTC (rev 738) @@ -251,11 +251,11 @@ * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ +#define MX_25L512 0x2010 /* Same as MX25V512 */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 #define MX_25L4005 0x2013 /* MX25L4005{,A} */ -#define MX_25L8005 0x2014 +#define MX_25L8005 0x2014 /* Same as MX25V8005 */ #define MX_25L1605 0x2015 /* MX25L1605{,A,D} */ #define MX_25L3205 0x2016 /* MX25L3205{,A} */ #define MX_25L6405 0x2017 /* MX25L3205{,D} */

1 0

Re: [flashrom] 'ERASED FAILED!' messages for ICH2 / SST49LF0002A/B
by Allan Bjorklund 30 Sep '09

30 Sep '09

On Wed Sep 30 5:03 , Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> sent: > >> Output of superiotool -dV: >> >> superiotool r >> > >Can you tell us which superiotool revision this is? Straight from >subversion or from some distribution package? In theory, superiotool >should have printed a revision number. It was from this web page, which I assume is the current svn snapshot: http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool I chose the zip archive link near the bottom of the page to retrieve the source. --Allan

2 1

[PATCH] Add -p gfxnvidia for flashing NVIDIA graphics cards
by Uwe Hermann 30 Sep '09

30 Sep '09

See patch. Please do NOT try write/erase on any important cards yet, it doesn't seem to fully work properly yet and you could "brick" your card. I tested a "RIVA TNT2 Model 64/Model 64 Pro", which successfully identified and read a Winbond W29C011 chip, but erase and write behaved incorrect and I finally bricked the card. Will look into recovery soon (likely will work via software I assume, no hardware hacking strictly required I think/hope, we'll see). As for the list of supported cards: I have no idea which of those may work (i.e. have the same flash programming interface), maybe none, maybe all of them (and lots more NVIDIA cards), we'll see as soon as others test more cards. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 3

[commit] r737 - trunk
by svn＠flashrom.org 30 Sep '09

30 Sep '09

Author: uwe Date: 2009-09-30 20:29:55 +0200 (Wed, 30 Sep 2009) New Revision: 737 Added: trunk/gfxnvidia.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/pcidev.c Log: Add initial support for flashing some NVIDIA graphics cards. The new option is '-p gfxnvidia', rest of the interface is as usual. I tested a successful identify and read on a "RIVA TNT2 Model 64/Model 64 Pro" card for now, erase and write did NOT work properly so far! Please do not attempt to write/erase cards yet, unless you can recover! In addition to the NVIDIA handling code it was required to call programmer_shutdown() in a lot more places, otherwise the graphics card will be disabled in the init function, but never enabled again as the shutdown function is not called. The shutdown handling may be changed to use atexit() later. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/Makefile 2009-09-30 18:29:55 UTC (rev 737) @@ -74,6 +74,9 @@ # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes +# Always enable NVIDIA graphics cards for now. +CONFIG_GFXNVIDIA ?= yes + # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes @@ -107,6 +110,11 @@ OBJS += nic3com.o endif +ifeq ($(CONFIG_GFXNVIDIA), yes) +FEATURE_CFLAGS += -D'GFXNVIDIA_SUPPORT=1' +OBJS += gfxnvidia.o +endif + ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' OBJS += satasii.o Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flash.h 2009-09-30 18:29:55 UTC (rev 737) @@ -88,6 +88,9 @@ #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif +#if GFXNVIDIA_SUPPORT == 1 + PROGRAMMER_GFXNVIDIA, +#endif #if DRKAISER_SUPPORT == 1 PROGRAMMER_DRKAISER, #endif @@ -437,6 +440,13 @@ uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +/* gfxnvidia.c */ +int gfxnvidia_init(void); +int gfxnvidia_shutdown(void); +void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); +uint8_t gfxnvidia_chip_readb(const chipaddr addr); +extern struct pcidev_status gfx_nvidia[]; + /* drkaiser.c */ int drkaiser_init(void); int drkaiser_shutdown(void); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flashrom.8 2009-09-30 18:29:55 UTC (rev 737) @@ -140,6 +140,8 @@ .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp +.BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)" +.sp .BR "* drkaiser" " (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards)" .sp .BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controllers)" @@ -180,6 +182,7 @@ .sp Currently the following programmers support this mechanism: .BR nic3com , +.BR gfxnvidia , .BR satasii . .sp The it87spi programmer has an optional parameter which will set the I/O base Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/flashrom.c 2009-09-30 18:29:55 UTC (rev 737) @@ -92,6 +92,25 @@ }, #endif +#if GFXNVIDIA_SUPPORT == 1 + { + .name = "gfxnvidia", + .init = gfxnvidia_init, + .shutdown = gfxnvidia_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + #if DRKAISER_SUPPORT == 1 { .name = "drkaiser", @@ -824,6 +843,9 @@ #if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); #endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs(gfx_nvidia); +#endif #if DRKAISER_SUPPORT == 1 print_supported_pcidevs(drkaiser_pcidev); #endif @@ -868,6 +890,7 @@ for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) printf(" %s", flashes[i]->name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); + programmer_shutdown(); exit(1); } else if (!flashes[0]) { printf("No EEPROM/flash device found.\n"); @@ -890,6 +913,7 @@ return read_flash(flashes[0], filename); } // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } @@ -935,12 +959,14 @@ if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } if (!filename && !erase_it) { printf("Error: No filename specified.\n"); // FIXME: flash writes stay enabled! + programmer_shutdown(); exit(1); } @@ -956,6 +982,7 @@ fprintf(stderr, "Erase is not working on this chip. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -963,11 +990,14 @@ } if (erase_flash(flash)) { emergency_help_message(); + programmer_shutdown(); return 1; } } else if (read_it) { - if (read_flash(flash, filename)) + if (read_flash(flash, filename)) { + programmer_shutdown(); return 1; + } } else { struct stat image_stat; @@ -976,6 +1006,7 @@ "and erase is needed for write. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -985,6 +1016,7 @@ fprintf(stderr, "Write is not working on this chip. "); if (!force) { fprintf(stderr, "Aborting.\n"); + programmer_shutdown(); return 1; } else { fprintf(stderr, "Continuing anyway.\n"); @@ -992,14 +1024,17 @@ } if ((image = fopen(filename, "r")) == NULL) { perror(filename); + programmer_shutdown(); exit(1); } if (fstat(fileno(image), &image_stat) != 0) { perror(filename); + programmer_shutdown(); exit(1); } if (image_stat.st_size != flash->total_size * 1024) { fprintf(stderr, "Error: Image size doesn't match\n"); + programmer_shutdown(); exit(1); } @@ -1008,6 +1043,7 @@ fclose(image); if (numbytes != size) { fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); + programmer_shutdown(); return 1; } } @@ -1022,12 +1058,14 @@ printf("Writing flash chip... "); if (!flash->write) { fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n"); + programmer_shutdown(); return 1; } ret = flash->write(flash, buf); if (ret) { fprintf(stderr, "FAILED!\n"); emergency_help_message(); + programmer_shutdown(); return 1; } else { printf("COMPLETE.\n"); Added: trunk/gfxnvidia.c =================================================================== --- trunk/gfxnvidia.c (rev 0) +++ trunk/gfxnvidia.c 2009-09-30 18:29:55 UTC (rev 737) @@ -0,0 +1,104 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define PCI_VENDOR_ID_NVIDIA 0x10de + +uint8_t *nvidia_bar; + +struct pcidev_status gfx_nvidia[] = { + {0x10de, 0x0010, PCI_NT, "NVIDIA", "Mutara V08 [NV2]" }, + {0x10de, 0x0018, PCI_NT, "NVIDIA", "RIVA 128" }, + {0x10de, 0x0020, PCI_NT, "NVIDIA", "RIVA TNT" }, + {0x10de, 0x0028, PCI_NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, + {0x10de, 0x0029, PCI_NT, "NVIDIA", "RIVA TNT2 Ultra" }, + {0x10de, 0x002c, PCI_NT, "NVIDIA", "Vanta/Vanta LT" }, + {0x10de, 0x002d, PCI_OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, + {0x10de, 0x00a0, PCI_NT, "NVIDIA", "Aladdin TNT2" }, + {0x10de, 0x0100, PCI_NT, "NVIDIA", "GeForce 256" }, + {0x10de, 0x0101, PCI_NT, "NVIDIA", "GeForce DDR" }, + {0x10de, 0x0103, PCI_NT, "NVIDIA", "Quadro" }, + {0x10de, 0x0110, PCI_NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0111, PCI_NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0112, PCI_NT, "NVIDIA", "GeForce2 GO" }, + {0x10de, 0x0113, PCI_NT, "NVIDIA", "Quadro2 MXR" }, + {0x10de, 0x0150, PCI_NT, "NVIDIA", "GeForce2 GTS/Pro" }, + {0x10de, 0x0151, PCI_NT, "NVIDIA", "GeForce2 GTS" }, + {0x10de, 0x0152, PCI_NT, "NVIDIA", "GeForce2 Ultra" }, + {0x10de, 0x0153, PCI_NT, "NVIDIA", "Quadro2 Pro" }, + {0x10de, 0x0200, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0201, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0202, PCI_NT, "NVIDIA", "GeForce 3 nFX Ultra" }, + {0x10de, 0x0203, PCI_NT, "NVIDIA", "Quadro 3 DDC" }, + + {}, +}; + +int gfxnvidia_init(void) +{ + uint32_t reg32; + + get_io_perms(); + + io_base_addr = pcidev_init(PCI_VENDOR_ID_NVIDIA, PCI_BASE_ADDRESS_0, + gfx_nvidia, programmer_param); + io_base_addr += 0x300000; + printf("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); + + /* Allow access to flash interface (will disable screen). */ + reg32 = pci_read_long(pcidev_dev, 0x50); + reg32 &= ~(1 << 0); + pci_write_long(pcidev_dev, 0x50, reg32); + + nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int gfxnvidia_shutdown(void) +{ + uint32_t reg32; + + /* Disallow access to flash interface (and re-enable screen). */ + reg32 = pci_read_long(pcidev_dev, 0x50); + reg32 |= (1 << 0); + pci_write_long(pcidev_dev, 0x50, reg32); + + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) +{ + mmio_writeb(val, nvidia_bar + addr); +} + +uint8_t gfxnvidia_chip_readb(const chipaddr addr) +{ + return mmio_readb(nvidia_bar + addr); +} Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-09-28 13:15:16 UTC (rev 736) +++ trunk/pcidev.c 2009-09-30 18:29:55 UTC (rev 737) @@ -28,7 +28,8 @@ struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs) +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, + struct pcidev_status *devs) { int i; uint32_t addr; @@ -37,12 +38,16 @@ if (dev->device_id != devs[i].device_id) continue; - /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ + /* + * Don't use dev->base_addr[x] (as value for 'bar'), won't + * work on older libpci. + */ addr = pci_read_long(dev, bar) & ~0x03; printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, dev->vendor_id, - dev->device_id, dev->bus, dev->dev, dev->func); + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); if (devs[i].status == PCI_NT) { printf("===\nThis PCI device is UNTESTED. Please " @@ -57,7 +62,8 @@ return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf) +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, + struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; char *msg = NULL;

1 0

motherboard report: GA-MA770T-UD3P
by Kevin Sopp 28 Sep '09

28 Sep '09

Flashing the bios on the Gigabyte GA-MA770T-UD3P worked out of the box.

2 2

[commit] r736 - trunk
by svn＠flashrom.org 28 Sep '09

28 Sep '09

Author: hailfinger Date: 2009-09-28 15:15:16 +0200 (Mon, 28 Sep 2009) New Revision: 736 Added: trunk/bitbang_spi.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.c Log: This is the bitbanging SPI driver infrastructure. If you want support for a particular piece of hardware, just fill in a few functions in spi_bitbang_master_table. That's it. On top of this, the RayeR SPI flasher should be supportable in ~20 LOC. Tested, trace looks OK. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/Makefile 2009-09-28 13:15:16 UTC (rev 736) @@ -68,6 +68,9 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes +# Bitbanging SPI infrastructure is not used yet. +CONFIG_BITBANG_SPI ?= no + # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -94,6 +97,11 @@ endif endif +ifeq ($(CONFIG_BITBANG_SPI), yes) +FEATURE_CFLAGS += -D'BITBANG_SPI_SUPPORT=1' +OBJS += bitbang_spi.o +endif + ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o Added: trunk/bitbang_spi.c =================================================================== --- trunk/bitbang_spi.c (rev 0) +++ trunk/bitbang_spi.c 2009-09-28 13:15:16 UTC (rev 736) @@ -0,0 +1,161 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" +#include "spi.h" + +/* Length of half a clock period in usecs */ +int bitbang_half_period = 0; + +enum spi_bitbang_master spi_bitbang_master = SPI_BITBANG_INVALID; + +const struct spi_bitbang_master_entry spi_bitbang_master_table[] = { + {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ +}; + +const int spi_bitbang_master_count = ARRAY_SIZE(spi_bitbang_master_table); + +void bitbang_set_cs(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_cs(val); +} + +void bitbang_set_sck(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_sck(val); +} + +void bitbang_set_mosi(int val) +{ + spi_bitbang_master_table[spi_bitbang_master].set_mosi(val); +} + +int bitbang_get_miso(void) +{ + return spi_bitbang_master_table[spi_bitbang_master].get_miso(); +} + +int bitbang_spi_init(void) +{ + bitbang_set_cs(1); + bitbang_set_sck(0); + buses_supported = CHIP_BUSTYPE_SPI; + return 0; +} + +uint8_t bitbang_spi_readwrite_byte(uint8_t val) +{ + uint8_t ret = 0; + int i; + + for (i = 7; i >= 0; i--) { + bitbang_set_mosi((val >> i) & 1); + programmer_delay(bitbang_half_period); + bitbang_set_sck(1); + ret <<= 1; + ret |= bitbang_get_miso(); + programmer_delay(bitbang_half_period); + bitbang_set_sck(0); + } + return ret; +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *bufout = NULL; + static unsigned char *bufin = NULL; + static int oldbufsize = 0; + int bufsize = max(writecnt + readcnt, 260); + int i; + + /* Arbitrary size limitation here. We're only constrained by memory. */ + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + + if (bufsize != oldbufsize) { + bufout = realloc(bufout, bufsize); + if (!bufout) { + fprintf(stderr, "Out of memory!\n"); + if (bufin) + free(bufin); + exit(1); + } + bufin = realloc(bufout, bufsize); + if (!bufin) { + fprintf(stderr, "Out of memory!\n"); + if (bufout) + free(bufout); + exit(1); + } + } + + memcpy(bufout, writearr, writecnt); + /* Shift out 0x00 while reading data. */ + memset(bufout + writecnt, 0x00, readcnt); + /* Make sure any non-read data is 0xff. */ + memset(bufin + writecnt, 0xff, readcnt); + + bitbang_set_cs(0); + for (i = 0; i < readcnt + writecnt; i++) { + bufin[i] = bitbang_spi_readwrite_byte(bufout[i]); + } + programmer_delay(bitbang_half_period); + bitbang_set_cs(1); + programmer_delay(bitbang_half_period); + memcpy(readarr, bufin + writecnt, readcnt); + + return 0; +} + +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64k bytes. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + + printf_debug("total_size is %d\n", total_size); + for (i = 0; i < total_size; i += 256) { + int l, r; + if (i + 256 <= total_size) + l = 256; + else + l = total_size - i; + + if ((r = spi_nbyte_program(i, &buf[i], l))) { + fprintf(stderr, "%s: write fail %d\n", __FUNCTION__, r); + return 1; + } + + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + /* loop */; + } + + return 0; +} Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/flash.h 2009-09-28 13:15:16 UTC (rev 736) @@ -145,6 +145,21 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); +enum spi_bitbang_master { + SPI_BITBANG_INVALID /* This must always be the last entry. */ +}; + +extern const int spi_bitbang_master_count; + +extern enum spi_bitbang_master spi_bitbang_master; + +struct spi_bitbang_master_entry { + void (*set_cs) (int val); + void (*set_sck) (int val); + void (*set_mosi) (int val); + int (*get_miso) (void); +}; + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { @@ -444,6 +459,14 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); +/* bitbang_spi.c */ +extern int bitbang_half_period; +extern const struct spi_bitbang_master_entry spi_bitbang_master_table[]; +int bitbang_spi_init(void); +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); + /* flashrom.c */ extern char *programmer_param; extern int verbose; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-09-25 01:31:51 UTC (rev 735) +++ trunk/flashrom.c 2009-09-28 13:15:16 UTC (rev 736) @@ -693,6 +693,12 @@ fprintf(stderr, "SPI programmer table miscompilation!\n"); exit(1); } +#if BITBANG_SPI_SUPPORT == 1 + if (spi_bitbang_master_count - 1 != SPI_BITBANG_INVALID) { + fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); + exit(1); + } +#endif setbuf(stdout, NULL); while ((opt = getopt_long(argc, argv, optstring,

1 0

Success: flashing BIOS on MSI K9AG Neo2-Digital (MS-7368)
by christian.ch.heinz＠gmail.com 28 Sep '09

28 Sep '09

Hello flashrom people, here is a quick success report on using flashrom with the MS-7368 (revision 1.0; I don't believe there are any later revisions, but I'm not sure). The exact flashrom version used was v0.9.1, SVN revision r721. In particular, I first upgraded the BIOS from version 1.9 to 1.10 (named 1.A on the MSI website), then downgraded to 1.7 and re-upgraded to 1.8 and finally to 1.10 again, with a reboot following each flashing. I also played around with a few of the flashrom options and everything worked flawlessly OOTB. Some details: # ./flashrom -r ... flashrom v0.9.1-runknown No coreboot table found. Found chipset "AMD SB600", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Reading flash... done. # ./superiotool superiotool r4623 Found Fintek F71882FG/F71883FG (vid=0x3419, id=0x4105) at 0x4e Platform: Linux 2.6.30-ARCH x86_64 AMD Athlon(tm) Dual Core Processor 4850e Probably nothing more to add, except that flashrom absolutely rocks :) Thanks and kudos, ch

2 1

flashrom works with an asus M3A78-EM
by Joshua Roys 28 Sep '09

28 Sep '09

# flashrom -w M3A78-EM-1902.ROM flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... done. Programming flash................................ done. COMPLETE. Verifying flash... VERIFIED. Thanks, Joshua Roys

2 1

3C905CX-TX-M not supported (But flashrom thinks it is).
by Marko Kraljevic 25 Sep '09

25 Sep '09

Hi, the other day I got a 3C905CX-TX-M NIC. I don't have the computer I tested it on up and running right now, but it is non-functional. Flashrom can not detect the AT49BV512 on it. A forced read delivers all 0xFF's, which I assume it is pulling out of the ether. I guess it *could* be blank; It seems unlikely to not autodetect and function on a forced read though. Anyways, this wouldn't be an issue, but the PCI device ID is the same as the 3C905C-TX [dev_id 0x9200] (*iirc - it might be one of the other supported 3C905 NICs*), so flashrom reports it as a supported NIC. I guess there should be a note somewhere, specifying that flashrom doesn't support 3com NICs with the newer, smaller, BGA package ASIC. Here's a photo of the card. On mine the flash is soldered on, but I believe I've seen socketed versions in the past. If they're all soldered on, I guess it doesn't matter much - apart from saving someone the time of soldering on a socket. http://electrontube.org/open/3com_mod/3C905CX-TX-M.jpg I'll try and get that computer back up this weekend and post the output. Mark

3 5

[commit] r735 - trunk
by svn＠flashrom.org 25 Sep '09

25 Sep '09

Author: uwe Date: 2009-09-25 03:31:51 +0200 (Fri, 25 Sep 2009) New Revision: 735 Modified: trunk/print_wiki.c Log: Enable drkaiser programmer support in wiki output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-09-25 01:22:42 UTC (rev 734) +++ trunk/print_wiki.c 2009-09-25 01:31:51 UTC (rev 735) @@ -541,7 +541,7 @@ print_supported_pcidevs_wiki(nics_3com); #endif #if DRKAISER_SUPPORT == 1 - /* FIXME: drkaiser_pcidev is missing here. */ + print_supported_pcidevs_wiki(drkaiser_pcidev); #endif #if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii);

1 0

[commit] r734 - trunk
by svn＠flashrom.org 25 Sep '09

25 Sep '09

Author: uwe Date: 2009-09-25 03:22:42 +0200 (Fri, 25 Sep 2009) New Revision: 734 Modified: trunk/board_enable.c trunk/print.c trunk/print_wiki.c Log: Mark the following boards as OK: - ASUS M3A78-EM (reported by Christian Heinz <christian.ch.heinz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000629.html - MSI MS-7368 (K9AG Neo2-Digital) (reported by Joshua Roys <roysjosh(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000632.html - GIGABYTE GA-MA770T-UD3P (reported by Kevin Sopp <baraclese(a)googlemail.com>) http://www.flashrom.org/pipermail/flashrom/2009-September/000529.html - Elitegroup P6VAP-A+ Tested by Uwe Hermann <uwe(a)hermann-uwe.de> on hardware. Maximum supported chip size in this board is 256 KB. Small changes in print.c were required to adjust for longer board names. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/board_enable.c 2009-09-25 01:22:42 UTC (rev 734) @@ -1064,6 +1064,7 @@ { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, { "ASUS", "M2V", }, + { "ASUS", "M3A78-EM", }, { "ASUS", "P2B", }, { "ASUS", "P2B-D", }, { "ASUS", "P2B-DS", }, @@ -1075,6 +1076,7 @@ { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, + { "Elitegroup", "P6VAP-A+", }, { "GIGABYTE", "GA-6BXC", }, { "GIGABYTE", "GA-6BXDU", }, { "GIGABYTE", "GA-6ZMA", }, @@ -1083,6 +1085,7 @@ { "GIGABYTE", "GA-EX58-UD4P", }, { "GIGABYTE", "GA-MA78GPM-DS2H", }, { "GIGABYTE", "GA-MA790GP-DS4H", }, + { "GIGABYTE", "GA-MA770T-UD3P", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, { "MSI", "MS-6570 (K7N2)", }, @@ -1091,6 +1094,7 @@ { "MSI", "MS-7236 (945PL Neo3)", }, { "MSI", "MS-7255 (P4M890M)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", }, { "NEC", "PowerMate 2000", }, { "PC Engines", "Alix.1c", }, { "PC Engines", "Alix.2c2", }, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/print.c 2009-09-25 01:22:42 UTC (rev 734) @@ -181,7 +181,7 @@ for (j = 0; j < 25 - strlen(b[i].vendor); j++) printf(" "); printf("%s", b[i].name); - for (j = 0; j < 23 - strlen(b[i].name); j++) + for (j = 0; j < 28 - strlen(b[i].name); j++) printf(" "); printf("\n"); } @@ -196,7 +196,7 @@ boardcount++; printf("\nSupported boards which need write-enable code (total: %d):" - "\n\nVendor: Board: " + "\n\nVendor: Board: " "Required option:\n\n", boardcount); for (i = 0; b[i].vendor_name != NULL; i++) { @@ -204,7 +204,7 @@ for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) printf(" "); printf("%s", b[i].board_name); - for (j = 0; j < 25 - strlen(b[i].board_name); j++) + for (j = 0; j < 30 - strlen(b[i].board_name); j++) printf(" "); if (b[i].lb_vendor != NULL) printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-09-25 01:09:18 UTC (rev 733) +++ trunk/print_wiki.c 2009-09-25 01:22:42 UTC (rev 734) @@ -119,6 +119,7 @@ { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, { "ASUS", "M2V", "http://asus.com/Product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, + { "ASUS", "M3A78-EM", "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D" }, { "ASUS", "P2B", "http://www.motherboard.cz/mb/asus/P2B.htm" }, { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, @@ -130,6 +131,7 @@ { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, @@ -137,6 +139,7 @@ { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-MA770T-UD3P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, { "MSI", "MS-6570 (K7N2)", "http://www.msi-computer.de/index.php?func=proddesc&prod_no=519&maincat_no=1" }, @@ -145,6 +148,7 @@ { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, { "MSI", "MS-7255 (P4M890M)", "http://www.tcsbahamas.com/P4M89.htm" }, { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=prodcpusupport&maincat_no=1&cat2_no=170&c…" }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241" }, { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" },

1 0

[commit] r733 - trunk
by svn＠flashrom.org 25 Sep '09

25 Sep '09

Author: uwe Date: 2009-09-25 03:09:18 +0200 (Fri, 25 Sep 2009) New Revision: 733 Modified: trunk/flashchips.c Log: Mark the SST SST49LF003A/B as read-tested. See http://www.coreboot.org/pipermail/coreboot/2009-July/050675.html. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-25 01:05:06 UTC (rev 732) +++ trunk/flashchips.c 2009-09-25 01:09:18 UTC (rev 733) @@ -2132,7 +2132,7 @@ .model_id = SST_49LF003A, .total_size = 384, .page_size = 64 * 1024, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PR, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub,

1 0

[commit] r732 - trunk
by svn＠flashrom.org 25 Sep '09

25 Sep '09

Author: uwe Date: 2009-09-25 03:05:06 +0200 (Fri, 25 Sep 2009) New Revision: 732 Modified: trunk/chipset_enable.c Log: Add chipset support for VIA VT82C596 by adding a PCI ID (trivial). This is successfully tested by me on the Elitegroup P6VAP-A+ board. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-09-23 22:01:33 UTC (rev 731) +++ trunk/chipset_enable.c 2009-09-25 01:05:06 UTC (rev 732) @@ -1046,6 +1046,7 @@ {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},

1 0

actual bios settings
by Bart Swinnen 24 Sep '09

24 Sep '09

Hi Does flashrom normally also reads actual BIOS setting of a board? I'm trying flashrom on IEI Wafer-LX-800 It finds PMC Pm49FL004 device and I can read it. It gives me a 512k bin file. If I write this file to another board of its kind, I still have the actual settings of that board and not the one stored in the board where I had the bin from. Am I missing something? Kind regards Bart Swinnen

3 4

[PATCH] Switch SST49LF004A/B to blockwise erase
by Carl-Daniel Hailfinger 24 Sep '09

24 Sep '09

Switch SST49LF004A/B to block erase, remove the hack which simulated (unsupported) chip erase. Annotate SST49LF004B quirks for TBL#. Add TEST_OK_PRW which is useful when a PREW chip gets a new erase routine. Change a few erase function prototypes to use unsigned int instead of int. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst49lf004b_eraseblocks/flash.h =================================================================== --- flashrom-sst49lf004b_eraseblocks/flash.h (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/flash.h (Arbeitskopie) @@ -225,6 +225,7 @@ #define TEST_OK_WRITE (1 << 3) #define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) #define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) +#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) #define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) #define TEST_OK_MASK 0x0f @@ -596,8 +597,8 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, int blocksize); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size); @@ -657,6 +658,7 @@ /* sst_fwhub.c */ int probe_sst_fwhub(struct flashchip *flash); int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); /* w39v040c.c */ Index: flashrom-sst49lf004b_eraseblocks/jedec.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/jedec.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/jedec.c (Arbeitskopie) @@ -175,7 +175,7 @@ return 0; } -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize) +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; @@ -204,7 +204,7 @@ return 0; } -int erase_block_jedec(struct flashchip *flash, unsigned int block, int blocksize) +int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) { chipaddr bios = flash->virtual_memory; Index: flashrom-sst49lf004b_eraseblocks/flashchips.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/flashchips.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/flashchips.c (Arbeitskopie) @@ -2141,6 +2141,9 @@ }, { + /* Contrary to the data sheet, TBL# on the SST49LF004B affects the top 128kB (instead of 64kB) + * and is only honored for 64k block erase, but not 4k sector erase. + */ .vendor = "SST", .name = "SST49LF004A/B", .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ @@ -2148,10 +2151,23 @@ .model_id = SST_49LF004A, .total_size = 512, .page_size = 64 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ - .erase = erase_sst_fwhub, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_sector_jedec, /* missing unlock */ + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */ + }, + }, .write = write_sst_fwhub, .read = read_memmapped, }, Index: flashrom-sst49lf004b_eraseblocks/sst_fwhub.c =================================================================== --- flashrom-sst49lf004b_eraseblocks/sst_fwhub.c (Revision 727) +++ flashrom-sst49lf004b_eraseblocks/sst_fwhub.c (Arbeitskopie) @@ -94,7 +94,7 @@ return 1; } -int erase_sst_fwhub_block(struct flashchip *flash, int offset, int page_size) +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size) { uint8_t blockstatus = clear_sst_fwhub_block_lock(flash, offset); -- http://www.hailfinger.org/

2 4

[commit] r731 - trunk
by svn＠flashrom.org 24 Sep '09

24 Sep '09

Author: hailfinger Date: 2009-09-24 00:01:33 +0200 (Thu, 24 Sep 2009) New Revision: 731 Modified: trunk/flash.h trunk/flashchips.c trunk/jedec.c trunk/sst_fwhub.c Log: Switch SST49LF004A/B to block erase, remove the hack which simulated (unsupported) chip erase. Annotate SST49LF004B quirks for TBL#. Add TEST_OK_PRW which is useful when a PREW chip gets a new erase routine. Change a few erase function prototypes to use unsigned int instead of int. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/flash.h 2009-09-23 22:01:33 UTC (rev 731) @@ -225,6 +225,7 @@ #define TEST_OK_WRITE (1 << 3) #define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) #define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) +#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) #define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) #define TEST_OK_MASK 0x0f @@ -596,8 +597,8 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, int blocksize); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size); @@ -657,6 +658,7 @@ /* sst_fwhub.c */ int probe_sst_fwhub(struct flashchip *flash); int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); /* w39v040c.c */ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/flashchips.c 2009-09-23 22:01:33 UTC (rev 731) @@ -2141,6 +2141,9 @@ }, { + /* Contrary to the data sheet, TBL# on the SST49LF004B affects the top 128kB (instead of 64kB) + * and is only honored for 64k block erase, but not 4k sector erase. + */ .vendor = "SST", .name = "SST49LF004A/B", .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ @@ -2151,7 +2154,20 @@ .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, .probe_timing = 1, /* 150 ns | routine is wrapper to probe_jedec (sst_fwhub.c) */ - .erase = erase_sst_fwhub, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_sector_jedec, /* missing unlock */ + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */ + }, + }, .write = write_sst_fwhub, .read = read_memmapped, }, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/jedec.c 2009-09-23 22:01:33 UTC (rev 731) @@ -175,7 +175,7 @@ return 0; } -int erase_sector_jedec(struct flashchip *flash, unsigned int page, int pagesize) +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; @@ -204,7 +204,7 @@ return 0; } -int erase_block_jedec(struct flashchip *flash, unsigned int block, int blocksize) +int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) { chipaddr bios = flash->virtual_memory; Modified: trunk/sst_fwhub.c =================================================================== --- trunk/sst_fwhub.c 2009-09-23 21:58:34 UTC (rev 730) +++ trunk/sst_fwhub.c 2009-09-23 22:01:33 UTC (rev 731) @@ -94,7 +94,7 @@ return 1; } -int erase_sst_fwhub_block(struct flashchip *flash, int offset, int page_size) +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size) { uint8_t blockstatus = clear_sst_fwhub_block_lock(flash, offset);

1 0

[PATCH] Change status of SST49LF020A to TEST_OK_PREW
by Nils 23 Sep '09

23 Sep '09

The attached patch changes the status of the SST49LF020A to TEST_OK_PREW. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> I tested it on the Wyse Winterm S50 see attached test results. Thanks, Nils.

2 1

[commit] r730 - trunk
by svn＠flashrom.org 23 Sep '09

23 Sep '09

Author: hailfinger Date: 2009-09-23 23:58:34 +0200 (Wed, 23 Sep 2009) New Revision: 730 Modified: trunk/flashchips.c Log: Change the status of the SST49LF020A to TEST_OK_PREW. I tested it on the Wyse Winterm S50 see attached test results. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-09-23 02:09:23 UTC (rev 729) +++ trunk/flashchips.c 2009-09-23 21:58:34 UTC (rev 730) @@ -2244,7 +2244,7 @@ .model_id = SST_49LF020A, .total_size = 256, .page_size = 4 * 1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .erase = erase_49lf040,

1 0

Re: [flashrom] flashrom failure on Shuttle barebone
by Ulf Mehlig 23 Sep '09

23 Sep '09

00:00.0 Memory controller [0580]: nVidia Corporation CK804 Memory Controller [10de:005e] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 5e 00 06 00 b0 00 a3 00 80 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 97 12 36 50 08 e0 e0 01 22 00 11 11 d0 00 00 00 50: 23 06 7f 80 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 00 00 70: 44 44 00 00 d0 09 00 00 00 00 00 00 88 00 00 00 80: 13 ff 88 00 fa 00 00 00 03 00 00 00 61 00 00 00 90: 0e 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation CK804 ISA Bridge [10de:0050] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 50 00 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 97 12 36 50 00 f0 ff fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 01 40 00 00 01 44 00 00 01 48 00 00 00 01 f9 ff 70: 10 00 ff ff 41 00 00 00 00 00 44 19 00 d2 20 01 80: 09 d0 00 12 01 08 00 00 c0 00 00 01 00 00 00 00 90: 00 00 00 00 00 00 00 00 21 64 87 a9 de bc 00 00 a0: 03 00 10 41 00 00 00 00 00 00 00 00 00 00 00 00 b0: 90 02 ef 02 00 00 00 00 00 00 00 00 00 00 00 00 c0: 35 82 80 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 14 10 01 00 00 00 d0 00 80 38 00 00 61 44 44 11 f0: 5a ff 5f bf 00 00 00 c0 10 ff ff ff 00 00 30 07 00:01.1 SMBus [0c05]: nVidia Corporation CK804 SMBus [10de:0052] (rev a2) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 12 Region 0: I/O ports at e400 [size=32] Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus 00: de 10 52 00 01 00 b0 00 a2 00 05 0c 00 00 80 00 10: 01 e4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4c 00 00 41 4c 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0c 01 03 01 40: 97 12 36 50 01 00 02 c0 00 00 00 00 00 00 00 00 50: 01 4c 00 00 41 4c 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005a] (rev a2) (prog-if 10 [OHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at d8204000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 5a 00 07 00 b0 00 a2 10 03 0c 00 00 80 00 10: 00 40 20 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 40: 97 12 36 50 01 00 02 fe 00 00 00 00 00 00 00 00 50: 07 00 00 00 1d 47 40 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 03 0d 30 07 00:02.1 USB Controller [0c03]: nVidia Corporation CK804 USB Controller [10de:005b] (rev a3) (prog-if 20 [EHCI]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at feb00000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: de 10 5b 00 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 00 b0 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 40: 97 12 36 50 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 3f 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 e4 00 80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 33 00 11 22 44 00 00 00 ff 03 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 ff ff ff 05 11 30 07 00:06.0 IDE interface [0101]: nVidia Corporation CK804 IDE [10de:0053] (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: AMD_IDE 00: de 10 53 00 05 00 b0 00 a2 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f0 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 97 12 36 50 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 01 00 00 00 00 00 a8 a8 a8 20 2a 00 99 20 60: 00 00 00 c5 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 10 e0 63 33 00 00 02 10 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 ff ff ff 0a 15 30 07 00:07.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0054] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at d800 [size=16] Region 5: Memory at d8202000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 54 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00 20: 01 d8 00 00 00 20 20 d8 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 40: 97 12 36 50 01 00 02 00 00 00 00 00 00 00 00 00 50: 17 00 00 15 00 00 00 00 a8 20 a8 20 66 00 20 20 60: 00 c7 00 c7 51 0c 00 00 08 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 c0 00 a0 4d 1e 00 00 02 04 00 80 c4 2f 90: 00 00 02 08 00 00 00 00 06 00 06 10 00 00 01 01 a0: 50 01 00 7c 00 00 00 00 00 00 00 00 33 bb aa 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 02 a8 d0: 0a 00 02 04 42 00 00 00 00 00 00 00 01 00 00 e0 e0: 0a 00 02 04 42 00 00 00 00 00 00 00 89 32 c1 e0 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 09 46 32 07 00:08.0 IDE interface [0101]: nVidia Corporation CK804 Serial ATA Controller [10de:0055] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c400 [size=16] Region 5: Memory at d8201000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv 00: de 10 55 00 07 00 b0 00 a3 85 01 01 00 00 00 00 10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00 20: 01 c4 00 00 00 10 20 d8 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: de 10 84 cb 01 00 02 00 00 00 00 00 00 00 00 00 50: 17 00 00 15 00 00 00 00 a8 a8 a8 a8 aa 00 99 99 60: 00 00 00 00 51 0c 00 00 08 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 06 00 06 10 00 00 01 01 a0: 50 01 00 00 00 00 00 00 00 00 00 00 33 bb aa 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 02 a8 d0: 0a 00 02 04 42 00 00 00 00 00 00 00 44 61 01 01 e0: 0a 00 02 04 42 00 00 00 00 00 00 00 b1 88 85 00 f0: 00 00 00 00 00 00 00 00 00 ff ff ff 00 00 30 07 00:09.0 PCI bridge [0604]: nVidia Corporation CK804 PCI Bridge [10de:005c] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=32 I/O behind bridge: 0000a000-0000afff Memory behind bridge: d8100000-d81fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR+ BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- 00: de 10 5c 00 07 01 a0 00 a2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 20 a0 a0 80 a2 20: 10 d8 10 d8 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 02 40: 00 00 07 00 01 00 02 00 07 00 00 00 00 00 44 01 50: 00 00 fe 7f 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 02 00 00 02 a0 00 00 00 00 00 00 08 00 00 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Bridge [0680]: nVidia Corporation CK804 Ethernet Controller [10de:0057] (rev a3) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at d8200000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Kernel driver in use: forcedeth 00: de 10 57 00 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 00 20 d8 01 b0 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 01 14 40: 97 12 36 50 01 00 02 fe 00 01 00 00 0a 00 00 10 50: 05 64 84 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0f 00 00 00 08 00 02 a8 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 11 00 00 00 40 ff ff ff 05 25 32 07 00:0b.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x2, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 8, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 21 34 01 03 90: 00 00 41 10 80 0c 40 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 4, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 02 90: 00 00 41 10 00 05 20 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 06 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 01 90: 00 00 81 10 00 05 10 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.0 PCI bridge [0604]: nVidia Corporation CK804 PCIE Bridge [10de:005d] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: d8000000-d80fffff Prefetchable memory behind bridge: 00000000d0000000-00000000d7ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] MSI: Enable- Count=1/2 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> 00: de 10 5d 00 07 01 10 00 a3 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 91 91 00 00 20: 00 d8 00 d8 01 d0 f1 d7 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 0e 00 40: 01 48 02 f8 00 00 00 00 05 58 82 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 01 35 01 00 90: 00 00 01 11 80 25 08 00 c0 01 40 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 01 00 e4 00 00 00 20 c8 00 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 69 01 61 01 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 e0 00 80 ff ef 00 03 b0 fe 00 80 c0 fe 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 80 00 00 d3 fe 00 c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 20 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 de e0 07 00 de e0 07 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 07 00 00 00 00 00 00 00 42 35 82 13 31 0b 00 00 90: 80 8e 05 38 07 07 7b 3e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 4e 64 12 46 2d 00 00 00 df ef 00 08 ef 63 eb 32 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 68 d0 c8 05 86 52 42 b8 31 c2 ae 86 0c 09 78 09 e0: 20 40 88 32 48 02 18 00 c5 13 13 00 80 09 69 30 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 00 08 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 eb 68 6f 60: bb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1a 22 00 00 80: 00 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 20 82 89 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3f 00 00 20 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 01 a7 0d 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 20 04 57 0c 19 11 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: ATI Technologies Inc RV370 5B60 [Radeon X300 (PCIE)] [1002:5b60] (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. Device [1462:0320] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at 9000 [size=256] Region 2: Memory at d8030000 (32-bit, non-prefetchable) [size=64K] [virtual] Expansion ROM at d8000000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: radeonfb 00: 02 10 60 5b 07 00 10 00 00 00 00 03 08 00 80 00 10: 08 00 00 d0 01 90 00 00 00 00 03 d8 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 20 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 0c 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 20 03 50: 01 58 02 06 00 00 00 00 10 80 01 00 a0 04 2c 01 60: 10 08 00 00 01 ad 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.1 Display controller [0380]: ATI Technologies Inc RV370 [Radeon X300SE] [1002:5b70] Subsystem: Micro-Star International Co., Ltd. Device [1462:0321] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: Memory at d8020000 (32-bit, non-prefetchable) [disabled] [size=64K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <4us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 00: 02 10 70 5b 00 00 10 00 00 00 80 03 08 00 00 00 10: 00 00 02 d8 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 21 03 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 02 06 00 00 00 00 10 00 01 00 80 04 00 00 60: 00 00 00 00 01 ad 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:06.0 Multimedia audio controller [0401]: VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller [1412:1724] (rev 01) Subsystem: Holco Enterprise Co, Ltd/Shuttle Computer Device [1297:5036] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at a000 [size=32] Region 1: I/O ports at a400 [size=128] Capabilities: [80] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ICE1724 00: 12 14 24 17 05 00 10 02 01 00 01 04 00 20 00 00 10: 01 a0 00 00 01 a4 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 97 12 36 50 30: 00 00 00 00 80 00 00 00 00 00 00 00 0c 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:07.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] (rev 80) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at d8100000 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at a800 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot +,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: firewire_ohci 00: 06 11 44 30 07 00 10 02 80 10 00 0c 08 20 00 00 10: 00 00 10 d8 01 a8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 44 30 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 00 20 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 02 e4 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- Dr. Ulf Mehlig · Laboratório de Biologia Vegetal Instituto de Estudos Costeiros (IECOS) Universidade Federal do Pará, Campus Bragança · Brazil ----------------------------------------------------------------------

3 2

[PATCH_v2] Enable flashrom on Wyse Winterm S50.
by Nils 23 Sep '09

23 Sep '09

Enable flashrom on Wyse Winterm S50. On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so flashrom doesn`t detect the cs5536. This patch is adding the cs5536 isa id [1022:2090] for chip detect. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> nils@debian:~/flashrom$ sudo flashrom flashrom v0.9.1-r727 No coreboot table found. Found chipset "AMD CS5536_2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF020A" (256 KB, LPC) at physical address 0xfffc0000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === No operations were specified. nils@debian:~/flashrom$ Nils

2 1

[commit] r729 - trunk
by svn＠flashrom.org 23 Sep '09

23 Sep '09

Author: hailfinger Date: 2009-09-23 04:09:23 +0200 (Wed, 23 Sep 2009) New Revision: 729 Modified: trunk/chipset_enable.c Log: Enable flashrom on Wyse Winterm S50. On the Wyse Winterm S50 lspci doesn`t show the cs5536 hostbridge and so flashrom doesn`t detect the cs5536. This patch is adding the cs5536 isa id [1022:2090] for chip detect. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-09-23 02:05:12 UTC (rev 728) +++ trunk/chipset_enable.c 2009-09-23 02:09:23 UTC (rev 729) @@ -972,6 +972,7 @@ {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},

1 0

dell s1850
by ron minnich 23 Sep '09

23 Sep '09

Using my GPIO finder posted earlier, I have the gpio needed to enable flashing on the dell. I would like to get a patch together but have not done this mainboard enable thing. I would like to do this in the most-approved manner. Basically need to match the dell mainboard, find the 8086:24d0 bridge, look up a BAR, and twiddle one little gpio line. The northbridge looks like this: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 4a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 34 3e 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 suggestions welcome. ron

2 7

[commit] r728 - trunk
by svn＠flashrom.org 23 Sep '09

23 Sep '09

Author: hailfinger Date: 2009-09-23 04:05:12 +0200 (Wed, 23 Sep 2009) New Revision: 728 Modified: trunk/board_enable.c Log: This enables flashing the Dell S1850 under Linux. This code has been tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-09-18 15:50:56 UTC (rev 727) +++ trunk/board_enable.c 2009-09-23 02:05:12 UTC (rev 728) @@ -569,6 +569,17 @@ } /** + * Suited for the Dell S1850. All parameters except the last one are documented + * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last + * parameter (GPIO number) has to be in the range [16,31] according to said + * Intel Datasheet and was found by exhaustive search. + */ +static int ich5_gpio23_raise(const char *name) +{ + return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); +} + +/** * Suited for MSI MS-7046. */ static int ich6_gpio19_raise(const char *name) @@ -992,6 +1003,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},

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