- flashrom - mail.coreboot.org

[patch] add intel_piix4_gpo_set()
by Luc Verhaegen 14 Dec '09

14 Dec '09

This is code from a an old board enable that i sent in 3 weeks ago. This board enable was not necessary (as flashing worked just fine without it too). But this function was also used to clean up the board enable for the epox ep bx3. I have tracked down the person for whom i wrote this board enable 2 years ago: irc user nyu, aka Robert Millan. Robert, can you verify that this code is not a regression for you? Uwe, in the original mail thread (http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you had several suggestions. I have taken over unsigned int and the bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere. "PIIX4{,E,M}" all over clutters up the place, and i fear that printing this to the user will generate more confusion than it will ever remove. Instead i have adjusted the initial function comment to mention this so that developers can rest assured in future that this will also be valid for their future board enables. Luc Verhaegen.

3 9

[commit] r803 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: libv Date: 2009-12-14 11:41:58 +0100 (Mon, 14 Dec 2009) New Revision: 803 Modified: trunk/board_enable.c Log: Boards: Formalize intel piix4 gpo setting. The function intel_piix4_gpo_set includes proper gpo pin checking, and gpo pin enables when necessary. This is a leftover from soyo SY-6BA+III code that turned out to be unnecessary, but still used for the epox ep-bx3 board enable which it cleans up and clarifies. Difference to old code: * typical bios delay io port 0xEB now never gets touched. * pci config byte 0xB0 was not altered before. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-14 04:24:42 UTC (rev 802) +++ trunk/board_enable.c 2009-12-14 10:41:58 UTC (rev 803) @@ -494,25 +494,6 @@ } /** - * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. - */ -static int board_epox_ep_bx3(const char *name) -{ - uint8_t tmp; - - /* Raise GPIO22. */ - tmp = INB(0x4036); - OUTB(tmp, 0xEB); - - tmp |= 0x40; - - OUTB(tmp, 0x4036); - OUTB(tmp, 0xEB); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -554,6 +535,83 @@ } /** + * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M} + */ +static int intel_piix4_gpo_set(unsigned int gpo, int raise) +{ + struct pci_dev *dev; + uint32_t tmp, base; + + dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + return -1; + } + + /* sanity check */ + if (gpo > 30) { + fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + return -1; + } + + /* these are dual function pins which are most likely in use already */ + if (((gpo >= 1) && (gpo <= 7)) || + ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { + fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + return -1; + } + + /* dual function that need special enable. */ + if ((gpo >= 22) && (gpo <= 26)) { + tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + switch (gpo) { + case 22: /* XBUS: XDIR#/GPO22 */ + case 23: /* XBUS: XOE#/GPO23 */ + tmp |= 1 << 28; + break; + case 24: /* RTCSS#/GPO24 */ + tmp |= 1 << 29; + break; + case 25: /* RTCALE/GPO25 */ + tmp |= 1 << 30; + break; + case 26: /* KBCSS#/GPO26 */ + tmp |= 1 << 31; + break; + } + pci_write_long(dev, 0xB0, tmp); + } + + /* GPO {0,8,27,28,30} are always available. */ + + dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + return -1; + } + + /* PM IO base */ + base = pci_read_long(dev, 0x40) & 0x0000FFC0; + + tmp = INL(base + 0x34); /* GPO register */ + if (raise) + tmp |= 0x01 << gpo; + else + tmp |= ~(0x01 << gpo); + OUTL(tmp, base + 0x34); + + return 0; +} + +/** + * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. + */ +static int board_epox_ep_bx3(const char *name) +{ + return intel_piix4_gpo_set(22, 1); +} + +/** * Set a GPIO line on a given intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise)

1 0

[patch] use pci_fill_info()
by Jonathan A. Kollasch 14 Dec '09

14 Dec '09

Use pci_fill_info() so device_class is valid. This is needed on NetBSD and probably other non-Linux platforms. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> ---

2 1

[commit] r802 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 05:24:42 +0100 (Mon, 14 Dec 2009) New Revision: 802 Modified: trunk/board_enable.c Log: Use pci_fill_info() so device_class is valid. This is needed on NetBSD and probably other non-Linux platforms. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-14 04:11:12 UTC (rev 801) +++ trunk/board_enable.c 2009-12-14 04:24:42 UTC (rev 802) @@ -605,7 +605,8 @@ int i, allowed; /* First, look for a known LPC bridge */ - for (dev = pacc->devices; dev; dev = dev->next) + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_CLASS); if ((dev->vendor_id == 0x8086) && (dev->device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ @@ -616,6 +617,7 @@ if (intel_ich_gpio_table[i].id) break; } + } if (!dev) { fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");

1 0

ASRock M3A790GXH/128M success
by Zachary Dillard 14 Dec '09

14 Dec '09

BIOS flash successful on this motherboard ASRock M3A790GXH/128M.

3 4

[commit] r801 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 05:11:12 +0100 (Mon, 14 Dec 2009) New Revision: 801 Modified: trunk/print.c trunk/print_wiki.c Log: Mark ASRock M3A790GXH/128M as supported, no board enable needed. Signed-off-by: Zachary O Dillard <teathief(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-12-14 04:04:18 UTC (rev 800) +++ trunk/print.c 2009-12-14 04:11:12 UTC (rev 801) @@ -260,6 +260,7 @@ { "ASI", "MB-5BLMP", }, { "ASRock", "A770CrossFire", }, { "ASRock", "K8S8X", }, + { "ASRock", "M3A790GXH/128M" }, { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "A7V400-MX", }, Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-12-14 04:04:18 UTC (rev 800) +++ trunk/print_wiki.c 2009-12-14 04:11:12 UTC (rev 801) @@ -105,6 +105,7 @@ { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X" }, + { "ASRock", "M3A790GXH/128M" "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" },

1 0

[PATCH] Fix eraseblock walking
by Carl-Daniel Hailfinger 14 Dec '09

14 Dec '09

Fix eraseblock walking and add a few more checks to make sure such bugs get caught in the future. I found this bug during a code review. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-blockerase_walk_fix/flashrom.c =================================================================== --- flashrom-blockerase_walk_fix/flashrom.c (Revision 769) +++ flashrom-blockerase_walk_fix/flashrom.c (Arbeitskopie) @@ -563,10 +563,11 @@ int erase_flash(struct flashchip *flash) { int i, j, k, ret = 0, found = 0; + unsigned int start, len; printf("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned long done = 0; + unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; printf_debug("Looking at blockwise erase function %i... ", k); @@ -594,13 +595,23 @@ * members so the loop below won't be executed for them. */ for (j = 0; j < eraser.eraseblocks[i].count; j++) { - ret = eraser.block_erase(flash, done + eraser.eraseblocks[i].size * j, eraser.eraseblocks[i].size); + start = done + eraser.eraseblocks[i].size * j; + len = eraser.eraseblocks[i].size; + printf_debug("0x%06x-0x%06x, ", start, len); + ret = eraser.block_erase(flash, start, len); if (ret) break; } if (ret) break; + done += eraser.eraseblocks[i].count * + eraser.eraseblocks[i].size; } + printf_debug("\n"); + if (done != flash->total_size * 1024) + fprintf(stderr, "ERROR: Erase region walking erased " + "0x%06x bytes total, expected 0x%06x bytes.", + done, flash->total_size * 1024); /* If everything is OK, don't try another erase function. */ if (!ret) break; -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 5

[commit] r800 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 05:04:18 +0100 (Mon, 14 Dec 2009) New Revision: 800 Modified: trunk/flashrom.c Log: Fix eraseblock walking and add a few more checks to make sure such bugs get caught in the future. I found this bug during a code review. A consistency check for eraseblock definitions has been merged as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-12-14 03:32:24 UTC (rev 799) +++ trunk/flashrom.c 2009-12-14 04:04:18 UTC (rev 800) @@ -806,10 +806,11 @@ int erase_flash(struct flashchip *flash) { int i, j, k, ret = 0, found = 0; + unsigned int start, len; printf("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned long done = 0; + unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; printf_debug("Looking at blockwise erase function %i... ", k); @@ -833,17 +834,39 @@ found = 1; printf_debug("trying... "); for (i = 0; i < NUM_ERASEREGIONS; i++) { + /* Blocks with zero size are bugs in flashchips.c. + * FIXME: This check should be performed on startup. + */ + if (eraser.eraseblocks[i].count && + !eraser.eraseblocks[i].size) { + fprintf(stderr, "ERROR: Erase region with size " + "0 for this chip. Please report a bug " + "at flashrom(a)flashrom.org\n"); + ret = 1; + break; + } /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ for (j = 0; j < eraser.eraseblocks[i].count; j++) { - ret = eraser.block_erase(flash, done + eraser.eraseblocks[i].size * j, eraser.eraseblocks[i].size); + start = done + eraser.eraseblocks[i].size * j; + len = eraser.eraseblocks[i].size; + printf_debug("0x%06x-0x%06x, ", start, + start + len - 1); + ret = eraser.block_erase(flash, start, len); if (ret) break; } if (ret) break; + done += eraser.eraseblocks[i].count * + eraser.eraseblocks[i].size; } + printf_debug("\n"); + if (done != flash->total_size * 1024) + fprintf(stderr, "ERROR: Erase region walking erased " + "0x%06x bytes total, expected 0x%06x bytes.", + done, flash->total_size * 1024); /* If everything is OK, don't try another erase function. */ if (!ret) break;

1 0

[PATCH] Split hw access and chip drivers out of flash.h
by Carl-Daniel Hailfinger 14 Dec '09

14 Dec '09

Split hardware access, OS abstraction and chip drivers out of flash.h to get a better overview of what belongs where. This patch is only the first step, but it hopefully will make working with the code and especially porting to new platforms easier. Subsequent patches should move #includes for the newly created files hwaccess.h and chipdrivers.h from flash.h to the files which need them. Programmers should live in a separate header file as well, but that would have made this patch pretty difficult to read. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-flash_h_split_chipdrivers_hwaccess/flash.h =================================================================== --- flashrom-flash_h_split_chipdrivers_hwaccess/flash.h (Revision 797) +++ flashrom-flash_h_split_chipdrivers_hwaccess/flash.h (Arbeitskopie) @@ -24,62 +24,11 @@ #ifndef __FLASH_H__ #define __FLASH_H__ 1 -#if defined(__GLIBC__) -#include <sys/io.h> -#endif #include <unistd.h> #include <stdint.h> #include <stdio.h> -#if NEED_PCI == 1 -#include <pci/pci.h> -#endif +#include "hwaccess.h" -/* for iopl and outb under Solaris */ -#if defined (__sun) && (defined(__i386) || defined(__amd64)) -#include <strings.h> -#include <sys/sysi86.h> -#include <sys/psw.h> -#include <asm/sunddi.h> -#endif - -#if (defined(__MACH__) && defined(__APPLE__)) -#define __DARWIN__ -#endif - -#if defined(__FreeBSD__) || defined(__DragonFly__) - #include <machine/cpufunc.h> - #define off64_t off_t - #define lseek64 lseek - #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) - #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) - #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) - #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) - #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) - #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) -#else -#if defined(__DARWIN__) - #include <DirectIO/darwinio.h> - #define off64_t off_t - #define lseek64 lseek -#endif -#if defined (__sun) && (defined(__i386) || defined(__amd64)) - /* Note different order for outb */ - #define OUTB(x,y) outb(y, x) - #define OUTW(x,y) outw(y, x) - #define OUTL(x,y) outl(y, x) - #define INB inb - #define INW inw - #define INL inl -#else - #define OUTB outb - #define OUTW outw - #define OUTL outl - #define INB inb - #define INW inw - #define INL inl -#endif -#endif - typedef unsigned long chipaddr; enum programmer { @@ -373,22 +322,13 @@ void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); -#if !defined(__DARWIN__) && !defined(__FreeBSD__) && !defined(__DragonFly__) -typedef struct { uint32_t hi, lo; } msr_t; -msr_t rdmsr(int addr); -int wrmsr(int addr, msr_t msr); -#endif -#if defined(__FreeBSD__) || defined(__DragonFly__) -/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ -#undef rdmsr -#undef wrmsr -#define rdmsr freebsd_rdmsr -#define wrmsr freebsd_wrmsr -typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); -int freebsd_wrmsr(int addr, msr_t msr); -#endif +/* cbtable.c */ +void lb_vendor_dev_from_string(char *boardstring); +int coreboot_init(void); +extern char *lb_part, *lb_vendor; +extern int partvendor_from_cbtable; + /* internal.c */ #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); @@ -428,9 +368,6 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -#if defined(__FreeBSD__) || defined(__DragonFly__) -extern int io_fd; -#endif /* dummyflasher.c */ #if DUMMY_SUPPORT == 1 @@ -545,12 +482,6 @@ int find_romentry(char *name); int handle_romentries(uint8_t *buffer, struct flashchip *flash); -/* cbtable.c */ -void lb_vendor_dev_from_string(char *boardstring); -int coreboot_init(void); -extern char *lb_part, *lb_vendor; -extern int partvendor_from_cbtable; - /* spi.c */ enum spi_controller { SPI_CONTROLLER_NONE, @@ -593,57 +524,14 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; extern void *spibar; -int probe_spi_rdid(struct flashchip *flash); -int probe_spi_rdid4(struct flashchip *flash); -int probe_spi_rems(struct flashchip *flash); -int probe_spi_res(struct flashchip *flash); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); -int spi_write_enable(void); -int spi_write_disable(void); -int spi_chip_erase_60(struct flashchip *flash); -int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); -int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -uint8_t spi_read_status_register(void); -int spi_disable_blockprotect(void); -int spi_byte_program(int addr, uint8_t byte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf); -uint32_t spi_get_valid_read_addr(void); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); +uint32_t spi_get_valid_read_addr(void); -/* 82802ab.c */ -int probe_82802ab(struct flashchip *flash); -int erase_82802ab(struct flashchip *flash); -int write_82802ab(struct flashchip *flash, uint8_t *buf); - -/* am29f040b.c */ -int probe_29f040b(struct flashchip *flash); -int erase_29f040b(struct flashchip *flash); -int write_29f040b(struct flashchip *flash, uint8_t *buf); - -/* pm29f002.c */ -int write_pm29f002(struct flashchip *flash, uint8_t *buf); - -/* en29f002a.c */ -int probe_en29f002a(struct flashchip *flash); -int erase_en29f002a(struct flashchip *flash); -int write_en29f002a(struct flashchip *flash, uint8_t *buf); - /* ichspi.c */ int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -670,97 +558,6 @@ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); extern uint8_t *sb600_spibar; -/* jedec.c */ -uint8_t oddparity(uint8_t val); -void toggle_ready_jedec(chipaddr dst); -void data_polling_jedec(chipaddr dst, uint8_t data); -void start_program_jedec(chipaddr bios); -int write_byte_program_jedec(chipaddr bios, uint8_t *src, - chipaddr dst); -int probe_jedec(struct flashchip *flash); -int erase_chip_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf); -int write_jedec_1(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); -int write_sector_jedec(chipaddr bios, uint8_t *src, - chipaddr dst, unsigned int page_size); - -/* m29f002.c */ -int erase_m29f002(struct flashchip *flash); -int write_m29f002t(struct flashchip *flash, uint8_t *buf); -int write_m29f002b(struct flashchip *flash, uint8_t *buf); - -/* m29f400bt.c */ -int probe_m29f400bt(struct flashchip *flash); -int erase_m29f400bt(struct flashchip *flash); -int block_erase_m29f400bt(struct flashchip *flash, int start, int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf); -int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf); -void toggle_ready_m29f400bt(chipaddr dst); -void data_polling_m29f400bt(chipaddr dst, uint8_t data); -void protect_m29f400bt(chipaddr bios); -void write_page_m29f400bt(chipaddr bios, uint8_t *src, - chipaddr dst, int page_size); - -/* mx29f002.c */ -int probe_29f002(struct flashchip *flash); -int erase_29f002(struct flashchip *flash); -int write_29f002(struct flashchip *flash, uint8_t *buf); - -/* pm49fl00x.c */ -int probe_49fl00x(struct flashchip *flash); -int erase_49fl00x(struct flashchip *flash); -int write_49fl00x(struct flashchip *flash, uint8_t *buf); - -/* sharplhf00l04.c */ -int probe_lhf00l04(struct flashchip *flash); -int erase_lhf00l04(struct flashchip *flash); -int write_lhf00l04(struct flashchip *flash, uint8_t *buf); -void toggle_ready_lhf00l04(chipaddr dst); -void data_polling_lhf00l04(chipaddr dst, uint8_t data); -void protect_lhf00l04(chipaddr bios); - -/* sst28sf040.c */ -int probe_28sf040(struct flashchip *flash); -int erase_28sf040(struct flashchip *flash); -int write_28sf040(struct flashchip *flash, uint8_t *buf); - -/* sst39sf020.c */ -int probe_39sf020(struct flashchip *flash); -int write_39sf020(struct flashchip *flash, uint8_t *buf); - -/* sst49lf040.c */ -int erase_49lf040(struct flashchip *flash); -int write_49lf040(struct flashchip *flash, uint8_t *buf); - -/* sst49lfxxxc.c */ -int probe_49lfxxxc(struct flashchip *flash); -int erase_49lfxxxc(struct flashchip *flash); -int write_49lfxxxc(struct flashchip *flash, uint8_t *buf); - -/* sst_fwhub.c */ -int probe_sst_fwhub(struct flashchip *flash); -int erase_sst_fwhub(struct flashchip *flash); -int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); -int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); - -/* w39v040c.c */ -int probe_w39v040c(struct flashchip *flash); -int erase_w39v040c(struct flashchip *flash); -int write_w39v040c(struct flashchip *flash, uint8_t *buf); - -/* w39V080fa.c */ -int probe_winbond_fwhub(struct flashchip *flash); -int erase_winbond_fwhub(struct flashchip *flash); -int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); - -/* w29ee011.c */ -int probe_w29ee011(struct flashchip *flash); - -/* w49f002u.c */ -int write_49f002(struct flashchip *flash, uint8_t *buf); - /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -768,11 +565,6 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); -/* stm50flw0x0x.c */ -int probe_stm50flw0x0x(struct flashchip *flash); -int erase_stm50flw0x0x(struct flashchip *flash); -int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); - /* serprog.c */ int serprog_init(void); int serprog_shutdown(void); @@ -787,4 +579,6 @@ void __attribute__((noreturn)) sp_die(char *msg); extern int sp_fd; +#include "chipdrivers.h" + #endif /* !__FLASH_H__ */ Index: flashrom-flash_h_split_chipdrivers_hwaccess/hwaccess.h =================================================================== --- flashrom-flash_h_split_chipdrivers_hwaccess/hwaccess.h (Revision 0) +++ flashrom-flash_h_split_chipdrivers_hwaccess/hwaccess.h (Revision 0) @@ -0,0 +1,99 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * + * Header file for hardware access and OS abstraction. Included from flash.h. + */ + +#ifndef __HWACCESS_H__ +#define __HWACCESS_H__ 1 + +#if defined(__GLIBC__) +#include <sys/io.h> +#endif +#if NEED_PCI == 1 +#include <pci/pci.h> +#endif + +/* for iopl and outb under Solaris */ +#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#include <strings.h> +#include <sys/sysi86.h> +#include <sys/psw.h> +#include <asm/sunddi.h> +#endif + +#if (defined(__MACH__) && defined(__APPLE__)) +#define __DARWIN__ +#endif + +#if defined(__FreeBSD__) || defined(__DragonFly__) + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) + #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) + #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) + #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) + #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) + #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) +#else +#if defined(__DARWIN__) + #include <DirectIO/darwinio.h> + #define off64_t off_t + #define lseek64 lseek +#endif +#if defined (__sun) && (defined(__i386) || defined(__amd64)) + /* Note different order for outb */ + #define OUTB(x,y) outb(y, x) + #define OUTW(x,y) outw(y, x) + #define OUTL(x,y) outl(y, x) + #define INB inb + #define INW inw + #define INL inl +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl + #define INB inb + #define INW inw + #define INL inl +#endif +#endif + +#if defined(__FreeBSD__) || defined(__DragonFly__) +extern int io_fd; +#endif + +#if !defined(__DARWIN__) && !defined(__FreeBSD__) && !defined(__DragonFly__) +typedef struct { uint32_t hi, lo; } msr_t; +msr_t rdmsr(int addr); +int wrmsr(int addr, msr_t msr); +#endif +#if defined(__FreeBSD__) || defined(__DragonFly__) +/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ +#undef rdmsr +#undef wrmsr +#define rdmsr freebsd_rdmsr +#define wrmsr freebsd_wrmsr +typedef struct { uint32_t hi, lo; } msr_t; +msr_t freebsd_rdmsr(int addr); +int freebsd_wrmsr(int addr, msr_t msr); +#endif + +#endif /* !__HWACCESS_H__ */ Index: flashrom-flash_h_split_chipdrivers_hwaccess/chipdrivers.h =================================================================== --- flashrom-flash_h_split_chipdrivers_hwaccess/chipdrivers.h (Revision 0) +++ flashrom-flash_h_split_chipdrivers_hwaccess/chipdrivers.h (Revision 0) @@ -0,0 +1,169 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * + * Header file for flash chip drivers. Included from flash.h. + * As a general rule, every function listed here should take a pointer to + * struct flashchip as first parameter. + */ + +#ifndef __CHIPDRIVERS_H__ +#define __CHIPDRIVERS_H__ 1 + +/* spi.c, should probably be in spi_chip.c */ +int probe_spi_rdid(struct flashchip *flash); +int probe_spi_rdid4(struct flashchip *flash); +int probe_spi_rems(struct flashchip *flash); +int probe_spi_res(struct flashchip *flash); +int spi_write_enable(void); +int spi_write_disable(void); +int spi_chip_erase_60(struct flashchip *flash); +int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_60_c7(struct flashchip *flash); +int spi_chip_erase_d8(struct flashchip *flash); +int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +uint8_t spi_read_status_register(void); +int spi_disable_blockprotect(void); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf); + +/* 82802ab.c */ +int probe_82802ab(struct flashchip *flash); +int erase_82802ab(struct flashchip *flash); +int write_82802ab(struct flashchip *flash, uint8_t *buf); + +/* am29f040b.c */ +int probe_29f040b(struct flashchip *flash); +int erase_29f040b(struct flashchip *flash); +int write_29f040b(struct flashchip *flash, uint8_t *buf); + +/* pm29f002.c */ +int write_pm29f002(struct flashchip *flash, uint8_t *buf); + +/* en29f002a.c */ +int probe_en29f002a(struct flashchip *flash); +int erase_en29f002a(struct flashchip *flash); +int write_en29f002a(struct flashchip *flash, uint8_t *buf); + +/* jedec.c */ +uint8_t oddparity(uint8_t val); +void toggle_ready_jedec(chipaddr dst); +void data_polling_jedec(chipaddr dst, uint8_t data); +void start_program_jedec(chipaddr bios); +int write_byte_program_jedec(chipaddr bios, uint8_t *src, + chipaddr dst); +int probe_jedec(struct flashchip *flash); +int erase_chip_jedec(struct flashchip *flash); +int write_jedec(struct flashchip *flash, uint8_t *buf); +int write_jedec_1(struct flashchip *flash, uint8_t *buf); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); +int write_sector_jedec(chipaddr bios, uint8_t *src, + chipaddr dst, unsigned int page_size); + +/* m29f002.c */ +int erase_m29f002(struct flashchip *flash); +int write_m29f002t(struct flashchip *flash, uint8_t *buf); +int write_m29f002b(struct flashchip *flash, uint8_t *buf); + +/* m29f400bt.c */ +int probe_m29f400bt(struct flashchip *flash); +int erase_m29f400bt(struct flashchip *flash); +int block_erase_m29f400bt(struct flashchip *flash, int start, int len); +int write_m29f400bt(struct flashchip *flash, uint8_t *buf); +int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf); +void toggle_ready_m29f400bt(chipaddr dst); +void data_polling_m29f400bt(chipaddr dst, uint8_t data); +void protect_m29f400bt(chipaddr bios); +void write_page_m29f400bt(chipaddr bios, uint8_t *src, + chipaddr dst, int page_size); + +/* mx29f002.c */ +int probe_29f002(struct flashchip *flash); +int erase_29f002(struct flashchip *flash); +int write_29f002(struct flashchip *flash, uint8_t *buf); + +/* pm49fl00x.c */ +int probe_49fl00x(struct flashchip *flash); +int erase_49fl00x(struct flashchip *flash); +int write_49fl00x(struct flashchip *flash, uint8_t *buf); + +/* sharplhf00l04.c */ +int probe_lhf00l04(struct flashchip *flash); +int erase_lhf00l04(struct flashchip *flash); +int write_lhf00l04(struct flashchip *flash, uint8_t *buf); +void toggle_ready_lhf00l04(chipaddr dst); +void data_polling_lhf00l04(chipaddr dst, uint8_t data); +void protect_lhf00l04(chipaddr bios); + +/* sst28sf040.c */ +int probe_28sf040(struct flashchip *flash); +int erase_28sf040(struct flashchip *flash); +int write_28sf040(struct flashchip *flash, uint8_t *buf); + +/* sst39sf020.c */ +int probe_39sf020(struct flashchip *flash); +int write_39sf020(struct flashchip *flash, uint8_t *buf); + +/* sst49lf040.c */ +int erase_49lf040(struct flashchip *flash); +int write_49lf040(struct flashchip *flash, uint8_t *buf); + +/* sst49lfxxxc.c */ +int probe_49lfxxxc(struct flashchip *flash); +int erase_49lfxxxc(struct flashchip *flash); +int write_49lfxxxc(struct flashchip *flash, uint8_t *buf); + +/* sst_fwhub.c */ +int probe_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); +int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); + +/* w39v040c.c */ +int probe_w39v040c(struct flashchip *flash); +int erase_w39v040c(struct flashchip *flash); +int write_w39v040c(struct flashchip *flash, uint8_t *buf); + +/* w39V080fa.c */ +int probe_winbond_fwhub(struct flashchip *flash); +int erase_winbond_fwhub(struct flashchip *flash); +int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); + +/* w29ee011.c */ +int probe_w29ee011(struct flashchip *flash); + +/* w49f002u.c */ +int write_49f002(struct flashchip *flash, uint8_t *buf); + +/* stm50flw0x0x.c */ +int probe_stm50flw0x0x(struct flashchip *flash); +int erase_stm50flw0x0x(struct flashchip *flash); +int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); + +#endif /* !__CHIPDRIVERS_H__ */ -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

3 4

[Patch] Add board match for ASRock P4i65GV.
by Luc Verhaegen 14 Dec '09

14 Dec '09

Idwer, please apply the ICH GPIO patch before applying this one. Thanks, Luc Verhaegen.

3 4

[Patch] Shuttle AK31
by Luc Verhaegen 14 Dec '09

14 Dec '09

Resending this patch to the newly formed flashrom ml. Ron already kindly acked this patch. Mateusz, the owner of this board gave me a brief comment on irc stating that it didn't work. Which is also the last i heard from him. Mateusz, get back to us and get us at least the flashrom output. Luc Verhaegen.

3 6

[commit] r799 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 04:32:24 +0100 (Mon, 14 Dec 2009) New Revision: 799 Added: trunk/chipdrivers.h trunk/hwaccess.h Modified: trunk/flash.h Log: Split hardware access, OS abstraction and chip drivers out of flash.h to get a better overview of what belongs where. This patch is only the first step, but it hopefully will make working with the code and especially porting to new platforms easier. Subsequent patches should move #includes for the newly created files hwaccess.h and chipdrivers.h from flash.h to the files which need them. Programmers should live in a separate header file as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Tested-by: Idwer Vollering <vidwer(a)gmail.com> Added: trunk/chipdrivers.h =================================================================== --- trunk/chipdrivers.h (rev 0) +++ trunk/chipdrivers.h 2009-12-14 03:32:24 UTC (rev 799) @@ -0,0 +1,169 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * + * Header file for flash chip drivers. Included from flash.h. + * As a general rule, every function listed here should take a pointer to + * struct flashchip as first parameter. + */ + +#ifndef __CHIPDRIVERS_H__ +#define __CHIPDRIVERS_H__ 1 + +/* spi.c, should probably be in spi_chip.c */ +int probe_spi_rdid(struct flashchip *flash); +int probe_spi_rdid4(struct flashchip *flash); +int probe_spi_rems(struct flashchip *flash); +int probe_spi_res(struct flashchip *flash); +int spi_write_enable(void); +int spi_write_disable(void); +int spi_chip_erase_60(struct flashchip *flash); +int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_60_c7(struct flashchip *flash); +int spi_chip_erase_d8(struct flashchip *flash); +int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); +int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); +int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); +uint8_t spi_read_status_register(void); +int spi_disable_blockprotect(void); +int spi_byte_program(int addr, uint8_t byte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf); + +/* 82802ab.c */ +int probe_82802ab(struct flashchip *flash); +int erase_82802ab(struct flashchip *flash); +int write_82802ab(struct flashchip *flash, uint8_t *buf); + +/* am29f040b.c */ +int probe_29f040b(struct flashchip *flash); +int erase_29f040b(struct flashchip *flash); +int write_29f040b(struct flashchip *flash, uint8_t *buf); + +/* pm29f002.c */ +int write_pm29f002(struct flashchip *flash, uint8_t *buf); + +/* en29f002a.c */ +int probe_en29f002a(struct flashchip *flash); +int erase_en29f002a(struct flashchip *flash); +int write_en29f002a(struct flashchip *flash, uint8_t *buf); + +/* jedec.c */ +uint8_t oddparity(uint8_t val); +void toggle_ready_jedec(chipaddr dst); +void data_polling_jedec(chipaddr dst, uint8_t data); +void start_program_jedec(chipaddr bios); +int write_byte_program_jedec(chipaddr bios, uint8_t *src, + chipaddr dst); +int probe_jedec(struct flashchip *flash); +int erase_chip_jedec(struct flashchip *flash); +int write_jedec(struct flashchip *flash, uint8_t *buf); +int write_jedec_1(struct flashchip *flash, uint8_t *buf); +int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); +int write_sector_jedec(chipaddr bios, uint8_t *src, + chipaddr dst, unsigned int page_size); + +/* m29f002.c */ +int erase_m29f002(struct flashchip *flash); +int write_m29f002t(struct flashchip *flash, uint8_t *buf); +int write_m29f002b(struct flashchip *flash, uint8_t *buf); + +/* m29f400bt.c */ +int probe_m29f400bt(struct flashchip *flash); +int erase_m29f400bt(struct flashchip *flash); +int block_erase_m29f400bt(struct flashchip *flash, int start, int len); +int write_m29f400bt(struct flashchip *flash, uint8_t *buf); +int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf); +void toggle_ready_m29f400bt(chipaddr dst); +void data_polling_m29f400bt(chipaddr dst, uint8_t data); +void protect_m29f400bt(chipaddr bios); +void write_page_m29f400bt(chipaddr bios, uint8_t *src, + chipaddr dst, int page_size); + +/* mx29f002.c */ +int probe_29f002(struct flashchip *flash); +int erase_29f002(struct flashchip *flash); +int write_29f002(struct flashchip *flash, uint8_t *buf); + +/* pm49fl00x.c */ +int probe_49fl00x(struct flashchip *flash); +int erase_49fl00x(struct flashchip *flash); +int write_49fl00x(struct flashchip *flash, uint8_t *buf); + +/* sharplhf00l04.c */ +int probe_lhf00l04(struct flashchip *flash); +int erase_lhf00l04(struct flashchip *flash); +int write_lhf00l04(struct flashchip *flash, uint8_t *buf); +void toggle_ready_lhf00l04(chipaddr dst); +void data_polling_lhf00l04(chipaddr dst, uint8_t data); +void protect_lhf00l04(chipaddr bios); + +/* sst28sf040.c */ +int probe_28sf040(struct flashchip *flash); +int erase_28sf040(struct flashchip *flash); +int write_28sf040(struct flashchip *flash, uint8_t *buf); + +/* sst39sf020.c */ +int probe_39sf020(struct flashchip *flash); +int write_39sf020(struct flashchip *flash, uint8_t *buf); + +/* sst49lf040.c */ +int erase_49lf040(struct flashchip *flash); +int write_49lf040(struct flashchip *flash, uint8_t *buf); + +/* sst49lfxxxc.c */ +int probe_49lfxxxc(struct flashchip *flash); +int erase_49lfxxxc(struct flashchip *flash); +int write_49lfxxxc(struct flashchip *flash, uint8_t *buf); + +/* sst_fwhub.c */ +int probe_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub(struct flashchip *flash); +int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); +int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); + +/* w39v040c.c */ +int probe_w39v040c(struct flashchip *flash); +int erase_w39v040c(struct flashchip *flash); +int write_w39v040c(struct flashchip *flash, uint8_t *buf); + +/* w39V080fa.c */ +int probe_winbond_fwhub(struct flashchip *flash); +int erase_winbond_fwhub(struct flashchip *flash); +int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); + +/* w29ee011.c */ +int probe_w29ee011(struct flashchip *flash); + +/* w49f002u.c */ +int write_49f002(struct flashchip *flash, uint8_t *buf); + +/* stm50flw0x0x.c */ +int probe_stm50flw0x0x(struct flashchip *flash); +int erase_stm50flw0x0x(struct flashchip *flash); +int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); + +#endif /* !__CHIPDRIVERS_H__ */ Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-12-14 03:07:31 UTC (rev 798) +++ trunk/flash.h 2009-12-14 03:32:24 UTC (rev 799) @@ -24,62 +24,11 @@ #ifndef __FLASH_H__ #define __FLASH_H__ 1 -#if defined(__GLIBC__) -#include <sys/io.h> -#endif #include <unistd.h> #include <stdint.h> #include <stdio.h> -#if NEED_PCI == 1 -#include <pci/pci.h> -#endif +#include "hwaccess.h" -/* for iopl and outb under Solaris */ -#if defined (__sun) && (defined(__i386) || defined(__amd64)) -#include <strings.h> -#include <sys/sysi86.h> -#include <sys/psw.h> -#include <asm/sunddi.h> -#endif - -#if (defined(__MACH__) && defined(__APPLE__)) -#define __DARWIN__ -#endif - -#if defined(__FreeBSD__) || defined(__DragonFly__) - #include <machine/cpufunc.h> - #define off64_t off_t - #define lseek64 lseek - #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) - #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) - #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) - #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) - #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) - #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) -#else -#if defined(__DARWIN__) - #include <DirectIO/darwinio.h> - #define off64_t off_t - #define lseek64 lseek -#endif -#if defined (__sun) && (defined(__i386) || defined(__amd64)) - /* Note different order for outb */ - #define OUTB(x,y) outb(y, x) - #define OUTW(x,y) outw(y, x) - #define OUTL(x,y) outl(y, x) - #define INB inb - #define INW inw - #define INL inl -#else - #define OUTB outb - #define OUTW outw - #define OUTL outl - #define INB inb - #define INW inw - #define INL inl -#endif -#endif - typedef unsigned long chipaddr; enum programmer { @@ -373,22 +322,13 @@ void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); -#if !defined(__DARWIN__) && !defined(__FreeBSD__) && !defined(__DragonFly__) -typedef struct { uint32_t hi, lo; } msr_t; -msr_t rdmsr(int addr); -int wrmsr(int addr, msr_t msr); -#endif -#if defined(__FreeBSD__) || defined(__DragonFly__) -/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ -#undef rdmsr -#undef wrmsr -#define rdmsr freebsd_rdmsr -#define wrmsr freebsd_wrmsr -typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); -int freebsd_wrmsr(int addr, msr_t msr); -#endif +/* cbtable.c */ +void lb_vendor_dev_from_string(char *boardstring); +int coreboot_init(void); +extern char *lb_part, *lb_vendor; +extern int partvendor_from_cbtable; + /* internal.c */ #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); @@ -428,9 +368,6 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -#if defined(__FreeBSD__) || defined(__DragonFly__) -extern int io_fd; -#endif /* dummyflasher.c */ #if DUMMY_SUPPORT == 1 @@ -545,12 +482,6 @@ int find_romentry(char *name); int handle_romentries(uint8_t *buffer, struct flashchip *flash); -/* cbtable.c */ -void lb_vendor_dev_from_string(char *boardstring); -int coreboot_init(void); -extern char *lb_part, *lb_vendor; -extern int partvendor_from_cbtable; - /* spi.c */ enum spi_controller { SPI_CONTROLLER_NONE, @@ -593,57 +524,14 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; extern void *spibar; -int probe_spi_rdid(struct flashchip *flash); -int probe_spi_rdid4(struct flashchip *flash); -int probe_spi_rems(struct flashchip *flash); -int probe_spi_res(struct flashchip *flash); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); -int spi_write_enable(void); -int spi_write_disable(void); -int spi_chip_erase_60(struct flashchip *flash); -int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); -int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); -int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); -int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -uint8_t spi_read_status_register(void); -int spi_disable_blockprotect(void); -int spi_byte_program(int addr, uint8_t byte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf); -uint32_t spi_get_valid_read_addr(void); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); +uint32_t spi_get_valid_read_addr(void); -/* 82802ab.c */ -int probe_82802ab(struct flashchip *flash); -int erase_82802ab(struct flashchip *flash); -int write_82802ab(struct flashchip *flash, uint8_t *buf); - -/* am29f040b.c */ -int probe_29f040b(struct flashchip *flash); -int erase_29f040b(struct flashchip *flash); -int write_29f040b(struct flashchip *flash, uint8_t *buf); - -/* pm29f002.c */ -int write_pm29f002(struct flashchip *flash, uint8_t *buf); - -/* en29f002a.c */ -int probe_en29f002a(struct flashchip *flash); -int erase_en29f002a(struct flashchip *flash); -int write_en29f002a(struct flashchip *flash, uint8_t *buf); - /* ichspi.c */ int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -670,97 +558,6 @@ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); extern uint8_t *sb600_spibar; -/* jedec.c */ -uint8_t oddparity(uint8_t val); -void toggle_ready_jedec(chipaddr dst); -void data_polling_jedec(chipaddr dst, uint8_t data); -void start_program_jedec(chipaddr bios); -int write_byte_program_jedec(chipaddr bios, uint8_t *src, - chipaddr dst); -int probe_jedec(struct flashchip *flash); -int erase_chip_jedec(struct flashchip *flash); -int write_jedec(struct flashchip *flash, uint8_t *buf); -int write_jedec_1(struct flashchip *flash, uint8_t *buf); -int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); -int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); -int write_sector_jedec(chipaddr bios, uint8_t *src, - chipaddr dst, unsigned int page_size); - -/* m29f002.c */ -int erase_m29f002(struct flashchip *flash); -int write_m29f002t(struct flashchip *flash, uint8_t *buf); -int write_m29f002b(struct flashchip *flash, uint8_t *buf); - -/* m29f400bt.c */ -int probe_m29f400bt(struct flashchip *flash); -int erase_m29f400bt(struct flashchip *flash); -int block_erase_m29f400bt(struct flashchip *flash, int start, int len); -int write_m29f400bt(struct flashchip *flash, uint8_t *buf); -int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf); -void toggle_ready_m29f400bt(chipaddr dst); -void data_polling_m29f400bt(chipaddr dst, uint8_t data); -void protect_m29f400bt(chipaddr bios); -void write_page_m29f400bt(chipaddr bios, uint8_t *src, - chipaddr dst, int page_size); - -/* mx29f002.c */ -int probe_29f002(struct flashchip *flash); -int erase_29f002(struct flashchip *flash); -int write_29f002(struct flashchip *flash, uint8_t *buf); - -/* pm49fl00x.c */ -int probe_49fl00x(struct flashchip *flash); -int erase_49fl00x(struct flashchip *flash); -int write_49fl00x(struct flashchip *flash, uint8_t *buf); - -/* sharplhf00l04.c */ -int probe_lhf00l04(struct flashchip *flash); -int erase_lhf00l04(struct flashchip *flash); -int write_lhf00l04(struct flashchip *flash, uint8_t *buf); -void toggle_ready_lhf00l04(chipaddr dst); -void data_polling_lhf00l04(chipaddr dst, uint8_t data); -void protect_lhf00l04(chipaddr bios); - -/* sst28sf040.c */ -int probe_28sf040(struct flashchip *flash); -int erase_28sf040(struct flashchip *flash); -int write_28sf040(struct flashchip *flash, uint8_t *buf); - -/* sst39sf020.c */ -int probe_39sf020(struct flashchip *flash); -int write_39sf020(struct flashchip *flash, uint8_t *buf); - -/* sst49lf040.c */ -int erase_49lf040(struct flashchip *flash); -int write_49lf040(struct flashchip *flash, uint8_t *buf); - -/* sst49lfxxxc.c */ -int probe_49lfxxxc(struct flashchip *flash); -int erase_49lfxxxc(struct flashchip *flash); -int write_49lfxxxc(struct flashchip *flash, uint8_t *buf); - -/* sst_fwhub.c */ -int probe_sst_fwhub(struct flashchip *flash); -int erase_sst_fwhub(struct flashchip *flash); -int erase_sst_fwhub_block(struct flashchip *flash, unsigned int offset, unsigned int page_size); -int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); - -/* w39v040c.c */ -int probe_w39v040c(struct flashchip *flash); -int erase_w39v040c(struct flashchip *flash); -int write_w39v040c(struct flashchip *flash, uint8_t *buf); - -/* w39V080fa.c */ -int probe_winbond_fwhub(struct flashchip *flash); -int erase_winbond_fwhub(struct flashchip *flash); -int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); - -/* w29ee011.c */ -int probe_w29ee011(struct flashchip *flash); - -/* w49f002u.c */ -int write_49f002(struct flashchip *flash, uint8_t *buf); - /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -768,11 +565,6 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); -/* stm50flw0x0x.c */ -int probe_stm50flw0x0x(struct flashchip *flash); -int erase_stm50flw0x0x(struct flashchip *flash); -int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); - /* serprog.c */ int serprog_init(void); int serprog_shutdown(void); @@ -787,4 +579,6 @@ void __attribute__((noreturn)) sp_die(char *msg); extern int sp_fd; +#include "chipdrivers.h" + #endif /* !__FLASH_H__ */ Added: trunk/hwaccess.h =================================================================== --- trunk/hwaccess.h (rev 0) +++ trunk/hwaccess.h 2009-12-14 03:32:24 UTC (rev 799) @@ -0,0 +1,99 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * + * Header file for hardware access and OS abstraction. Included from flash.h. + */ + +#ifndef __HWACCESS_H__ +#define __HWACCESS_H__ 1 + +#if defined(__GLIBC__) +#include <sys/io.h> +#endif +#if NEED_PCI == 1 +#include <pci/pci.h> +#endif + +/* for iopl and outb under Solaris */ +#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#include <strings.h> +#include <sys/sysi86.h> +#include <sys/psw.h> +#include <asm/sunddi.h> +#endif + +#if (defined(__MACH__) && defined(__APPLE__)) +#define __DARWIN__ +#endif + +#if defined(__FreeBSD__) || defined(__DragonFly__) + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) + #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) + #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) + #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) + #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) + #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) +#else +#if defined(__DARWIN__) + #include <DirectIO/darwinio.h> + #define off64_t off_t + #define lseek64 lseek +#endif +#if defined (__sun) && (defined(__i386) || defined(__amd64)) + /* Note different order for outb */ + #define OUTB(x,y) outb(y, x) + #define OUTW(x,y) outw(y, x) + #define OUTL(x,y) outl(y, x) + #define INB inb + #define INW inw + #define INL inl +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl + #define INB inb + #define INW inw + #define INL inl +#endif +#endif + +#if defined(__FreeBSD__) || defined(__DragonFly__) +extern int io_fd; +#endif + +#if !defined(__DARWIN__) && !defined(__FreeBSD__) && !defined(__DragonFly__) +typedef struct { uint32_t hi, lo; } msr_t; +msr_t rdmsr(int addr); +int wrmsr(int addr, msr_t msr); +#endif +#if defined(__FreeBSD__) || defined(__DragonFly__) +/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ +#undef rdmsr +#undef wrmsr +#define rdmsr freebsd_rdmsr +#define wrmsr freebsd_wrmsr +typedef struct { uint32_t hi, lo; } msr_t; +msr_t freebsd_rdmsr(int addr); +int freebsd_wrmsr(int addr, msr_t msr); +#endif + +#endif /* !__HWACCESS_H__ */

1 0

[Patch] Yet another way of doing the intel ich gpio set.
by Luc Verhaegen 14 Dec '09

14 Dec '09

After last night, i was disgusted to such an extent that i went and did this code that should meet all the (at least) logical demands made earlier. And to think that this started with adding 1 more simple board enable (http://www.flashrom.org/pipermail/flashrom/2009-October/000750.html). Some remarks here: * we do not care about the name of the intel ICH. ICH name was detected and mentioned before anyway. * we do not try to match a specific intel ICH in the board enable. That's what the big table was for to begin with. * This tiny 190 line function is entirely redone if we have a second io line that needs to be toggled. * dell poweredge: comment is useless, use the commit message. There might be a time when 50 boards might need exactly this gpio pin raised. * i might have messed up a bit or so in the gpio line checking masks, but cannot be bothered to go and trawl through everything yet again to verify this. Feel free to go and correct capitalisation. I'm off to do some real code on unichrome. Luc Verhaegen.

4 6

[PATCH] print.c fix - remove empty pcidevs header
by Adam Jurkowski 14 Dec '09

14 Dec '09

Don't print out supported PCI devices header if all following lines are excluded from build. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl> --- best regards, Adam Jurkowski

2 4

[commit] r798 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 04:07:31 +0100 (Mon, 14 Dec 2009) New Revision: 798 Modified: trunk/print.c Log: Don't print out supported PCI devices header if all following lines are excluded from build. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-12-13 22:28:00 UTC (rev 797) +++ trunk/print.c 2009-12-14 03:07:31 UTC (rev 798) @@ -231,8 +231,10 @@ print_supported_chipsets(); print_supported_boards(); #endif +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); +#endif #if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); #endif

1 0

[PATCH] Make internal/onboard programmer support optional
by Carl-Daniel Hailfinger 13 Dec '09

13 Dec '09

Internal (onboard) programming was the only feature which could not be disabled. Make various pieces of code conditional on support for internal programming. Code shared between PCI device programmers and onboard programming is now conditional as well. It is now possible to build only with dummy support: make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use case only, and it also facilitates porting to a new architecture because it is possible to focus on highlevel code only. Note: Either internal or dummy programmer needs to be compiled in due to the current behaviour of always picking a default programmer if -p is not specified. Picking an arbitrary external programmer as default wouldn't make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_internal_optional/flash.h =================================================================== --- flashrom-programmer_internal_optional/flash.h (Revision 768) +++ flashrom-programmer_internal_optional/flash.h (Arbeitskopie) @@ -30,7 +30,9 @@ #include <unistd.h> #include <stdint.h> #include <stdio.h> +#if NEED_PCI == 1 #include <pci/pci.h> +#endif /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) @@ -81,7 +83,9 @@ typedef unsigned long chipaddr; enum programmer { +#if INTERNAL_SUPPORT == 1 PROGRAMMER_INTERNAL, +#endif #if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, #endif @@ -97,7 +101,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, #endif +#if INTERNAL_SUPPORT == 1 PROGRAMMER_IT87SPI, +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -266,6 +272,7 @@ extern struct flashchip flashchips[]; +#if INTERNAL_SUPPORT == 1 struct penable { uint16_t vendor_id; uint16_t device_id; @@ -313,11 +320,13 @@ extern const struct board_info boards_bad[]; extern const struct board_info laptops_ok[]; extern const struct board_info laptops_bad[]; +#endif /* udelay.c */ void myusec_delay(int usecs); void myusec_calibrate_delay(void); +#if NEED_PCI == 1 /* pcidev.c */ #define PCI_OK 0 #define PCI_NT 1 /* Not tested */ @@ -335,11 +344,14 @@ }; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +#endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); +#if NEED_PCI == 1 /* FIXME: This should be CONFIG_PCIDEV_PROGRAMMER */ void print_supported_pcidevs(struct pcidev_status *devs); +#endif void print_supported_wiki(void); /* board_enable.c */ @@ -350,20 +362,9 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; - /* chipset_enable.c */ -extern enum chipbustype buses_supported; int chipset_flash_enable(void); -extern struct decode_sizes max_rom_decode; -extern unsigned long flashbase; - /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); @@ -386,13 +387,16 @@ #endif /* internal.c */ +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); +#endif void get_io_perms(void); void release_io_perms(void); +#if INTERNAL_SUPPORT == 1 int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -402,6 +406,7 @@ uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +#endif void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -425,6 +430,7 @@ #endif /* dummyflasher.c */ +#if DUMMY_SUPPORT == 1 int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); @@ -439,34 +445,43 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +#endif /* nic3com.c */ +#if NIC3COM_SUPPORT == 1 int nic3com_init(void); int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +#endif /* gfxnvidia.c */ +#if GFXNVIDIA_SUPPORT == 1 int gfxnvidia_init(void); int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); extern struct pcidev_status gfx_nvidia[]; +#endif /* drkaiser.c */ +#if DRKAISER_SUPPORT == 1 int drkaiser_init(void); int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); extern struct pcidev_status drkaiser_pcidev[]; +#endif /* satasii.c */ +#if SATASII_SUPPORT == 1 int satasii_init(void); int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); extern struct pcidev_status satas_sii[]; +#endif /* ft2232_spi.c */ #define FTDI_FT2232H 0x6010 @@ -485,7 +500,16 @@ int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); /* flashrom.c */ +extern enum chipbustype buses_supported; +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; +extern struct decode_sizes max_rom_decode; extern char *programmer_param; +extern unsigned long flashbase; extern int verbose; extern const char *flashrom_version; #define printf_debug(x...) { if (verbose) printf(x); } @@ -508,6 +532,7 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* cbtable.c */ +void lb_vendor_dev_from_string(char *boardstring); int coreboot_init(void); extern char *lb_part, *lb_vendor; extern int partvendor_from_cbtable; @@ -515,12 +540,14 @@ /* spi.c */ enum spi_controller { SPI_CONTROLLER_NONE, +#if INTERNAL_SUPPORT == 1 SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-programmer_internal_optional/spi.c =================================================================== --- flashrom-programmer_internal_optional/spi.c (Revision 768) +++ flashrom-programmer_internal_optional/spi.c (Arbeitskopie) @@ -40,6 +40,7 @@ .write_256 = NULL, }, +#if INTERNAL_SUPPORT == 1 { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -81,6 +82,7 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ @@ -299,11 +301,13 @@ { /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -1030,10 +1034,12 @@ int result; switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_WBSIO: fprintf(stderr, "%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); +#endif default: break; } Index: flashrom-programmer_internal_optional/Makefile =================================================================== --- flashrom-programmer_internal_optional/Makefile (Revision 768) +++ flashrom-programmer_internal_optional/Makefile (Arbeitskopie) @@ -43,13 +43,11 @@ LIBS += -lpci -OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ - sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o \ - w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ - sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ - flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ - ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - pcidev.o print.o +OBJS = jedec.o stm50flw0x0x.o w39v080fa.o sharplhf00l04.o w29ee011.o \ + sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o w39v040c.o \ + w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o m29f002.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o layout.o spi.o \ + flashrom.o print.o physmap.o internal.o udelay.o all: pciutils features dep $(PROGRAM) @@ -65,6 +63,9 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +# Always enable internal/onboard support for now. +CONFIG_INTERNAL ?= yes + # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes @@ -92,6 +93,12 @@ # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no +ifeq ($(CONFIG_INTERNAL), yes) +FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' +OBJS += chipset_enable.o board_enable.o cbtable.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -108,16 +115,19 @@ ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o +NEED_PCI := yes endif ifeq ($(CONFIG_GFXNVIDIA), yes) FEATURE_CFLAGS += -D'GFXNVIDIA_SUPPORT=1' OBJS += gfxnvidia.o +NEED_PCI := yes endif ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' OBJS += satasii.o +NEED_PCI := yes endif FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") @@ -136,8 +146,14 @@ ifeq ($(CONFIG_DRKAISER), yes) FEATURE_CFLAGS += -D'DRKAISER_SUPPORT=1' OBJS += drkaiser.o +NEED_PCI := yes endif +ifeq ($(NEED_PCI), yes) +FEATURE_CFLAGS += -D'NEED_PCI=1' +OBJS += pcidev.o +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' OBJS += print_wiki.o Index: flashrom-programmer_internal_optional/chipset_enable.c =================================================================== --- flashrom-programmer_internal_optional/chipset_enable.c (Revision 768) +++ flashrom-programmer_internal_optional/chipset_enable.c (Arbeitskopie) @@ -32,27 +32,6 @@ #include <fcntl.h> #include "flash.h" -unsigned long flashbase = 0; - -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ - -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; - -/** - * Programmers supporting multiple buses can have differing size limits on - * each bus. Store the limits for each bus in a common struct. - */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; - extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Index: flashrom-programmer_internal_optional/flashrom.c =================================================================== --- flashrom-programmer_internal_optional/flashrom.c (Revision 768) +++ flashrom-programmer_internal_optional/flashrom.c (Arbeitskopie) @@ -33,10 +33,38 @@ const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; + +#if INTERNAL_SUPPORT == 1 enum programmer programmer = PROGRAMMER_INTERNAL; +#elif DUMMY_SUPPORT == 1 +enum programmer programmer = PROGRAMMER_DUMMY; +#else +/* Activating the #error explodes on make dep. */ +//#error Neither internal nor dummy selected +#endif + char *programmer_param = NULL; +/** + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. + */ +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; + +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + const struct programmer_entry programmer_table[] = { +#if INTERNAL_SUPPORT == 1 { .name = "internal", .init = internal_init, @@ -53,6 +81,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if DUMMY_SUPPORT == 1 { @@ -149,6 +178,7 @@ }, #endif +#if INTERNAL_SUPPORT == 1 { .name = "it87spi", .init = it87spi_init, @@ -165,6 +195,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -289,6 +320,8 @@ return 0; } +unsigned long flashbase = 0; + int min(int a, int b) { return (a < b) ? a : b; @@ -656,7 +689,9 @@ " -E | --erase: erase flash device\n" " -V | --verbose: more verbose output\n" " -c | --chip <chipname>: probe only for specified flash chip\n" +#if INTERNAL_SUPPORT == 1 " -m | --mainboard <[vendor:]part>: override mainboard settings\n" +#endif " -f | --force: force write without checking image\n" " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" @@ -752,7 +787,7 @@ char *filename = NULL; - char *tempstr = NULL, *tempstr2 = NULL; + char *tempstr = NULL; print_version(); @@ -836,18 +871,12 @@ } erase_it = 1; break; +#if INTERNAL_SUPPORT == 1 case 'm': tempstr = strdup(optarg); - strtok(tempstr, ":"); - tempstr2 = strtok(NULL, ":"); - if (tempstr2) { - lb_vendor = tempstr; - lb_part = tempstr2; - } else { - lb_vendor = NULL; - lb_part = tempstr; - } + lb_vendor_dev_from_string(tempstr); break; +#endif case 'f': force = 1; break; @@ -1014,7 +1043,8 @@ "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " "tested (-V, -rV,\n-wV, -EV), and mention which " - "mainboard you tested. Thanks for your help!\n===\n"); + "mainboard or programmer you tested. Thanks for your " + "help!\n===\n"); } size = flash->total_size * 1024; @@ -1108,7 +1138,9 @@ } numbytes = fread(buf, 1, size, image); +#if INTERNAL_SUPPORT == 1 show_id(buf, size, force); +#endif fclose(image); if (numbytes != size) { fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); Index: flashrom-programmer_internal_optional/internal.c =================================================================== --- flashrom-programmer_internal_optional/internal.c (Revision 768) +++ flashrom-programmer_internal_optional/internal.c (Arbeitskopie) @@ -31,6 +31,7 @@ int io_fd; #endif +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter) { struct pci_dev *temp; @@ -99,6 +100,7 @@ return NULL; } +#endif void get_io_perms(void) { @@ -122,6 +124,7 @@ #endif } +#if INTERNAL_SUPPORT == 1 int internal_init(void) { int ret = 0; @@ -163,6 +166,7 @@ return 0; } +#endif void internal_chip_writeb(uint8_t val, chipaddr addr) { Index: flashrom-programmer_internal_optional/layout.c =================================================================== --- flashrom-programmer_internal_optional/layout.c (Revision 768) +++ flashrom-programmer_internal_optional/layout.c (Arbeitskopie) @@ -23,8 +23,10 @@ #include <ctype.h> #include "flash.h" +#if INTERNAL_SUPPORT == 1 char *mainboard_vendor = NULL; char *mainboard_part = NULL; +#endif int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -38,6 +40,7 @@ romlayout_t rom_entries[MAX_ROMLAYOUT]; +#if INTERNAL_SUPPORT == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; int show_id(uint8_t *bios, int size, int force) @@ -126,6 +129,7 @@ return 0; } +#endif int read_romlayout(char *name) { Index: flashrom-programmer_internal_optional/cbtable.c =================================================================== --- flashrom-programmer_internal_optional/cbtable.c (Revision 768) +++ flashrom-programmer_internal_optional/cbtable.c (Arbeitskopie) @@ -30,6 +30,20 @@ char *lb_part = NULL, *lb_vendor = NULL; int partvendor_from_cbtable = 0; +void lb_vendor_dev_from_string(char *boardstring) +{ + char *tempstr2 = NULL; + strtok(boardstring, ":"); + tempstr2 = strtok(NULL, ":"); + if (tempstr2) { + lb_vendor = boardstring; + lb_part = tempstr2; + } else { + lb_vendor = NULL; + lb_part = boardstring; + } +} + static unsigned long compute_checksum(void *addr, unsigned long length) { uint8_t *ptr; Index: flashrom-programmer_internal_optional/print.c =================================================================== --- flashrom-programmer_internal_optional/print.c (Revision 768) +++ flashrom-programmer_internal_optional/print.c (Arbeitskopie) @@ -144,6 +144,7 @@ } } +#if INTERNAL_SUPPORT == 1 void print_supported_chipsets(void) { int i, j, chipsetcount = 0; @@ -221,12 +222,15 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } +#endif void print_supported(void) { print_supported_chips(); +#if INTERNAL_SUPPORT == 1 print_supported_chipsets(); print_supported_boards(); +#endif printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #if NIC3COM_SUPPORT == 1 @@ -244,6 +248,7 @@ } +#if INTERNAL_SUPPORT == 1 /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ @@ -391,4 +396,5 @@ {}, }; +#endif -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 5

[commit] r797 - trunk
by svn＠flashrom.org 13 Dec '09

13 Dec '09

Author: hailfinger Date: 2009-12-13 23:28:00 +0100 (Sun, 13 Dec 2009) New Revision: 797 Modified: trunk/Makefile trunk/cbtable.c trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c trunk/internal.c trunk/layout.c trunk/print.c trunk/spi.c Log: Internal (onboard) programming was the only feature which could not be disabled. Make various pieces of code conditional on support for internal programming. Code shared between PCI device programmers and onboard programming is now conditional as well. It is now possible to build only with dummy support: make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use case only, and it also facilitates porting to a new architecture because it is possible to focus on highlevel code only. Note: Either internal or dummy programmer needs to be compiled in due to the current behaviour of always picking a default programmer if -p is not specified. Picking an arbitrary external programmer as default wouldn't make sense. Build and runtime tested in all 1024 possible build combinations. The only failures are by design as mentioned above. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/Makefile 2009-12-13 22:28:00 UTC (rev 797) @@ -43,13 +43,11 @@ LIBS += -lpci -OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ - sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o \ - w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ - sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ - flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ - ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - pcidev.o print.o +OBJS = jedec.o stm50flw0x0x.o w39v080fa.o sharplhf00l04.o w29ee011.o \ + sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o w39v040c.o \ + w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o m29f002.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o layout.o spi.o \ + flashrom.o print.o physmap.o internal.o udelay.o all: pciutils features dep $(PROGRAM) @@ -65,6 +63,9 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +# Always enable internal/onboard support for now. +CONFIG_INTERNAL ?= yes + # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes @@ -95,6 +96,12 @@ # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no +ifeq ($(CONFIG_INTERNAL), yes) +FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' +OBJS += chipset_enable.o board_enable.o cbtable.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -111,16 +118,19 @@ ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o +NEED_PCI := yes endif ifeq ($(CONFIG_GFXNVIDIA), yes) FEATURE_CFLAGS += -D'GFXNVIDIA_SUPPORT=1' OBJS += gfxnvidia.o +NEED_PCI := yes endif ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' OBJS += satasii.o +NEED_PCI := yes endif FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") @@ -139,6 +149,7 @@ ifeq ($(CONFIG_DRKAISER), yes) FEATURE_CFLAGS += -D'DRKAISER_SUPPORT=1' OBJS += drkaiser.o +NEED_PCI := yes endif ifeq ($(CONFIG_BUSPIRATESPI), yes) @@ -155,6 +166,11 @@ endif endif +ifeq ($(NEED_PCI), yes) +FEATURE_CFLAGS += -D'NEED_PCI=1' +OBJS += pcidev.o +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' OBJS += print_wiki.o Modified: trunk/cbtable.c =================================================================== --- trunk/cbtable.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/cbtable.c 2009-12-13 22:28:00 UTC (rev 797) @@ -30,6 +30,20 @@ char *lb_part = NULL, *lb_vendor = NULL; int partvendor_from_cbtable = 0; +void lb_vendor_dev_from_string(char *boardstring) +{ + char *tempstr2 = NULL; + strtok(boardstring, ":"); + tempstr2 = strtok(NULL, ":"); + if (tempstr2) { + lb_vendor = boardstring; + lb_part = tempstr2; + } else { + lb_vendor = NULL; + lb_part = boardstring; + } +} + static unsigned long compute_checksum(void *addr, unsigned long length) { uint8_t *ptr; Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/chipset_enable.c 2009-12-13 22:28:00 UTC (rev 797) @@ -32,27 +32,6 @@ #include <fcntl.h> #include "flash.h" -unsigned long flashbase = 0; - -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ - -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; - -/** - * Programmers supporting multiple buses can have differing size limits on - * each bus. Store the limits for each bus in a common struct. - */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; - extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/flash.h 2009-12-13 22:28:00 UTC (rev 797) @@ -30,7 +30,9 @@ #include <unistd.h> #include <stdint.h> #include <stdio.h> +#if NEED_PCI == 1 #include <pci/pci.h> +#endif /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) @@ -81,7 +83,9 @@ typedef unsigned long chipaddr; enum programmer { +#if INTERNAL_SUPPORT == 1 PROGRAMMER_INTERNAL, +#endif #if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, #endif @@ -97,7 +101,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, #endif +#if INTERNAL_SUPPORT == 1 PROGRAMMER_IT87SPI, +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -269,6 +275,7 @@ extern struct flashchip flashchips[]; +#if INTERNAL_SUPPORT == 1 struct penable { uint16_t vendor_id; uint16_t device_id; @@ -316,11 +323,13 @@ extern const struct board_info boards_bad[]; extern const struct board_info laptops_ok[]; extern const struct board_info laptops_bad[]; +#endif /* udelay.c */ void myusec_delay(int usecs); void myusec_calibrate_delay(void); +#if NEED_PCI == 1 /* pcidev.c */ #define PCI_OK 0 #define PCI_NT 1 /* Not tested */ @@ -338,11 +347,14 @@ }; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +#endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); +#endif void print_supported_wiki(void); /* board_enable.c */ @@ -353,20 +365,9 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; - /* chipset_enable.c */ -extern enum chipbustype buses_supported; int chipset_flash_enable(void); -extern struct decode_sizes max_rom_decode; -extern unsigned long flashbase; - /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); @@ -389,13 +390,16 @@ #endif /* internal.c */ +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); +#endif void get_io_perms(void); void release_io_perms(void); +#if INTERNAL_SUPPORT == 1 int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -405,6 +409,7 @@ uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +#endif void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -428,6 +433,7 @@ #endif /* dummyflasher.c */ +#if DUMMY_SUPPORT == 1 int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); @@ -442,34 +448,43 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +#endif /* nic3com.c */ +#if NIC3COM_SUPPORT == 1 int nic3com_init(void); int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +#endif /* gfxnvidia.c */ +#if GFXNVIDIA_SUPPORT == 1 int gfxnvidia_init(void); int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); extern struct pcidev_status gfx_nvidia[]; +#endif /* drkaiser.c */ +#if DRKAISER_SUPPORT == 1 int drkaiser_init(void); int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); extern struct pcidev_status drkaiser_pcidev[]; +#endif /* satasii.c */ +#if SATASII_SUPPORT == 1 int satasii_init(void); int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); extern struct pcidev_status satas_sii[]; +#endif /* ft2232_spi.c */ #define FTDI_FT2232H 0x6010 @@ -498,7 +513,16 @@ int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ +extern enum chipbustype buses_supported; +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; +extern struct decode_sizes max_rom_decode; extern char *programmer_param; +extern unsigned long flashbase; extern int verbose; extern const char *flashrom_version; #define printf_debug(x...) { if (verbose) printf(x); } @@ -522,6 +546,7 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* cbtable.c */ +void lb_vendor_dev_from_string(char *boardstring); int coreboot_init(void); extern char *lb_part, *lb_vendor; extern int partvendor_from_cbtable; @@ -529,12 +554,14 @@ /* spi.c */ enum spi_controller { SPI_CONTROLLER_NONE, +#if INTERNAL_SUPPORT == 1 SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/flashrom.c 2009-12-13 22:28:00 UTC (rev 797) @@ -33,10 +33,38 @@ const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; + +#if INTERNAL_SUPPORT == 1 enum programmer programmer = PROGRAMMER_INTERNAL; +#elif DUMMY_SUPPORT == 1 +enum programmer programmer = PROGRAMMER_DUMMY; +#else +/* Activating the #error explodes on make dep. */ +//#error Neither internal nor dummy selected +#endif + char *programmer_param = NULL; +/** + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. + */ +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; + +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + const struct programmer_entry programmer_table[] = { +#if INTERNAL_SUPPORT == 1 { .name = "internal", .init = internal_init, @@ -53,6 +81,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if DUMMY_SUPPORT == 1 { @@ -149,6 +178,7 @@ }, #endif +#if INTERNAL_SUPPORT == 1 { .name = "it87spi", .init = it87spi_init, @@ -165,6 +195,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -308,6 +339,8 @@ return 0; } +unsigned long flashbase = 0; + int min(int a, int b) { return (a < b) ? a : b; @@ -866,7 +899,9 @@ " -E | --erase: erase flash device\n" " -V | --verbose: more verbose output\n" " -c | --chip <chipname>: probe only for specified flash chip\n" +#if INTERNAL_SUPPORT == 1 " -m | --mainboard <[vendor:]part>: override mainboard settings\n" +#endif " -f | --force: force write without checking image\n" " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" @@ -962,7 +997,7 @@ char *filename = NULL; - char *tempstr = NULL, *tempstr2 = NULL; + char *tempstr = NULL; print_version(); @@ -1046,18 +1081,12 @@ } erase_it = 1; break; +#if INTERNAL_SUPPORT == 1 case 'm': tempstr = strdup(optarg); - strtok(tempstr, ":"); - tempstr2 = strtok(NULL, ":"); - if (tempstr2) { - lb_vendor = tempstr; - lb_part = tempstr2; - } else { - lb_vendor = NULL; - lb_part = tempstr; - } + lb_vendor_dev_from_string(tempstr); break; +#endif case 'f': force = 1; break; @@ -1224,7 +1253,8 @@ "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " "tested (-V, -rV,\n-wV, -EV), and mention which " - "mainboard you tested. Thanks for your help!\n===\n"); + "mainboard or programmer you tested. Thanks for your " + "help!\n===\n"); } size = flash->total_size * 1024; @@ -1318,7 +1348,9 @@ } numbytes = fread(buf, 1, size, image); +#if INTERNAL_SUPPORT == 1 show_id(buf, size, force); +#endif fclose(image); if (numbytes != size) { fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/internal.c 2009-12-13 22:28:00 UTC (rev 797) @@ -31,6 +31,7 @@ int io_fd; #endif +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter) { struct pci_dev *temp; @@ -99,6 +100,7 @@ return NULL; } +#endif void get_io_perms(void) { @@ -122,6 +124,7 @@ #endif } +#if INTERNAL_SUPPORT == 1 int internal_init(void) { int ret = 0; @@ -163,6 +166,7 @@ return 0; } +#endif void internal_chip_writeb(uint8_t val, chipaddr addr) { Modified: trunk/layout.c =================================================================== --- trunk/layout.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/layout.c 2009-12-13 22:28:00 UTC (rev 797) @@ -23,8 +23,10 @@ #include <ctype.h> #include "flash.h" +#if INTERNAL_SUPPORT == 1 char *mainboard_vendor = NULL; char *mainboard_part = NULL; +#endif int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -38,6 +40,7 @@ romlayout_t rom_entries[MAX_ROMLAYOUT]; +#if INTERNAL_SUPPORT == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; int show_id(uint8_t *bios, int size, int force) @@ -126,6 +129,7 @@ return 0; } +#endif int read_romlayout(char *name) { Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/print.c 2009-12-13 22:28:00 UTC (rev 797) @@ -144,6 +144,7 @@ } } +#if INTERNAL_SUPPORT == 1 void print_supported_chipsets(void) { int i, j, chipsetcount = 0; @@ -221,12 +222,15 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } +#endif void print_supported(void) { print_supported_chips(); +#if INTERNAL_SUPPORT == 1 print_supported_chipsets(); print_supported_boards(); +#endif printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #if NIC3COM_SUPPORT == 1 @@ -244,6 +248,7 @@ } +#if INTERNAL_SUPPORT == 1 /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ @@ -394,4 +399,5 @@ {}, }; +#endif Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-12-09 11:39:02 UTC (rev 796) +++ trunk/spi.c 2009-12-13 22:28:00 UTC (rev 797) @@ -40,6 +40,7 @@ .write_256 = NULL, }, +#if INTERNAL_SUPPORT == 1 { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -81,6 +82,7 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ @@ -308,11 +310,13 @@ { /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -1042,10 +1046,12 @@ int result; switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_WBSIO: fprintf(stderr, "%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); +#endif default: break; }

1 0

NF7-S v2.0
by Dana Goyette 13 Dec '09

13 Dec '09

Board is Abit NF7-S 2.0; dmidecode says version is "2.X,1.0" Current BIOS version is 26. Trying to flash this BIOS version: http://www.nforcershq.com/forum/nf7-s-2-0-official-d27-bios-with-new-4276-s… Official BIOS versions are here: http://www.abit.com.tw/page/en/download/download_bios_detail.php?pFILE_TYPE…

1 0

[PATCH] LibFlashrom: File Structure
by Sean Nelson 12 Dec '09

12 Dec '09

This patch moves the current files into folders, library related in libflashrom/, CLI related in cli/, QT4 gui in qt4/. The Qt4.5 gui hasn't been integrated into the tree yet. Please review at your leisure. Yes, this is a very large patch. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 2

succesful bios upgrade on MSI K9A2 CF-F
by Tim Kuip 11 Dec '09

11 Dec '09

I used flashrom under kubuntu 9.10 to upgrade ami bios 7388 v1.8 to to v1.10 on my MSI K9A2 board. If you need any detailed information, please ask. Regards, Tim Kuip

1 0

No EEPROM/Flash Device found
by N oxer 11 Dec '09

11 Dec '09

Hi, After being told that I could use flashrom to update my BIOS on my Toshiba Satellite L30-101 and it told me that there was no EEPROM/Flash device found. So I went on to the flashrom IRC channel and asked about this and they said I have to e-mail the following terminal commands this email address. To save room, I posted them on my pastebin.ca account and can be found at the links below: flashrom -V : http://pastebin.ca/1711385 lspci -nnvvvxxx : http://pastebin.ca/1711389 superiotool -deV : http://pastebin.ca/1711394 and also a link to the BIOS update : http://support1.toshiba-tro.de/tedd-files2/0/bios-20071106150302.ZIP I was just wondering if there is anything I am able to do about this? As I am trying to update my BIOS to resolve some battery problems with my laptop but Toshiba only have an .exe file to update it with and none of my machines use Windows.

1 0

Dell Demension E521 link: Dell BIOS
by LittleDeadPenguin 11 Dec '09

11 Dec '09

http://support.dell.com/support/downloads/download.aspx?c=us&cs=19&l=en&s=d…

1 0

Dell Dimension E521 (MCP51) lspci -nnvvvxxx
by LittleDeadPenguin 11 Dec '09

11 Dec '09

00:00.0 RAM memory [0500]: nVidia Corporation C51 Host Bridge [10de:02f0] (rev a2) Subsystem: nVidia Corporation C51 Host Bridge [10de:02f0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 1: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 800MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 f0 02 06 00 b0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 f0 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: de 10 f0 02 08 e0 e0 01 22 00 11 11 22 20 11 00 50: 23 06 7f 80 03 05 7f 80 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 05 00 70: 44 44 41 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 1f 00 64 0c 03 00 00 00 7f 00 00 00 90: 78 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 61 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 10 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.1 RAM memory [0500]: nVidia Corporation C51 Memory Controller 0 [10de:02fa] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 0 [10de:02fa] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- INTx- 00: de 10 fa 02 00 01 20 40 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 fa 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 10 00 21 21 14 00 11 11 00 00 03 00 00 00 60: 21 88 13 02 de 8f e1 1f 08 72 4e 10 02 3f 00 20 70: 10 32 54 0a 10 00 00 00 a0 00 00 00 38 00 00 01 80: 00 00 00 00 00 00 00 00 00 00 50 3f 90 3f 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 01 00 00 00 80 f9 fd 00 e0: 00 00 c9 fe 00 00 00 00 00 fc ff ff 00 00 00 00 f0: 00 00 00 00 c7 02 28 00 00 00 00 00 00 00 00 00 00:00.2 RAM memory [0500]: nVidia Corporation C51 Memory Controller 1 [10de:02fe] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 1 [10de:02fe] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 fe 02 00 00 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 fe 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: de 10 fe 02 1b 1c 1c 60 1b 1c c0 21 00 00 00 00 50: 36 00 38 c9 01 00 00 00 39 00 3b c9 02 1f 1c 80 60: 02 1f 1c 00 00 00 00 00 02 10 1c a0 02 0c 1c 90 70: 02 10 1c 90 02 14 1c 90 02 0c 1c 80 02 10 1c 80 80: 02 14 1c 80 02 18 1c 80 02 1c 1c 80 01 10 1c 80 90: 02 14 1c 80 11 00 11 00 32 01 00 00 00 00 00 00 a0: c2 00 40 41 10 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 41 23 05 08 c0: fd ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.3 RAM memory [0500]: nVidia Corporation C51 Memory Controller 5 [10de:02f8] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 5 [10de:02f8] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 f8 02 00 00 a0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 f8 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: de 10 f8 02 00 00 00 00 02 10 1c 80 02 10 1c a0 50: 02 0c 1c 90 02 10 1c 90 02 14 1c 90 02 0c 1c 80 60: 02 10 1c 80 02 14 1c 80 02 18 1c 80 02 1c 1c 80 70: 01 10 1c 80 1f 20 c0 81 00 00 00 00 3e 30 40 c9 80: 01 00 00 00 45 30 47 c9 02 1f 1c 80 70 20 00 40 90: 89 da 01 09 00 00 00 00 11 00 10 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 08 00 00 00 0c 19 00 00 10 00 02 00 00 04 40 04 c0: 00 00 00 00 00 00 00 00 01 01 00 05 00 00 00 00 d0: 00 00 f0 03 00 04 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 60 ea 10 10 18 00 00 20 00 00 00 00 00 00 00 00 00:00.4 RAM memory [0500]: nVidia Corporation C51 Memory Controller 4 [10de:02f9] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 4 [10de:02f9] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 f9 02 06 00 a0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 f9 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: ef dd 7b 2f f7 de 7b 2f f7 de 7b 2f f7 02 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 70: 0a 00 00 00 03 00 00 00 25 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 05 00 00 00 04 00 00 00 90: 03 04 00 00 01 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.5 RAM memory [0500]: nVidia Corporation C51 Host Bridge [10de:02ff] (rev a2) Subsystem: nVidia Corporation C51 Host Bridge [10de:02ff] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] #00 [00fe] Capabilities: [fc] #00 [0000] 00: de 10 ff 02 06 00 b0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 ff 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: 17 00 00 00 00 fe fe 00 00 fe fe 00 00 fe fe 00 50: 00 fe fe 00 00 fe fe 00 00 fe fe 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.6 RAM memory [0500]: nVidia Corporation C51 Memory Controller 3 [10de:027f] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 3 [10de:027f] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 7f 02 00 01 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 7f 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 08 00 00 00 00 00 00 00 00 80 cb fe 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.7 RAM memory [0500]: nVidia Corporation C51 Memory Controller 2 [10de:027e] (rev a2) Subsystem: nVidia Corporation C51 Memory Controller 2 [10de:027e] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 7e 02 00 00 20 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 7e 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: de 10 7e 02 11 00 00 00 74 05 00 00 11 00 00 00 50: 64 06 00 00 60 00 60 00 60 60 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04 b0: ff ff 03 00 10 11 00 00 ac 10 20 00 30 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fc] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: fd800000-fd8fffff Prefetchable memory behind bridge: 00000000fd700000-00000000fd7fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0300c Data: 4149 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 fc 02 07 04 10 00 a1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 00 20: 80 fd 80 fd 71 fd 71 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 11 3c 11 02 90: 00 00 11 10 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fd] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00008000-00008fff Memory behind bridge: fde00000-fdefffff Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0300c Data: 4151 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 fd 02 07 04 10 00 a1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 81 81 00 00 20: e0 fd e0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 51 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 11 3c 11 01 90: 00 00 11 10 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: nVidia Corporation C51 PCI Express Bridge [10de:02fb] (rev a1) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fdc00000-fdcfffff Prefetchable memory behind bridge: 00000000fd900000-00000000fd9fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0300c Data: 4159 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 fb 02 07 04 10 00 a1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 b1 b1 00 00 20: c0 fd c0 fd 91 fd 91 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 59 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 1f 28 00 00 01 3d 11 00 90: 00 00 01 11 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 VGA compatible controller [0300]: nVidia Corporation C51 [GeForce 6150 LE] [10de:0241] (rev a2) (prog-if 00 [VGA controller]) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fc000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at e0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at fb000000 (64-bit, non-prefetchable) [size=16M] [virtual] Expansion ROM at f4000000 [disabled] [size=128K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Kernel driver in use: nvidia Kernel modules: nvidia, nvidiafb 00: de 10 41 02 07 00 b0 00 a2 00 00 03 00 00 00 00 10: 00 00 00 fc 0c 00 00 e0 00 00 00 00 04 00 00 fb 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 48 00 00 00 00 00 00 00 07 01 00 00 40: 28 10 ed 01 00 00 00 00 01 50 02 00 00 00 00 00 50: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 00 00 04 00 00 00 00 00 00 00 01 00 00 00 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: 00 00 b0 01 00 00 00 08 00 00 00 00 ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00:09.0 RAM memory [0500]: nVidia Corporation MCP51 Host Bridge [10de:0270] (rev a2) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=9 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 0: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 800MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 70 02 06 00 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 40: de 10 84 cb 08 e0 e9 01 22 20 00 00 d0 00 00 00 50: 23 05 7f 80 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 05 00 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 55 00 80: 23 55 55 00 fa 00 64 0c 03 00 00 00 7f 00 00 00 90: 78 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 ISA bridge [0601]: nVidia Corporation MCP51 LPC Bridge [10de:0260] (rev a3) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 60 02 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 28 10 ed 01 00 00 ff fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f9 ff 70: 10 00 ff ff c5 00 00 00 00 00 45 19 00 c0 00 03 80: 09 20 00 d8 01 10 00 00 c0 00 00 01 00 00 00 00 90: 00 00 00 00 00 00 00 00 21 47 65 b7 ef cd 00 00 a0: 00 00 30 80 00 00 01 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 08 80 08 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:0a.1 SMBus [0c05]: nVidia Corporation MCP51 SMBus [10de:0264] (rev a3) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 10 Region 4: I/O ports at 1c00 [size=64] Region 5: I/O ports at 1c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus Kernel modules: i2c-nforce2 00: de 10 64 02 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 1c 00 00 41 1c 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 00 00 40: 28 10 ed 01 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 10 00 00 01 14 00 00 01 18 00 00 00 00 00 00 70: 01 00 00 00 00 00 c8 fe 00 00 fe fe 01 20 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 10 05 00 00 a0 80 00 80 74 00 00 41 44 44 11 f0: 5a ff 5f bf 00 00 00 c0 10 00 00 00 00 00 00 00 00:0a.2 RAM memory [0500]: nVidia Corporation MCP51 Memory Controller 0 [10de:0272] (rev a3) Subsystem: Dell Device [1028:01ed] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 72 02 00 04 a0 00 a3 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10 50: 10 10 10 10 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 03 00 00 12 00 00 00 02 00 00 00 10 01 12 00 70: 32 33 00 00 03 00 00 00 00 00 00 00 12 01 00 00 80: 10 00 00 00 00 00 00 00 00 00 00 00 30 02 00 00 90: 00 00 00 00 01 20 00 00 01 00 00 00 00 09 00 00 a0: 01 02 00 00 00 10 00 00 05 00 00 00 01 00 00 00 b0: 00 10 00 80 01 00 00 80 00 00 00 00 02 00 00 00 c0: 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 USB Controller [0c03]: nVidia Corporation MCP51 USB Controller [10de:026d] (rev a3) (prog-if 10 [OHCI]) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at fe02f000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd Kernel modules: ohci-hcd 00: de 10 6d 02 07 00 b0 00 a3 10 03 0c 00 00 80 00 10: 00 f0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 0f 01 03 01 40: 28 10 ed 01 01 00 02 fe 00 00 00 00 00 00 00 00 50: 0c 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.1 USB Controller [0c03]: nVidia Corporation MCP51 USB Controller [10de:026e] (rev a3) (prog-if 20 [EHCI]) Subsystem: Dell Device [1028:01ed] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 22 Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00: de 10 6e 02 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 02 03 01 40: 28 10 ed 01 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 0a 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 74 00 80: 01 00 02 fe 00 80 00 00 00 00 00 00 15 16 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 11 22 33 00 00 00 00 ff 00 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:0e.0 IDE interface [0101]: nVidia Corporation MCP51 Serial ATA Controller [10de:0266] (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 21 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at e000 [size=16] Region 5: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: sata_nv Kernel modules: sata_nv 00: de 10 66 02 07 00 b0 00 a1 85 01 01 00 00 00 00 10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00 20: 01 e0 00 00 00 d0 02 fe 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 40: 28 10 ed 01 01 b0 02 00 00 00 00 00 00 00 00 00 50: 07 00 00 00 00 00 00 00 a8 20 a8 20 66 00 20 20 60: 00 c7 00 c6 51 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 c0 50 08 f3 d3 00 00 08 b0 00 00 08 04 90: 00 00 08 80 00 00 00 00 06 00 06 10 00 00 01 01 a0: 14 10 00 2c 00 00 00 00 00 00 00 00 33 33 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 0a 00 02 36 42 00 00 00 00 00 00 00 0f 00 10 80 e0: 0a 00 02 6c 42 00 00 00 00 00 00 00 00 00 30 e0 f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00:0f.0 IDE interface [0101]: nVidia Corporation MCP51 Serial ATA Controller [10de:0267] (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: Dell Device [1028:01ed] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 20 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at cc00 [size=16] Region 5: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: sata_nv Kernel modules: sata_nv 00: de 10 67 02 07 00 b0 00 a1 85 01 01 00 00 00 00 10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00 20: 01 cc 00 00 00 c0 02 fe 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: 28 10 ed 01 01 b0 02 00 00 00 00 00 00 00 00 00 50: 07 00 00 00 00 00 00 00 a8 a8 a8 a8 aa 00 99 99 60: 00 00 00 00 51 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00 80: 00 00 00 c0 b7 6c b1 84 00 00 0e 21 78 b0 0a d1 90: 00 00 68 10 00 00 00 00 06 00 06 10 00 00 01 01 a0: 14 10 00 00 00 00 00 00 00 00 00 00 33 33 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 0a 00 02 36 42 00 00 00 00 00 00 00 0f 00 f0 07 e0: 0a 00 02 36 42 00 00 00 00 00 00 00 08 00 14 00 f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00:10.0 PCI bridge [0604]: nVidia Corporation MCP51 PCI Bridge [10de:026f] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=32 I/O behind bridge: 00009000-00009fff Memory behind bridge: fdb00000-fdbfffff Prefetchable memory behind bridge: fda00000-fdafffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- Capabilities: [b8] Subsystem: Gammagraphx, Inc. Device [0000:0000] Capabilities: [8c] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 6f 02 07 00 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 20 90 90 80 02 20: b0 fd b0 fd a0 fd a0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 ff 00 04 02 40: 00 00 03 00 01 00 02 00 05 00 00 00 00 00 44 00 50: 00 00 fe df 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 fe 1f 01 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 00 00 00 00 c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:10.1 Audio device [0403]: nVidia Corporation MCP51 High Definition Audio [10de:026c] (rev a2) Subsystem: Dell Device [1028:01ed] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin B routed to IRQ 23 Region 0: Memory at fe024000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: de 10 6c 02 06 00 b0 00 a2 00 03 04 00 00 80 00 10: 00 40 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 02 05 40: 28 10 ed 01 01 50 02 c0 00 00 00 00 01 01 0f 00 50: 05 6c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 46 00 29 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 01 00 e4 00 00 00 20 c8 0e 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 69 01 61 01 00 00 04 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 1f 01 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 0a 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 90: 03 00 e0 00 00 ff ef 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 03 00 f4 00 00 02 fe 00 b0: 03 00 f0 00 80 4f f0 00 00 00 00 00 00 00 00 00 c0: 13 80 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 01 20 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 01 00 80 00 01 00 a0 00 50: 01 00 00 00 01 00 40 00 01 00 c0 00 01 00 e0 00 60: 00 00 00 00 e0 3f 18 00 e0 3f 38 00 e0 3f 18 00 70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 80: 20 25 00 00 00 00 00 00 24 c2 68 ae 20 13 82 28 90: 10 04 01 00 6a 80 10 67 24 00 00 80 20 20 27 00 a0: ff 02 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 b0: 11 98 90 1c 18 00 00 00 90 16 1f a2 aa 06 1a 76 c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: e0 74 1c a3 5f 1d c1 65 e5 91 ec 37 ab 36 cd 4b e0: 40 97 da 70 a9 09 e0 71 21 86 dd 71 34 35 84 1a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k8temp Kernel modules: k8temp 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 04 00 40 00 10 0a 00 00 00 00 00 00 00 00 50: 48 3c b6 99 e9 00 00 00 00 00 00 00 00 08 62 5d 60: d3 00 00 00 01 77 1f 00 00 00 00 00 00 00 00 00 70: 11 01 32 51 21 40 70 50 00 2a 00 08 17 21 00 00 80: 00 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00 90: 03 00 00 00 02 00 00 00 00 10 1f 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 a0 07 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 01 a7 0d 00 00 00 80 08 25 25 25 00 e0: 00 00 00 00 7e 60 34 00 19 17 00 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 b1 0f 06 00 04:07.0 Ethernet controller [0200]: Broadcom Corporation BCM4401-B0 100Base-TX [14e4:170c] (rev 02) Subsystem: Dell Device [1028:01ed] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fdbfe000 (32-bit, non-prefetchable) [size=8K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- Kernel driver in use: b44 Kernel modules: b44 00: e4 14 0c 17 06 00 10 00 02 00 00 02 00 40 00 00 10: 00 e0 bf fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 ed 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 00 02 fe 00 40 00 34 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 18 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 40 00 00 00 c0 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

Dell Dimention E512 (MCP51) flashrom -V
by LittleDeadPenguin 11 Dec '09

11 Dec '09

Calibrating delay loop... 622M loops per second. OK. No coreboot table found. Found chipset "NVIDIA MCP51", enabling flash write... OK. Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A25L40P, 512 KB: spi_command called, but no SPI chipset detected Probing for AMIC Technology A49LF040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMIC Technology A29040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI chipset detected Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset detected Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI chipset detected Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI chipset detected Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset detected Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset detected Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI chipset detected Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset detected Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset detected Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset detected Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset detected Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset detected Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x9d, id2 0x6e Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI chipset detected Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI chipset detected Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0x9d, did 0x6e Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no SPI chipset detected Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI chipset detected No operations were specified.

1 0

cannot work on Intel ICH7/ICH7R & SST SST25VF016B (2048 KB, SPI)
by Water Chen 11 Dec '09

11 Dec '09

Hi, flashrom cannot work on Intel ICH7/ICH7R / SST SST25VF016B (2048 KB, SPI). MB: Supermicro X7SLM-L / http://www.supermicro.com/products/motherboard/Core2Duo/945/X7SLM-L.cfm The outputs of 'flashrom -V', 'lspci -nnvvvxxx', 'superiotool -deV', 'dd if=/dev/mem of=sm_x7slm.system.rom bs=64k count=1 skip=15' are attached. # ./flashrom -w BIOS_X7SLM-L.ROM flashrom v0.9.1-r792 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... spi_write_status_register failed during command execution spi_write_status_register failed Erasing flash before programming... Erasing flash chip... spi_write_status_register failed during command execution spi_write_status_register failed spi_disable_blockprotect failed FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Thank you. Water Chen

2 2

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom