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[commit] r891 - trunk
by repository service 04 Feb '10

04 Feb '10

Author: oxygene Date: Thu Feb 4 09:29:18 2010 New Revision: 891 URL: http://flashrom.org/trac/coreboot/changeset/891 Log: Properly initialize USB device in dediprog driver. That's necessary to use bulk transfers, and just the right thing in any case. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/dediprog.c Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Thu Feb 4 03:40:16 2010 (r890) +++ trunk/dediprog.c Thu Feb 4 09:29:18 2010 (r891) @@ -294,6 +294,8 @@ dev->descriptor.idVendor, dev->descriptor.idProduct); dediprog_handle = usb_open(dev); + usb_set_configuration(dediprog_handle, 1); + usb_claim_interface(dediprog_handle, 0); /* URB 6. Command A. */ if (dediprog_command_a()) return 1;

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(update) Gigabyte GA-7ZXE v1.1
by Charles M 04 Feb '10

04 Feb '10

In the last message I stated the board was 1.0, but it's actually 1.1 (the board was a little dirty and I mistook the 1.1 for 1.0). Superiotool didn't find the super i/o chip. From a quick glance it appears to be a VIA VT82C686B chip. Cheers, Charles

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Re: [flashrom] [commit] r885 - trunk
by Luc Verhaegen 04 Feb '10

04 Feb '10

On Thu, Jan 28, 2010 at 08:02:37PM +0100, svn(a)flashrom.org wrote: > Author: uwe > Date: 2010-01-28 20:02:36 +0100 (Thu, 28 Jan 2010) > New Revision: 885 > > Modified: > trunk/board_enable.c > Log: > The GIGABYTE GA-7ZM has a maximum decode size (parallel chips) of 512 KB. > > Add this information to the new field in the board-enable table. We match the > board via two sets of PCI IDs. However, as we don't need a board-enable > function for this board (it works out of the box; well, at least if you remove > the JP9 jumper on the board), change the code to allow NULL as value for > the board-enable function. There will likely be more boards in the future where > we want to record a maximum decode size but which don't need a board-enable. > > This is hardware-tested on the GIGABYTE GA-7ZM by successfully writing a 512KB > image of random bytes to a chip in this board. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Sean Nelson <audiohacked(a)gmail.com> > > > > Modified: trunk/board_enable.c > =================================================================== > --- trunk/board_enable.c 2010-01-27 10:08:33 UTC (rev 884) > +++ trunk/board_enable.c 2010-01-28 19:02:36 UTC (rev 885) > @@ -1208,6 +1208,7 @@ > {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, w836xx_memw_enable_2e}, > {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, nvidia_mcp_gpio31_raise}, > {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, board_epox_ep_bx3}, > + {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, NULL}, > {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, it87xx_probe_spi_flash}, > {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, it8705f_write_enable_2e}, > {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, nvidia_mcp_gpio21_raise}, http://www.google.de/#q=1106%3A0686+1106%3A0686+1106%3A3058+1458%3Aa000&aq=… reveals that there are at least two different boards which matches this. You are only matching the southbridge here, and a relatively bogus (and common) subsystem id, which only tells us that it's a gigabyte board. The VT82C686 was a _hugely_ successful southbridge. I cannot even begin to count how many gigabyte boards use this chipset. So, first; swap the pairs around. Second, use 0x1106, 0x0305, 0, 0 to at least narrow the northbridge down. A further check on the gigabyte gives me 17 possible combinations of the different kt133 variations and the 686 southbridge. This makes it completely impossible to even consider the above change a sufficient match. Please provide the output of flashrom -V so we can identify a DMI match. The above logic should give you some idea of the investigation required to get a good match. It just takes a few minutes to do so too. Luc Verhaegen.

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[commit] r887 - trunk
by repository service 04 Feb '10

04 Feb '10

Author: uwe Date: Sun Jan 31 21:13:06 2010 New Revision: 887 URL: http://flashrom.org/trac/coreboot/changeset/887 Log: Add the Tekram P6Pro-A5 board as supported (trivial). The board doesn't need a board-enable, writing works out of the box. Also, the board can only decode 256KB. I verified this by writing a 512KB image of random bytes (which fails), whereas 256KB of random bytes can be written correctly. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/print_wiki.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jan 29 00:55:12 2010 (r886) +++ trunk/board_enable.c Sun Jan 31 21:13:06 2010 (r887) @@ -1235,6 +1235,7 @@ {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, w836xx_memw_enable_2e}, + {0x1106, 0x3038, 0x0925, 0x1234, 0, 0, 0, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, it87xx_probe_spi_flash}, Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jan 29 00:55:12 2010 (r886) +++ trunk/print_wiki.c Sun Jan 31 21:13:06 2010 (r887) @@ -167,6 +167,7 @@ { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, + { "Tekram", "P6Pro-A5", "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm" }, { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" },

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[commit] r890 - trunk
by repository service 04 Feb '10

04 Feb '10

Author: uwe Date: Thu Feb 4 03:40:16 2010 New Revision: 890 URL: http://flashrom.org/trac/coreboot/changeset/890 Log: Add a second set of PCI IDs for the Tekram P6Pro-A5 (trivial). (Re-)tested on hardware, detection works OK. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Feb 2 12:09:03 2010 (r889) +++ trunk/board_enable.c Thu Feb 4 03:40:16 2010 (r890) @@ -1235,7 +1235,7 @@ {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, w836xx_memw_enable_2e}, - {0x1106, 0x3038, 0x0925, 0x1234, 0, 0, 0, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, it87xx_probe_spi_flash},

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ANNOUNCE: flashrom 0.9.1 is out
by Carl-Daniel Hailfinger 04 Feb '10

04 Feb '10

After many months of testing, and 5 months after tagging the release, we are happy to announce that flashrom 0.9.1 is ready for your machines. flashrom is a utility for reading, writing, erasing and verifying flash ROM chips on mainboards, SATA/network controller cards and external programmers. flashrom is often used to flash BIOS/EFI/coreboot/firmware images because it allows you to update your BIOS/EFI/coreboot/firmware without opening the computer and without any special boot procedures. After nine years of development and constant improvement, we have added support for every BIOS flash ROM technology present on x86 mainboards and every flash ROM chip we ever saw in the wild. Highlights of flashrom include: * Parallel, LPC, FWH and SPI flash interfaces. * Support for on-mainboard programming and external programmers. * 192 flash chip families and half a dozen variants of each family. * Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more have all been verified to work. * 78 different chipsets, some with multiple flash controllers. * Special mainboard enabling code for dozens of nonstandard mainboards. * No physical access needed. root access is sufficient. * No bootable floppy disk, bootable CD-ROM or other media needed. * No keyboard or monitor needed. Simply reflash remotely via SSH. * No instant reboot needed. Reflash your ROM in a running system, verify it, be happy. The new firmware will be present next time you boot. * Crossflashing and hotflashing is possible as long as the flash chips are electrically and logically compatible (same protocol). Great for recovery. * Scriptability. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. * Speed. flashrom is much faster than vendor flash tools. * Supports Linux, FreeBSD, DragonFly BSD, Nexenta, Solaris, Mac OS X. Please refer to the README for build instructions. Thanks go to everyone who contributed to flashrom over the years. Please note that rewriting your flash chip can be dangerous and flashrom developers make no guarantees whatsoever. That said, many users have successfully replaced proprietary tools such as awdflash, amiflash and afudos with flashrom. If you have a laptop, we advise against using flashrom for now. Many laptops share their flash chip between the main CPU and an undocumented embedded controller which may crash the machine during flashing. This will be addressed once we manage to get docs for those embedded controllers. flashrom has its own home page at http://www.flashrom.org/ You can see a list of downloads at http://www.flashrom.org/Downloads New major user-visible features include: * 3Com NICs flashing * Silicon Image SATA controller flashing * ITE IT87* SuperI/O SPI flashing * FT2232H/FT4232H based SPI external programmer support * Universal external programmer protocol * AVR based external programmer support attached via serial line * Dummy flasher driver to trace execution * Automatic write/erase verification * Dozens of added flash chips * Support for new chipsets * Support for new boards * Fast bus type dependent probing * No root privileges needed for most external flashers Infrastructural improvements and fixes: * External flasher infrastructure * Improved SPI abstraction * SPI multicommand infrastructure * Partial read support infrastructure * Accurate timing information for probing * Tarball export target * User interface cleanup * Block protection printing for more chips * Probing accuracy improvements for old SPI chips on ICH * MMIO abstraction layer * Chip access abstraction layer * More intelligent error handling for ICH/VIA SPI * Fix corner case SB600 SPI hangs on non-SPI boards * Downgrade to byte program for certain chip families because they don't support page program * Detection of no-ID responses from chips * Elan SC520 runtime detection * 100x speedup for writes to some SPI chips * Improved error messages * Correctness fixes * Various workarounds for broken hardware * Code cleanups

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Error reading Winbond W25x16 on Intel DX48BT2
by Finnbarr Murphy 03 Feb '10

03 Feb '10

Greetings, Here is a failure report against an Intel DX48BT2 motherboard which uses a ICH9R and a Winbond W25x16 containing the BIOS. Command I executed was: ./flashrom -c W25x16 -rV out.bin flashrom v0.9.1-r889 No coreboot table found. DMI string 0: " " DMI string 1: " " DMI string 2: " " DMI string 3: "Intel Corporation" DMI string 4: "DX48BT2" DMI string 5: "AAE26191-205" Found chipset "Intel ICH9R", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa tried to set 0xdc to 0xb on ICH9R failed (WARNING ONLY) Root Complex Register Block address = 0xfed1c000 GCS = 0x171464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00001a1b (FRAP) BMWAG 0, BMRAG 0, BRWA 26, BRRA 27 0x54: 0x00000000 (FREG0) 0x58: 0x01ff003a (FREG1) 0x5C: 0x00390003 (FREG2) 0x60: 0x00020001 (FREG3) 0x64: 0x00000fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00420004 (SSFS, SSFC) 0x94: 0x0006 (PREOP) 0x96: 0x00f0 (OPTYPE) 0x98: 0x2002009f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) WARNING: SPI Configuration Lockdown activated. Generating OPCODES... done SPI Read Configuration: prefetching enabled, caching enabled, FAILED! This chipset supports the following protocols: FWH,SPI. Calibrating delay loop... 805M loops per second, 100 myus = 199 us. OK. Probing for Winbond W25x16, 2048 KB: RDID returned 0xef 0x30 0x15. probe_spi_rdid_generic: id1 0xef, id2 0x3015 Invalid OPCODE 0x05 Chip status register is 0a Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... Invalid OPCODE 0x03 done. Any idea what is going on? According to the W25x16 documentation opcodes 0x03 and 0x05 are supported. OS is Fedora 12. - Finnbarr P. Murphy

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SST SST49LF080A status report - TEST_OK_PR
by Peter Lemenkov 03 Feb '10

03 Feb '10

Hello All! Here are various logs for this chip. Flashrom successfully detects chipset and flash-chip and reads bios image, which was later processed by bios_extract. Unfortunately, I don't know too much about this board, except what can be read from dmidecode, because I've got only ssh access on it. -- With best regards, Peter Lemenkov. Sent from Moscow, Mow, Russia

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Write the second flash device
by Piotr Piwko 03 Feb '10

03 Feb '10

Hello, Does flashrom support writing the second flash devices connected to LPC bus? In my system I have one built-in flash device and the second one which is connected to the same LPC bus. I can also change device ID[3:0] pins, so I'm able to choose from which flash the system should be run. In this case I would like to write the flash device which is not bootable, but unfortunately the flashrom application detects only the boot device (under 0xFFF0 0000) - no matter from which flash device system is run. Is there any possibility to choose FWH device for flashrom? Thank you in advance for engagement, -- Piotr Piwko http://www.embedded-engineering.pl/

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[PATCH] Handle denied access to cbtable gracefuly
by Carl-Daniel Hailfinger 02 Feb '10

02 Feb '10

Stefan: Could you please test this one on Mac OS X? In theory it should even allow us to kill the start=0x400 special case for Mac OS X. Create a physical memory mapping function which requests cached readonly memory. This should take care of picky Linux kernels which do not allow uncached mappings to cached areas. Handle mapping failure gracefully (no forced exit()) if the caller specifies it. Such cached areas which can handle mapping failure are DMI tables and coreboot tables. On retry and repeated failure we just ignore those tables. That is not perfect, but a lot better than aborting flashrom due to an error in nonessential functionality. This should fix flashrom on a sizable number of machines where it currently aborts early. Yes, I could have exploited a Linux kernel bug to "solve" this, but relying on such bugs is not exactly the best idea. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-physmap_graceful_error_cbtable/flash.h =================================================================== --- flashrom-physmap_graceful_error_cbtable/flash.h (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/flash.h (Arbeitskopie) @@ -343,6 +343,7 @@ /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); Index: flashrom-physmap_graceful_error_cbtable/physmap.c =================================================================== --- flashrom-physmap_graceful_error_cbtable/physmap.c (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/physmap.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +37,10 @@ return map_physical(phys_addr, len); } +/* The OS X driver does not differentiate between mapping types. */ +#define sys_physmap_rw_uncached sys_physmap +#define sys_physmap_ro_cached sys_physmap + void physunmap(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); @@ -51,8 +56,10 @@ #endif static int fd_mem = -1; +static int fd_mem_cached = -1; -void *sys_physmap(unsigned long phys_addr, size_t len) +/* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ +void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -69,6 +76,26 @@ return MAP_FAILED == virt_addr ? NULL : virt_addr; } +/* For reading DMI/coreboot/whatever tables. We should never write, and we + * do not care about caching. + */ +void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +{ + void *virt_addr; + + if (-1 == fd_mem_cached) { + /* Open the memory device CACHED. */ + if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { + perror("Critical error: open(" MEM_DEV ")"); + exit(2); + } + } + + virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, + fd_mem_cached, (off_t)phys_addr); + return MAP_FAILED == virt_addr ? NULL : virt_addr; +} + void physunmap(void *virt_addr, size_t len) { if (len == 0) { @@ -80,7 +107,12 @@ } #endif -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +#define PHYSMAP_NOFAIL 0 +#define PHYSMAP_MAYFAIL 1 +#define PHYSMAP_RW 0 +#define PHYSMAP_RO 1 + +void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; @@ -100,7 +132,11 @@ descr, (unsigned long)len, phys_addr); } - virt_addr = sys_physmap(phys_addr, len); + if (readonly) { + virt_addr = sys_physmap_ro_cached(phys_addr, len); + } else { + virt_addr = sys_physmap_rw_uncached(phys_addr, len); + } if (NULL == virt_addr) { if (NULL == descr) @@ -114,12 +150,23 @@ fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } - exit(3); + if (!mayfail) + exit(3); } return virt_addr; } +void *physmap(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); +} + +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); +} + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, Index: flashrom-physmap_graceful_error_cbtable/cbtable.c =================================================================== --- flashrom-physmap_graceful_error_cbtable/cbtable.c (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/cbtable.c (Arbeitskopie) @@ -6,6 +6,7 @@ * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2006-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -194,24 +195,36 @@ #define BYTES_TO_MAP (1024*1024) int coreboot_init(void) { - uint8_t *table_area; + uint8_t *table_area = NULL; unsigned long addr, start; - struct lb_header *lb_table; + struct lb_header *lb_table = NULL; struct lb_record *rec, *last; #ifdef __DARWIN__ /* This is a hack. DirectIO fails to map physical address 0x00000000. * Why? + * FIXME: This hack should be unnecessary with the low megabyte retries. */ start = 0x400; #else start = 0x0; #endif - table_area = physmap("low megabyte", start, BYTES_TO_MAP); + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + while (!table_area) { + msg_pinfo("Trying a smaller mapping.\n"); + start += 0x400; + /* Outside lower 1 MB? Abort. */ + if (start > 0x100000) { + msg_perr("Failed getting access to low megabyte. " + "Ignoring any coreboot tables.\n"); + return -1; + } + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) - lb_table = find_lb_table(table_area, 0xf0000, BYTES_TO_MAP); + lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); @@ -219,7 +232,12 @@ start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); - table_area = physmap("high tables", start, BYTES_TO_MAP); + table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); + if (!table_area) { + msg_perr("Failed getting access to coreboot " + "high tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } -- Developer quote of the year: "We are juggling too many chainsaws and flaming arrows and tigers."

3 6

[commit] r889 - trunk
by repository service 02 Feb '10

02 Feb '10

Author: hailfinger Date: Tue Feb 2 12:09:03 2010 New Revision: 889 URL: http://flashrom.org/trac/coreboot/changeset/889 Log: Create a physical memory mapping function which requests cached readonly memory. This should take care of picky Linux kernels which do not allow uncached mappings to cached areas. Handle mapping failure gracefully (no forced exit()) if the caller specifies it. Such cached areas which can handle mapping failure are DMI tables and coreboot tables. On failure we just ignore those tables. That is not perfect, but a lot better than aborting flashrom due to an error in nonessential functionality. This should fix flashrom on a sizable number of machines where it currently aborts early. Yes, I could have exploited a Linux kernel bug to "solve" this, but relying on such bugs is not exactly the best idea. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Vincent Pelletier <plr.vincent(a)gmail.com> Modified: trunk/cbtable.c trunk/flash.h trunk/physmap.c Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Mon Feb 1 06:49:46 2010 (r888) +++ trunk/cbtable.c Tue Feb 2 12:09:03 2010 (r889) @@ -6,6 +6,7 @@ * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2006-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -207,11 +208,15 @@ #else start = 0x0; #endif - table_area = physmap("low megabyte", start, BYTES_TO_MAP); + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + if (!table_area) { + msg_perr("Failed getting access to coreboot low tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) - lb_table = find_lb_table(table_area, 0xf0000, BYTES_TO_MAP); + lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); @@ -219,7 +224,12 @@ start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); - table_area = physmap("high tables", start, BYTES_TO_MAP); + table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); + if (!table_area) { + msg_perr("Failed getting access to coreboot " + "high tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Mon Feb 1 06:49:46 2010 (r888) +++ trunk/flash.h Tue Feb 2 12:09:03 2010 (r889) @@ -343,6 +343,7 @@ /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Mon Feb 1 06:49:46 2010 (r888) +++ trunk/physmap.c Tue Feb 2 12:09:03 2010 (r889) @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +37,10 @@ return map_physical(phys_addr, len); } +/* The OS X driver does not differentiate between mapping types. */ +#define sys_physmap_rw_uncached sys_physmap +#define sys_physmap_ro_cached sys_physmap + void physunmap(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); @@ -51,8 +56,10 @@ #endif static int fd_mem = -1; +static int fd_mem_cached = -1; -void *sys_physmap(unsigned long phys_addr, size_t len) +/* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ +void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -69,6 +76,26 @@ return MAP_FAILED == virt_addr ? NULL : virt_addr; } +/* For reading DMI/coreboot/whatever tables. We should never write, and we + * do not care about caching. + */ +void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +{ + void *virt_addr; + + if (-1 == fd_mem_cached) { + /* Open the memory device CACHED. */ + if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { + perror("Critical error: open(" MEM_DEV ")"); + exit(2); + } + } + + virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, + fd_mem_cached, (off_t)phys_addr); + return MAP_FAILED == virt_addr ? NULL : virt_addr; +} + void physunmap(void *virt_addr, size_t len) { if (len == 0) { @@ -80,7 +107,12 @@ } #endif -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +#define PHYSMAP_NOFAIL 0 +#define PHYSMAP_MAYFAIL 1 +#define PHYSMAP_RW 0 +#define PHYSMAP_RO 1 + +void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; @@ -100,7 +132,11 @@ descr, (unsigned long)len, phys_addr); } - virt_addr = sys_physmap(phys_addr, len); + if (readonly) { + virt_addr = sys_physmap_ro_cached(phys_addr, len); + } else { + virt_addr = sys_physmap_rw_uncached(phys_addr, len); + } if (NULL == virt_addr) { if (NULL == descr) @@ -114,12 +150,23 @@ fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } - exit(3); + if (!mayfail) + exit(3); } return virt_addr; } +void *physmap(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); +} + +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); +} + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,

1 0

report for chip W49F002U (flashrom -wV)
by Ram Cohen 01 Feb '10

01 Feb '10

Attached: report Ram Cohen

1 0

[PATCH] Adds support for ST M29W512B. Tested and works for me.
by Jeff Kent 01 Feb '10

01 Feb '10

Adds support for ST M29W512B. Tested and works for me. Signed-off-by: Jeffrey A. Kent <jakent(a)gmail.com> --- Index: flashchips.c =================================================================== --- flashchips.c (revision 887) +++ flashchips.c (working copy) @@ -5050,6 +5050,30 @@ .read = read_memmapped, }, + { + .vendor = "ST", + .name = "M29W512B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = ST_ID, + .model_id = ST_M29W512B, + .total_size = 64, + .page_size = 64 * 1024, + .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + { .vendor = "ST", .name = "M50FLW040A", Index: flashchips.h =================================================================== --- flashchips.h (revision 887) +++ flashchips.h (working copy) @@ -473,6 +473,7 @@ #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 +#define ST_M29W512B 0x27 #define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */ #define S29C51001T 0x01

2 1

[commit] r888 - trunk
by repository service 01 Feb '10

01 Feb '10

Author: snelson Date: Mon Feb 1 06:49:46 2010 New Revision: 888 URL: http://flashrom.org/trac/coreboot/changeset/888 Log: Adds support for ST M29W512B. Tested and works for me. Signed-off-by: Jeffrey A. Kent <jakent(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jan 31 21:13:06 2010 (r887) +++ trunk/flashchips.c Mon Feb 1 06:49:46 2010 (r888) @@ -5050,6 +5050,30 @@ .read = read_memmapped, }, + { + .vendor = "ST", + .name = "M29W512B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = ST_ID, + .model_id = ST_M29W512B, + .total_size = 64, + .page_size = 64 * 1024, + .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + { .vendor = "ST", .name = "M50FLW040A", Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jan 31 21:13:06 2010 (r887) +++ trunk/flashchips.h Mon Feb 1 06:49:46 2010 (r888) @@ -473,6 +473,7 @@ #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 +#define ST_M29W512B 0x27 #define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */ #define S29C51001T 0x01

1 0

[PATCH] Fix Winbond W25X{10, 20, 40, 80} incorrect erase blocks
by Sean Nelson 01 Feb '10

01 Feb '10

Fix erase blocks for Winbond W25X* SPI chips.

1 0

Parallel chips and addressability.
by Luc Verhaegen 01 Feb '10

01 Feb '10

Uwe just added another chip to the board enable to track what the board can address when writing. Addressing issues only happen when using parallel flash, when not all the lines are wired up. Now, the biggest use case of flashrom is people updating the factory inserted flashchip to a new bios version. Only the corebooters would stick a bigger parallel chip in their motherboards and try to flash that. The number of reports of board addressing issues is going to be insanely low, compared to the high number of possibly "faulty" boards out there. My point in this email is: Tracking chipset addressing issues is fine, and necessary. But tracking board addressing issues is a fight against windmills, only a few people will run into this. We are better off trying to detect wrap around, before anything is actually harmed. This is not foolproof, as we might end up in a sitution where things did go wrong, and we only afterwards were able to tell that it was address wrap around. In this case, we should be as graceful as possible. Here is some logic for such detection: - probing works, so we know how big the flash is and what type it is. It's parallel, and the size is not bigger than the chipset addressing size. - read in the flash. * if all 0xFF: - it's either been erased, and we can just write it destructively. - or the bottom half is erased, and the top half isn't. We can write to it anyway, as we will only write this part. Erase is the only bit we should be scared off. (1) * else: - compare top and bottom half (even when the chip wraps around 4x, this is good enough). * if mismatched: * No wrapping! and we are free to write. * else - check if the image present or the image that is supposed to get written is coreboot. * coreboot: Complain loudly and continue anyway. Catting the image twice to match the size is not that nice. But the corebooter should not be protected like average joe user. * else: Complain loudly and bail out. Tell the user to use a --force or somesuch option to write this thing. If the user still proceeds, it's his own fault. Now, from this logic we might proceed to writing, which is always preceded by an erase. (1) is the scary bit here. We do not want to erase the whole chip when we can only address half. But, since the visible half is all 0xFF, we do not need to erase at all. Since we do not erase this chip at all, we can only end up overwriting the empty, visible part of the chip anyway. If we do an erase on a wrapped board, then we might be able to do a blockwise erase, and see the first block in both halves change. And as such detect wrap around too. So when subsequently writing a wrapped around chip, we will see the following: * If the image is a catted coreboot, then verify will work (we're wrapping anyway). Upon reboot, it will Just Work. * If not, verify will fail... And... We can see the wrapping too, and tell the user about it. We can then provide information on bailout on how to execute a blockwise restore (with blockwise erase -- do we have this for all parallel chips?) of the original image. Luc Verhaegen.

1 0

Acer Aspire Revo R3600
by Andrew Morgan 31 Jan '10

31 Jan '10

Here's the output of various tools for the Acer Aspire Revo R3600. It is a 'nettop', a rather compact 'desktop' which you can hide behind the monitor. It has a socketed W25X80AVAIZ (8Mbit SPI) flash chip, datasheet: http://www.winbond.com.tw/NR/rdonlyres/93A5FE5A-EEF2-417B-87A8-CB8144F6120D… The board says: Acer MCP7AS01 REV : 1.0 Link to BIOS: http://global-download.acer.com/GDFiles/BIOS/BIOS/BIOS_Acer_R01.A2L_A_AR360… -- Andrew. flashrom v0.9.1-r886 No coreboot table found. DMI string 0: "Acer" DMI string 1: "Aspire R3600" DMI string 2: " " DMI string 3: "Acer" DMI string 4: "FMCP7A-ION" DMI string 5: " " This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... 695M loops per second, 100 myus = 175 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x02 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x02 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x7f, id2 0xfc Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x05, id2 0xe0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xa8, id2 0x24, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x7f, id2 0xfc Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x02 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x10, id2 0x02 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x7f, id2 0xfc Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x10, id2 0x02, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x7f25, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. 00:00.0 Host bridge [0600]: nVidia Corporation MCP79 Host Bridge [10de:0a82] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 82 0a 06 00 a0 00 b1 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.1 RAM memory [0500]: nVidia Corporation MCP79 Memory Controller [10de:0a88] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: de 10 88 0a 04 00 a0 00 b1 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 ISA bridge [0601]: nVidia Corporation MCP79 LPC Bridge [10de:0aad] (rev b2) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: I/O ports at 4f00 [size=256] 00: de 10 ad 0a 0f 00 a0 00 b2 00 01 06 00 00 80 00 10: 01 4f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 00:03.1 RAM memory [0500]: nVidia Corporation MCP79 Memory Controller [10de:0aa4] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 a4 0a 00 04 a0 00 b1 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.2 SMBus [0c05]: nVidia Corporation MCP79 SMBus [10de:0aa2] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at 4900 [size=64] Region 4: I/O ports at 4d00 [size=64] Region 5: I/O ports at 4e00 [size=64] Capabilities: <access denied> Kernel driver in use: nForce2_smbus Kernel modules: i2c-nforce2 00: de 10 a2 0a 01 00 b0 00 b1 00 05 0c 00 00 80 00 10: 01 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4d 00 00 01 4e 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 00 00 00:03.3 RAM memory [0500]: nVidia Corporation MCP79 Memory Controller [10de:0a89] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 89 0a 00 00 20 00 b1 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.5 Co-processor [0b40]: nVidia Corporation MCP79 Co-processor [10de:0aa3] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 11 Region 0: Memory at fae80000 (32-bit, non-prefetchable) [size=512K] 00: de 10 a3 0a 06 00 a0 00 b1 00 40 0b 00 00 80 00 10: 00 00 e8 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 03 01 00:04.0 USB Controller [0c03]: nVidia Corporation MCP79 OHCI USB 1.1 Controller [10de:0aa5] (rev b1) (prog-if 10) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at fae7f000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: ohci_hcd 00: de 10 a5 0a 07 00 b0 00 b1 10 03 0c 00 00 80 00 10: 00 f0 e7 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 09 01 03 01 00:04.1 USB Controller [0c03]: nVidia Corporation MCP79 EHCI USB 2.0 Controller [10de:0aa6] (rev b1) (prog-if 20) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at fae7ec00 (32-bit, non-prefetchable) [size=256] Capabilities: <access denied> Kernel driver in use: ehci_hcd 00: de 10 a6 0a 06 00 b0 00 b1 20 03 0c 00 00 80 00 10: 00 ec e7 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 0f 02 03 01 00:08.0 Audio device [0403]: nVidia Corporation MCP79 High Definition Audio [10de:0ac0] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin A routed to IRQ 21 Region 0: Memory at fae78000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: de 10 c0 0a 06 00 b0 00 b1 00 03 04 00 00 00 00 10: 00 80 e7 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 02 05 00:09.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Bridge [10de:0aab] (rev b1) (prog-if 01) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> 00: de 10 ab 0a 04 00 b0 00 b1 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 02 02 00:0a.0 Ethernet controller [0200]: nVidia Corporation MCP79 Ethernet [10de:0ab0] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at fae7d000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at d080 [size=8] Region 2: Memory at fae7e800 (32-bit, non-prefetchable) [size=256] Region 3: Memory at fae7e400 (32-bit, non-prefetchable) [size=16] Capabilities: <access denied> Kernel driver in use: forcedeth Kernel modules: forcedeth 00: de 10 b0 0a 07 00 b0 00 b1 00 00 02 00 00 00 00 10: 00 d0 e7 fa 81 d0 00 00 00 e8 e7 fa 00 e4 e7 fa 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14 00:0b.0 SATA controller [0106]: nVidia Corporation MCP79 AHCI Controller [10de:0ab9] (rev b1) (prog-if 01) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 29 Region 0: I/O ports at d000 [size=8] Region 1: I/O ports at cc00 [size=4] Region 2: I/O ports at c880 [size=8] Region 3: I/O ports at c800 [size=4] Region 4: I/O ports at c480 [size=16] Region 5: Memory at fae76000 (32-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: ahci 00: de 10 b9 0a 07 04 b0 00 b1 01 06 01 00 00 00 00 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 20: 81 c4 00 00 00 60 e7 fa 00 00 00 00 25 10 22 02 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01 00:0c.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0ac4] (rev b1) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 c4 0a 04 04 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 02 00 00:10.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0aa0] (rev b1) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: faf00000-fbffffff Prefetchable memory behind bridge: 00000000e0000000-00000000f9ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel modules: shpchp 00: de 10 a0 0a 07 00 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 e1 e1 00 00 20: f0 fa f0 fb 01 e0 f1 f9 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 1a 00 00:15.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0ac6] (rev b1) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 c6 0a 04 04 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 02 00 00:16.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0ac7] (rev b1) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: feb00000-febfffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 c7 0a 06 04 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 20 20: b0 fe b0 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 01 02 00 00:17.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0ac7] (rev b1) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 c7 0a 04 04 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0f 01 02 00 00:18.0 PCI bridge [0604]: nVidia Corporation MCP79 PCI Express Bridge [10de:0ac7] (rev b1) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: <access denied> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 c7 0a 04 04 10 00 b1 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0e 01 02 00 03:00.0 VGA compatible controller [0300]: nVidia Corporation ION VGA [10de:087d] (rev b1) Subsystem: Acer Incorporated [ALI] Device [1025:0222] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 22 Region 0: Memory at fb000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at e0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at f8000000 (64-bit, prefetchable) [size=32M] Region 5: I/O ports at ec00 [size=128] [virtual] Expansion ROM at fafe0000 [disabled] [size=128K] Capabilities: <access denied> Kernel driver in use: nvidia Kernel modules: nvidia, nvidiafb 00: de 10 7d 08 07 00 10 00 b1 00 00 03 00 00 00 00 10: 00 00 00 fb 0c 00 00 e0 00 00 00 00 0c 00 00 f8 20: 00 00 00 00 01 ec 00 00 00 00 00 00 25 10 22 02 30: 00 00 00 00 60 00 00 00 00 00 00 00 07 01 00 00 05:00.0 Ethernet controller [0200]: Atheros Communications Inc. AR5001 Wireless Network Adapter [168c:001c] (rev 01) Subsystem: Foxconn International, Inc. Device [105b:e008] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at febf0000 (64-bit, non-prefetchable) [size=64K] Capabilities: <access denied> Kernel driver in use: ath5k Kernel modules: ath5k 00: 8c 16 1c 00 07 00 10 00 01 00 00 02 10 00 00 00 10: 04 00 bf fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 01 50 00 00 5b 10 08 e0 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 01 00 00 superiotool r5050 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. No Super I/O found

1 1

How hard to get this going?
by Robert Moonen 31 Jan '10

31 Jan '10

Hi, I am Robert(linux4all) Moonen and have supplied the attached file for a motherboard I would like to convert to coreboot. regards Robert

1 0

Re: [flashrom] ASUS M2N32 SLI Deluxe
by Vincent Pelletier 30 Jan '10

30 Jan '10

Le samedi 30 janvier 2010 17:34:59, vous avez écrit : > Attachments generated with: > # flashrom -V > flashrom.out 2>&1 As advised on IRC, rebuilt flashrom with start = 0x400, without success. Then, with start = 0x1000 I get attached file. -- Vincent Pelletier

1 0

ASUS M2N32 SLI Deluxe
by Vincent Pelletier 30 Jan '10

30 Jan '10

Attachments generated with: # flashrom -V > flashrom.out 2>&1 # lspci -nnvvvxxx > lspci.out 2>&1 # superiotool -deV > superiotool.out 2>&1 Also, if it helps, I attached dmidecode output: # dmidecode > dmidecode.out Link for bios download: http://support.asus.com/download/download.aspx?model=M2N32-SLI Deluxe -- Vincent Pelletier

1 0

[RFC] Firmware Hub chipdriver Unification
by Sean Nelson 30 Jan '10

30 Jan '10

This Patch provides a unified chip driver for Firmware Hub (FWH). It is heavily based on 80802ab.c and combines all related code from the following: sharplhf00l04.c sst28sf040.c sst49lfxxxc.c stm50flw0x0x.c Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> --- This is the first of 3 patches for FWH unification. Patch 1: fwhub driver Patch 2: connect/convert fwh drivers Patch 3: decouple old fwh drivers This is a Request of comments, the signoff is in case no one has any problems ;-)

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[Patch] Preliminary general superio support.
by Luc Verhaegen 30 Jan '10

30 Jan '10

Very untested and new. Sent in to show off what is being worked on and to get first impressions. Last i tried it worked fine on: * Winbond W83627EHF on MSI Fuzzy CN700 (nothing needed, just detection). * Winbond W83697HF on Asus 7V8X-MX SE (needing superio rom write enable) To be tested still: * it8705F rom write enable (have shuttle board here that i should still test on). * it87 spi code (have nonspi board here that i should still test on). Luc Verhaegen.

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flashrom v0.9.1-r884 reports:
by Iulius Cezar 29 Jan '10

29 Jan '10

Hi, I've tested latest build and I tough I should fill some missing info from 4 chips that I have: Erase for MX25L8005, MX25L1605 and SST25VF032B (reports attached) Also for Winbond W25x32, even Probe shows up as supported didn't worked for me(report attached) Test board is ASUS P6T6 WS Revolution. Thanks.

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[PATCH] Allow DMI supported board enables with subsystem ID zero.
by Michael Karcher 29 Jan '10

29 Jan '10

Hello Zach, please apply this patch additionally to the earlier patch I sent you. The board should get recognized then (You will see a line "Disabling write protection for Intel SE440BX-2" in the flashrom -V log), and please send again a flashrom -V output, so I can see whether identifying the chip is now possible. This is needed for the Intel SE440BX-2 as well as the Asus P5A. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 40db653..66afab4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1312,7 +1312,8 @@ static struct board_pciid_enable *board_match_pci_card_ids(void) struct board_pciid_enable *board = board_pciid_enables; for (; board->vendor_name; board++) { - if (!board->first_card_vendor || !board->first_card_device) + if (!board->first_card_vendor || + (!board->first_card_device && !board->dmi_pattern)) continue; if (!pci_card_find(board->first_vendor, board->first_device, -- 1.6.5

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[PATCH/RFC] finish jedec converstion
by Sean Nelson 29 Jan '10

29 Jan '10

Complete the addition of Feature Bits for all Jedec based chips. Add Zero entries for FWH, SPI and "Odd Jedec" (FEATURE_ADDR_555) chips. Add FEATURE_SHORT_RESET fix feature_bits to 0 for SST49LF040B rewrite jedec functions to use getaddrmask convert write_49f002 to write_jedec_1 convert write_w39v040c to write_jedec_1 convert probe_w39v040c to probe_jedec convert write_49lf040 to write_jedec_1 convert write_pm29f002 to write_jedec convert write_29f040b to write_jedec_1 convert probe_29f040b to probe_jedec convert erase_chip_29f040b to erase_chip_block_jedec convert erase_sector_29f040b to erase_sector_jedec convert write_m29f002b to write_jedec convert write_m29f002t to write_jedec convert *_29f002 to *_jedec decouple unused files from Makefile: am29f040b.c en29f002a.c m29f002.c mx29f002.c pm29f002.c sst49lf040.c w39v040c.c w49f002u.c Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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