- flashrom - mail.coreboot.org

[commit] r911 - trunk
by repository service 24 Feb '10

24 Feb '10

Author: mkarcher Date: Wed Feb 24 01:04:40 2010 New Revision: 911 URL: http://flashrom.org/trac/coreboot/changeset/911 Log: Replace PCI_OK/PCI_NT by OK/NT We don't need to duplicate OK and NT as PCI_OK and PCI_NT if the symbols are already there (defined for the chipset enable table). Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/atahpt.c trunk/drkaiser.c trunk/flash.h trunk/gfxnvidia.c trunk/nic3com.c trunk/pcidev.c trunk/print_wiki.c trunk/satasii.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/atahpt.c Wed Feb 24 01:04:40 2010 (r911) @@ -31,9 +31,9 @@ #define PCI_VENDOR_ID_HPT 0x1103 struct pcidev_status ata_hpt[] = { - {0x1103, 0x0004, PCI_NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, - {0x1103, 0x0005, PCI_NT, "Highpoint", "HPT372A/372N"}, - {0x1103, 0x0006, PCI_NT, "Highpoint", "HPT302/302N"}, + {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, + {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, + {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, {}, }; Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/drkaiser.c Wed Feb 24 01:04:40 2010 (r911) @@ -29,7 +29,7 @@ #define PCI_MAGIC_DRKAISER_VALUE 0xa971 struct pcidev_status drkaiser_pcidev[] = { - {0x1803, 0x5057, PCI_OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, + {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Feb 24 01:00:21 2010 (r910) +++ trunk/flash.h Wed Feb 24 01:04:40 2010 (r911) @@ -311,8 +311,6 @@ #if NEED_PCI == 1 /* pcidev.c */ -#define PCI_OK 0 -#define PCI_NT 1 /* Not tested */ extern uint32_t io_base_addr; extern struct pci_access *pacc; Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/gfxnvidia.c Wed Feb 24 01:04:40 2010 (r911) @@ -28,29 +28,29 @@ uint8_t *nvidia_bar; struct pcidev_status gfx_nvidia[] = { - {0x10de, 0x0010, PCI_NT, "NVIDIA", "Mutara V08 [NV2]" }, - {0x10de, 0x0018, PCI_NT, "NVIDIA", "RIVA 128" }, - {0x10de, 0x0020, PCI_NT, "NVIDIA", "RIVA TNT" }, - {0x10de, 0x0028, PCI_NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, - {0x10de, 0x0029, PCI_NT, "NVIDIA", "RIVA TNT2 Ultra" }, - {0x10de, 0x002c, PCI_NT, "NVIDIA", "Vanta/Vanta LT" }, - {0x10de, 0x002d, PCI_OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, - {0x10de, 0x00a0, PCI_NT, "NVIDIA", "Aladdin TNT2" }, - {0x10de, 0x0100, PCI_NT, "NVIDIA", "GeForce 256" }, - {0x10de, 0x0101, PCI_NT, "NVIDIA", "GeForce DDR" }, - {0x10de, 0x0103, PCI_NT, "NVIDIA", "Quadro" }, - {0x10de, 0x0110, PCI_NT, "NVIDIA", "GeForce2 MX" }, - {0x10de, 0x0111, PCI_NT, "NVIDIA", "GeForce2 MX" }, - {0x10de, 0x0112, PCI_NT, "NVIDIA", "GeForce2 GO" }, - {0x10de, 0x0113, PCI_NT, "NVIDIA", "Quadro2 MXR" }, - {0x10de, 0x0150, PCI_NT, "NVIDIA", "GeForce2 GTS/Pro" }, - {0x10de, 0x0151, PCI_NT, "NVIDIA", "GeForce2 GTS" }, - {0x10de, 0x0152, PCI_NT, "NVIDIA", "GeForce2 Ultra" }, - {0x10de, 0x0153, PCI_NT, "NVIDIA", "Quadro2 Pro" }, - {0x10de, 0x0200, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, - {0x10de, 0x0201, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, - {0x10de, 0x0202, PCI_NT, "NVIDIA", "GeForce 3 nFX Ultra" }, - {0x10de, 0x0203, PCI_NT, "NVIDIA", "Quadro 3 DDC" }, + {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, + {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, + {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, + {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, + {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" }, + {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" }, + {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, + {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" }, + {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" }, + {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" }, + {0x10de, 0x0103, NT, "NVIDIA", "Quadro" }, + {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" }, + {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" }, + {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" }, + {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" }, + {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" }, + {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" }, + {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" }, + {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" }, {}, }; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/nic3com.c Wed Feb 24 01:04:40 2010 (r911) @@ -36,20 +36,20 @@ struct pcidev_status nics_3com[] = { /* 3C90xB */ - {0x10b7, 0x9055, PCI_OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, - {0x10b7, 0x9001, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, - {0x10b7, 0x9004, PCI_OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" }, - {0x10b7, 0x9005, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" }, - {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, - {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" }, - {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" }, - {0x10b7, 0x9058, PCI_OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, + {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, + {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, + {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" }, + {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" }, + {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, + {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" }, + {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" }, + {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, /* 3C905C */ - {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, + {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, /* 3C980C */ - {0x10b7, 0x9805, PCI_NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" }, + {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" }, {}, }; Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/pcidev.c Wed Feb 24 01:04:40 2010 (r911) @@ -49,7 +49,7 @@ dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); - if (devs[i].status == PCI_NT) { + if (devs[i].status == NT) { printf("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " @@ -117,6 +117,6 @@ printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? " (untested)" : ""); + (devs[i].status == NT) ? " (untested)" : ""); } } Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/print_wiki.c Wed Feb 24 01:04:40 2010 (r911) @@ -541,7 +541,7 @@ "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? (c) ? "?2" : "?" : "OK"); + (devs[i].status == NT) ? (c) ? "?2" : "?" : "OK"); } } Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Wed Feb 24 01:00:21 2010 (r910) +++ trunk/satasii.c Wed Feb 24 01:04:40 2010 (r911) @@ -30,12 +30,12 @@ uint16_t id; struct pcidev_status satas_sii[] = { - {0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, - {0x1095, 0x3112, PCI_OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, - {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, - {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, - {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"}, - {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, + {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x3124, NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, + {0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"}, + {0x1095, 0x3512, NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"}, {}, };

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Re: [flashrom] [PATCH] Fix PIIX4 GPO set
by Luc Verhaegen 24 Feb '10

24 Feb '10

On Thu, Feb 11, 2010 at 07:48:15PM +0100, Michael Karcher wrote: > Intel datasheet says "byte accesses only". Looks like they mean it. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > board_enable.c | 11 +++++++---- > 1 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 5d89929..76b5a6a 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -578,6 +578,7 @@ static int board_artecgroup_dbe6x(const char *name) > */ > static int intel_piix4_gpo_set(unsigned int gpo, int raise) > { > + unsigned int gpo_byte, gpo_bit; > struct pci_dev *dev; > uint32_t tmp, base; > > @@ -632,12 +633,14 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise) > /* PM IO base */ > base = pci_read_long(dev, 0x40) & 0x0000FFC0; > > - tmp = INL(base + 0x34); /* GPO register */ > + gpo_byte = gpo >> 3; > + gpo_bit = gpo & 7; > + tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ > if (raise) > - tmp |= 0x01 << gpo; > + tmp |= 0x01 << gpo_bit; > else > - tmp |= ~(0x01 << gpo); > - OUTL(tmp, base + 0x34); > + tmp |= ~(0x01 << gpo_bit); > + OUTB(tmp, base + 0x34 + gpo_byte); > > return 0; > } > -- > 1.6.5 Acked-by: Luc Verhaegen <libv(a)skynet.be> Luc Verhaegen.

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[commit] r910 - trunk
by repository service 24 Feb '10

24 Feb '10

Author: mkarcher Date: Wed Feb 24 01:00:21 2010 New Revision: 910 URL: http://flashrom.org/trac/coreboot/changeset/910 Log: Fix PIIX4 GPO set Intel datasheet says "byte accesses only". Looks like they mean it. Also fix use of or instead of and for lowering GPOs. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Feb 22 16:52:57 2010 (r909) +++ trunk/board_enable.c Wed Feb 24 01:00:21 2010 (r910) @@ -578,6 +578,7 @@ */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) { + unsigned int gpo_byte, gpo_bit; struct pci_dev *dev; uint32_t tmp, base; @@ -632,12 +633,14 @@ /* PM IO base */ base = pci_read_long(dev, 0x40) & 0x0000FFC0; - tmp = INL(base + 0x34); /* GPO register */ + gpo_byte = gpo >> 3; + gpo_bit = gpo & 7; + tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ if (raise) - tmp |= 0x01 << gpo; + tmp |= 0x01 << gpo_bit; else - tmp |= ~(0x01 << gpo); - OUTL(tmp, base + 0x34); + tmp &= ~(0x01 << gpo_bit); + OUTB(tmp, base + 0x34 + gpo_byte); return 0; }

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[PATCH] splitting the code into subdirs
by Sean Nelson 23 Feb '10

23 Feb '10

Move files into a directory structure. File operations: mkdir {chips,programmer,cli,include} svn add {chips,programmer,cli,include} svn mv 82802ab.c chips/ svn mv flashchips.c chips/ svn mv jedec.c chips/ svn mv m29f400bt.c chips/ svn mv pm49fl00x.c chips/ svn mv sharplhf00l04.c chips/ svn mv spi.c chips/ svn mv sst28sf040.c chips/ svn mv sst49lfxxxc.c chips/ svn mv sst_fwhub.c chips/ svn mv stm50flw0x0x.c chips/ svn mv w29ee011.c chips/ svn mv w39v040c.c chips/ svn mv w39v080fa.c chips/ svn mv atahpt.c programmer/ svn mv bitbang_spi.c programmer/ svn mv board_enable.c programmer/ svn mv buspirate_spi.c programmer/ svn mv cbtable.c programmer/ svn mv chipset_enable.c programmer/ svn mv dediprog.c programmer/ svn mv dmi.c programmer/ svn mv drkaiser.c programmer/ svn mv dummyflasher.c programmer/ svn mv ft2232_spi.c programmer/ svn mv gfxnvidia.c programmer/ svn mv hwaccess.c programmer/ svn mv ichspi.c programmer/ svn mv internal.c programmer/ svn mv it87spi.c programmer/ svn mv nic3com.c programmer/ svn mv pcidev.c programmer/ svn mv physmap.c programmer/ svn mv programmer.c programmer/ svn mv satasii.c programmer/ svn mv sb600spi.c programmer/ svn mv serprog.c programmer/ svn mv udelay.c programmer/ svn mv wbsio_spi.c programmer/ svn mv cli_classic.c cli/ svn mv cli_output.c cli/ svn mv print.c cli/ svn mv print_wiki.c cli/ svn mv spi.h include/ svn mv chipdrivers.h include/ svn mv coreboot_tables.h include/ svn mv flash.h include/ svn mv flashchips.h include/ svn mv hwaccess.h include/ Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Michael Karcher 23 Feb '10

23 Feb '10

Am Montag, den 22.02.2010, 20:40 -0800 schrieb Spangler, Mike T: > Yes. I have both vendor BIOS and LinuxBios systems all running Linux. > If you send me your GPIO code I'll run it for you on both systems. > Don't think flashrom will work with vendor BIOS, but will try. OK, nice. Please try flashrom with the vendor BIOS. If it works, I will make the GPIO code to find whats different. If it doesn't work, I'm out of ideas, as I can be quite confident that the vendor tool does no special magic to enable flash writing, so flashrom should not need, too. Regards, Michael Karcher

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 23 Feb '10

23 Feb '10

Michael, could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time. Thanks a lot in advance! Regards, Carl-Daniel On 31.10.2009 15:30, Spangler, Mike T wrote: > Carl-Daniel - > > I can tell everyone's very busy. Just wanted to make sure that I haven't been forgotten. The system is still up and ready for testing. > > Mike > > > > -----Original Message----- > From: Spangler, Mike T > Sent: Friday, September 18, 2009 4:48 PM > To: 'Carl-Daniel Hailfinger' > Cc: flashrom(a)flashrom.org > Subject: RE: [flashrom] Trial of ARIMA:HDAMA Motherboard > > Carl-Daniel - > > Yes, we are stuck with factory bios for now and a lot of it's due to our reliance on HP hardware and their maintenance requirements. We do have legacy Linux Networx gear that I could run coreboot on with gPXE. I'll have to investigate that solution at a later date. > > Also, the good thing about my method of reading the bios and flashing what I read is that it moves my bios settings with the flash. If you pull the flash off of the factory distribution, you have to redo the bios settings for every node one at a time. > > Below is the lspci output per your request: > > > > > > 0000:00:18.0 Class 0600: 1022:1100 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Capabilities: [80] #08 [2101] > Capabilities: [a0] #08 [2101] > Capabilities: [c0] #08 [2101] > 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 > 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 > 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 > 60: 10 00 01 00 e4 00 00 00 00 c8 00 0f 74 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 > 90: 56 04 51 02 00 01 04 00 07 00 00 00 00 00 00 00 > a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 > b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 > c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:18.1 Class 0600: 1022:1101 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 > 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 > 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 > 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 > c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:18.2 Class 0600: 1022:1102 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 > 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: fd 2f 13 bf d0 00 00 00 d7 ff 5e 81 d0 87 9f 90 > c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 05 12 57 44 8d 44 e0 76 fe 8e 08 60 6d c8 54 69 > e0: 14 44 63 6b e5 42 f3 db 33 8e 62 1c f4 4c b9 3a > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:18.3 Class 0600: 1022:1103 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 > 50: 08 86 bb c0 60 00 00 00 16 16 16 00 40 d7 be 22 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 3c 00 00 80 db e5 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 > e0: 00 00 00 00 20 0c 57 00 1b 01 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:19.0 Class 0600: 1022:1100 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Capabilities: [80] #08 [2101] > Capabilities: [a0] #08 [2101] > Capabilities: [c0] #08 [2101] > 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 > 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 > 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 > 60: 11 00 01 00 e4 00 00 00 00 c8 00 0f 7c 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 > 90: 56 04 51 02 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 > b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 > c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 > d0: 0c 34 01 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:19.1 Class 0600: 1022:1101 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 > 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 > 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 > 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 > c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:19.2 Class 0600: 1022:1102 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 > 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 6f 68 15 bf d0 00 00 00 50 3e 50 02 c0 a1 42 d4 > c0: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 58 6f ff 13 b4 43 27 ba b5 7f 19 9f 74 7f eb bb > e0: f9 f6 cf bb 95 cd f3 bc 7d dc 8d af fd 99 ce a3 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:00:19.3 Class 0600: 1022:1103 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 > 50: 88 71 e6 db 21 00 00 00 16 16 16 00 c0 d3 be 22 > 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 36 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 > e0: 00 00 00 00 20 10 55 00 1b 01 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:01.0 Class 0604: 1022:7450 (rev 12) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 > Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 > I/O behind bridge: 00002000-00001fff > Memory behind bridge: fb000000-fb0fffff > Prefetchable memory behind bridge: 00000000fb100000-00000000fb000000 > BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- > Capabilities: [a0] Capabilities: [b8] #08 [8000] > Capabilities: [c0] #08 [0041] > 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 > 10: 00 00 00 00 00 00 00 00 01 02 02 40 21 11 20 22 > 20: 00 fb 00 fb 11 fb 01 fb 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 > 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 01 2c 00 00 > 50: 00 00 03 00 00 00 05 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 07 b8 03 00 08 01 03 00 0e 00 0e 00 02 00 02 00 > b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 > c0: 08 00 41 00 22 00 11 11 22 00 00 00 22 04 35 00 > d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 04 04 10 00 04 04 0d 00 04 04 16 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:01.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Region 0: Memory at fb100000 (64-bit, non-prefetchable) > 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 > 10: 04 00 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 00 00 00 00 03 00 00 00 04 00 10 fb 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:02.0 Class 0604: 1022:7450 (rev 12) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 > Bus: primary=01, secondary=03, subordinate=03, sec-latency=64 > I/O behind bridge: 00002000-00001fff > Memory behind bridge: fb100000-fb0fffff > Prefetchable memory behind bridge: 00000000fa000000-00000000faf00000 > BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- > Capabilities: [a0] Capabilities: [b8] #08 [8000] > 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 > 10: 00 00 00 00 00 00 00 00 01 03 03 40 21 11 20 a3 > 20: 10 fb 00 fb 01 fa f1 fa 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 > 40: 05 00 1f 00 00 00 00 00 00 00 00 00 01 2c 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 07 b8 c3 00 10 01 03 00 0e 00 0e 00 02 00 02 00 > b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:02.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Region 0: Memory at fb101000 (64-bit, non-prefetchable) > 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 > 10: 04 10 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 00 00 00 00 03 00 00 00 04 10 10 fb 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:03.0 Class 0604: 1022:7460 (rev 07) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 > Bus: primary=01, secondary=04, subordinate=04, sec-latency=64 > I/O behind bridge: 00001000-00001fff > Memory behind bridge: f8000000-f90fffff > Prefetchable memory behind bridge: fb100000-fb0fffff > Expansion ROM at 00001000 [disabled] [size=4K] > BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- > Capabilities: [c0] #08 [0083] > Capabilities: [f0] #08 [8000] > 00: 22 10 60 74 47 01 30 02 07 00 04 06 00 40 01 00 > 10: 00 00 00 00 00 00 00 00 01 04 04 40 10 10 00 22 > 20: 00 f8 00 f9 10 fb 00 fb 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0f 08 > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 08 f0 83 00 22 00 00 00 d0 00 00 00 22 00 01 00 > d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 08 00 0f 00 08 00 11 00 0f 00 17 00 00 00 00 00 > f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:04.0 Class 0601: 1022:7468 (rev 05) > Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 0 > 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 01 30 07 c0 01 00 00 02 9f fd 00 01 00 00 00 c0 > 50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:04.1 Class 0101: 1022:7469 (rev 03) (prog-if 8a [Master SecP PriP]) > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 > Region 4: I/O ports at 0f00 [size=16] > 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 40 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 > 40: 43 f0 0f 00 00 00 00 00 5e 5e 5e 20 2a 00 ff 20 > 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:04.2 Class 0c05: 1022:746a (rev 02) > Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Interrupt: pin D routed to IRQ 0 > Region 0: I/O ports at 2400 > 00: 22 10 6a 74 01 00 00 02 02 00 05 0c 00 40 00 00 > 10: 01 24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 > 40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:01:04.3 Class 0000: 1022:746b (rev 05) > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > 00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 40 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 00 d1 00 04 00 00 00 00 20 14 10 00 00 00 00 00 > 50: 00 80 00 00 0f 00 00 00 01 20 00 00 00 00 00 00 > 60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 54 ac 76 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:02:03.0 Class 0200: 14e4:16a6 (rev 02) > Subsystem: 14e4:000c > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 (16000ns min), cache line size 10 > Interrupt: pin A routed to IRQ 19 > Region 0: Memory at fb000000 (64-bit, non-prefetchable) [size=1026M] > Expansion ROM at 00010000 [disabled] > Capabilities: [40] PCI-X non-bridge device. > Command: DPERE- ERO- RBC=0 OST=0 > Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) > Status: D0 PME-Enable- DSel=0 DScale=1 PME- > Capabilities: [50] Vital Product Data > Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- > Address: fcfb626b00cc0528 Data: 0109 > 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 > 10: 04 00 00 fb 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 > 30: 00 00 20 40 40 00 00 00 00 00 00 00 00 01 40 00 > 40: 07 48 00 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 > 50: 03 58 00 00 0a 80 a0 22 05 00 86 00 28 05 cc 00 > 60: 6b 62 fb fc 09 01 00 00 98 02 02 10 00 00 3f 76 > 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 > 80: 00 00 00 00 9f 13 88 f6 34 00 13 04 82 10 08 00 > 90: 09 92 00 01 83 01 00 00 00 00 00 00 83 01 00 00 > a0: 00 00 00 00 bb 00 00 00 00 00 00 00 cd 01 00 00 > b0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 > c0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 > d0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 > e0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 > f0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 > > 0000:02:04.0 Class 0200: 14e4:16a6 (rev 02) > Subsystem: 14e4:000c > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Latency: 64 (16000ns min), cache line size 10 > Interrupt: pin A routed to IRQ 19 > Region 0: Memory at fb010000 (64-bit, non-prefetchable) [size=106M] > Expansion ROM at 00010000 [disabled] > Capabilities: [40] PCI-X non-bridge device. > Command: DPERE- ERO+ RBC=0 OST=0 > Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) > Status: D0 PME-Enable- DSel=0 DScale=1 PME- > Capabilities: [50] Vital Product Data > Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- > Address: fcfd56ebfbf37f4c Data: eff5 > 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 > 10: 04 00 01 fb 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 > 30: 00 00 ad 06 40 00 00 00 00 00 00 00 00 01 40 00 > 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 > 50: 03 58 b8 00 f7 e5 fe 79 05 00 86 00 4c 7f f3 fb > 60: eb 56 fd fc f5 ef 00 00 9a 02 02 10 00 00 3f 76 > 70: be 12 00 00 df 00 00 00 50 00 00 00 00 00 00 00 > 80: 03 58 b8 00 5f bf f5 eb 34 00 00 00 fe 10 08 00 > 90: 01 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:03:01.0 Class 0280: 14c1:8043 (rev 04) > Subsystem: 14c1:8043 > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- > Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ > Interrupt: pin A routed to IRQ 17 > Region 0: Memory at fa000000 (64-bit, prefetchable) > Capabilities: [44] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- > Address: 0000000000000000 Data: 0000 > Capabilities: [54] PCI-X non-bridge device. > Command: DPERE- ERO- RBC=0 OST=0 > Status: Bus=3 Dev=1 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=3, DMOST=0, DMCRS=2, RSCEM-00: c1 14 43 80 42 00 30 80 04 00 80 02 10 40 00 00 > 10: 0c 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 14 43 80 > 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00 > 40: 00 00 00 55 05 54 80 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 07 00 00 00 08 03 63 08 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 ac 00 60 dd 48 b1 80 > > 0000:04:00.0 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Interrupt: pin D routed to IRQ 0 > Region 0: Memory at f9000000 (32-bit, non-prefetchable) > 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 80 00 > 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:04:00.1 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- > Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Interrupt: pin D routed to IRQ 0 > Region 0: Memory at f9001000 (32-bit, non-prefetchable) > 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 00 00 > 10: 00 10 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:04:00.2 Class 0c03: 1022:7463 (rev 02) (prog-if 20) > Subsystem: 1022:7463 > Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- > Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Interrupt: pin D routed to IRQ 0 > Region 0: Memory at f9003000 (32-bit, non-prefetchable) > Region 1: Memory at f9004000 (32-bit, non-prefetchable) [size=32] > Capabilities: [80] #0a [4000] > Capabilities: [88] Power Management version 2 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+) > Status: D0 PME-Enable- DSel=0 DScale=0 PME- > 00: 22 10 63 74 02 00 10 02 02 20 03 0c 00 40 00 00 > 10: 00 30 00 f9 00 40 00 f9 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 63 74 > 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00 > 40: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 20 20 01 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 22 10 63 74 01 00 00 00 40 30 00 01 00 00 00 00 > 80: 0a 88 00 40 00 00 00 00 01 00 82 fe 00 00 00 00 > 90: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 0000:04:06.0 Class 0300: 1002:4752 (rev 27) > Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- > Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- > Interrupt: pin A routed to IRQ 0 > Region 0: Memory at f8000000 (32-bit, non-prefetchable) > Region 1: I/O ports at 1000 [size=256] > Region 2: Memory at f9002000 (32-bit, non-prefetchable) [size=4K] > Capabilities: [5c] Power Management version 2 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 PME-Enable- DSel=0 DScale=0 PME- > 00: 02 10 52 47 83 00 90 02 27 00 00 03 10 40 00 00 > 10: 00 00 00 f8 01 10 00 00 00 20 00 f9 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 5c 00 00 00 00 00 00 00 00 01 08 00 > 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > > > > > > > > > > > > > > -----Original Message----- > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: Friday, September 18, 2009 3:18 PM > To: Spangler, Mike T > Cc: flashrom(a)flashrom.org > Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard > > Hi Mike, > > > On 18.09.2009 18:55, Spangler, Mike T wrote: > >> I've corrected my email and am now sending to the group. >> >> > > Thanks. > > > >>> Of course I'd prefer it if you tried to flash coreboot (new name of >>> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >>> have the factory BIOS around somewhere. Is it the one at >>> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >>> >>> >> I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. >> >> > > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? > We coreboot/flashrom developers are always interested in helping people > update coreboot to the latest and greatest. So if you need PXE booting, > there's no need to move back to the factory BIOS, a simple coreboot > update should suffice. > > > >> So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. >> > > That's one option. The other option would be to extract the BIOS from > the .ROM file. That looks reasonably easy. No guarantees, though. > dd if=something.ROM of=bios.bin bs=1k count=512 > > > >> This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. >> >> > > flashrom strives to be the most reliable flashing tool out there. The > current version has builtin verification for every step it does. > > > >>> Hmm ok. I think we have enough docs to iterate through all possible >>> board enables. How many of these boards do you have (in case we trash >>> the ROM of one of them)? >>> >>> >> The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. >> >> > > Great. And with hotplugging/hotflashing it should be possible to reflash > a trashed chip in another board. > > Can you supply the output of "lspci -nnvvvxxx" as root? That will allow > me to dig further. I'd like to limit the search to a reasonable subset > of options. > > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ > > -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

3 5

[PATCH] Replace PCI_OK/PCI_NT by OK/NT
by Michael Karcher 23 Feb '10

23 Feb '10

We don't need to duplicate OK and NT as PCI_OK and PCI_NT if the symbols are already there (defined for the chipset enable table). Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- New revision rebased to current svn. Intent to commit quite soon. atahpt.c | 6 +++--- drkaiser.c | 2 +- flash.h | 2 -- gfxnvidia.c | 46 +++++++++++++++++++++++----------------------- nic3com.c | 20 ++++++++++---------- pcidev.c | 4 ++-- print_wiki.c | 2 +- satasii.c | 12 ++++++------ 8 files changed, 46 insertions(+), 48 deletions(-) diff --git atahpt.c atahpt.c index b878d02..c87bc36 100644 --- atahpt.c +++ atahpt.c @@ -31,9 +31,9 @@ #define PCI_VENDOR_ID_HPT 0x1103 struct pcidev_status ata_hpt[] = { - {0x1103, 0x0004, PCI_NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, - {0x1103, 0x0005, PCI_NT, "Highpoint", "HPT372A/372N"}, - {0x1103, 0x0006, PCI_NT, "Highpoint", "HPT302/302N"}, + {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, + {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, + {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, {}, }; diff --git drkaiser.c drkaiser.c index f13c13e..572fee3 100644 --- drkaiser.c +++ drkaiser.c @@ -29,7 +29,7 @@ #define PCI_MAGIC_DRKAISER_VALUE 0xa971 struct pcidev_status drkaiser_pcidev[] = { - {0x1803, 0x5057, PCI_OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, + {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; diff --git flash.h flash.h index c73dbb5..ff2004c 100644 --- flash.h +++ flash.h @@ -311,8 +311,6 @@ void internal_delay(int usecs); #if NEED_PCI == 1 /* pcidev.c */ -#define PCI_OK 0 -#define PCI_NT 1 /* Not tested */ extern uint32_t io_base_addr; extern struct pci_access *pacc; diff --git gfxnvidia.c gfxnvidia.c index cc66ace..ec41279 100644 --- gfxnvidia.c +++ gfxnvidia.c @@ -28,29 +28,29 @@ uint8_t *nvidia_bar; struct pcidev_status gfx_nvidia[] = { - {0x10de, 0x0010, PCI_NT, "NVIDIA", "Mutara V08 [NV2]" }, - {0x10de, 0x0018, PCI_NT, "NVIDIA", "RIVA 128" }, - {0x10de, 0x0020, PCI_NT, "NVIDIA", "RIVA TNT" }, - {0x10de, 0x0028, PCI_NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, - {0x10de, 0x0029, PCI_NT, "NVIDIA", "RIVA TNT2 Ultra" }, - {0x10de, 0x002c, PCI_NT, "NVIDIA", "Vanta/Vanta LT" }, - {0x10de, 0x002d, PCI_OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, - {0x10de, 0x00a0, PCI_NT, "NVIDIA", "Aladdin TNT2" }, - {0x10de, 0x0100, PCI_NT, "NVIDIA", "GeForce 256" }, - {0x10de, 0x0101, PCI_NT, "NVIDIA", "GeForce DDR" }, - {0x10de, 0x0103, PCI_NT, "NVIDIA", "Quadro" }, - {0x10de, 0x0110, PCI_NT, "NVIDIA", "GeForce2 MX" }, - {0x10de, 0x0111, PCI_NT, "NVIDIA", "GeForce2 MX" }, - {0x10de, 0x0112, PCI_NT, "NVIDIA", "GeForce2 GO" }, - {0x10de, 0x0113, PCI_NT, "NVIDIA", "Quadro2 MXR" }, - {0x10de, 0x0150, PCI_NT, "NVIDIA", "GeForce2 GTS/Pro" }, - {0x10de, 0x0151, PCI_NT, "NVIDIA", "GeForce2 GTS" }, - {0x10de, 0x0152, PCI_NT, "NVIDIA", "GeForce2 Ultra" }, - {0x10de, 0x0153, PCI_NT, "NVIDIA", "Quadro2 Pro" }, - {0x10de, 0x0200, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, - {0x10de, 0x0201, PCI_NT, "NVIDIA", "GeForce 3 nFX" }, - {0x10de, 0x0202, PCI_NT, "NVIDIA", "GeForce 3 nFX Ultra" }, - {0x10de, 0x0203, PCI_NT, "NVIDIA", "Quadro 3 DDC" }, + {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, + {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, + {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, + {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" }, + {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" }, + {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" }, + {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" }, + {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" }, + {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" }, + {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" }, + {0x10de, 0x0103, NT, "NVIDIA", "Quadro" }, + {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" }, + {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" }, + {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" }, + {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" }, + {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" }, + {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" }, + {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" }, + {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" }, + {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" }, + {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" }, {}, }; diff --git nic3com.c nic3com.c index a4878d2..d3dcce5 100644 --- nic3com.c +++ nic3com.c @@ -36,20 +36,20 @@ uint16_t id; struct pcidev_status nics_3com[] = { /* 3C90xB */ - {0x10b7, 0x9055, PCI_OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, - {0x10b7, 0x9001, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, - {0x10b7, 0x9004, PCI_OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" }, - {0x10b7, 0x9005, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" }, - {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, - {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" }, - {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" }, - {0x10b7, 0x9058, PCI_OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, + {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, + {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, + {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" }, + {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" }, + {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, + {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" }, + {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" }, + {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, /* 3C905C */ - {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, + {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, /* 3C980C */ - {0x10b7, 0x9805, PCI_NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" }, + {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" }, {}, }; diff --git pcidev.c pcidev.c index 6c92c0a..fcb04e6 100644 --- pcidev.c +++ pcidev.c @@ -49,7 +49,7 @@ uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); - if (devs[i].status == PCI_NT) { + if (devs[i].status == NT) { printf("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " @@ -117,6 +117,6 @@ void print_supported_pcidevs(struct pcidev_status *devs) printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? " (untested)" : ""); + (devs[i].status == NT) ? " (untested)" : ""); } } diff --git print_wiki.c print_wiki.c index bbbaf45..20e0850 100644 --- print_wiki.c +++ print_wiki.c @@ -541,7 +541,7 @@ void print_supported_pcidevs_wiki(struct pcidev_status *devs) "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, - (devs[i].status == PCI_NT) ? (c) ? "?2" : "?" : "OK"); + (devs[i].status == NT) ? (c) ? "?2" : "?" : "OK"); } } diff --git satasii.c satasii.c index 90995c9..90d38bd 100644 --- satasii.c +++ satasii.c @@ -30,12 +30,12 @@ uint8_t *sii_bar; uint16_t id; struct pcidev_status satas_sii[] = { - {0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, - {0x1095, 0x3112, PCI_OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, - {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, - {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, - {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"}, - {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, + {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x3124, NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, + {0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"}, + {0x1095, 0x3512, NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"}, {}, }; -- 1.6.5

1 0

[PATCH] Add Abit VT6X4 board enable
by Michael Karcher 22 Feb '10

22 Feb '10

This board has *no* usable IDs at all, neither DMI nor PCI subsystem IDs. You have to force it using "-m abit:vt6x4" Try 3: really correct polarity of the GPIO Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index ae46fb0..e49b1ea 100644 --- a/board_enable.c +++ b/board_enable.c @@ -973,6 +973,15 @@ static int via_apollo_gpo0_lower(const char *name) } /** + * Suited for Abit VT6X5: Pro133x + VT82C686A + */ +static int via_apollo_gpo4_lower(const char *name) +{ + return via_apollo_gpo_set(4, 0); +} + + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1216,6 +1225,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, intel_ich_gpio16_raise}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, w83627hf_gpio24_raise_2e}, -- 1.6.5

1 0

[PATCH] chipdrivers cleanup
by Sean Nelson 22 Feb '10

22 Feb '10

Remove remaining JEDEC chipdrivers, but move lock-related functions to chiplocks.c Fix whitespace for ST_M29W512B. SVN RM: (maybe not now; as a note) w39v040c.c - only function in use left is printlock_w39v040c w39v080fa.c - function names state *_winbond_fwhub but this is JEDEC; only functions used are lock related pm49fl00x.c - finally converted to JEDEC sst_fwhub.c - contrary to function/file names this is JEDEC Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 1

[PATCH] purge dead chipdrivers
by Sean Nelson 22 Feb '10

22 Feb '10

patch to remove all references to dead chipdrivers. We also need to 'svn rm' the following files: am29f040b.c en29f002a.c m29f002.c mx29f002.c pm29f002.c sst49lf040.c w49f002u.c Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 2

[commit] r909 - trunk
by repository service 22 Feb '10

22 Feb '10

Author: snelson Date: Mon Feb 22 16:52:57 2010 New Revision: 909 URL: http://flashrom.org/trac/coreboot/changeset/909 Log: patch to remove all references to dead chipdrivers. We also need to 'svn rm' the following files: am29f040b.c en29f002a.c m29f002.c mx29f002.c pm29f002.c sst49lf040.c w49f002u.c Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Deleted: trunk/am29f040b.c trunk/en29f002a.c trunk/m29f002.c trunk/mx29f002.c trunk/pm29f002.c trunk/sst49lf040.c trunk/w49f002u.c Modified: trunk/chipdrivers.h Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Feb 21 22:17:00 2010 (r908) +++ trunk/chipdrivers.h Mon Feb 22 16:52:57 2010 (r909) @@ -60,21 +60,6 @@ int erase_82802ab_block(struct flashchip *flash, unsigned int page, unsigned int pagesize); int write_82802ab(struct flashchip *flash, uint8_t *buf); -/* am29f040b.c */ -int probe_29f040b(struct flashchip *flash); -int erase_29f040b(struct flashchip *flash); -int erase_sector_29f040b(struct flashchip *flash, unsigned int blockaddr, unsigned int blocksize); -int erase_chip_29f040b(struct flashchip *flash, unsigned int blockaddr, unsigned int blocksize); -int write_29f040b(struct flashchip *flash, uint8_t *buf); - -/* pm29f002.c */ -int write_pm29f002(struct flashchip *flash, uint8_t *buf); - -/* en29f002a.c */ -int probe_en29f002a(struct flashchip *flash); -int erase_en29f002a(struct flashchip *flash); -int write_en29f002a(struct flashchip *flash, uint8_t *buf); - /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); @@ -90,11 +75,6 @@ int erase_chip_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec_common(struct flashchip *flash, uint8_t *src, chipaddr dst, unsigned int page_size, unsigned int mask); -/* m29f002.c */ -int erase_m29f002(struct flashchip *flash); -int write_m29f002t(struct flashchip *flash, uint8_t *buf); -int write_m29f002b(struct flashchip *flash, uint8_t *buf); - /* m29f400bt.c */ int probe_m29f400bt(struct flashchip *flash); int erase_m29f400bt(struct flashchip *flash); @@ -106,13 +86,6 @@ void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size); -/* mx29f002.c */ -int probe_29f002(struct flashchip *flash); -int erase_29f002(struct flashchip *flash); -int erase_chip_29f002(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -int erase_sector_29f002(struct flashchip *flash, unsigned int address, unsigned int blocklen); -int write_29f002(struct flashchip *flash, uint8_t *buf); - /* pm49fl00x.c */ int probe_49fl00x(struct flashchip *flash); int erase_49fl00x(struct flashchip *flash); @@ -131,14 +104,6 @@ int erase_sector_28sf040(struct flashchip *flash, unsigned int address, unsigned int sector_size); int write_28sf040(struct flashchip *flash, uint8_t *buf); -/* sst39sf020.c */ -int probe_39sf020(struct flashchip *flash); -int write_39sf020(struct flashchip *flash, uint8_t *buf); - -/* sst49lf040.c */ -int erase_49lf040(struct flashchip *flash); -int write_49lf040(struct flashchip *flash, uint8_t *buf); - /* sst49lfxxxc.c */ int probe_49lfxxxc(struct flashchip *flash); int erase_49lfxxxc(struct flashchip *flash); @@ -170,9 +135,6 @@ /* w29ee011.c */ int probe_w29ee011(struct flashchip *flash); -/* w49f002u.c */ -int write_49f002(struct flashchip *flash, uint8_t *buf); - /* stm50flw0x0x.c */ int probe_stm50flw0x0x(struct flashchip *flash); int erase_stm50flw0x0x(struct flashchip *flash);

1 0

Re: [flashrom] [PATCH 2/2] Add Abit VT6X4 board enable
by Michael Karcher 22 Feb '10

22 Feb '10

Am Montag, den 22.02.2010, 00:37 +0100 schrieb Michael Karcher: > This board has *no* usable IDs at all, neither DMI nor PCI > subsystem IDs. You have to force it using "-m abit:vt6x4" As seen on IRC, this patch doesn't help flashing on that board. The only difference I find between our code and the vendor board enable is that flashrom now uses a 32 bit access to the GPIO data register (the datasheet *seems* to indicate that this is fine). MMX, can you please try changing the INL/OUTL in via_apollo_gpo_set to INB/OUTB. This will be a quick hack I don't want that way in flashrom, but I would be very interested to hear whether it helps. Regards, Michael Karcher

1 1

[PATCH] Add Abit VT6X4 board enable
by Michael Karcher 22 Feb '10

22 Feb '10

This board has *no* usable IDs at all, neither DMI nor PCI subsystem IDs. You have to force it using "-m abit:vt6x4" Try 2: correct polarity of the GPIO Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index ae46fb0..8018c3a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -973,6 +973,15 @@ static int via_apollo_gpo0_lower(const char *name) } /** + * Suited for Abit VT6X5: Pro133x + VT82C686A + */ +static int via_apollo_gpo4_raise(const char *name) +{ + return via_apollo_gpo_set(4, 1); +} + + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1216,6 +1225,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, intel_ich_gpio16_raise}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, via_apollo_gpo4_raise}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, w83627hf_gpio24_raise_2e}, -- 1.6.5

1 0

[PATCH 2/2] Add Abit VT6X4 board enable
by Michael Karcher 22 Feb '10

22 Feb '10

This board has *no* usable IDs at all, neither DMI nor PCI subsystem IDs. You have to force it using "-m abit:vt6x4" Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index ae46fb0..8018c3a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -973,6 +973,15 @@ static int via_apollo_gpo0_lower(const char *name) } /** + * Suited for Abit VT6X5: Pro133x + VT82C686A + */ +static int via_apollo_gpo4_raise(const char *name) +{ + return via_apollo_gpo_set(4, 1); +} + + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1216,6 +1225,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, intel_ich_gpio16_raise}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, via_apollo_gpo4_raise}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, w83627hf_gpio24_raise_2e}, -- 1.6.5

1 0

[PATCH 1/2] Factor out Via Apollo GPO setting
by Michael Karcher 22 Feb '10

22 Feb '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 49 +++++++++++++++++++++++++++++++++++++------------ 1 files changed, 37 insertions(+), 12 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2de5fd7..ae46fb0 100644 --- a/board_enable.c +++ b/board_enable.c @@ -915,14 +915,11 @@ static int board_kontron_986lcd_m(const char *name) return ret; } -/** - * Suited for Soyo SY-7VCA: Pro133A + VT82C686. - */ -static int board_soyo_sy_7vca(const char *name) +static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; + struct pci_dev *dev; uint32_t base; - uint8_t tmp; + uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); @@ -931,23 +928,51 @@ static int board_soyo_sy_7vca(const char *name) return -1; } - /* GPO0 output from PM IO base + 0x4C */ + printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); - tmp &= ~0x03; + switch(gpio) + { + case 0: + tmp &= ~0x03; + break; + case 1: + tmp |= 0x04; + break; + case 2: + tmp |= 0x08; + break; + case 3: + tmp |= 0x10; + break; + } pci_write_byte(dev, 0x54, tmp); /* PM IO base */ base = pci_read_long(dev, 0x48) & 0x0000FF00; /* Drop GPO0 */ - tmp = INB(base + 0x4C); - tmp &= ~0x01; - OUTB(tmp, base + 0x4C); + tmp = INL(base + 0x4C); + if (raise) + tmp |= 1U << gpio; + else + tmp &= ~(1U << gpio); + OUTL(tmp, base + 0x4C); return 0; } /** + * Suited for Soyo SY-7VCA: Pro133A + VT82C686. + */ +static int via_apollo_gpo0_lower(const char *name) +{ + return via_apollo_gpo_set(0, 0); +} + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1239,7 +1264,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, board_soyo_sy_7vca}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, via_apollo_gpo0_lower}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, via_vt823x_gpio15_raise}, -- 1.6.5

1 0

HPT360/HPT370 ATA controller flash interface
by Michael Karcher 21 Feb '10

21 Feb '10

Hello flashrom developers, (obtained from reversing the vendor update tool) Supported IDs (names stolen from pci.ids, the double 372N is not my fault): 1103:0004 HPT366/368/370/370A/372/372N 1103:0005 HPT372A/372N 1103:0006 HPT302/302N Flash enable at 58L.24 (setpci syntax), set to enable flash writing Flash interface select at 70B, 1 = mmapped in ROM addr space, 0 = io mapped IO-mapped access: (BAR4)+0x90 -> DWORD Address (BAR4)+0x94 -> BYTE/WORD/DWORD data access. memmapped chip access was not shown in the tool, but the flash disable code disables the extension ROM BAR. So probably its just mmapped read/write in that area. Maximum Chip size supported by the vendor tool: 128K Regards, Michael Karcher

3 4

[commit] r908 - trunk
by repository service 21 Feb '10

21 Feb '10

Author: uwe Date: Sun Feb 21 22:17:00 2010 New Revision: 908 URL: http://flashrom.org/trac/coreboot/changeset/908 Log: Add initial (non-working) code for Highpoint ATA/RAID controllers. It's disabled by default. The current status is detailed at: http://www.flashrom.org/pipermail/flashrom/2010-January/001828.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/atahpt.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/print_wiki.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Feb 19 01:52:10 2010 (r907) +++ trunk/Makefile Sun Feb 21 22:17:00 2010 (r908) @@ -83,6 +83,10 @@ # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes +# Highpoint (HPT) ATA/RAID controller support. +# IMPORTANT: This code is not yet working! +CONFIG_ATAHPT ?= no + # Always enable FT2232 SPI dongles for now. CONFIG_FT2232SPI ?= yes @@ -138,6 +142,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_ATAHPT), yes) +FEATURE_CFLAGS += -D'ATAHPT_SUPPORT=1' +PROGRAMMER_OBJS += atahpt.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_FT2232SPI), yes) FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") # This is a totally ugly hack. Added: trunk/atahpt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/atahpt.c Sun Feb 21 22:17:00 2010 (r908) @@ -0,0 +1,85 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define BIOS_ROM_ADDR 0x90 +#define BIOS_ROM_DATA 0x94 + +#define REG_FLASH_ACCESS 0x58 + +#define PCI_VENDOR_ID_HPT 0x1103 + +struct pcidev_status ata_hpt[] = { + {0x1103, 0x0004, PCI_NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, + {0x1103, 0x0005, PCI_NT, "Highpoint", "HPT372A/372N"}, + {0x1103, 0x0006, PCI_NT, "Highpoint", "HPT302/302N"}, + + {}, +}; + +int atahpt_init(void) +{ + uint32_t reg32; + + get_io_perms(); + + io_base_addr = pcidev_init(PCI_VENDOR_ID_HPT, PCI_BASE_ADDRESS_4, + ata_hpt, programmer_param); + + /* Enable flash access. */ + reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); + reg32 |= (1 << 24); + pci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int atahpt_shutdown(void) +{ + uint32_t reg32; + + /* Disable flash access again. */ + reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); + reg32 &= ~(1 << 24); + pci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); + + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void atahpt_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + +uint8_t atahpt_chip_readb(const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flash.h Sun Feb 21 22:17:00 2010 (r908) @@ -55,6 +55,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, #endif +#if ATAHPT_SUPPORT == 1 + PROGRAMMER_ATAHPT, +#endif #if INTERNAL_SUPPORT == 1 PROGRAMMER_IT87SPI, #endif @@ -328,7 +331,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -466,6 +469,15 @@ extern struct pcidev_status satas_sii[]; #endif +/* atahpt.c */ +#if ATAHPT_SUPPORT == 1 +int atahpt_init(void); +int atahpt_shutdown(void); +void atahpt_chip_writeb(uint8_t val, chipaddr addr); +uint8_t atahpt_chip_readb(const chipaddr addr); +extern struct pcidev_status ata_hpt[]; +#endif + /* ft2232_spi.c */ #define FTDI_FT2232H 0x6010 #define FTDI_FT4232H 0x6011 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flashrom.8 Sun Feb 21 22:17:00 2010 (r908) @@ -146,6 +146,8 @@ .sp .BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controllers)" .sp +.BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" +.sp .BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI translation unit)" .sp .BR "* ft2232spi" " (for flash ROMs attached to a FT2232H/FT4232H based USB SPI programmer)" @@ -185,7 +187,8 @@ Currently the following programmers support this mechanism: .BR nic3com , .BR gfxnvidia , -.BR satasii . +.BR satasii , +.BR atahpt . .sp The it87spi programmer has an optional parameter which will set the I/O base port of the IT87* SPI controller interface to the port specified in the Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flashrom.c Sun Feb 21 22:17:00 2010 (r908) @@ -44,7 +44,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 +#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all external programmers except one. #endif enum programmer programmer = @@ -60,6 +60,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII #endif +#if ATAHPT_SUPPORT == 1 + PROGRAMMER_ATAHPT +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI #endif @@ -206,6 +209,25 @@ .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + +#if ATAHPT_SUPPORT == 1 + { + .name = "atahpt", + .init = atahpt_init, + .shutdown = atahpt_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Feb 19 01:52:10 2010 (r907) +++ trunk/print_wiki.c Sun Feb 21 22:17:00 2010 (r908) @@ -566,6 +566,9 @@ #if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii); #endif +#if ATAHPT_SUPPORT == 1 + print_supported_pcidevs_wiki(ata_hpt); +#endif printf("\n|}\n"); }

1 0

Recommendation for board to be used only with flashrom?
by Daniel Clark 20 Feb '10

20 Feb '10

I'm looking for a well-supported by flashrom, preferably very inexpensive board to use only as a PLCC programmer for other devices [1]. Anyone have a specific recommendation? [1] Talk:Openbiosprog - Currently Available Alternatives? http://www.randomprojects.org/wiki/Talk:Openbiosprog Thanks, -- Daniel JB Clark | Free Software Activist | http://pobox.com/~dclark

1 0

Re: [flashrom] [PATCH] Probe/Read tested for SST29EE020A
by Peter Lemenkov 19 Feb '10

19 Feb '10

Hello All! 2010/2/19 Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>: > http://www.flashrom.org/pipermail/flashrom/2010-February/002318.html > > Should we commit single patches for each positive test report we get, > or collect them? I believe, that committing each (un)successful report in a separated patch is a better idea, than combining them into one or more larger patches (that means some unavoidable delay). -- With best regards, Peter Lemenkov. Sent from Moscow, Mow, Russia

1 0

[PATCH] Probe/Read tested for SST29EE020A
by Michael Karcher 19 Feb '10

19 Feb '10

http://www.flashrom.org/pipermail/flashrom/2010-February/002318.html Should we commit single patches for each positive test report we get, or collect them? --- flashchips.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/flashchips.c b/flashchips.c index cfe9dba..6b29f5b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3763,7 +3763,7 @@ struct flashchip flashchips[] = { .total_size = 256, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10, .block_erasers = -- 1.6.5

1 0

[PATCH] fix kontron 986lcd-m and winbond w39v080fa
by Stefan Reinauer 19 Feb '10

19 Feb '10

See patch. This is what I had to do to get the combo working again.

3 9

Successful BIOS read on eMachines 333cs
by Andre Robatino 19 Feb '10

19 Feb '10

The following command ran successfully on an eMachines 333cs. (I checked that my.rom was the same as the original ROM file flashed to the BIOS.) flashrom -rV my.rom > flashrom.txt The smolt URL for this machine is http://www.smolts.org/client/show/pub_7982b3d7-a650-4770-8128-d385918bf9bd The file flashrom.txt is attached.

1 0

Re: [flashrom] data for Elitegroup ECS GF8100VM-M3 v1.0
by Carl-Daniel Hailfinger 19 Feb '10

19 Feb '10

Hallo Marcel, On 19.02.2010 02:37, marcel partap wrote: > Hallo Carl-Daniel, > nice to see progress on newer nforce, finally the day where users can > apply bios bugfixes without resorting to obsolete disk operating > systems disks are near - woohoo!! ;) > guess it indeed does use SPI, hope you can figure something out from > this log. Thank you for the log. It definitely helps us a lot. > flashrom v0.9.1-runknown > Probably r906 (in case someone looks at this report later on). > No coreboot table found. > DMI string 0: "ECS" > DMI string 1: "GeForce 8000 series" > DMI string 2: "1.0 " > DMI string 3: "ECS" > DMI string 4: "GeForce 8000 series" > DMI string 5: "1.0 " > Found chipset "NVIDIA MCP78S", enabling flash write... > This chipset is not really supported yet. Guesswork... > ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 > Guessed flash bus type is SPI > Found SMBus device 10de:0752 at 00:01:1 > SPI BAR is at 0xf9e80000, after clearing low bits BAR is at 0xf9e80000 > Mapping MCP67 SPI at 0xf9e80000, unaligned size 0x544. > SPI control is 0xc01a, enable=0, idle=0 > SPI on this chipset is not supported yet. > OK. > This chipset supports the following protocols: None. > And more confirmation that the code so far works fine. I hope to find some time to work on full SPI support around mid April. Regards, Carl-Daniel -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

1 0

[commit] r907 - trunk
by repository service 19 Feb '10

19 Feb '10

Author: snelson Date: Fri Feb 19 01:52:10 2010 New Revision: 907 URL: http://flashrom.org/trac/coreboot/changeset/907 Log: Here's a very quick patch to fix the missing unlock code. Fixes missing unlock for certain chips: * unlock_49lf00x * Pm49fl002 * Pm49fl004 * unlock_49flxxxc * SST49LF160C * unlock_winbond_fwhub * W39V080FA * W39V080FA (dual mode) Fixes missing printlock for certain chip: * printlock_w39v040c * W39V040C Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/Makefile trunk/chipdrivers.h trunk/flash.h trunk/flashchips.c trunk/flashrom.c trunk/pm49fl00x.c trunk/sst49lfxxxc.c trunk/w39v040c.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Feb 18 13:24:38 2010 (r906) +++ trunk/Makefile Fri Feb 19 01:52:10 2010 (r907) @@ -41,7 +41,7 @@ LDFLAGS += -L/usr/local/lib endif -CHIP_OBJS = jedec.o stm50flw0x0x.o w39v080fa.o sharplhf00l04.o w29ee011.o \ +CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o sharplhf00l04.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Thu Feb 18 13:24:38 2010 (r906) +++ trunk/chipdrivers.h Fri Feb 19 01:52:10 2010 (r907) @@ -117,6 +117,7 @@ int probe_49fl00x(struct flashchip *flash); int erase_49fl00x(struct flashchip *flash); int write_49fl00x(struct flashchip *flash, uint8_t *buf); +int unlock_49fl00x(struct flashchip *flash); /* sharplhf00l04.c */ int probe_lhf00l04(struct flashchip *flash); @@ -145,6 +146,7 @@ int erase_block_49lfxxxc(struct flashchip *flash, unsigned int address, unsigned int sector_size); int erase_chip_49lfxxxc(struct flashchip *flash, unsigned int addr, unsigned int blocksize); int write_49lfxxxc(struct flashchip *flash, uint8_t *buf); +int unlock_49lfxxxc(struct flashchip *flash); /* sst_fwhub.c */ int probe_sst_fwhub(struct flashchip *flash); @@ -157,11 +159,13 @@ int probe_w39v040c(struct flashchip *flash); int erase_w39v040c(struct flashchip *flash); int write_w39v040c(struct flashchip *flash, uint8_t *buf); +int printlock_w39v040c(struct flashchip *flash); /* w39V080fa.c */ int probe_winbond_fwhub(struct flashchip *flash); int erase_winbond_fwhub(struct flashchip *flash); int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); +int unlock_winbond_fwhub(struct flashchip *flash); /* w29ee011.c */ int probe_w29ee011(struct flashchip *flash); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Feb 18 13:24:38 2010 (r906) +++ trunk/flash.h Fri Feb 19 01:52:10 2010 (r907) @@ -206,6 +206,8 @@ int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); } block_erasers[NUM_ERASEFUNCTIONS]; + int (*printlock) (struct flashchip *flash); + int (*unlock) (struct flashchip *flash); int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Feb 18 13:24:38 2010 (r906) +++ trunk/flashchips.c Fri Feb 19 01:52:10 2010 (r907) @@ -49,6 +49,8 @@ * .eraseblocks[] = Array of { blocksize, blockcount } * .block_erase = Block erase function * } + * .printlock = Chip lock status function + * .unlock = Chip unlock function * .write = Chip write function * .read = Chip read function */ @@ -3330,7 +3332,6 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ - /* .erase = NULL, Was: erase_49fl00x */ .block_erasers = { { @@ -3344,6 +3345,7 @@ .block_erase = erase_chip_block_jedec, } }, + .unlock = unlock_49fl00x, .write = write_49fl00x, .read = read_memmapped, }, @@ -3360,7 +3362,6 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ - /* .erase = NULL, Was: erase_49fl00x */ .block_erasers = { { @@ -3374,6 +3375,7 @@ .block_erase = erase_chip_block_jedec, } }, + .unlock = unlock_49fl00x, .write = write_49fl00x, .read = read_memmapped, }, @@ -4406,7 +4408,6 @@ .tested = TEST_OK_PRW, .probe = probe_49lfxxxc, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ - /* .erase = NULL, Was: erase_49flxxxc */ .block_erasers = { { @@ -4422,6 +4423,7 @@ .block_erase = erase_block_49lfxxxc, } }, + .unlock = unlock_49lfxxxc, .write = write_49lfxxxc, .read = read_memmapped, }, @@ -5740,7 +5742,6 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_FIXME, - /* .erase = NULL, Was erase_w39v040c */ .block_erasers = { { @@ -5751,6 +5752,7 @@ .block_erase = erase_chip_block_jedec, } }, + .printlock = printlock_w39v040c, .write = write_jedec_1, .read = read_memmapped, }, @@ -5915,7 +5917,6 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_FIXME, - /* .erase = NULL, Was erase_winbond_fwhub */ .block_erasers = { { @@ -5926,6 +5927,7 @@ .block_erase = erase_chip_block_jedec, } }, + .unlock = unlock_winbond_fwhub, .write = write_jedec_1, .read = read_memmapped, }, @@ -5942,7 +5944,6 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_FIXME, - /* .erase = NULL, Was erase_winbond_fwhub */ .block_erasers = { { @@ -5953,6 +5954,7 @@ .block_erase = erase_chip_block_jedec, } }, + .unlock = unlock_winbond_fwhub, .write = write_jedec_1, .read = read_memmapped, }, Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu Feb 18 13:24:38 2010 (r906) +++ trunk/flashrom.c Fri Feb 19 01:52:10 2010 (r907) @@ -838,6 +838,9 @@ flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); + if (flash->printlock) + flash->printlock(flash); + return flash; } @@ -1147,12 +1150,18 @@ fprintf(stderr, "Continuing anyway.\n"); } } + if (flash->unlock) + flash->unlock(flash); + if (erase_flash(flash)) { emergency_help_message(); programmer_shutdown(); return 1; } } else if (read_it) { + if (flash->unlock) + flash->unlock(flash); + if (read_flash(flash, filename)) { programmer_shutdown(); return 1; @@ -1160,6 +1169,9 @@ } else { struct stat image_stat; + if (flash->unlock) + flash->unlock(flash); + if (flash->tested & TEST_BAD_ERASE) { fprintf(stderr, "Erase is not working on this chip " "and erase is needed for write. "); Modified: trunk/pm49fl00x.c ============================================================================== --- trunk/pm49fl00x.c Thu Feb 18 13:24:38 2010 (r906) +++ trunk/pm49fl00x.c Fri Feb 19 01:52:10 2010 (r907) @@ -36,6 +36,12 @@ } } +int unlock_49fl00x(struct flashchip *flash) +{ + write_lockbits_49fl00x(flash->virtual_registers, flash->total_size * 1024, 0, flash->page_size); + return 0; +} + int erase_49fl00x(struct flashchip *flash) { int i; Modified: trunk/sst49lfxxxc.c ============================================================================== --- trunk/sst49lfxxxc.c Thu Feb 18 13:24:38 2010 (r906) +++ trunk/sst49lfxxxc.c Fri Feb 19 01:52:10 2010 (r907) @@ -82,6 +82,11 @@ return 0; } +int unlock_49lfxxxc(struct flashchip *flash) +{ + return write_lockbits_49lfxxxc(flash, 0); +} + int erase_sector_49lfxxxc(struct flashchip *flash, unsigned int address, unsigned int sector_size) { unsigned char status; Modified: trunk/w39v040c.c ============================================================================== --- trunk/w39v040c.c Thu Feb 18 13:24:38 2010 (r906) +++ trunk/w39v040c.c Fri Feb 19 01:52:10 2010 (r907) @@ -50,6 +50,32 @@ return 1; } +int printlock_w39v040c(struct flashchip *flash) +{ + chipaddr bios = flash->virtual_memory; + uint8_t lock; + + chip_writeb(0xAA, bios + 0x5555); + programmer_delay(10); + chip_writeb(0x55, bios + 0x2AAA); + programmer_delay(10); + chip_writeb(0x90, bios + 0x5555); + programmer_delay(10); + + lock = chip_readb(bios + 0xfff2); + + chip_writeb(0xAA, bios + 0x5555); + programmer_delay(10); + chip_writeb(0x55, bios + 0x2AAA); + programmer_delay(10); + chip_writeb(0xF0, bios + 0x5555); + programmer_delay(40); + + printf("%s: Boot block #TBL is %slocked, rest of chip #WP is %slocked.\n", + __func__, lock & 0x4 ? "" : "un", lock & 0x8 ? "" : "un"); + return 0; +} + int erase_w39v040c(struct flashchip *flash) { int i;

1 0

[PATCH] quick fix for chip locks
by Sean Nelson 19 Feb '10

19 Feb '10

Here's a very quick patch to fix the missing unlock code. Fixes missing unlock for certain chips: * unlock_49lf00x * Pm49fl002 * Pm49fl004 * unlock_49flxxxc * SST49LF160C * unlock_winbond_fwhub * W39V080FA * W39V080FA (dual mode) Fixes missing printlock for certain chip: * printlock_w39v040c * W39V040C Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> --- Let's get this regression fixed ASAP.

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